I Microprocessor and Master1 RISC-V Trace Encoder (TRACE)1.1 Terminology1.2 Introduction1.3 Features1.4 Architectural Overview1.5 Functional Description1.5.1 Synchronization1.5.2 Address Mode1.5.3 Optional Sideband Signals1.5.4 Filtering1.5.5 Anchor Tag1.5.6 Memory Writing Mode1.5.7 Automatic Restart1.6 Encoder Output Packets1.6.1 Header1.6.2 Index1.6.3 Payload1.6.3.1 Format 3 Packets1.6.3.2 Format 2 Packets1.6.3.3 Format 1 Packets1.7 Interrupt1.8 Programming Procedures1.8.1 Encoder Option Configuration1.8.2 Filter Configuration1.8.3 Enable Encoder1.8.4 Disable Encoder1.8.5 Notify1.8.6 Decode Data Packets1.8.7 AHB Configuration1.8.8 Software Retention1.9 Register Summary1.10 Registers2 Low-Power CPU2.1 Overview2.2 Features2.3 Configuration and Status Registers (CSRs)2.3.1 Register Summary2.3.2 Registers2.4 Interrupts and Exceptions2.4.1 Interrupts2.4.2 Interrupt Handling2.4.3 Exceptions2.5 Debugging2.5.1 Features2.5.2 Functional Description2.5.3 Register Summary2.5.4 Registers2.6 Hardware Trigger2.6.1 Features2.6.2 Functional Description2.6.3 Trigger Execution Flow2.6.4 Register Summary2.6.5 Registers2.7 Performance Counter2.8 System Access2.8.1 Memory Access2.8.2 Peripheral Access2.9 Event Task Matrix Feature2.10 Sleep and Wake-Up Process2.10.1 Features2.10.2 Process2.10.3 Wake-Up Sources2.10.4 Sleep Rejection2.11 Physical Memory Protection2.11.1 Features2.11.2 Functional Description2.11.3 Register Summary2.11.4 Registers3 GDMA Controller (GDMA-AHB, GDMA-AXI)3.1 Overview3.2 Features3.3 Architecture3.4 Functional Description3.4.1 Linked List3.4.2 Peripheral-to-Memory and Memory-to-Peripheral Data Transfer3.4.3 Memory-to-Memory Data Transfer3.4.4 Enabling GDMA3.4.5 Linked List Reading Process3.4.6 Interrupt Response Mechanism for GDMA-AXI Linked List Switching3.4.7 EOF3.4.8 Accessing Memory3.4.9 Arbitration3.4.10 Bus Error Response Information Logging3.4.11 Automatic Clock Gating3.5 Event Task Matrix Feature3.6 Interrupts3.7 Programming Procedures3.7.1 Programming Procedures for GDMA's Transmit Channel3.7.2 Programming Procedures for GDMA's Receive Channel3.7.3 Programming Procedures for Memory-to-Memory Transfer3.7.4 Programming Procedures for Channel Priority and Weight3.8 Register Summary3.8.1 GDMA-AHB Register Summary3.8.1.1 GDMA-AHB-HP Register Summary3.8.1.2 GDMA-AHB-LP Register Summary3.8.2 GDMA-AXI Register Summary3.9 Registers3.9.1 GDMA-AHB-HP Registers3.9.2 GDMA-AHB-LP Registers3.9.3 GDMA-AXI Registers4 2D-DMA Controller (2D-DMA)4.1 Overview4.2 Features4.3 Architecture4.4 Functional Description4.4.1 Transfer Mode4.4.2 Linked List4.4.3 Padding in 2D-MOD1 Mode and DSCR-PORT Mode4.4.4 Peripheral-to-Memory and Memory-to-Peripheral Data Transfer4.4.5 Memory-to-Memory Data Transfer4.4.6 Macroblock Reordering4.4.6.1 Macroblock Reordering in TX Direction4.4.6.2 Macroblock Reordering in RX Direction4.4.7 Color Space Conversion4.4.8 Enabling 2D-DMA4.4.9 Linked List Reading Process4.4.10 EOF4.4.11 Accessing Memory4.4.12 Arbitration4.5 Event Task Matrix Feature4.6 Interrupts4.7 Programming Procedures4.7.1 General Configurations for 2D-DMA4.7.2 Mode-Specific Configurations for 2D-DMA4.7.3 Configurations for 2D-DMA's Transmit Channel4.7.4 Configurations for 2D-DMA's Receive Channel4.7.5 Configurations for Memory-to-Memory Transfer4.7.6 Configurations for Channel Priority and Weight4.7.7 Resetting 2D-DMA While it Runs4.8 Register Summary4.9 RegistersII System Component5 Watchdog Timers (WDT)5.1 Overview5.2 Digital Watchdog Timers5.2.1 Features5.2.2 Functional Description5.2.2.1 Clock Source and 32-Bit Counter5.2.2.2 Stages and Timeout Actions5.2.2.3 Write Protection5.2.2.4 Flash Boot Protection5.3 Super Watchdog5.3.1 Features5.3.2 Super Watchdog Controller5.3.2.1 Structure5.3.2.2 Workflow5.4 Interrupts5.5 Register Summary5.6 Registers6 RTC Timer6.1 Introduction6.2 Feature List6.3 Functional Description6.4 Event Task Matrix Feature6.5 Interrupts6.6 Register Summary6.7 Registers7 Debug Assistant7.1 Overview7.2 Features7.3 Functional Description7.3.1 Region Read/Write Monitoring7.3.2 SP Monitoring7.3.3 PC and SP Logging7.3.4 Lockup Monitoring7.3.5 CPU/DMA Bus Access Logging7.4 Interrupts7.5 Programming Procedures7.5.1 Region Monitoring and SP Monitoring Configuration7.5.2 PC and SP Logging Configuration7.5.3 Lockup Monitoring Configuration7.5.4 CPU/DMA Bus Access Logging Configuration7.5.4.1 Bus Access Logging 1 Configuration7.5.4.2 Bus Access Logging 2 Configuration7.6 Register Summary7.6.1 Bus Logging Configuration Registers7.6.2 Other Registers7.7 Registers7.7.1 Bus Logging Configuration Registers7.7.2 Other Registers8 LP Mailbox8.1 Overview8.2 Features8.3 Functional Description8.3.1 Message Registers8.3.2 Interrupts8.3.3 Inter-Core Communication8.4 Register Summary8.5 Registers9 Power Supply Detector (PSDET)9.1 Overview9.2 Features9.3 Functional Description9.3.1 Architecture9.3.2 Brown-out Detector9.3.3 Voltage Glitch Detectors9.4 Interrupts9.5 Register Summary9.6 RegistersIII Cryptography/Security Component10 AES Accelerator (AES)10.1 Introduction10.2 Features10.3 Clock and Reset10.4 AES Working Modes10.5 Typical AES Working Mode10.5.1 Key, Plaintext, and Ciphertext10.5.2 Endianness10.5.3 Operation Process 10.6 DMA-AES Working Mode10.6.1 Key, Plaintext, and Ciphertext10.6.2 Endianness10.6.3 Standard Incrementing Function10.6.4 Block Number10.6.5 Initialization Vector10.6.6 Block Operation Process10.6.7 GCM Operation Process10.7 GCM Algorithm10.7.1 Hash Subkey10.7.2 J010.7.3 Authentication Tag10.7.4 AAD Block Number10.7.5 Number of Effective Bits of Incomplete Blocks10.8 Pseudo-Round Anti-DPA Function10.9 Interrupts10.10 Memory Summary10.11 Register Summary10.12 Registers11 ECC Accelerator (ECC)11.1 Overview11.2 Feature List11.3 ECC Basics11.3.1 Elliptic Curve and Points on the Curves11.3.2 Affine Coordinates and Jacobian Coordinates11.3.3 Memory Blocks11.3.4 Data and Data Block11.3.5 Writing Data11.3.6 Reading Data11.3.7 Standard Calculation and Jacobian Calculation11.4 Function Description11.4.1 Curve Mode11.4.2 Working Modes11.4.2.1 Affine Point Multiplication (Affine Point Multi)11.4.2.2 Affine Point Verification (Affine Point Verif)11.4.2.3 Affine Point Verification + Affine Point Multiplication (Affine Point Verif + Multi)11.4.2.4 Jacobian Point Multiplication (Jacobian Point Multi)11.4.2.5 Point Addition (Point Add)11.4.2.6 Jacobian Point Verification (Jacobian Point Verif)11.4.2.7 Affine Point Verification + Jacobian Point Multiplication (Affine Point Verif + Jacobian Point Multi)11.4.2.8 Mod Addition (Mod Add)11.4.2.9 Mod Subtraction (Mod Sub)11.4.2.10 Mod Multiplication (Mod Multi)11.4.2.11 Mod Division (Mod Div)11.4.3 Enhancing Anti-Attack Performance11.4.4 Clock11.4.5 Reset11.5 Interrupts11.6 Programming Procedures11.7 Register Summary11.8 Registers12 HMAC Accelerator (HMAC)12.1 Overview12.2 Feature List12.3 Functional Description12.3.1 Upstream Mode12.3.2 Downstream Mode - JTAG Enable Feature12.3.3 Downstream Mode - RSA Digital Signature Peripheral and Key Derivation Feature12.4 HMAC eFuse Configuration12.5 HMAC Process (Detailed)12.5.1 Enable HMAC module12.5.2 Configure HMAC keys and key purposes12.5.3 Downstream mode process12.5.4 Upstream mode process12.6 HMAC Algorithm Details12.6.1 Padding Bits12.6.2 HMAC Algorithm Structure12.6.3 Hardware Occupation12.7 Register Summary12.8 Registers13 RSA Accelerator (RSA)13.1 Introduction13.2 Features13.3 Functional Description13.3.1 Definitions and Representations13.3.2 Large-Number Modular Exponentiation13.3.3 Large-Number Modular Multiplication13.3.4 Large-Number Multiplication13.3.5 Options for Additional Acceleration13.4 Interrupts13.5 Memory Summary13.6 Register Summary13.7 Registers14 SHA Accelerator (SHA)14.1 Overview14.2 Features14.3 Working Modes14.4 Function Description14.4.1 Preprocessing14.4.1.1 Padding the Message14.4.1.2 Parsing the Message14.4.1.3 Setting the Initial Hash Value14.4.2 Hash Operation14.4.2.1 Typical SHA Mode Process14.4.2.2 DMA-SHA Mode Process14.4.3 Message Digest14.5 Interrupt14.6 Register Summary14.7 Registers15 RSA Digital Signature Peripheral (RSA_DS)15.1 Overview15.2 Features15.3 Functional Description15.3.1 Overview15.3.2 Private Key Operands15.3.3 Software Prerequisites15.3.4 RSA_DS Operation at the Hardware Level15.3.4.1 Hardware Occupation15.3.5 RSA_DS Operation at the Software Level15.4 Memory Summary15.5 Register Summary15.6 Registers16 ECDSA Digital Signature Peripheral (ECDSA_DS)16.1 Introduction16.2 Features16.3 ECDSA Basics16.3.1 Domain Parameters16.3.2 Key Generation16.3.3 Signature Generation16.3.4 Signature Verification16.4 Functional Description16.4.1 ECDSA_DS Working Modes16.4.2 Key Source16.4.3 Data and Data Block16.4.3.1 Writing Data16.4.3.2 Reading Data16.4.3.3 Padding the Message16.4.3.4 Parsing the Message16.4.4 Security Features16.4.4.1 High Anti-Attack Performance16.4.4.2 State-Dependent Register Access Control16.4.4.3 Hardware Occupation16.5 Programming Procedures16.5.1 ECDSA_DS Process16.5.1.1 IDLE Stage16.5.1.2 PREP Stage16.5.1.3 LOAD Stage16.5.1.4 PROC Stage16.5.1.5 GAIN Stage16.5.1.6 POST Stage16.5.1.7 ECDSA_DS SHA Interface16.5.2 Clock16.5.3 Reset16.6 Interrupts16.7 Memory Blocks16.8 Register Summary16.9 RegistersIV Image and Voice Processing17 JPEG Codec17.1 Terminology17.2 Overview17.3 Feature List17.4 Architectural Overview17.5 Functional Description17.5.1 JPEG Encoder17.5.1.1 Pause17.5.1.2 Color Space Conversion17.5.1.3 Configurable Quantization Coefficient Table17.5.1.4 Stuffed Zero Byte17.5.1.5 EOI Marker17.5.1.6 Timeout Detection17.5.2 JPEG Decoder17.5.2.1 Multiple Components17.5.2.2 Parsing RST Marker17.5.2.3 Configurable Quantization Coefficient Table17.5.2.4 Configurable Huffman Table17.5.2.5 Timeout Detection17.6 Interrupts17.7 Programming Procedures17.7.1 JPEG Encoder17.7.2 JPEG Decoder17.7.3 Reset17.8 Register Summary17.9 Registers18 Pixel-Processing Accelerator (PPA)18.1 Overview18.2 Terminology18.3 Features18.4 Architectural Overview18.5 Functional Description18.5.1 PPA Color Space18.5.1.1 SRM Color Space18.5.1.2 BLEND Color Space18.5.2 PPA 2D-DMA Linked List Configuration18.5.2.1 SRM Special Configuration18.5.3 Scaling - Rotation - Mirroring (SRM)18.5.3.1 Basic Functionality18.5.3.2 Pixel Block Reorder18.5.4 Layer Blending (BLEND)18.5.4.1 Basic Functionality18.5.4.2 Filled Image Output18.6 Interrupts18.7 Programming Procedures18.7.1 PPA Clock Reset Configuration18.7.2 SRM Configuration18.7.3 BLEND CLUT Configuration18.7.4 BLEND Configuration18.7.5 BLEND Image Filling Configuration18.7.6 Error Handling18.8 Register Summary18.9 Registers19 Audio Sample Rate Converter19.1 Overview19.2 Terminology19.3 Features19.4 Architectural Overview19.5 Functional Description19.5.1 Clock19.5.2 Reset19.5.3 Resampler19.5.4 Fractional Sample Rate Converter19.5.5 Input/Output Data Length19.5.5.1 No Residual Data19.5.5.2 Residual Data Handling19.5.6 DMA Interface19.6 Interrupts19.7 Configuration Procedure19.7.1 Usage Restrictions and Notes19.8 Application Example19.9 Register Summary19.10 Registers20 LCD and Camera Controller (LCD_CAM)20.1 Overview20.2 Features20.3 Functional Description20.3.1 Block Diagram20.3.2 Signal Description20.3.3 LCD_CAM Module Clocks20.3.3.1 LCD Clock20.3.3.2 Camera Clock20.3.4 LCD_CAM Reset20.3.5 LCD_CAM Data Format Control20.3.5.1 LCD Data Format Control20.3.5.2 Camera Data Format Control20.3.6 YUV-RGB Data Format Conversion20.3.6.1 YUV Formats20.3.6.2 Format Conversion Configuration20.3.7 LCD_CAM Timing20.3.7.1 LCD Timing (RGB Format)20.3.7.2 LCD Timing (I8080/MOTO6800 Format)20.4 Interrupts20.5 Software Configuration Process20.5.1 Configure LCD (RGB Format) as TX Mode20.5.2 Configure LCD (I8080/MOTO6800 Format) as TX Mode20.5.3 Configure Camera as RX Mode20.6 Register Summary20.7 RegistersV Connectivity Interface21 UART Controller (UART)21.1 Overview21.2 Features21.3 UART Structure21.4 Functional Description21.4.1 Clock and Reset21.4.2 UART FIFO21.4.3 Baud Rate Generation and Detection21.4.3.1 Baud Rate Generation21.4.3.2 Baud Rate Detection21.4.4 UART Data Frame21.4.5 AT_CMD Character Structure21.4.6 RS48521.4.6.1 Driver Control21.4.6.2 Turnaround Delay21.4.6.3 Bus Snooping21.4.7 IrDA21.4.8 Wakeup21.4.9 Flow Control21.4.9.1 Hardware Flow Control21.4.9.2 Software Flow Control21.4.10 GDMA Mode21.5 Interrupts21.6 Programming Procedures21.6.1 Register Type21.6.2 Detailed Steps21.6.2.1 Initializing UARTn21.6.2.2 Configuring UARTn Communication21.6.2.3 Enabling UARTn21.7 Register Summary21.7.1 UART Register Summary21.7.2 LP UART Register Summary21.7.3 UHCI Register Summary21.8 Registers21.8.1 UART Registers21.8.2 LP UART Registers21.8.3 UHCI Registers22 USB Serial/JTAG Controller22.1 Overview22.2 Feature List22.3 Functional Description22.3.1 CDC-ACM USB Interface Functional Description22.3.2 CDC-ACM Firmware Interface Functional Description22.3.3 USB-to-JTAG Interface: JTAG Command Processor22.3.4 USB-to-JTAG Interface: CMD_REP Usage Example22.3.5 USB-to-JTAG Interface: Response Capture Unit22.3.6 USB-to-JTAG Interface: Control Transfer Requests22.4 Interrupts22.5 Programming Procedures22.6 Register Summary22.7 Registers23 LED PWM Controller (LEDC)23.1 Overview23.2 Features23.3 Architectural Overview23.4 Functional Description23.4.1 Clock23.4.2 Reset23.4.3 Timers23.4.3.1 Clock Divider Configuration23.4.3.2 20-Bit Counter23.4.3.3 Timer Configuration Constraints23.4.4 PWM Generators23.4.4.1 PWM Output Signal Dithering23.4.4.2 Applying the Changed Configuration23.4.5 Duty Cycle Fading23.4.5.1 Linear Duty Cycle Fading23.4.5.2 Gamma Curve Fading23.4.5.3 Suspend and Resume Duty Cycle Fading23.5 Event Task Matrix Feature23.6 Interrupts23.7 Programming Procedures23.8 Memory Blocks23.9 Register Summary23.10 Registers24 Motor Control PWM (MCPWM)24.1 Overview24.2 Features24.3 Modules24.3.1 Overview24.3.1.1 Timer Module24.3.1.2 Operator Module24.3.1.3 Capture Module24.3.1.4 ETM Module24.3.2 PWM Timer Module24.3.2.1 Configurations of the PWM Timer Module24.3.2.2 PWM Timer's Working Modes and Timing Event Generation24.3.2.3 Shadow Register of PWM Timer24.3.2.4 PWM Timer Synchronization and Phase Locking24.3.3 PWM Operator Module24.3.3.1 PWM Generator Module24.3.3.2 Dead Time Generator Module24.3.3.3 PWM Carrier Module24.3.3.4 Fault Detection Module24.3.4 Capture Module24.3.4.1 Introduction24.3.4.2 Capture Timer24.3.4.3 Capture Channel24.3.5 ETM Module24.3.5.1 Overview24.3.5.2 MCPWM-Related ETM Events24.3.5.3 MCPWM-Related ETM Tasks24.4 Interrupts24.5 Register Summary24.6 Registers25 Remote Control Peripheral (RMT)25.1 Overview25.2 Features25.3 Functional Description25.3.1 Architecture25.3.2 RAM25.3.2.1 Structure of RAM25.3.2.2 Use of RAM25.3.2.3 RAM Access25.3.3 Clock25.3.4 Transmitter25.3.4.1 Normal TX Mode25.3.4.2 Wrap TX Mode25.3.4.3 TX Modulation25.3.4.4 Continuous TX Mode25.3.4.5 Simultaneous TX Mode25.3.5 Receiver25.3.5.1 Normal RX Mode25.3.5.2 Wrap RX Mode25.3.5.3 RX Filtering25.3.5.4 RX Demodulation25.3.6 Configuration Update25.4 Interrupts25.5 Register Summary25.6 Registers26 Parallel IO Controller (PARLIO)26.1 Introduction26.2 Glossary26.3 Features26.4 Architectural Overview26.5 Functional Description26.5.1 Clock Generator26.5.2 Clock & Reset Restriction26.5.3 Master-Slave Mode26.5.4 Receive Modes of the RX Unit26.5.4.1 Level Enable Mode26.5.4.2 Pulse Enable Mode26.5.4.3 Software Enable Mode26.5.5 RX Unit GDMA SUC EOF Generation26.5.6 TX Unit EOF Generation26.5.7 RX Unit Timeout26.5.8 Unlimited Length Data Transmission of TX Unit26.5.9 TX Chip Select Function26.5.10 Output Clock Gating of TX Unit26.5.11 Bus Idle Value of TX Unit26.5.12 Data Transfer in a Single Frame26.5.13 Bit Reversal in One Byte26.6 Interrupts26.7 Programming Procedures26.7.1 Data Receiving Operation Process26.7.2 Data Transmitting Operation Process26.8 Application Examples26.8.1 Co-working with SPI26.8.2 Co-working with I2S26.8.3 Co-working with LCD26.9 Register Summary26.10 RegistersVI Analog Signal Processing27 Touch Sensor (TOUCH)27.1 Terminology27.2 Feature List27.3 Architectural Overview27.3.1 Touch Panel27.3.2 Capacitive Touch Pin27.3.3 Touch Sensor27.4 Functional Description27.4.1 Touch FSM27.4.2 Sampled Signal Preprocessing27.4.2.1 Measurement Process27.4.2.2 Trigger Source of Measurement27.4.2.3 Scan Mode27.4.2.4 Frequency Hopping27.4.3 Touch Detection27.4.3.1 Sampled Value27.4.3.2 Hardware Touch Detection27.4.4 Proximity Mode27.4.5 Sleep Mode27.4.6 Moisture Tolerance27.4.7 Water Rejection27.5 Interrupts27.6 Register Summary27.6.1 Interrupt and Status Register Summary27.6.2 Configuration Register Summary27.7 Registers27.7.1 Interrupt and Status Registers27.7.2 Configuration Registers28 SAR ADC Digital Controller (ADC)28.1 Overview28.2 Features28.2.1 ADC Channels28.2.2 ADC Clock28.3 Trigger Control28.3.1 Features28.3.2 Functional Description28.3.2.1 Trigger Mode Selection28.3.2.2 Timer Trigger28.3.2.3 Software Trigger and Stop28.4 Pattern Table28.4.1 Features28.4.2 Functional Description28.4.2.1 Pattern Table Structure28.4.2.2 Scan Length and Pointer28.4.2.3 Update Timing28.4.2.4 Channel and Mode Selection28.5 SAR Control FSM28.5.1 Features28.5.2 Functional Description28.5.2.1 State Machine Flow28.5.2.2 Continuous Sampling Mode28.5.2.3 SAR Power Control28.5.2.4 State Query28.6 Data Processing28.6.1 Features28.6.2 Functional Description28.6.2.1 Data Arbitration28.6.2.2 IIR Filter28.6.2.3 Reading Latest Sample28.7 Threshold Monitor28.7.1 Features28.7.2 Functional Description28.7.2.1 Threshold Configuration28.7.2.2 Comparison Logic28.7.2.3 All-Channel Monitoring Mode28.8 DMA Control28.8.1 Features28.8.2 Functional Description28.8.2.1 DMA Enable28.8.2.2 EOF Frame Management28.8.2.3 DMA Data Format28.8.2.4 FIFO Overflow28.9 ETM Events28.9.1 Features28.9.2 Functional Description28.9.2.1 ETM Trigger Inputs28.9.2.2 ETM Event Outputs28.9.2.3 ETM Clock28.10 Interrupts28.11 Register Summary28.12 Registers29 Analog Voltage Comparator29.1 Introduction29.2 Feature List29.3 Architectural Overview29.4 Functional Description29.4.1 Reference Voltage Configuration29.4.2 PAD COMP Controller29.4.3 Clock29.4.4 Reset29.5 Event Task Matrix29.6 Interrupts29.7 Programming Procedures29.8 Register Summary29.9 RegistersVII AppendixRelated Documentation and ResourcesGlossaryAbbreviations for PeripheralsAbbreviations Related to RegistersAccess Types for RegistersProgramming Reserved Register FieldIntroductionProgramming Reserved Register FieldInterrupt Configuration RegistersRevision History
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31 2726252423 22 1514 8 7 210Reset
31 2322 2019 1817 0Reset 31 0Reset fl
31 0Reset 31 0Reset 31 0Reset
31 0Reset 31 0Reset 31 0Reset
31 109 65 10Reset
31 43 0Reset fi 31 43 0Reset fi
31 65 0Reset fi
31 65 0Reset fi fi
31 876543210Reset
31 876543210Reset
31 876543210Reset
31 876543210Reset
31 76543210Reset
31 76543210Reset
31 76543210Reset
31 76543210Reset
31 65 432 0Reset 31 43210Reset fi fi fi fi
31 87 6543210Reset fi fi fi fi fi fi
31 1312 11 0Reset fi 31 131211 0Reset fi
31 543210Reset fi fi fi fi
31 0Reset fi fi 31 43 0Reset fi
31 10Reset fi
31 109 876543210Reset fi fi fi fi fl fi fi fi
31 1312 11 0Reset fi 31 1098 0Reset fi
31 43210Reset fi fi fi
31 0Reset fi fi 31 43 0Reset fi
31 10Reset fi 31 0Reset fi
31 0Reset fi 31 1615 0Reset fi 31 10Reset fi
31 292827 26 2221 20 19 1716 15 14 1211 10 9 76 5 4 21 0Reset fi fi fi fi fi fi
fi fi 31 0Reset
31 282726252423 22 1514 8 7 210Reset
31 2322 2019 1817 0Reset 31 0Reset fl
31 0Reset 31 0Reset 31 0Reset
31 0Reset 31 0Reset
31 2726252423 22 1514 8 7 210Reset
31 2322 2019 1817 0Reset 31 0Reset fl
31 0Reset 31 0Reset
31 0Reset 31 0Reset 31 0Reset
31 0Reset
31 87 65 10Reset
31 43 0Reset fi 31 43 0Reset fi 31 65 0Reset fi
31 65 0Reset fi fi
31 11109876543210Reset
31 11109876543210Reset
31 11109876543210Reset
31 11109876543210Reset
31 11109876543210Reset
31 11109876543210Reset
31 11109876543210Reset
31 11109876543210Reset
31 109876 43210Reset fi fi fi fi fi fi
fi fi 31 1312 11 0Reset fi
31 131211 0Reset fi
31 543210Reset fi fi fi fi
31 0Reset fi fi
31 1110987 543210Reset fi fi fi fi fl fi fi
fi fi fi 31 1312 11 0Reset fi
31 1098 0Reset fi
31 43210Reset fi fi fi
31 0Reset fi fi 31 1615 0Reset fi fi
31 210Reset fi fi
31 6543210Reset fi fi fi fi fi fi
31 0Reset fi 31 0Reset fi
31 0Reset fi 31 0Reset fi
31 10Reset 31 10Reset
31 543210Reset fi fi fi fi fi
313029282726252423 22 181716151413121110987 210Reset fl fl fl fl fl fl
fl fl fl fl fl fl fl fl fl fl fl fl
31 2322 2019 1817 0Reset 31 0Reset fl
31 0Reset 31 0Reset 31 0Reset
31 0Reset
313029282726252423 22 181716151413121110987 210Reset fl fl fl fl fl fl
fl fl fl fl fl fl fl fl fl fl fl fl
31 2322 2019 1817 0Reset 31 0Reset fl
31 0Reset 31 0Reset 31 0Reset
31 0Reset 31 43 0Reset 31 43 0Reset
31 109 65 0Reset 31 109 65 0Reset
31 3210Reset fi 31 987 43 0Reset fi fi fi
31 987 43 0Reset fi fi fi 31 65 0Reset fi
31 65 0Reset fi 31 210Reset
31 0Reset 31 0Reset 31 0Reset
• • • • • • • • fi
MemoryRx Channel 0Tx Channel 0Rx Channel 1Tx Channel 1Rx Channel 2Tx Channel 2Tx Channel 3ArbiterPeriSelectRx0 CSC Rx0 ReorderTx0 Reorder Tx0 CSCTx1 CSCTx2 CSCTx3 CSCAXI_BUSJPEGPPA2D-DMA Controller fi fi • fi fi fi • fi fi fi
• fi fi fi × × × × • fi fi fi fi fi fi fi
fi • • fi • • fi fi • • fi • • fi fi fi fi fi fi
fi fi • • • • • • fi fi fi fi fi fi • • fi fi fi fi fi fi fi
× × × × × × × fi • fi • × × ×
fi fi
fi fi fi fi fi fi
fi × × × × × × × fi fi fi fi × × × × fi fi fi fi ×
• • • • • • • • • •
fi fi fi fi fi fi fi 256 ∗ Q = A[9 : 0] ∗ x + B[10 : 0] ∗ y + C[9 : 0] ∗ z + D[17 : 0] fi fi fi fi fi fi• • • • • • fi fi fi fi fi fi fi fi fi
→ → → → → → → → → → fi → → → → → → → → →
→ → fi fi fi fi fi fi fi fi fi fi fi fi
fi fi fi fi fi • • fi • fi fi fi fl
• • • • fi fi fi fi fi fi fi fi •
• fi • fi fi• fi fi • • fi fi •
• fi fi fi fi • • • • • • • • • •
• • • • • • • • fl• fl• • fl• fl • • • • • fl• fl
• • fl• fl fi fi fi fi fi fi • fi fi • fi fi • fi × × × × • fi fi fi fi fi fi fi fi
fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi
fi fi
fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi
fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi
fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi
fi fi fi fi fi fi fi fi fi fi
fi fi fi fi fi fi fi
fi 31 27262524 23 1716 15 121110 98 6543210Reset fi fi fl fl fl fi fi
fi fi fi fi fi fi
fi fi 31 11109 0Reset fi fi
31 2423222120 19 0Reset fi fi fi 31 0Reset fi
31 87 65 43 0Reset fi fi fi fi fi
31 7654 3 0Reset fi fi fi
31 65 321 0Reset fi fi fi fi
31 32 0Reset fi 31 2120 0Reset fi fi fi
3128270Reset fi fi fi 31 2120 0Reset fi fi 31 2827 0Reset fi fi
31 2120 0Reset fi fi fi 31 2827 0Reset fi fi fi
31 43 210Reset fi fi fi 31 2827 1413 0Reset fi fi
31 27262524 23 1716 15 121110 98 6543210Reset fi fi fi fi fi
fi fi fi fi fi fi
31 121110 0Reset fi
31 252423222120 19 0Reset fi fi fi fi
31 0Reset fi 31 87 543 0Reset fi fi fi fi fi
31 7654 3 0Reset fi fi fi
31 65 321 0Reset fi fi fi fi
31 65 32 0Reset fi fi
31 2120 0Reset fi fi fi 31 2827 0Reset fi fi fi 31 2120 0Reset fi fi
31 2827 0Reset fi fi 31 2120 0Reset fi fi fi 31 2827 0Reset fi fi fi
31 43 210Reset fi fi fi
31 3210Reset fi fi fi 31 0Reset fi
31 0Reset fi 31 0Reset fi
31 0Reset fi 31 171615 0Reset fi fi
31 171615 0Reset fi fi
31 131211109876543210Reset
31 131211109876543210Reset
31 131211109876543210Reset
31 131211109876543210Reset
31 14131211109876543210Reset
31 14131211109876543210Reset
31 14131211109876543210Reset
31 14131211109876543210Reset
31 2928 24232221 171615141312111098765 210Reset
31 2524 23 1917 0Reset fi
31 0Reset 31 0Reset 31 0Reset
31 0Reset
31 2928 24232221 171615141312111098765 210Reset
31 2423 23 1917 0Reset fi
31 0Reset 31 0Reset 31 0Reset
31 0Reset 31 0Reset
31 2625 2221 1918 1514 1211 87 43 0Reset 31 0Reset
31 32 0Reset fi 31 32 0Reset fi
fi fl
• • • • • •
Timer Group 0MWDT0TIMG0_WDT_ENTIMG0_WDTFEED_REGTIMG0_WDT_WKEYTIMG0_WDT_CPU_RESET Signal TIMG0_WDT_CORE_RESET SignalTIMG0_WDT_INT SignalLP_DYN_SLOW_CLKRTCRWDTRTC_WDT_CPU_RESET SignalRTC_WDT_SYS_RESET SignalRTC_WDT_INT SignalPrescaler (16 bits)TIMG0_WDTCONFIG1_REGTIMG0_WDT_CLK_PRESCALETIMG0_WDT_DIVCNT_RSTmwdt0 clkRTC_WDT_ENRTC_WDT_FEEDRTC_WDT_WKEYRTC_WDT_CORE_RESET SignalDIGITALMWDT0 clock Selection & gatingTimer Group 1MWDT1TIMG1_WDT_ENTIMG1_WDTFEED_REGTIMG1_WDT_WKEYTIMG1_WDT_CPU_RESET SignalTIMG1_WDT_CORE_RESET SignalTIMG1_WDT_INT SignalPrescaler (16 bits)TIMG1_WDTCONFIG1_REGTIMG1_WDT_CLK_PRESCALETIMG1_WDT_DIVCNT_RSTmwdt1 clkMWDT1 clock Selection & gating • fi • fi fi • fi fi fi fi
fi fi fi fi fi fi Thold0= RT CW DT ST G0HOLD << (EF USEW DT DELAY SEL + 1) << fi fi fi
fi fi fi fi fi fi fi fi fi fi fl fi fi • • •
fl • • • • • • • fl
fi fi fi fi fi fi fi fi fi fi fi
3130 2827 2524 2221 1918 1615 131211109 8 0Reset fi fi fi fi fi fi
fi fi fi fi 31 0Reset fi
31 0Reset fi 31 0Reset fi 31 0Reset fi
31 30 0Reset fi 31 0Reset fi fi fi fi fi fi
313029 201918 17 10Reset fi fi fl fl fi fi fi
31 0Reset fi fi fi fi fi fi 3130 29 0Reset
3130 29 0Reset 3130 29 0Reset fi fi
3130 29 0Reset fi fi 3130 0Reset
fi fi • • • fi• fi • fi fi • • fl fl• fi
fi fi fi fi fi fi • fi fi fi fi • fi fi fifi fi fi fi • fi
• fi • fl• • • fl fi
fi fi fi
fi fi fi fi fi fi
fi 31 0Reset fi 31 30 1615 0Reset fi fi
31 0Reset fi 31 30 1615 0Reset fi fi
31302928 270Reset fi fi fi fi fi 31 0Reset
31 1615 0Reset 31 0Reset 31 1615 0Reset
3130 29 0Reset fl 3130 29 0Reset fl
3130 29 0Reset fi fl fi 3130 29 0Reset fi fl fi
3130 29 0Reset fl 3130 29 0Reset fl
3130 29 0Reset fi fl fi 3130 29 0Reset fi fl fi
3130 0Reset fi
• fi • fi • • fi • fi fi fi
fi fl fi fi fi fi fi fi fi fi fi • • •
• • • • • • • fi fi fi fi fi fi fi • • • • •
fi fi • • • • fifi
fi • fi• fi • fi • fi • • • • fi fi fi fi fi fi • • fi fi
fi • • fi • fi • fi fi fi • fi • fi • fi • fi fi • • • fi fi • fi •
fi • fi fi fi fi fi•
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fi fi • fl − − • fl fi fi fi fi fi • • fi fi fi • • fi • fi • fi fi fi
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fi• • • • fi • fl − − • fl
fi fi fi fi fi fi fi fi fi fi fi fi fi fl
fi fi fi fi fi fi fi fi fi fi
fi fi fi fi
fi fi fi fi
fi fi fi 31 2423 1615 8 7 543 0Reset fi fi fi fi fi fi fi
fi fi 31 1615 87 0Reset fi fi
31 0Reset fi 31 43 0Reset fi fi fi fi fi fi fi fi fi
31 0Reset fi 31 0Reset fi
31 30 87 0Reset fi fi
31 2423 1615 87 0Reset fi fi fi fi
31 0Reset fi 31 0Reset fi 31 0Reset
31 10Reset fi
31 210Reset fl fl fl fi fl 31 10Reset fi
31 2827 0Reset
31 1312 11 109876543210Reset fi fi fi fi fi
fi fi fi fi fi fi
31 0Reset fi 31 0Reset fi
31 0Reset fi 31 0Reset fi
31 0Reset fi 31 0Reset fi
31 0Reset fi 31 0Reset fi 31 0Reset
31 0Reset 31 0Reset fi 31 0Reset fi
31 0Reset
31 109876543210Reset
31 109876543210Reset
31 109876543210Reset
31 210Reset fi fi
31 210Reset fi fi 31 0Reset
31 0Reset 31 0Reset 31 0Reset
31 0Reset 31 210Reset
31 0Reset 31 210Reset
31 65 0Reset 31 0Reset
31 0Reset 31 21 0Reset
31 65 0Reset fi 31 0Reset fi
31 0Reset fi 31 21 0Reset fi
31 10Reset fi 31 2827 0Reset
fi • • • ∼
Message0Message1Message15...LP_INTR_CtrlAPB...HP_INTR_CtrlLP MailBoxBUSHP CPUHP CPULP CPUMB_LP_INTRMB_HP_INTRLP_INTR_MAPINTR_Matrixcore0_intr_vectorcore1_intr_vectorlpcore_intr_vector ∼ • •
fi • ∼• • • • • fi fi
• fi fi fi
fi 31 0Reset 31 0Reset
31 0Reset 31 0Reset 31 0Reset 31 0Reset
31 0Reset 31 0Reset 31 0Reset 31 0Reset
31 0Reset 31 0Reset 31 0Reset 31 0Reset
31 0Reset 31 0Reset 31 10Reset fi
31 161514131211109876543210Reset
31 161514131211109876543210Reset
31 161514131211109876543210Reset
31 161514131211109876543210Reset
31 161514131211109876543210Reset
31 161514131211109876543210Reset
31 161514131211109876543210Reset
31 161514131211109876543210Reset
• fl •
µ fi fi • fi fl fi fi • fi
fi • • • fi • • fi
fi fi • •
fi fi fi fi
fi fi fi fi fi
fi
3130292827 1817 876 5 0Reset fi fl fi fi fi fi fi fi
fi 31 30 0Reset fi 31 3029 26 25 0Reset fi
31 0Reset fi 31 30 0Reset 31 30 0Reset
31 30 0Reset 31 30 0Reset 31 30 0Reset
31 30 0Reset 31 30 0Reset 31 30 0Reset
3130 0Reset fi fi fi
fi • •
• fi • fi fi fi
• • • • •
fi fi 12 fi
fi fi fi fi fi 1 2 fi fi fi
fi fi fi
fi • •
X Y X X = X1||X2|| · · · ||Xn−1||Xn X1, X2, · · · , Xn−1 Xn = 0 X X 0 < <= 127 fi X∗n X∗n= Xn||0128− X X1||X2|| · · · ||Xn−1||X∗n X||0128− • •
32 128 32 128 P C P C · · · fi fi fi • • fi • • fi • • •
fi • • fi • • • • • H J0 T0
AAD C P 232− 1 AAD C P 232− 1 H AAD
32 J0 P C J0 T0 T0 t fi T fi H fi H K0128 fi H fi fi J0J0 J0 fi J0 fi fi t 1 <= t <= 128• t = 128 T0 fi fi • 1 < = t < 128 t fi T0 tT0 t fi T0 4 5 t
AAD P C T0 fi• fi C C • C fi fi • • • fi
• fi [pseudobase, pseudobase + (2pseudoinc− 1)] fi fi • fi
fi fi fi fi fi fi fi fi
fi 31 0Reset 31 0Reset 31 0Reset
31 5432 0Reset fi fi 31 10Reset fi
31 10Reset fi 31 32 0Reset fi 31 0Reset
31 10Reset fi 32 128 31 0Reset 31 76 0Reset
31 10Reset fi 31 10Reset fi 31 10Reset fi
31 10Reset fi 31 109 76 54 10Reset fi fi fi fi
31 21 0Reset 31 10Reset fi
31 10Reset fi 31 10Reset fi 31 2827 0Reset
• fi fi • • • fi y2= x3+ ax + b p• p • a b p• (x, y)
fi • fi y2= x3+ ax + b p• Y2= X3+ aXZ4+ bZ6 p fi (x, y) (X, Y, Z)• fi x = X/Z2 py = Y /Z3 p• fi X = xY = yZ = 1 D[255 : 0] D[n][31 : 0](n = 0, 1, · · · , 7) fiD[255 : 0] = D[7][31 : 0] , D[6][31 : 0], D[5][31 : 0], D[4][31 : 0], D[3][31 : 0], D[2][31 : 0], D[1][31 : 0], D[0][31 : 0]
fi D[n][31 : 0](n = 0, 1, · · · , N − 1) 4 × n N • D[0] • D[1] 4• · · ·• D[N − 1] 4 × (N − 1) fi fi D[n][31 : 0](n = 0, 1, · · · , N − 1) 4 × n N • D[0] • D[1] 4• · · ·• D[N − 1] 4 × (N − 1) fi fi fi fi fi fi fi
fi fi fi fi fi fi fi fi fi fi fi fi
fi fi fi Q = (Qx, Qy) = (Jx, Jy, Jz) = k · (Px, Py)• (Qx, Qy) fi • (Jx, Jy, Jz) • Px Py k • Qx Qy Jx Jy Jz fi fi fi fi fi (Px, Py) • Px Py • fi fi fi fi fi fi fi (Px, Py) Q = (Qx, Qy) = (Jx, Jy, Jz) = k · (Px, Py)• (Qx, Qy) fi • (Jx, Jy, Jz) • Px Py k • fi Qx Qy Jx Jy Jz Q = (Qx, Qy, Qz) = k · (Px, Py, 1)
• (Qx, Qy, Qz) • • Px Py k • Qx Qy Qz R = (Rx, Ry) = (Jx, Jy, Jz) = (Px, Py, 1) + (Qx, Qy, Qz)• (Rx, Ry) fi • (Jx, Jy, Jz) • • Px Py Qx Qy Qz • Rx Ry Jx Jy Jz fi fi (Qx, Qy, Qz) • (Qx, Qy, Qz) • Qx Qy Qz • fi fi fi fi fi fi (Px, Py) Q = (Qx, Qy, Qz) = k · (Px, Py, 1)• (Qx, Qy, Qz)
• • Px Py k • fi Qx Qy Qz R = A + B N• fi • R = A − B N• fi • R = A · B N•
fi • R = A · B−1 N• fi • • • • • fi • fi
• fi fi fi fi fi fi • • • • fi
fi fi fi
fi fi fi
fi 31 10Reset 31 10Reset
31 10Reset 31 10Reset
313029 28 1098 543 210Reset fi fi fi fi
fi fi fi fi fi fi fi fi fi fi fi
31 10Reset fi 31 2827 0Reset
• • • • • • fl fi fi fi
• M • • • • fi
fi fi y y (y − 4) (y − 4) fi
fi m fi fi fi fi
fi m fi fi fi n >= 0 • fi • fi
• • fi fl m k k fim + 1 + k≡448(mod512) m fi
fi 0 0 0 fi
• fi fi fi fi • • fi • • • fi
fi fi fi fi fi fi
fi 31 10Reset fi 31 10Reset fi fi fi fi 31 10Reset
31 10Reset fi 31 10Reset fi 31 10Reset fi
31 10Reset fi 31 10Reset fi
31 10Reset 31 10Reset fi 31 10Reset fi
31 10Reset 31 43 0Reset fi 31 32 0Reset fi fi
31 0Reset fi 31 0Reset 31 10Reset fi
31 0Reset 31 0Reset 31 3029 0Reset
fi fl • • • • • fi fi
fi N = 32 × n fi b b = 232 b n =N32Z = (Zn−1Zn−2· · · Z0)bX = (Xn−1Xn−2· · · X0)bY = (Yn−1Yn−2· · · Y0)bM = (Mn−1Mn−2· · · M0)br = (rn−1rn−2· · · r0)b Zn−1· · · Z0 Xn−1· · · X0 Yn−1· · · Y0 Mn−1· · · M0 rn−1· · · r0 b Zn−1 Xn−1 Yn−1 Mn−1 rn−1 fi Z X Y M Z0 X0 Y0 M0 r0 fi fi R = bn r r = R2 M M′ M′= − M−1 b M−1 M Z = XY M X Y M r M′ N = 32 × n n ∈ {1, 2, 3, . . . , 128} Z X Y M r N M′ fi fi (N32− 1) M′ fi
Xi Yi Mi ri i ∈ {0, 1, . . . , n − 1} b fi fi Zi i ∈ {0, 1, . . . , n − 1} Xi ri Z = X × Y M r M′ N = 32 × n n ∈ {1, 2, 3, . . . , 128} fi fi fi (N32− 1) M′ Xi Yi Mi ri i ∈ {0, 1, . . . , n − 1} b fi fi Zi i ∈ {0, 1, . . . , n − 1}
Xi Yi Mi M′ ri Z = X × Y Z X Y N = 32 × n n ∈ {1, 2, 3, . . . , 64} ˆN Z 2 × N fi (ˆN32− 1) (N16− 1) Xi Yi ∈ {0, 1, . . . , n − 1} b fi n N32 Xi i ∈ {0, 1, . . . , n − 1} i Yi i ∈ {0, 1, . . . , n − 1} i n + i 4 × (n + i) Zi i ∈ {0, 1, . . . , ˆn − 1} ˆn 2 × n Xi Yi fi fi fi
fi fi Z = XY M fi Y fi Y Y = (eYN−1eYN−2· · ·eYt+1eYteYt−1· · ·eY0)2• N Y •eYt •eYN−1eYN−2 eYt+1 • eYt−1eYt−2 eY0 m tm eYt−1eYt−2, · · · ,eY0 t − m fi • fi eYi i > α α fi α N α t eYN−1eYN−2 eYt+1 α t Z = XY M • fi Y fi • Z = XY M• N • Y • X M
• α fi Z = XY M 174.7 × 106 1.023 × 106 0.546 × 106 0.540 × 106 • fi • fi • fi • fi
fi fi fi fi fi fi fi
fi 31 0Reset M′ 31 76 0Reset fi 31 10Reset fi
31 10Reset fi 31 10Reset fi 31 10Reset
31 10Reset fi 31 10Reset fi 31 1211 0Reset fi fi fi
31 10Reset fi 31 10Reset fi 31 10Reset
31 10Reset 31 10Reset 31 3029 0Reset
fi • • • • • •
• fi fi fi fi fi fi fi
M m M • k k m + 1 + k ≡ 448 mod m • k k m + 1 + k ≡ 896 mod m N • N M(1) M(2) M(N) fi i (i)0 (i)1 (i)15 (i)0 (i)1 (i)15 • N fi i (i)0 (i)1 (i)15 fi fi (i)0 fi fi (i)15
(0) t t tt t t fi t• 1 < = t <= 9 tlength = 7′h48 tstring 8′h30 + 8′ht01′b1 23′b0 t0= t t0 tstring 32′h38800000• 10 < = t <= 99 tlength = 7′h50 tstring 8′h30 + 8′ht18′h30 + 8′ht01′b1 15′b0 t0= t10 t1= t/10 t0 t1 tstring 32′h35368000• 100 < = t < 512 tlength = 7′h58 tstring 8′h30 + 8′ht28′h30 + 8′ht18′h30 + 8′ht01′b1 7′b0 t0= t10 t1= ( t/10) 10 t2= t/100 t0 t1 t2 tstring 32′h32333180
M fi • fi • 1• fi fi • fi 2 • 3 • • •
• fi 1• • • 3 • • • • fi •
• • fi • fi fi fi • M • fi • • •
• • fi fi fi • M • • • •
fi fi fi t roundup(t/32) • fi • • •
• fi • fi fi
fi fi
fi 31 43 0Reset fi 31 0Reset fi
31 65 0Reset fi 31 65 0Reset fi 31 10Reset 31 10Reset
31 10Reset 31 10Reset 31 10Reset
31 10Reset 31 10Reset 31 3029 0Reset 31 10Reset fi
31 10Reset fi 31 10Reset fi 31 0Reset 31 0Reset
fi RSADSKEY RSADSKEY • Z = XY M • fl RSADSKEY • • RSADSKEY HMACKEY Z = XY M Z X Y M fl RSADSKEY • HM ACKEY RSADSKEY
• RSADSKEY X Z fi • s s • xs s s x x s x [Y ]4096 8 [x]t (s − t) s fi [x]s 8= 0000010116= 0000010100000000 16= 0000000000000101 8= 0001001116= 0001001100000000 16= 0000000000010011• Y M r M′ Y M Y M r M′ C C C Z = XY M N = 32 × x x ∈ {1, 2, 3, . . . , 128} Z X Y M r N M′ fl
[C ]12672[C ]12672RSA signature calculationMD checkInvoke SHA256 to calculate CALC_MDCBC decryptionZXXHardware levelCBC encryptionMake Y, M, DSA_KEY and IV readyCalculate and M’Extend Y, M, Build [P ]12672Invoke SHA256 to calculate MDSoftware level153246789101112¯rDerive Y, M, M’, , ... from [P ]12672¯r¯r fi C • Y M fi[L]32=N32−1 [L]32 32 [RSADSKEY]256 RSADSKEY [HM ACKEY ]256 1256 RSADSKEY [IV ]128 • r M′ M • Y M r [Y ]4096 [M ]4096 [r]4096 Y M r • [MD]256 [Y ]4096||[M]4096||[r]4096||[M′]32||[L]32||[IV ]128• [P ]12672 [Y ]4096||[M]4096||[r]4096||[Box]384 [Box]384 [MD]256||[M′]32||[L]32||[β]64) [β]64 []64 [β]64 P
• C [C]12672 [P ]12672 [RSA DSKEY ]256 [IV ]128 C C [C]12672[bY ]4096||[cM]4096||[br]4096||[dBox]384 [bY ]4096 [cM]4096 [br]4096 [dBox]384 C [Y ]4096 [M ]4096 [r]4096 [Box]384 C X IV C P CRSADSKEYIV IV[IV]128 fi [RSA DSKEY ]256• HM ACKEY • RSADSKEY P [Y ]4096 [M ]4096 [r]4096 [M′]32 [L]32 [β]64 • [CALCMD]256[CALCMD]256 [M D]256 [CALCM D]256 [MD]256 • [β]64 [β]64 X Y M r M′ XY M fi L Z Z = XY M •
• • fi fi fi fi • • • • • • fi C X IV RSADSKEY HMACKEY C X IV • RSADSKEY fi fi • fi RSADSKEY RSADSKEY
fi RSADSKEY • fi RSADSKEY • • RSADSKEY IV IV X Xii ∈ {0, 1, . . . , n − 1} n =N32 b fi fi X N C C • bYii ∈ {0, 1, . . . , 127} • cMii ∈ {0, 1, . . . , 127} • brii ∈ {0, 1, . . . , 127} • dBoxii ∈ {0, 1, . . . , 11} b fi • Z
• Z • Z • Z Zii ∈ {0, 1, . . . , n − 1} n =N32 Z
r
RSADSKEY fi fi RSADSKEY fi
31 10Reset fi 31 10Reset fi
31 10Reset fi 31 10Reset 31 43 0Reset fi RSADSKEY
31 210Reset 31 210Reset RSADSKEY
31 0Reset fi 31 3029 0Reset
fi fi fi fi • fi• fi fi • fi fi • fi fi fi fi • p fi fi fi fi fi a b
G n G • fi fi fi• p• fi a b• G n • d n • • • Q Q = dG • Q Qx Qy m e e z z Ln e Ln n k n n
x y kG r x n r k s k−1 (z + d ∗ r) n s k r s m r s fi fi fi Q m r s e e z z Ln e Ln n fi r s n n r s u1= z ∗ s−1 n u2= r ∗ s−1 n (x1, y1) = u1∗ G + u2∗ Q G Q r = x1 n r x1 n fi fi
fi fi fi fi
fi D[255 : 0] D[n][31 : 0](n = 0, 1, · · · , 7) fiD[255 : 0] = D[7][31 : 0] , D[6][31 : 0], D[5][31 : 0], D[4][31 : 0], D[3][31 : 0], D[2][31 : 0], D[1][31 : 0], D[0][31 : 0] fi D[n][31 : 0] 4 × n • D[0] • D[1] • · · ·• D[7] fi
fi D[n][31 : 0] 4 × n • D[0] • D[1] • · · ·• D[7] M LM M LA LA LM+ 1 + LA≡ 448 mod LM N M(1) M(2) M(N)
fi • • fi fi • • fi fi fi fi • •
• IDLEYesNoPOSTGAINPREPLOADPROCSignatureVerification? fi
d fi fi fi fi fi z fi fi fi fi z • z z • z fi • fi r s Qx Qy • fi
• fi fi Key[255 : 0] Key[255 : 224] Key[31 : 0] fi fi • • fi • • rs • Qx Qy z
• 1• fi • fi 2 • • • • • fi
0123HP_SYS_CLKRST_REG_CRYPTO_CLK_SRC_SELXTAL_CLKRC_FAST_CLKREF_240M_CLKclk_sec_oriclk_aesCGHP_SYS_CLKRST_REG_CRYPTO_AES_CLK_ENclk_shaCGHP_SYS_CLKRST_REG_CRYPTO_SHA_CLK_ENclk_hmacCGHP_SYS_CLKRST_REG_CRYPTO_HMAC_CLK_ENCGclk_ecdsaCGHP_SYS_CLKRST_REG_CRYPTO_ECDSA_CLK_ENclk_eccHP_SYS_CLKRST_REG_CRYPTO_ECC_CLK_ENCPLL_CLKCLK_DIVHP_SYS_CLKRST_SEC_DPA_CFG_SEL • • • • fi fi fi CGsystem_apb_clkHP_SYS_CLKRST_REG_CRYPTO_SEC_CLK_ENclk_apb_ecdsaCGHP_SYS_CLKRST_REG_CRYPTO_ECDSA_CLK_EN fi fi
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31 10Reset fi 31 43210Reset
31 43210Reset 31 43210Reset
31 43210Reset 31 21 0Reset
31 10Reset 31 10Reset fi 31 0Reset
31 0Reset 31 0Reset 31 0Reset 31 0Reset
31 0Reset 31 0Reset 31 0Reset 31 0Reset
31 0Reset 31 0Reset 31 0Reset
31 43 0Reset fi 31 10Reset fi fi 31 10Reset fi
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• • • Y = (0.299 × R) + (0.587 × G) + (0.114 × B)U = (−0.1687 × R) + (−0.3313 × G) + (0.5 × B) + 128V = (0.5 × R) + (−0.4187 × G) + (−0.0813 × B) + 128
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31 26252423222120191817161514131211109876543210Reset
31 26252423222120191817161514131211109876543210Reset
31 26252423222120191817161514131211109876543210Reset
31 2928 2322 1716 11 10 0Reset
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31 302928 201918 1098 0Reset 31 0Reset
31 0Reset fi 31 0Reset fi 31 0Reset fi
31 0Reset fi 31 0Reset fi 31 0Reset fi
31 0Reset fi 31 0Reset fi 31 0Reset fi
31 0Reset fi 31 0Reset fi 31 0Reset fi
31 3029 2625 0Reset 31 242322 1615 0Reset
3130292826250Reset 31 0Reset 31 2928272625 0Reset
3130292827 2524 2221 1918 1615 0Reset 31 2423 0Reset 31 0Reset
31 0Reset 31 65 0Reset fi 2− 1 31 30 0Reset fi
31 2827 0Reset
fi fi SRM BLEND2D-DMASRM input SRM output BLEND0 input BLEND outputPPAaxi_infBLEND1 input
• • fi fi fi fi fi Addr Gento 2D-DMASRM Coordinate CalculationFIFO0FIFO1Bilinear InterpolationRXColor ModeConvertfrom 2D-DMAARGB8888TXFIFOReorder CTRLTX CTRLAddr Gento 2D-DMAto 2D-DMASRMCLUTCTRLCLUTCLUTCLUTCTRLfrom 2D-DMAfrom 2D-DMAAPBAPBRXColor ModeConvertRXColor ModeConvertBLENDCoreARGB8888ARGB8888TXFIFO TX CTRLto 2D-DMABLEND
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255-RAWPPA_SRM_RX_FIX_ALPHAPPA_SRM_RX_ALPHA_INVRAW Alpha10X01100011PPA_SRM_RX_ALPHA_MOD fi fi fi fi fi fi fi fi fi • Y U Vfull Y UVlimit Ylimit=220256Yfull+ 16 Ulimit=225256Ufull+ 16 Vlimit=225256Vfull+ 16• Y U Vlimit R =298256Ylimit+409256Vlimit−56906256 G =298256Ylimit−100256Ulimit−208256Vlimit+34707256
B =298256Ylimit+516256Ulimit−70836256• Y U Vlimit R =298256Ylimit+459256Vlimit−63367256 G =298256Ylimit−55256Ulimit−136256Vlimit+19681256 B =298256Ylimit+541256Ulimit−73918256 fi fi fi fi • Y U Vlimit Y UVfull Yfull=298256Ylimit+4768256 Ufull=291256Ulimit+4550256 Vfull=291256Vlimit+4550256• Y U Vlimit Ylimit=4096256+66256R +129256G +25256B Ulimit=32768256−38256R −74256G +112256B Vlimit=32768256+112256R −94256G −18256B• Y U Vlimit Ylimit=4096256+47256R +157256G +16256B Ulimit=32768256−26256R −86256G +112256B Vlimit=32768256+112256R −102256G −10256B fi fi fi GRAY =R∗P P ARGB2GRAY R+G∗P P ARGB2GRAY G+B∗P P ARGB2GRAY B256 fi fi fi fi
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fi fi fi fi fi fi fi fi Xmiddle Ymiddle fi
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fi fi fi fi fi fl • •
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fi fi fi fi • fi 2× 12× fi fl • fi fi fi fi fi • • fi fi 2× 12×
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31 10Reset 31 8 7 210Reset
31 8 7 54321 0Reset fl 31 210Reset fi fi
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31 2423 0Reset 3124230Reset 31 2423 0Reset
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P eriod = (M CP W M T IMERP ERIOD + 1) × TP T clk
P eriod = (2 × MCP W M T IM ERP ERIOD) × TP T clk
fi fi P eriod = (2 × MCP W M T IM ERP ERIOD) × TP T clk
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fi fi fi
31 5432 10Reset fi fi fi fi
31 210Reset 31 9876543210Reset fi fi fi
31 654 210Reset fi fi fi fi
31 0Reset fi 31 13121110 32 10Reset fi fi fi fi fi
31 0Reset 31 3210Reset
31 876543210Reset fi fi fi fi fi
fi fi fi
31 3029282726252423222120191817161514131211109876543210Reset
31 3029282726252423222120191817161514131211109876543210Reset
31 3029282726252423222120191817161514131211109876543210Reset
31 3029282726252423222120191817161514131211109876543210Reset
31 3029282726252423222120191817161514131211109876543210Reset fi fi fi fi fi fi
fi fi fi fi fi fi fi
fi fi fi fi fi fi fi fi
fi fi fi fi fi fi fi fi fi
31 6543210Reset fi fi
31 222120191817161514131211109876543210Reset fi fi fi fi fi fi
fi fi fi fi fi fi fi
fi fi fi fi fi fi fi fi fi
31 1615 0Reset fi 31 1615 0Reset fi 31 10Reset fi
3128270Reset
fi • • • •
• fi Same as TX Channel nRMT_REF_CNT_RST_CHnRMT_DIV_CNT_CHnmem_rdatanRMT_CARRIER_EN_CHnRMT_CONTI_MODE_CHnRMT_TX_LIM_CHnRMT_TX_WRAP_EN_CHnTX Channel nblock2...block3block7block1block0RAM RMT_MEM_SIZE_CHn/mRMT_MEM_RD_RST_CHnRMT_MEM_WR_RST_CHmTX Channel 0mem_wdatarmt_sclkmem_rdnmem_wr4clk_divCarrier_GeneratorRMT_IDLE_OUT_EN_CHnsig_outRMT_CARRIER_HIGH_CHnRMT_CARRIER_LOW_CHnRMT_CARRIER_OUT_LV_CHnModulator0 1 CK Div Counter CLRFSMtx_enFlip_FlopDENRMT_IDLE_OUT_LV_CHn1 0 ComparatorperiodlevelDetect_Edge 0 1 1 0DemodulatorFilter RMT_CARRIER_EN_CH4RMT_CARRIER_HIGH_THRES_CH4RMT_CARRIER_LOW_THRES_CH4RMT_CARRIER_OUT_LV_CH4Receiverrmt_sclk RMT_RX_FILTER_EN_CH4CK Div Counter CLRFSMrx_enHP_SYS_CLKRST_RMT_CLK_DIV_NUMERATORHP_SYS_CLKRST_RMT_CLK_DIV_DENOMINATORHP_SYS_CLKRST_RMT_CLK_DIV_NUMFrac Divider(8 bits)PLL_F80M_CLK RC_FAST_CLK Clock2 10 XTAL_CLK HP_SYS_CLKRST_RMT_CLK_SRC_SEL HP_SYS_CLKRST_RMT_CLK_ENAPB BUSSame as RX Channel 4RX Channel msig _inclk_divTransmittermem_wrmmem_rdata0mem_rd0RMT_RX_FILTER_THRES_CH4RX Channel 4GDMA TX INFGDMA RX INFModulator • • • •
• • fi 5 × Tapbclk+ 6 × Trmtsclk< period × Tclkdiv 1.5 × Tapbclk< 9 × Trmtsclk period × Tclkdiv • (5 × Tapbclk+ 6 × Trmtsclk)• × Tclkdiv (215− 1)× Trmtsclk×
fi • • fi fi fl fi fi fl fi • • fi • •
fi fi fi fi fi fi
fi fi fi fi • fi • fi fi fi fi •
• • fi • fi 10 × Tapbclk+ 19 × Trmtsclk< period × Tclkdiv fi fi fi • • fi
fi fi fi fi fi fi fi fi fi fi • • fi fi fi fi fi fi
fi fi • • • • • fi
• fi • • • fi fi fi fi
fi fi fi fi fi fi fi fi fi fi fi fi fi fi
fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi
fi 31 0Reset 31 0Reset
31 2625242322212019 1615 876543210Reset fi fi fi fi fi fi fi fi fi fi
fi fi fi fi fi fi fi fi fi
31 30292827 242322 87 0Reset fi fi fi fi fi fi fi fi
31 1615141312 543210Reset fi fi fi fi fi fi fi fi fi
31 1615 0Reset fi fi 31 30 272625 2423 1817 1211 43210Reset fi fi
31 876543210Reset fi fi
31 27262524 222120 11109 0Reset fl
31 2827262524 222120 11109 0Reset fi fi fi fl
31 3029282726252423222120191817161514131211109876543210Reset
31 3029282726252423222120191817161514131211109876543210Reset
31 3029282726252423222120191817161514131211109876543210Reset
31 3029282726252423222120191817161514131211109876543210Reset 31 1615 0Reset fi fi
31 2221201918 98 0Reset fi fi fi fi fi
31 543210Reset fi fi 31 98 0Reset fi 31 2827 0Reset
fl fi fi
• • fi • • • fi fi • fi fi
RegisterGroupClockGeneratorXTAL_CLKPLL_F160M_CLKRC_FASK_CLKRX FIFOControl//TX FIFOControl//IOBus////RX FIFO_infTX FIFO_infRX FIFOTX FIFORXDPAD_CLK_RXPAD_CLK_TXCLK_TX_outTXDAXIPARLIO//CLK_TXCLK_RX//GDMA_push_inf//GDMA_pop_infGDMAClock DomainsCLK_RX_outRX CoreAPBTX Core fi fi fi
fi fi (28− 1) fi fi fi (28− 1) PLL_F160M_CLKXTAL_CLKRC_FAST_CLK PAD_CLK_RXDIVCLK_RX_inINVCLK_RX_out DIVCLK_TX_inCLK_TX_outINVHP_SYS_CLKRST_PARLIO_TX_CLK_SRC_SELRX_INV_OTX_INV_OClock GeneratorHP_SYS_CLKRST_PARLIO_RX_CLK_SRC_SELGateGateRX_Gate_EnTX_Gate_EnINVCLK_RX CLK_TXINVRX_INV_ITX_INV_I0123PLL_F160M_CLKXTAL_CLKRC_FAST_CLK PAD_CLK_TX0123 fi
fi fi fi • • • • • • fi • • • • • • • •
• • • fi fi
fi fi fi fi SW_ENABLE/Valid data/ Mode DescriptionSub-mode
fi • fi fi fi • fi fi • fi fi fi • fi fi fi fi (216− 1) fi fi fi
fi fi fi fi fi fi fi fi fi fi fi fi fi fl fi (219− 1)
(219− 1) fi • • fi fi fi fi {{b0, b1}, {b2, b3}, {b4, b5}, {b6, b7}} {{b6, b7}, {b4, b5}, {b2, b3}, {b0, b1}} • • fi
fi fi fi fi fi fi fi fi fi
fi fi fi fl • fi fi fi fi
fi fi fi fi fi fi • fi fi fi fi fi fi fi fi
fi fi fi fi fi fi fi fi fi fi fi fi fi
fi fi fi fi fi fi
fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi
fi 31 3029 27262524 21 20 0Reset fi fi fi fi fi
31 292827 9 8 0Reset fi fi fi
31302928 1312 11 0Reset fi fi fi fi fi 31 30 0Reset fi
31 292827 9 8 0Reset fi fi fi 31 30 0Reset fi
313029 1413 12 0Reset fi fi fi fi fi 3130 29 0Reset fi fi
31 30 0Reset fi fi 31 30 0Reset 31 3210Reset
31 3210Reset 31 3210Reset
31 3210Reset 31 1312 8 7 0Reset 31 13 12 0Reset
31 1312 6 5 0Reset 3130 29 0Reset fi fi
3130 29 0Reset fi fi 31 1615 0Reset fi fi
31 30 0Reset 31 2827 0Reset
fi fi • • • • fi • • • fi
• fi • • • • fi• • ChipProtective coverSubstrateElectrodeC Touch panel fi
fi fi fi fi
FrequencyMode 0 DBIAS 0DRV_HS 0DRV_LS 0DRES_LPF 0DCAP_LPF 0DCAP_DRV 0BUF_DRVEN_CALFrequencyMode 1DBIAS 1DRV_HS 1DRV_LS 1DRES_LPF 1DCAP_LPF 1DCAP_DRV 1BUF_DRVEN_CALFrequencyMode 2DBIAS 2DRV_HS 2DRV_LS 2DRES_LPF 2DCAP_LPF 2DCAP_DRV 2BUF_DRVEN_CALFREQ_SCAN_CNT_LIMIT012TouchChannel 0 EN_CHANNEL 0EN_BUF 0TouchPanel 0TouchChannel 1 EN_CHANNEL 1EN_BUF 1TouchPanel 1(……)TouchChannel 13EN_CHANNEL 13EN_BUF 13TouchPanel 13TouchSensor TOUCH_XPDTOUCH_OUT fi fi Ω Ω Ω Ω fi fi
CPUtouch_xpdtouch_outwakeupTimer SoftwareSCAN_CTRL WORK_UNITinterrupttouch_work_starttouch_work_doneFilterSCAN_CURtouch_meas_outupdate_cur_datatouch_filter_donetouch_filter_startfreq_cntTouch FSM ...Touch Sensor • •
• fi fi fi fi • fl TOUCH_OUTDIVdiv_num = LP_ANA_DIV_NUM[2:1]10AON_FAST_CLKLP_ANA_DIV_NUM[0]10LP_ANA_TOUCH_OUT_SELTOUCH_OUT_DIVCLK GATELP_ANA_TOUCH_OUT_GATEtouch_clktouch_data fi fi fi fi fi •
• fi fi fi fi fi
fi • • fi fi •
Touch 0Touch 1Touch 2StartTouch 13…samplesleep. . .samplesleepsamplesample • fi • fi
Touch 0Touch 1Touch 2StartTouch 13…Sleep. . .Freq 0 Freq 1 Freq 2 Freq 0 Freq 1 Freq 2 Freq 0 Freq 1 Freq 2 SleepFreq 0 Freq 1 Freq 2 Freq 0 Freq 1 Freq 2 SleepFreq 0 Freq 1 Freq 2 Sleep fi fi • • • • • • fi • fi •
fi fi fi fi fi fi fi fi fi fi fi fi • fi • fi • fi
• fi fi fi• fi fi fi fi • fl fi • fl fi fi fi fi fi
• fi 2• fi • fi fi fi • fi • fi • fi • fi
fi • fi • fi • fi • fi fi fi • fi • fi fi
fi fi fi fi
fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi
fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi
fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi
fi 31 76543210Reset
31 76543210Reset
3176543210Reset
31 76543210Reset
31 2019 161514 0Reset 31 2322 1918 1615 0Reset touchsmoothdata < benchmark − passivenoisethreshold
31 2322 1918 1615 0Reset touchsmoothdata < benchmark − passivenoisethreshold 31 2423 1615 87 0Reset
31 2524 2322 1817 1312 98 76 0Reset 31 3029 1514 0Reset
31 30 0Reset fi fi fi 31 3029 2019 109 0Reset fi fi fi
31 1716 210Reset fi fi fi fi
31 3029 282726 232221 6 5 21 0Reset fi fi fi fi fi fi fi
31 2827262524 2221 1918 16 15 0Reset fi fi fi fi fi fi fi fi fi fi fi fi fi
31 3029 2019 109 0Reset fi fi fi
31 2928 2120 171615 1312 98 76 54 32 10Reset fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi
313029 15 14 0Reset fi fi fi
31 2322 1918 171615 0Reset fi fi fi 31 2120 171615 0Reset fi fi fi
31 1615 0Reset fi fi 31 161514 0Reset
31 131211 87 43 0Reset fi fi fi fi fi fi fi fi
31 242322 1817 1312 98 76 0Reset fi fi fi fi Ω Ω Ω Ω fi fi fi fi fi fi fi
31 242322 1817 1312 98 76 0Reset fi fi fi fi Ω Ω Ω Ω fi fi fi fi fi fi fi
31 242322 1817 1312 98 76 0Reset fi fi fi fi Ω Ω Ω Ω fi fi fi fi fi fi fi
31 1514 1312 1110 432 0Reset fi fi fi fi fi
313029282726 1211 109 8 7 0Reset fi fi fi fi fi fi
fi fi 31 3029 1514 0Reset fi fi
31 16 15 0Reset fi 31 16 15 0Reset fi 31 16 15 0Reset fi
3130 0Reset fi
fi flSAR ADC Digital Controller Block DiagramAPB Bus ETM I/OADC Register Bank (adc_reg)CTRL · PATT_TAB · FSM_WAIT · FILTER · THRES · DMA_CONF · INT_* · CTRL_DATEetm_sar*_trigger / etm_sar*_stop → Trigger ControlTrigger ControlOFF / SCAN / SW / ETMPattern Table16-entry × 2SAR FSM ×2IDLE→XPD→RSTB→READData ProcessingArbiter + IIR ×2Threshold Monitor2 comparatorstrigger meas_start + channel 22-bit sample filtered dataAnalog SAR 1/2sar_clk / sar_valid / sar_dataDMA Controlasync FIFO + EOFPDMAin_push / in_push_datasar_xpden_paden_gndasar_validsar_datafilt data44-bit pktInterrupt Aggregator (INT_RAW / INT_ST / INT_ENA / INT_CLR)7 sources → adc_reg_intsar1_done / sar2_done thres0/1_high · thres0/1_lowfifo_overflowadc_reg_intBus Interface Register Bank Functional Block External Block Interrupt Agg Data Flow Config Path Int Source ETM Path • •
• • → → → • fi • • • fl• • fi
• fi• • • • • • • × • • •
• • • • fi ∼ fi 23 1817 1211 65 0 23 1817 1211 65 0 23 1817 1211 65 0 23 1817 1211 65 0
fi fi fi 5 210 fi fi fi ∼ • •
• • • → → → • • • • • • • • fi Tconv fi Tconv Tconv
• → fi ≈ × • fi Tconv 0ADC_XPD_WAIT = 2, ADC_RSTB_WAIT = 1 (drawable stand-ins), CONTINUE_MODE_EN = 1, ADC_SAR1_PATT_TYPE = 0 (advance on done), triggered oncex axis is the ADC working clock; the waits count SAR conversions, T_conv compressed (24 clk real)5 10 15 20 25 3035 40clkSAR conversion(analog, free-running)shaded = sampling aperture (first 5 clk of the conversion)Sampling triggertrigger #1FSM stateIDLE XPD (2 conversions) RSTB (1 conversion) READ (one sample per T_conv, channel rolls)SAR powerSAR stays poweredChannelch[0] ch[1] ch[2] ch[3] ch[4] ch[5]Data updateSample data(invalid) s[0] ch[0] s[1] ch[1] s[2] ch[2] s[3] ch[3] s[4]start-up = (2 + 1 + 1) x T_convsteady state: one sample per T_conv, channel rollingXPD power-up wait RSTB wait (pure wait) READ (sampling) current channel SAR conversion + aperture data update pulse
0ADC_XPD_WAIT = 2, ADC_RSTB_WAIT = 1 (drawable stand-ins), CONTINUE_MODE_EN = 1, ADC_SAR1_PATT_TYPE = 1 (advance on start), triggered oncex axis is the ADC working clock; the waits count SAR conversions, T_conv compressed (24 clk real)5 10 15 20 25 3035 40clkSAR conversion(analog, free-running)shaded = sampling aperture (first 5 clk of the conversion)Sampling triggertrigger #1FSM stateIDLE XPD (2 conversions) RSTB (1 conversion) READ (one sample per T_conv, channel holds)SAR powerSAR stays poweredChannelch[0] (holds)Data updateSample data(invalid) sample[0] sample[1] sample[2] sample[3] sample[4]start-up = (2 + 1 + 1) x T_convsteady state: one sample per T_conv, channel holdingXPD power-up wait RSTB wait (pure wait) READ (sampling) channel (fixed ch[0]) SAR conversion + aperture data update pulse → → → ADC_SAR1_TRIGGER_MODE = 2 (SW), ADC_SAR1_CONTINUE_MODE_EN = 0; ADC_XPD_WAIT = 2, ADC_RSTB_WAIT = 1 (drawable stand-ins)x axis is the ADC working clock; the waits count SAR conversions, T_conv compressed (24 clk real)0 5 10 15 20 25 30 35 40 45clkSAR conversion(analog, free-running)shaded = sampling aperture (first 5 clk of the conversion)APB writeTRIGGER_STARTwrite 1 #1 write 1 #2FSM stateIDLE XPD (2 conversions) RSTB (1 conversion)READ (takes the sample) IDLE XPD (2 conversions) RSTB (1 conversion)READ (takes the sample)SAR powerSAR powers down in IDLE and must power up again for the next sampleChannelch[0] ch[1] ch[2]Data updateSample data(invalid) sample[0] (ch[0]) sample[1]per sample = (2 + 1 + 1) x T_convsoftware gapsameXPD power-up wait RSTB (channel settling) READ (sampling) current channel SAR conversion + aperture data update pulse fi fi fi fi ×
≈ fi × × ≈ × × × • • • • • fi • • fi •
• • fi fi fi fi fi • fi • • • • • • fi sumn= sumn−1−sumn−1k+ adcdinnfil tered datan=sumnk fi fi fi fi • • • •
fi fi fi• • • • fi • > • < fi • → • • fl
• • • • fl fi fl fl fl • • • • • •
• • • • • fi fi fi fi fl fl
fi fi fi fi fi
31 2827 262524232221 1817 1413 43 210Reset fi fi fi fi fi fi
31 2827 262524232221 1817 1413 43 210Reset fi fi fi fi fi fi
3125242312110Reset fi fi 31 2928 2625 0Reset fi fi fi k fi k k k k k k fi fi fi
31 87 43 0Reset fi Tconv fi Tconv 31 2928 0Reset
31 2928 0Reset 31 2423 0Reset fi 31 2423 0Reset fi
31 2423 0Reset fi 31 2423 0Reset fi 31 2423 0Reset fi
31 2423 0Reset fi 31 2423 0Reset fi 31 2423 0Reset fi
3130 2423 1918 1413 0Reset fi fi fi fi fi 31 2221 0Reset
31 2221 0Reset 31 1716 0Reset fi 31 1716 0Reset fi
31 654 0Reset fi fi 31 1716 0Reset fi 31 1716 0Reset fi
31 654 0Reset fi fi 31 282726 0Reset fi
3130292827262524 0Reset
3130292827262524 0Reset
3130292827262524 0Reset
3130292827262524 0Reset 3130 171615 0Reset fi fi
3130 0Reset fi
• • • • fi
fi • • • • fi • fi
fi • fi • fi
• fi • • µ• fi fi fi fi • • •
fi • • • →
• • • • • fi • • • fi
• fi • fi fi fi fi fi fi fi
fi fi fifi fi
fi fi fi fi fi
fi fi 3130 2827 201918171615 1211 87 43 0Reset fi fi fi fi
fi fi fi fi fi fi fi fi
31 0Reset fi fi 31 1615 0Reset fi 31 1615 0Reset fi
31 9876543210Reset
31 9876543210Reset
31 9876543210Reset
31 9876543210Reset
31 0Reset 31 0Reset 31 0Reset
31 0Reset 31 0Reset 31 0Reset
31 3210Reset
31 9876 432 0Reset fi fi fi × × fi fi
31 10Reset 31 292827 0Reset fi
• • • • fi •
• fi • • • fifi• fi • • fi • • • • • • • • • • fi
•
fl fi fi fi fi fi
fi • • • • • • • • • • • • • • • • • • • • • fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi
fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi
fi fi fi fi fi fi fi fi fi fi fi fi fi 31 2019 16 15 210Reset • fi fi fi fi • fi fi
fi fi fi • fi • • fl fi fi • fi
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