1 Module Overview 1.1 Features 1.2 Series Comparison 1.3 Applications 2 Block Diagram 3 Pin Definitions 3.1 Pin Layout 3.2 Pin Description 4 Boot Configurations 4.1 Chip Boot Mode Control 4.2 Secure Debug Controller (SDC) 4.3 ROM Messages Printing Control 4.4 JTAG Signal Source Control 4.5 Chip Power-up and Reset 5 Peripherals 5.1 Peripheral Overview 5.2 Peripheral Description 5.2.1 Image and Voice Processing 5.2.1.1 JPEG Codec 5.2.1.2 Pixel-Processing Accelerator (PPA) 5.2.1.3 Audio Sample Rate Converter (ASRC) 5.2.1.4 CORDIC Accelerator (CORDIC) 5.2.1.5 LCD and Camera Controller (LCD_CAM) 5.2.2 Connectivity Interface 5.2.2.1 UART Controller (UART) 5.2.2.2 SPI Controller (SPI) 5.2.2.3 I2C Controller (I2C) 5.2.2.4 I2S Controller (I2S) 5.2.2.5 Pulse Count Controller (PCNT) 5.2.2.6 USB 2.0 High-Speed OTG 5.2.2.7 USB Serial/JTAG Controller (USB_SERIAL_JTAG) 5.2.2.8 Ethernet Media Access Controller (EMAC) 5.2.2.9 CAN FD Controller 5.2.2.10 SD/MMC Host Controller (SDHOST) 5.2.2.11 LED PWM Controller (LEDC) 5.2.2.12 Motor Control PWM (MCPWM) 5.2.2.13 Remote Control Peripheral (RMT) 5.2.2.14 Parallel IO Controller (PARLIO) 5.2.2.15 BitScrambler 5.2.3 Analog Signal Processing 5.2.3.1 Touch Sensor (TOUCH) 5.2.3.2 Temperature Sensor (TSENS) 5.2.3.3 ADC Controller (ADC) 5.2.3.4 DAC Controller (DAC) 5.2.3.5 Analog Voltage Comparator 6 Electrical Characteristics 6.1 Absolute Maximum Ratings 6.2 Recommended Operating Conditions 6.3 DC Characteristics (3.3 V, 25 °C) 7 Module Schematics 8 Peripheral Schematics 9 Module Dimensions 10 PCB Layout Recommendations 10.1 PCB Land Pattern 10.2 Module Placement for PCB Design 11 Product Handling 11.1 Storage Conditions 11.2 Electrostatic Discharge (ESD) 11.3 Reflow Profile 11.4 Ultrasonic Vibration Related Documentation and Resources Revision History PRELIMINARY ESP32-S31-WROOM-3 Datasheet Pre-release v0.1 2.4 GHz Wi-Fi 6, Bluetooth ® 5.4 (LE), Bluetooth ® Classic, Zigbee and Thread (802.15.4) module Built around ESP32-S31 series of SoCs, RISC-V 32-bit dual-core microprocessor 54 GPIOs, rich set of peripherals On-board PCB antenna ESP32-S31-WROOM-3 www.espressif.com 1 Module Overview 1 Module Overview Note: Check the link or the QR code to make sure that you use the latest version of this document: https://espressif.com/documentation/esp32-s31-wroom-3_datasheet_en.pdf 1.1 Features CPU and On-Chip Memory • ESP32-S31 embedded, RISC-V 32-bit dual-core microprocessor, up to 320 MHz • ULP-RISC-V coprocessor • 320 KB ROM • 512 KB shared SRAM • 32 KB low-power SRAM • Concurrent access to flash and PSRAM • PSRAM: Up to 32 MB (optional) Wi-Fi • 1T1R in 2.4 GHz band • Operating frequency: 2412 ~ 2484 MHz • Compliant with IEEE 802.11b/g/n/ax protocol: • 20 MHz and 40 MHz bandwidth • Data rate up to 150 Mbps • Supports key Wi-Fi 6 features such as OFDMA, MU-MIMO, and TWT • Four virtual Wi-Fi interfaces • Supports Station mode, SoftAP mode, Station + SoftAP mode, and promiscuous mode • Antenna diversity • 802.11mc FTM Bluetooth ® Bluetooth LE • Full support for the Bluetooth 5.4 (LE) core specification • Bluetooth Mesh 1.1 • LE Audio (Isochronous Channels, BIS and CIS) • Direction Finding (AoA/AoD) • Periodic Advertising with Responses (PAwR) • LE Connection Subrating • LE Power Control • Speed: 125 Kbps, 500 Kbps, 1 Mbps, 2 Mbps • LE Advertising Extensions and Multiple Advertising Sets • Simultaneous Operation of Broadcaster, Observer, Central, and Peripheral Devices Bluetooth Classic • Data rates: Basic rate 1 Mbps, Enhanced data rate 2 Mbps, 3 Mbps • Asynchronous connection-oriented (ACL) links, synchronous connection-oriented (SCO) and enhanced synchronous connection-oriented (eSCO) links • Channel Classification and adaptive frequency hopping (AFH) • Secure simple pairing (SSP) • Secure Connections Espressif Systems 2 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 1 Module Overview IEEE 802.15.4 • Compliant with IEEE 802.15.4-2015 protocol • OQPSK PHY in 2.4 GHz band • Data rate: 250 Kbps • Thread 1.4 • Zigbee 3.0 • Matter • Application-layer protocols (HomeKit, MQTT, etc.) Peripherals • UART, SPI, I2C, I2S, Pulse Counter Controller, USB 2.0 High-Speed OTG, USB Serial/JTAG Controller, Ethernet Media Access Controller, Two-Wire Automotive Interface, SD/MMC Host Controller, LED PWM Controller, Motor Control PWM, Remote Control Peripheral, Parallel IO Controller, Touch Sensor, Temperature Sensor, ADC Controller, DAC Controller, Analog Voltage Comparator, General-Purpose Timer, System Timer, Watchdog Timer Integrated Components on Module • 40 MHz crystal oscillator • Up to 32 MB SPI flash (optional) Antenna Options • On-board PCB antenna Operating Conditions • Operating voltage/Power supply: 3.0 ~ 3.6 V • Operating ambient temperature: –40 ~ 85 °C 1.2 Series Comparison ESP32-S31-WROOM-3 modules are powerful, generic Wi-Fi, Bluetooth ® 5.4 (LE), Bluetooth ® Classic and IEEE 802.15.4 MCUs that have a rich set of peripherals. They are an ideal choice for a wide variety of application scenarios related to Internet of Things (IoT), such as embedded systems, smart home, wearable electronics, etc. ESP32-S31-WROOM-3 comes with a PCB antenna. The ordering information for the modules is as follows: Table 1-1. ESP32-S31-WROOM-3 (ANT) Series Comparison Embedded Ambient Size 2 Part Number Flash PSRAM Chip Temp. 1 (°C) (mm) ESP32-S31-WROOM-3-N8R16V 8 MB (Quad SPI) 16 MB (Octal SPI) ESP32-S31NRV16 –40 ~ 85 22.0 × 30.0 × 3.5 ESP32-S31-WROOM-3-N16R16V 16 MB (Quad SPI) ESP32-S31-WROOM-3-N32R16V 32 MB (Quad SPI) 1 Ambient temperature specifies the recommended temperature range of the environment immediately outside the Espressif module. 2 For details, refer to Section 9 Module Dimensions. At the core of the modules is ESP32-S31, RISC-V 32-bit dual-core microprocessor that operates at up to 320 Espressif Systems 3 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 1 Module Overview MHz. You can power off the CPU and make use of the low-power coprocessor to constantly monitor the peripherals for changes or crossing of thresholds. 1.3 Applications • Smart Home • Industrial Automation • Health Care • Consumer Electronics • Smart Agriculture • POS Machines • Service Robot • Audio Devices • Generic Low-power IoT Sensor Hubs • Generic Low-power IoT Data Loggers • Cameras for Video Streaming • USB Devices • Speech Recognition • Image Recognition • Wi-Fi + Bluetooth Networking Card • Touch and Proximity Sensing Espressif Systems 4 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY Contents Contents 1 Module Overview 2 1.1 Features 2 1.2 Series Comparison 3 1.3 Applications 4 2 Block Diagram 9 3 Pin Definitions 10 3.1 Pin Layout 10 3.2 Pin Description 10 4 Boot Configurations 14 4.1 Chip Boot Mode Control 15 4.2 Secure Debug Controller (SDC) 16 4.3 ROM Messages Printing Control 16 4.4 JTAG Signal Source Control 17 4.5 Chip Power-up and Reset 17 5 Peripherals 19 5.1 Peripheral Overview 19 5.2 Peripheral Description 19 5.2.1 Image and Voice Processing 19 5.2.1.1 JPEG Codec 19 5.2.1.2 Pixel-Processing Accelerator (PPA) 20 5.2.1.3 Audio Sample Rate Converter (ASRC) 21 5.2.1.4 CORDIC Accelerator (CORDIC) 22 5.2.1.5 LCD and Camera Controller (LCD_CAM) 22 5.2.2 Connectivity Interface 23 5.2.2.1 UART Controller (UART) 23 5.2.2.2 SPI Controller (SPI) 23 5.2.2.3 I2C Controller (I2C) 26 5.2.2.4 I2S Controller (I2S) 26 5.2.2.5 Pulse Count Controller (PCNT) 27 5.2.2.6 USB 2.0 High-Speed OTG 28 5.2.2.7 USB Serial/JTAG Controller (USB_SERIAL_JTAG) 29 5.2.2.8 Ethernet Media Access Controller (EMAC) 29 5.2.2.9 CAN FD Controller 31 5.2.2.10 SD/MMC Host Controller (SDHOST) 32 5.2.2.11 LED PWM Controller (LEDC) 32 5.2.2.12 Motor Control PWM (MCPWM) 33 5.2.2.13 Remote Control Peripheral (RMT) 33 5.2.2.14 Parallel IO Controller (PARLIO) 34 5.2.2.15 BitScrambler 35 Espressif Systems 5 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY Contents 5.2.3 Analog Signal Processing 35 5.2.3.1 Touch Sensor (TOUCH) 36 5.2.3.2 Temperature Sensor (TSENS) 36 5.2.3.3 ADC Controller (ADC) 37 5.2.3.4 DAC Controller (DAC) 37 5.2.3.5 Analog Voltage Comparator 38 6 Electrical Characteristics 39 6.1 Absolute Maximum Ratings 39 6.2 Recommended Operating Conditions 39 6.3 DC Characteristics (3.3 V, 25 °C) 39 7 Module Schematics 41 8 Peripheral Schematics 42 9 Module Dimensions 43 10 PCB Layout Recommendations 44 10.1 PCB Land Pattern 44 10.2 Module Placement for PCB Design 44 11 Product Handling 45 11.1 Storage Conditions 45 11.2 Electrostatic Discharge (ESD) 45 11.3 Reflow Profile 45 11.4 Ultrasonic Vibration 46 Related Documentation and Resources 47 Revision History 48 Espressif Systems 6 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY List of Tables List of Tables 1-1 ESP32-S31-WROOM-3 (ANT) Series Comparison 3 3-1 Pin Definitions 11 4-1 Default Configuration of Strapping Pins 14 4-2 Description of Timing Parameters for the Strapping Pins 15 4-3 Chip Boot Mode Control 15 4-4 UART0 ROM Message Printing Control 16 4-5 USB Serial/JTAG ROM Message Printing Control 17 4-6 JTAG Signal Source Control 17 4-7 Description of Timing Parameters for Power-up and Reset 18 6-1 Absolute Maximum Ratings 39 6-2 Recommended Operating Conditions 39 6-3 DC Characteristics (3.3 V, 25 °C) 39 Espressif Systems 7 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY List of Figures List of Figures 2-1 ESP32-S31-WROOM-3 Block Diagram 9 3-1 Pin Layout (Top View) 10 4-1 Visualization of Timing Parameters for the Strapping Pins 15 4-2 Visualization of Timing Parameters for Power-up and Reset 17 7-1 ESP32-S31-WROOM-3 Schematics 41 8-1 Peripheral Schematics 42 9-1 Physical Dimensions 43 10-1 Recommended PCB Land Pattern 44 11-1 Reflow Profile 45 Espressif Systems 8 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 2 Block Diagram 2 Block Diagram GND ESP32-S31 40 MHz Crystal 3V3 EN GPIOs Antenna QSPI Flash(opt.) SPICS0 SPICLK SPID SPIQ SPIHD SPIWP VDD_SPI PSRAM(opt.) RF Matching ESP32-S31-WROOM-3 Figure 2-1. ESP32-S31-WROOM-3 Block Diagram Espressif Systems 9 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 3 Pin Definitions 3 Pin Definitions 3.1 Pin Layout The pin diagram below shows the approximate location of pins on the module. For the actual diagram drawn to scale, please refer to Figure 9 Module Dimensions. Pin Layout (Top View) Keepout Zone Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 Pin 10 Pin 11 Pin 12 Pin 13 Pin 14 Pin 15 Pin 16 Pin 17 Pin 18 Pin 19 Pin 20 Pin 21 Pin 22 Pin 23 Pin 24 Pin 25 Pin 96 GND GND 3V3 3V3 EN IO2 IO3 IO0 IO1 IO4 IO5 IO6 IO7 IO8 IO9 IO10 IO11 IO12 IO13 IO14 IO15 IO16 IO17 IO18 IO19 GND Pin 26 Pin 27 Pin 28 Pin 29 Pin 30 Pin 31 Pin 32 Pin 33 Pin 34 Pin 35 Pin 36 Pin 37 Pin 38 Pin 39 Pin 40 Pin 41 Pin 42 Pin 43 Pin 44 Pin 45 Pin 46 Pin 47 GND SD_D0 SD_D1 SD_D2 SD_D3 SD_CLK SD_CMD NC NC NC NC NC NC NC USB_DP USB_DM IO33 IO34 IO35 IO36 IO37 GND Pin 97 GND Pin 48 Pin 49 Pin 50 Pin 51 Pin 52 Pin 53 Pin 54 Pin 55 Pin 56 Pin 57 Pin 58 Pin 59 Pin 60 Pin 61 Pin 62 Pin 63 Pin 64 Pin 65 Pin 66 Pin 67 Pin 68 Pin 69 Pin 70 Pin 71 Pin 72 GND IO38 IO39 IO40 IO42 IO43 IO44 IO45 IO46 IO47 IO48 IO49 IO50 IO51 IO52 IO53 IO54 IO55 IO56 IO57 TX0 RX0 IO60 IO61 GND GND Pin 95 GND GND GND GND GNDGND GND GND Pin 99 GND Pin 98 GND Pin 73 Pin 74 Pin 75 Pin 76 Pin 77 Pin 78 Pin 79 Pin 80 Pin 81 Pin 82 Pin 83 Pin 84 Pin 85 Pin 86 Pin 87 Pin 88 Pin 89 Pin 90 Pin 91 Pin 92 Pin 93 Pin 94 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND NC GND GND GND Figure 3-1. Pin Layout (Top View) Note A: “Keepout Zone” refers to the antenna clearance (keep-out) area. 3.2 Pin Description The module has 99 pins. See pin definitions in Table 3-1 Pin Definitions. Espressif Systems 10 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 3 Pin Definitions For peripheral pin configurations, please refer to Section 5.2 Peripheral Description. Table 3-1. Pin Definitions Name No. Type 1 Function GND 1, 2, 26, 47, 48, 72 ~90, 92 ~99 P Ground 3V3 3, 4 P Power supply EN 5 I High: on, enables the chip. Low: off, the chip powers off. Note: Do not leave the EN pin floating. IO2 6 I/O/T GPIO2, LP_GPIO2, LP_UART_DTRN, LP_SPI_CK, LP_PROBE_TOP_OUT2, lcd_data19_out IO3 7 I/O/T GPIO3, LP_GPIO3, LP_UART_DSRN, LP_SPI_CS, LP_PROBE_TOP_OUT3, lcd_data20_out IO0 8 I/O/T GPIO0, LP_GPIO0, XTAL_32K_N, LP_PROBE_TOP_OUT0 IO1 9 I/O/T GPIO1, LP_GPIO1, XTAL_32K_P, LP_PROBE_TOP_OUT1 IO4 10 I/O/T GPIO4, LP_GPIO4, LP_UART_RTSN, LP_SPI_D, LP_PROBE_TOP_OUT4, lcd_data21_out IO5 11 I/O/T GPIO5, LP_GPIO5, LP_UART_CTSN, LP_SPI_Q, LP_PROBE_TOP_OUT5, lcd_data22_out IO6 12 I/O/T GPIO6, LP_GPIO6, TOUCH_CHANNEL0, LP_UART_TXD, LP_I2C_SCL, LP_PROBE_TOP_OUT6 IO7 13 I/O/T GPIO7, LP_GPIO7, TOUCH_CHANNEL1, LP_UART_RXD, LP_I2C_SDA, LP_PROBE_TOP_OUT7, lcd_data23_out IO8 14 I/O/T GPIO8, TOUCH_CHANNEL2, gmac_phy_txd0, lcd_data0_out IO9 15 I/O/T GPIO9, TOUCH_CHANNEL3, gmac_phy_txd1, lcd_data1_out, spi2_hold, dbg_psram_ck IO10 16 I/O/T GPIO10, TOUCH_CHANNEL4, gmac_phy_txd2, lcd_data2_out, spi2_cs, dbg_psram_cs IO11 17 I/O/T GPIO11, TOUCH_CHANNEL5, gmac_phy_txd3, lcd_data3_out, spi2_d, dbg_psram_d IO12 18 I/O/T GPIO12, TOUCH_CHANNEL6, gmac_phy_txen, lcd_data4_out, spi2_ck, dbg_psram_q IO13 19 I/O/T GPIO13, TOUCH_CHANNEL7, gmac_rmii_clk, lcd_data5_out, spi2_q, dbg_psram_wp IO14 20 I/O/T GPIO14, TOUCH_CHANNEL8, gmac_rx_clk, lcd_data6_out, spi2_wp, dbg_psram_hold IO15 21 I/O/T GPIO15, TOUCH_CHANNEL9, gmac_phy_rxdv, lcd_data7_out, spi2_io4, dbg_psram_dq4 IO16 22 I/O/T GPIO16, TOUCH_CHANNEL10, gmac_phy_rxd3, lcd_data8_out, spi2_io5, dbg_psram_dq5 IO17 23 I/O/T GPIO17, TOUCH_CHANNEL11, gmac_phy_rxd2, lcd_data9_out, spi2_io6, dbg_psram_dq6 Cont’d on next page Espressif Systems 11 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 3 Pin Definitions Table 3-1 – cont’d from previous page Name No. Type 1 Function IO18 24 I/O/T GPIO18, TOUCH_CHANNEL12, gmac_phy_rxd1, lcd_data10_out, spi2_io7, dbg_psram_dq7 IO19 25 I/O/T GPIO19, TOUCH_CHANNEL13, gmac_phy_rxd0, lcd_data11_out, spi2_dqs, dbg_psram_dqs_0 SD_D0 27 I/O/T SDIO_DATA0, GPIO20, spi2_ck, dbg_flash_ck SD_D1 28 I/O/T SDIO_DATA1, GPIO21, spi2_d, dbg_flash_d SD_D2 29 I/O/T SDIO_DATA2, GPIO22, spi2_q, dbg_flash_cs SD_D3 30 I/O/T SDIO_DATA3, GPIO23, spi2_cs, dbg_flash_q SD_CLK 31 I/O/T SDIO_CLK, GPIO24, spi2_hold, dbg_flash_wp SD_CMD 32 I/O/T SDIO_CMD, GPIO25, spi2_wp, dbg_flash_hold NC 33 ~39 - NC USB_DP 40 I/O/T USB_DP USB_DM 41 I/O/T USB_DM IO33 42 I/O/T GPIO33, USB1P1_N0, lcd_data12_out IO34 43 I/O/T GPIO34, USB1P1_P0, lcd_data13_out IO35 44 I/O/T GPIO35, ref_gmac_clk, lcd_data14_out, sd2_cdata0 IO36 45 I/O/T GPIO36, gmac_phy_rxdv, lcd_data15_out, sd2_cdata1 IO37 46 I/O/T GPIO37, gmac_phy_txen, lcd_data16_out, sd2_cdata2, PAD COMP0 (MUX4) IO38 49 I/O/T GPIO38, gmac_phy_rxd3, lcd_data17_out, sd2_cdata3, PAD COMP1 (MUX4) IO39 50 I/O/T GPIO39, gmac_phy_rxd2, lcd_data18_out, sd2_cclk, PAD COMP2 (MUX4) IO40 51 I/O/T GPIO40, gmac_phy_rxd1, lcd_pclk_out, sd2_ccmd, PAD COMP3 (MUX4) IO42 52 I/O/T GPIO42, ADC1_CHANNEL0_N, gmac_rx_clk IO43 53 I/O/T GPIO43, ADC1_CHANNEL0_P, gmac_rmii_clk, lcd_h_enable IO44 54 I/O/T GPIO44, ADC1_CHANNEL1_N, gmac_phy_txd0, lcd_h_sync IO45 55 I/O/T GPIO45, ADC1_CHANNEL1_P, gmac_phy_txd1, lcd_v_sync IO46 56 I/O/T GPIO46, ADC1_CHANNEL2_N, gmac_phy_txd2, cam_data0_in IO47 57 I/O/T GPIO47, ADC1_CHANNEL2_P, gmac_phy_txd3, cam_data1_in IO48 58 I/O/T GPIO48, ADC1_CHANNEL3_N, cam_data2_in IO49 59 I/O/T GPIO49, ADC1_CHANNEL3_P, cam_data3_in IO50 60 I/O/T GPIO50, ADC2_CHANNEL0_N, cam_data4_in IO51 61 I/O/T GPIO51, ADC2_CHANNEL0_P, cam_data5_in IO52 62 I/O/T GPIO52, ADC2_CHANNEL1_N, cam_data6_in, spi2_cs IO53 63 I/O/T GPIO53, ADC2_CHANNEL1_P, cam_data7_in, spi2_ck IO54 64 I/O/T MTDO, GPIO54, ADC2_CHANNEL2_N, cam_pclk, spi2_d IO55 65 I/O/T MTCK, GPIO55, ADC2_CHANNEL2_P, cam_xclk, spi2_q IO56 66 I/O/T MTDI, GPIO56, ADC2_CHANNEL3_N, cam_v_sync, spi2_hold IO57 67 I/O/T MTMS, GPIO57, ADC2_CHANNEL3_P, cam_h_sync, spi2_wp TX0 68 I/O/T uart0_txd, GPIO58 Cont’d on next page Espressif Systems 12 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 3 Pin Definitions Table 3-1 – cont’d from previous page Name No. Type 1 Function RX0 69 I/O/T uart0_rxd, GPIO59 IO60 70 I/O/T GPIO60 IO61 71 I/O/T GPIO61 NC 91 - NC 1 P: power supply; I: input; O: output; T: high impedance. Espressif Systems 13 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 4 Boot Configurations 4 Boot Configurations Note: The content below is excerpted from ESP32-S31 Series Datasheet > Chapter Boot Configurations. For the strapping pin mapping between the chip and modules, please refer to Chapter 7 Module Schematics. The chip allows for configuring the following boot parameters through strapping pins and eFuse parameters at power-up or a hardware reset, without microcontroller interaction. • Chip boot mode – Strapping pin: GPIO60 and GPIO61 • ROM message printing – Strapping pin: GPIO60 – eFuse parameter: EFUSE_UART_PRINT_CONTROL and EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT • JTAG signal source – Strapping pin: GPIO37 – eFuse parameter: EFUSE_DIS_PAD_JTAG, EFUSE_DIS_USB_JTAG, and EFUSE_JTAG_SEL_ENABLE The default values of all the above eFuse parameters are 0, which means that they are not burnt. Given that eFuse is one-time programmable, once programmed to 1, it can never be reverted to 0. The default values of the strapping pins, namely the logic levels, are determined by pins’ internal weak pull-up/pull-down resistors at reset if the pins are not connected to any circuit, or connected to an external high-impedance circuit. Table 4-1. Default Configuration of Strapping Pins Strapping Pin Default Configuration Bit Value GPIO61 Weak pull-up 1 GPIO60 Weak pull-up 1 To change the bit values, the strapping pins should be connected to external pull-down/pull-up resistances. If the ESP32-S31 is used as a device by a host MCU, the strapping pin voltage levels can also be controlled by the host MCU. All strapping pins have latches. At Chip Reset, the latches sample the bit values of their respective strapping pins and store them until the chip is powered down or shut down. The states of latches cannot be changed in any other way. It makes the strapping pin values available during the entire chip operation, and the pins are freed up to be used as regular IO pins after reset. The timing of signals connected to the strapping pins should adhere to the setup time and hold time specifications in Table 4-2 and Figure 4-1. Espressif Systems 14 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 4 Boot Configurations Table 4-2. Description of Timing Parameters for the Strapping Pins Parameter Description Min (ms) t SU Setup time is the time reserved for the power rails to stabilize before the CHIP_PU pin is pulled high to activate the chip. 0 t H Hold time is the time reserved for the chip to read the strapping pin values after CHIP_PU is already high and before these pins start operating as regular IO pins. 3 Strapping pin V IH_nRST V IH t SU t H CHIP_PU Figure 4-1. Visualization of Timing Parameters for the Strapping Pins 4.1 Chip Boot Mode Control GPIO60 and GPIO61 control the boot mode after the reset is released. See Table 4-3 Chip Boot Mode Control. Table 4-3. Chip Boot Mode Control Boot Mode GPIO61 GPIO60 SPI boot mode 1 1 Any value Joint download boot mode 2 0 0 1 Bold marks the default value and configuration. 2 Joint Download Boot mode supports the following download methods: • USB-Serial-JTAG Download Boot • USB-OTG Download Boot • UART Download Boot • GPSPI Download Boot In addition to SPI Boot and Joint Download Boot modes, ESP32-S31 also supports SPI Download Boot mode. Espressif Systems 15 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 4 Boot Configurations 4.2 Secure Debug Controller (SDC) ESP32-S31 is the first chip to support the Secure Debug Controller (SDC). When all of the following conditions are met, the chip supports SDC-related commands in Joint Download Boot mode: • The chip has entered Joint download boot mode • eFuse bit EFUSE_RMA_ENA has been burned Note: SDC-related capabilities are not affected by eFuse bits EFUSE_DIS_DOWNLOAD_MODE and EFUSE_ENABLE_SECURE_DOWNLOAD. Before using SDC, complete eFuse and certificate configuration as follows: 1. Burn the SDC public-key hash into eFuse; 2. In Joint Download Boot mode, transfer the SDC certificate to the chip via esptool; the ROM verifies the certificate in hardware. After successful certificate verification, the ROM temporarily enables the following debugging capabilities at the hardware level (even if the corresponding eFuse bits have been burned to disable them): • Software JTAG, even if EFUSE_SOFT_DIS_JTAG has been burned; • Download mode, even if EFUSE_DIS_DOWNLOAD_MODE has been burned; • Forced entry into SPI Boot mode for application software debugging. The SDC authorization state is valid only for the current run. After power-on reset, the verification result is cleared; to debug again, repeat certificate transfer and verification. 4.3 ROM Messages Printing Control During the boot process, the messages by the ROM code can be printed to: • (Default) UART0 and USB Serial/JTAG controller • USB Serial/JTAG controller • UART0 EFUSE_UART_PRINT_CONTROL and GPIO60 control ROM messages printing to UART0 as shown in Table 4-4 UART0 ROM Message Printing Control. Table 4-4. UART0 ROM Message Printing Control UART0 ROM Code Printing EFUSE_UART_PRINT_CONTROL GPIO60 Enabled 0 Ignored 1 0 2 1 Disabled 1 1 2 0 3 Ignored 1 Bold marks the default value and configuration. Espressif Systems 16 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 4 Boot Configurations EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT controls the printing to USB Serial/JTAG controller as shown in Table 4-5 USB Serial/JTAG ROM Message Printing Control. Table 4-5. USB Serial/JTAG ROM Message Printing Control USB Serial/JTAG ROM Code Printing EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT Enabled 0 Disabled 1 1 Bold marks the default value and configuration. 4.4 JTAG Signal Source Control The strapping pin GPIO37 can be used to control the source of JTAG signals during the early boot process. This pin does not have any internal pull resistors and the strapping value must be controlled by the external circuit that cannot be in a high impedance state. As Table 4-6 JTAG Signal Source Control shows, GPIO37 is used in combination with EFUSE_DIS_PAD_JTAG, EFUSE_DIS_USB_JTAG, and EFUSE_JTAG_SEL_ENABLE . Table 4-6. JTAG Signal Source Control JTAG Signal Source EFUSE_DIS_PAD_JTAG EFUSE_DIS_USB_JTAG EFUSE_JTAG_SEL_ENABLE GPIO37 USB Serieal/JTAG Controller 0 0 0 Ignored 0 0 1 1 1 0 Ignored Ignored JTAG pins 2 0 0 1 0 0 1 Ignored Ignored JTAG is disabled 1 1 Ignored Ignored 1 Bold marks the default value and configuration. 2 JTAG pins refer to MTDI, MTCK, MTMS, and MTDO. 4.5 Chip Power-up and Reset Once the power is supplied to the chip, its power rails need a short time to stabilize. After that, CHIP_PU – the pin used for power-up and reset – is pulled high to activate the chip. For information on CHIP_PU as well as power-up and reset timing, see Figure 4-2 and Table 4-7. V IL_nRST t ST BL t RST 2.8 V VDDA1,VDDA2, VDDA3, VDDA4, VDDPST_1, VDDPST_2, VDDPST_3, VDDPST_4 CHIP_PU Figure 4-2. Visualization of Timing Parameters for Power-up and Reset Espressif Systems 17 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 4 Boot Configurations Table 4-7. Description of Timing Parameters for Power-up and Reset Parameter Description Min (ms) t ST BL Time reserved for the power rails of VDDA1, VDDA2, VDDA3, VDDA4, VDDPST_1, VDDPST_2, VDDPST_3, VDDPST_4 to sta- bilize before the CHIP_PU pin is pulled high to activate the chip 1 t RST Time reserved for CHIP_PU to stay below V IL_nRST to reset the chip (see Table 6-3) 1 Espressif Systems 18 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 5 Peripherals 5 Peripherals 5.1 Peripheral Overview ESP32-S31 integrates a rich set of peripherals including UART, SPI, I2C, I2S, Pulse Counter Controller, USB 2.0 High-Speed OTG, USB Serial/JTAG Controller, Ethernet Media Access Controller, CAN FD Controller, SD/MMC Host Controller, LED PWM Controller, Motor Control PWM, Remote Control Peripheral, Parallel IO Controller, Touch Sensor, Temperature Sensor, ADC Controller, DAC Controller, Analog Voltage Comparator, General-Purpose Timer, System Timer, Watchdog Timer, etc. Note: The content below is sourced from ESP32-S31 Series Datasheet > Section Peripherals. Some information may not be applicable to ESP32-S31-WROOM-3 as not all the IO signals are exposed on the module. 5.2 Peripheral Description This section describes the chip’s peripheral capabilities, covering connectivity interfaces and on-chip sensors that extend its functionality. 5.2.1 Image and Voice Processing This subsection describes the peripherals for image and voice processing. 5.2.1.1 JPEG Codec ESP32-S31’s JPEG codec is an image codec, which is based on the JPEG baseline standard, for compressing (encoding) and decompressing (decoding) images to reduce the bandwidth required to transmit images or the space required to store images, making it possible to process large-resolution images. Feature List When used as an encoder, the JPEG codec has the following features: • Integrated discrete cosine transform algorithm • Integrated canonical Huffman coding • RGB888, RGB565, YUV444, YUV422, YUV420 and GRAY as original input image formats • Supports converting (if needed) and compressing RGB888, RGB565, or YUV444 images into YUV444, YUV422, or YUV420 formats, and supports converting (if needed) and compressing YUV422 images into YUV422 or YUV420 formats. Compression is only available for YUV444, YUV422, and YUV420 formats • Four configurable quantization coefficient tables with 8-bit or 16-bit precision • Performance: – Still image compression: up to 4K resolution – Dynamic image compression: up to 720P@30fps (excluding header encoding time) Espressif Systems 19 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 5 Peripherals • Automatically added stuffed zero byte • Automatically added EOI marker When used as a decoder, the JPEG codec has the following features: • Integrated inverse discrete cosine transform algorithm • Integrated Huffman decoding • Supported image formats for compressed bitstream decoding: YUV444, YUV422, YUV420, and GRAY. • Four configurable quantization coefficient tables with 8-bit or 16-bit precision • Two DC and two AC Huffman tables • Supports image decoding of any resolution. However, the resolution of the output decoded image differs from the format of the input image: – YUV444, GRAY: both the horizontal and vertical resolutions of the output decoded image are multiples of 8, i.e., 150 × 150 images with an output resolution of 152 × 152 – YUV422: the horizontal resolution of the output decoded image is the multiples of 16 and the vertical resolution is multiples of 8, i.e., 150 × 150 images with an output resolution of 160 × 152 – YUV420: both the horizontal and vertical resolutions of the output decoded image are multiples of 16, i.e., 150 × 150 images with an output resolution of 160 × 160 • Performance: – Still image decoding: up to 4K resolution – Dynamic image decoding: up to 720P@30fps (excluding header parsing time) Pin Assignment The JPEG Codec does not interact directly with IOs, so it has no pins assigned. 5.2.1.2 Pixel-Processing Accelerator (PPA) ESP32-S31 includes a pixel-processing accelerator (PPA) with scaling-rotation-mirror (SRM) and image blending (BLEND) functionalities. Feature List • Image rotation, scaling, and mirroring by SRM: – Input formats: ARGB8888, RGB888, RGB565, YUV422, YUV420, GRAY – Output formats: ARGB8888, RGB888, RGB565, YUV422, YUV420, GRAY – Counterclockwise rotation angles: 0°, 90°, 180°, 270° – Horizontal and vertical scaling with scaling factors of 4-bit integer part and 8-bit fractional part – Horizontal and vertical mirroring • Blending two layers of the same size and filling images with specific pixels by BLEND: – Foreground input formats: ARGB8888, RGB888, RGB565, L4, L8, A4, A8 Espressif Systems 20 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 5 Peripherals – Background input formats: ARGB8888, RGB888, RGB565, YUV422, YUV420, GRAY, L4, L8 – Output formats: ARGB8888, RGB888, RGB565, YUV422, YUV420, GRAY – Layer blending based on the Alpha channel. If layers lack an Alpha channel, it can be provided through register configuration. – Special color filtering by setting color-key ranges of foreground and background layers Pin Assignment The pixel-processing accelerator does not directly interact with IOs, so it has no pins assigned. 5.2.1.3 Audio Sample Rate Converter (ASRC) Audio Sample Rate Converter (ASRC) is an accelerator-type audio processing module used for high-quality conversion of audio signals between different sample rates. It enables collaboration between devices with varying sample rate standards. This module typically interacts with on-chip or off-chip memory through a DMA interface to achieve efficient transmission and processing of audio data. Feature List • Supports conversion between 8 kHz, 16 kHz, 32 kHz, 44.1 kHz, and 48 kHz • Input and output signal width is 16 bits, using Q1.15 format • Sample rate conversion uses two integer resamplers and one fractional sample rate converter (FRC) in a cascade, with the cascade configurable via software: – The integer resampler’s conversion factor can be set to 2 or 1 2 – The FRC supports conversion factors configurable between 0 and 2 (excluding 0 and 2) • Supports multiple channel modes, including: – Mono receive (Rx) / Mono transmit (Tx) – Stereo receive (Rx) / Stereo transmit (Tx), processed in parallel – Mono receive / Stereo transmit – Stereo receive / Mono transmit • Supports input data of any length, and generates EOF (End of Frame) flags based on output length • When two channels are used independently, each channel supports the following modes: – Mono input, mono output – Mono input, stereo output (both channels use the same data) – Stereo input, mono output (choose one channel for processing) • When both channels are used together, each channel can be configured as stereo input or output Espressif Systems 21 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 5 Peripherals 5.2.1.4 CORDIC Accelerator (CORDIC) ESP32-S31 includes a hardware CORDIC accelerator. Its core principle is to iteratively approach a target angle by executing a sequence of fixed-angle rotations associated with computation cycles, enabling mathematical operations such as trigonometric function calculations. Feature List • Supports q1.15 and q1.31 fixed-point formats • Supports circular, linear, and hyperbolic systems • Supports rotation mode and vectoring mode • Supported functions: sin, cos, sinh, cosh, atan(x), atan(y/x), atanh, modulus, square root, and natural logarithm • Configurable computation precision (number of operation cycles) • Supports polling-based result readout • Supports interrupt-based result readout • Supports direct DMA connection mode Pin Assignment The CORDIC accelerator does not need direct interaction with IO and therefore requires no dedicated pin assignment. 5.2.1.5 LCD and Camera Controller (LCD_CAM) The LCD and Camera controller (LCD_CAM) on the ESP32-S31, consisting of an independent LCD control module and a camera control module, is a versatile component designed to facilitate interfacing with both LCDs and cameras. Feature List • Operation modes: – LCD master TX mode – Camera slave RX mode – Camera master RX mode • Simultaneous connection to an external LCD and a camera • External LCD interface: – 8/16/24-bit parallel output modes – RGB, MOTO6800, and I8080 LCD formats – LCD data retrieved from internal memory or external memory via GDMA • External camera (DVP image sensor) interface: Espressif Systems 22 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 5 Peripherals – 8/16-bit parallel input modes – Camera data stored in internal or external memory via GDMA • Interrupt support Pin Assignment For CAM and LCD interfaces of the Camera-LCD controller, the pins used can be chosen from any GPIOs via the GPIO Matrix. 5.2.2 Connectivity Interface This subsection describes the connectivity interfaces on the chip that enable communication and interaction with external devices and networks. 5.2.2.1 UART Controller (UART) The UART controllers in ESP32-S31 are used for asynchronous serial data transmission and reception between the chip and external UART devices. ESP32-S31 includes four UART controllers in the main system and one low-power LP UART. Feature List • Programmable baud rates up to 5 MBaud • RAM shared by TX FIFOs and RX FIFOs • Support for various lengths of data bits and stop bits • Parity bit support • Special character AT_CMD detection • RS485 protocol support (not applicable to LP UART) • IrDA protocol support (not applicable to LP UART) • High-speed data communication using GDMA (not applicable to LP UART) • Receive timeout feature • UART as the wake-up source • Software and hardware flow control Pin Assignment UART0 and LP UART each have fixed direct-connected pins via the HP IO MUX and LP IO MUX. They also support mapping to other pins through the GPIO Matrix. UART1, UART2, and UART3 are routed to any HP GPIO pins via the GPIO Matrix. 5.2.2.2 SPI Controller (SPI) The Serial Peripheral Interface (SPI) is a synchronous serial interface commonly used for communicating with external peripherals. The ESP32-S31 chip integrates four SPI controllers: Espressif Systems 23 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 5 Peripherals • MSPI controller, including two sub-controllers – FLASH MSPI controller * FLASH MSPI SPI0 * FLASH MSPI SPI1 – PSRAM MSPI controller * PSRAM MSPI SPI0 * PSRAM MSPI SPI1 • General Purpose SPI2 (GP-SPI2) • General Purpose SPI3 (GP-SPI3) • Low-Power SPI (LP-SPI) Feature List GP-SPI has the following features: • Works as master or as slave • Half- and full-duplex communications • CPU- and DMA-controlled transfers • Various data modes – GP-SPI2 * 1-bit SPI mode * 2-bit Dual SPI mode * 4-bit Quad SPI mode * QPI mode * 8-bit Octal SPI mode (available only when GP-SPI2 works as a master) * OPI mode (available only when GP-SPI2 works as a master) – GP-SPI3 * 1-bit SPI mode * 2-bit Dual SPI mode * 4-bit Quad SPI mode * QPI mode • Configurable module clock frequency – Master: up to 80 MHz – Slave: up to 60 MHz • Configurable data length – CPU-controlled transfer as master or as slave: 1–64 bytes Espressif Systems 24 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 5 Peripherals – DMA-controlled single transfer as master: 1–32 KB – DMA-controlled configurable segmented transfer as master: data length is unlimited – DMA-controlled single transfer or segmented transfer as slave: data length is unlimited • Configurable bit read/write order • Independent interrupts for CPU-controlled transfer and DMA-controlled transfer • Configurable clock polarity and phase • Four SPI clock modes: mode 0–mode 3 • Multiple CS lines as master – GP-SPI2: CS0–CS5 – GP-SPI3: CS0–CS2 • Able to communicate with SPI devices, such as a sensor, a screen controller, as well as a flash or RAM chip LP-SPI is a simplified version of GP-SPI and has a subset of GP-SPI’s features: • Works as a master or as a slave • Half- and full-duplex communications • CPU-controlled transfer • 1-bit SPI data mode • Configurable module clock frequency: – Master: up to 40 MHz – Slave: up to 40 MHz • Configurable data length: – CPU-controlled transfer as master or as slave: 1–64 bytes • Configurable bit read/write order • Interrupts for CPU-controlled transfer • Configurable clock polarity and phase • Four SPI clock modes: mode 0–mode 3 • One CS line as master: CS0 • Wake-up feature as slave (the only new feature compared with GP-SPI) Pin Assignment The Flash SPI interface uses the dedicated digital pins 27–33. The GP-SPI2 controller includes one four-line interface and one eight-line interface. The pins connected to the four-line interface are multiplexed via the IO MUX with GPIO20 to GPIO25, or GPIO50 to GPIO52, as well as the JTAG interface. The pins connected to the eight-line interface are multiplexed with GPIO9 to GPIO19, which also serves as the first set of RMII interface pins for the EMAC. If high-speed performance is not critical for the GP-SPI2 interface, you can select pins from any GPIOs via the GPIO Matrix. Espressif Systems 25 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 5 Peripherals For GP-SPI3, the pins used can be chosen from any GPIOs via the GPIO Matrix. The pins for the LP-SPI interface can be chosen from any pins via the LP GPIO Matrix. 5.2.2.3 I2C Controller (I2C) ESP32-S31 has two HP_I2C bus interfaces and one LP_I2C bus interface. The HP_I2C interfaces can operate in either I2C master or slave mode, while the LP_I2C interface supports master mode only. Feature List • Standard mode (100 Kbit/s) • Fast mode (400 Kbit/s) • Up to 800 Kbit/s (constrained by SCL and SDA pull-up strength) • 7-bit and 10-bit addressing mode • Dual address mode • 7-bit broadcast address Pin Assignment For I2C, the pins used can be chosen from any GPIOs via the GPIO Matrix. 5.2.2.4 I2S Controller (I2S) The I2S Controller in the ESP32-S31 chip provides a flexible communication interface for streaming digital data in multimedia applications, particularly digital audio applications. Feature List • Master mode and slave mode • Full-duplex and half-duplex communications • Separate TX and RX units that can work independently or simultaneously • A variety of audio standards supported: – TDM Philips standard – TDM MSB alignment standard – TDM PCM standard – PDM standard • Various TX/RX modes – TDM TX mode, up to 16 channels supported – TDM RX mode, up to 16 channels supported – PDM TX mode * Raw PDM data transmission Espressif Systems 26 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 5 Peripherals * PCM-to-PDM data format conversion, up to 2 channels supported – PDM RX mode * Raw PDM data reception • Configurable clock source with frequency up to 96 MHz • Configurable high-precision sample clock with a variety of sampling frequencies supported • 8/16/24/32-bit data width • Synchronous counter in TX mode • ETM feature • Direct memory access • Standard I2S interface interrupts Pin Assignment The pins for the I2S controller can be chosen from any GPIOs via the GPIO Matrix. 5.2.2.5 Pulse Count Controller (PCNT) The Pulse Count controller (PCNT) in ESP32-S31 captures pulses and counts pulse edges in seven modes. Feature List • Four independent pulse counters (units) that count from 1 to 65535 • Each unit consists of two independent channels sharing one pulse counter • All channels have input pulse signals (e.g., sig_ch0_un) with their corresponding control signals (e.g., ctrl_ch0_un) • Independently filter glitches of input pulse signals (sig_ch0_un and sig_ch1_un) and control signals (ctrl_ch0_un and ctrl_ch1_un) on each unit • Each channel has the following parameters: 1. Selection between counting on positive or negative edges of the input pulse signal 2. Configuration to Increment, Decrement, or Disable counter mode for control of signal’s high and low states 3. Step count alert triggered by setting the upcount/downcount step threshold 4. Clearing of the pulse count controller value by setting the clear register or sending a clear signal through GPIO input 5. Generation and recording of a corresponding event signal for each counter mode, with the ability to report it to the interrupt task • Maximum frequency of pulses: f AP B_CLK 2 Espressif Systems 27 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 5 Peripherals Pin Assignment The pins for the Pulse Count controller can be chosen from any GPIOs via the GPIO Matrix. 5.2.2.6 USB 2.0 High-Speed OTG The ESP32-S31 chip features a USB 2.0 High-Speed On-The-Go peripheral (OTG_HS) with an integrated transceiver. This OTG_HS complies with the USB 2.0 specification, OTG Revision 1.3, and OTG Revision 2.0 specifications. The interface supports USB 2.0 High-Speed mode (480 Mbit/s), Full-Speed mode (12 Mbit/s), and Low-Speed mode (1.5 Mbit/s). • When OTG_HS operates in High-Speed or Full-Speed modes, it can be configured as either a Host or a Device. • When OTG_HS operates in Low-Speed mode, it can only be configured as a Host. Feature List General Features • USB 2.0 specification, OTG Revision 1.3 and OTG Revision 2.0 specifications • High-Speed, Full-Speed, and Low-Speed data rates • As a host and a device in High-Speed mode and Full-Speed mode • Dynamic FIFO (DFIFO) sizing, each device EP/host channel can dynamically allocate a maximum of 4 KB FIFO. • Up to 8 non-periodic transactions and 16 periodic transactions per microframe • Multiple modes of memory access – Scatter/Gather DMA mode – Buffer DMA mode – Slave Mode • Integrated UTMI High-Speed transceiver Device Mode Features • Endpoint 0 always present, bi-directional, consisting of EP0 IN and EP0 OUT • 15 additional endpoints 1–15, configurable as IN or OUT • Maximum of eight IN endpoints concurrently active at any time, including EP0 IN • All OUT endpoints share a single RX FIFO • Each IN endpoint has a dedicated TX FIFO Host Mode Features • 16 host channels • RX FIFO: shared by all periodic and non-periodic transactions • Two TX FIFO: Espressif Systems 28 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 5 Peripherals – One shared by all non-periodic transactions – One shared by all periodic transactions • All of the above FIFOs share a 4 KB RAM. • The size of each FIFO is configurable, with a maximum of 4 KB. Pin Assignment The pins connected to USB2 OTG PHY DM (USB_D-) and USB2 OTG PHY DP (USB_D+) signals of USB 2.0 High-Speed OTG are dedicated pin 44 and pin 45. Other signals can be routed to any GPIOs via the GPIO matrix. 5.2.2.7 USB Serial/JTAG Controller (USB_SERIAL_JTAG) ESP32-S31 contains a USB Serial/JTAG controller. This unit can be used to program the SoC’s flash, read program output, as well as attach a debugger to the running program. All of these are possible for any computer with a USB host without any active external components. Feature List • USB 2.0 full speed compliant, capable of up to 12 Mbit/s transfer speed (note that this controller does not support the faster 480 Mbit/s high-speed transfer mode) • CDC-ACM virtual serial port and JTAG adapter functionality • programming the chip’s flash • CPU debugging with compact JTAG instructions • a full-speed USB PHY integrated in the chip Pin Assignment The pins for the USB Serial/JTAG controller are multiplexed with GPIO33 and GPIO34 via IO MUX. 5.2.2.8 Ethernet Media Access Controller (EMAC) By using the external Ethernet PHY (physical layer), ESP32-S31 can send and receive data via Ethernet MAC (Media Access Controller) according to the IEEE 802.3 standard. ESP32-S31 Ethernet MAC complies with the following standards: • IEEE 802.3-2002 for Ethernet MAC • IEEE 1588-2008 standard for precise networked clock synchronization • IEEE 802.3 standard Media Independent Interface (MII), Reduced Media Independent Interface (RMII), and Reduced Gigabit Media Independent Interface (RGMII) • IEEE 802.3az-2010 for Energy Efficient Ethernet • IEEE 802.1Q for VLAN frame format Espressif Systems 29 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 5 Peripherals Feature List • Data rates of 10/100/1000 Mbit/s through an external PHY interface • Communication with an external Ethernet PHY through IEEE 802.3-compliant MII, RMII, or RGMII interface (only one can be used at a time) • Full-duplex and half-duplex modes – Carrier Sense Multiple Access or Collision Detection (CSMA/CD) protocol in half-duplex mode – IEEE 802.3x flow control in full-duplex mode – Optional forwarding of received pause control frame to the user application in full-duplex mode – Back-pressure flow control in half-duplex mode – Automatic transmission of zero-quanta pause frame on deassertion of flow control input in full-duplex mode • Preamble and start-of-frame data (SFD) insertion in Transmit, and deletion in Receive paths • Automatic CRC and padding (all 0) generation controllable on a per-frame basis • Options for automatic padding generation for data below the minimum frame length • Programmable frame length supporting jumbo frames of up to 16 KB • Programmable inter-frame gap (IFG) from 40 to 96 bit times in steps of 8 • Flexible address filtering modes: – Up to nine 48-bit perfect address filters with per-byte masking – Up to nine 48-bit source address (SA) comparisons with per-byte masking – Option to pass all multicast addressed frames – Promiscuous mode to pass all frames without filtering for network monitoring – Passes all incoming packets (as per filter) with a status report • Separate 32-bit status returned for transmission and reception packets • IEEE 802.1Q VLAN tag detection for reception frames • Separate transmission, reception, and control interfaces for the application • Management Data Input/Output (MDIO) interface for PHY device configuration and management • Checksum offload for received IPv4 and TCP packets encapsulated by the Ethernet frame • Checking IPv4 header checksum and TCP, UDP, or ICMP checksum encapsulated in IPv4 or IPv6 datagrams • 64-bit timestamp for each transmitted and received frame (see IEEE 1588-2008) • Energy Efficient Ethernet support (see IEEE 802.3az-2010) • CRC replacement, SA insertion/replacement, and VLAN insertion/replacement/deletion in transmit frames • Two FIFOs: 1024-byte TX FIFO and 256-byte RX FIFO Espressif Systems 30 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 5 Peripherals • Receive status vectors inserted into RX FIFO after the EOF (end of frame) transfer, allowing multiple-frame storage without requiring an additional FIFO for status • Option to forward good runt frames • Statistics generation with pulse signaling for dropped or corrupted frames due to RX FIFO overflow • Automatic re-transmission of collision frames • Frame discarding in cases of late collisions, excessive collisions, excessive deferrals, or underflow conditions • Software control for TX FIFO flushing Pin Assignment EMAC RGMII interface corresponds to the following designated pins in IO MUX: • The pins are multiplexed with GPIO8–GPIO19 EMAC RMII interface corresponds to the following designated pins in IO MUX: • The pins are multiplexed with GPIO8, GPIO9, GPIO12, GPIO13, GPIO15, GPIO18, GPIO19 EMAC MII interface uses the available RGMII pins and additionally requires three arbitrary GPIOs for signals such as rxderr/csr/col. MDIO and other signals can be routed to any GPIOs via the GPIO Matrix. 5.2.2.9 CAN FD Controller The CAN FD is a multi-master multi-cast communication protocol. The CAN FD controller facilitates the communication based on this protocol. The CAN FD controllers integrated in ESP32-S31 are protocol-compatible with the CAN FD specification but have not been formally certified. Feature List • compliant with ISO11898-1:2015 • RX buffer FIFO with 128 words (6 CAN FD frames with 64-byte data payloads, 21 CAN/CAN FD frames with 8-byte data payloads) • 4 TX buffers (1 CAN FD frame in each TX buffer) • 32-bit APB interface • support of ISO and non-ISO CAN FD protocol • timestamping and time triggered transmission • three single-bit filters and one range filter • support interrupts • loopback, bus monitoring, ACK forbidden, self test, and restricted operation modes Pin Assignment The pins for the CAN FD Controller can be chosen from any GPIOs via the GPIO Matrix. Espressif Systems 31 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 5 Peripherals 5.2.2.10 SD/MMC Host Controller (SDHOST) ESP32-S31 has an SD/MMC Host Controller. Feature List • Supports two external cards • SD Memory Card Specifications v3.0 and v3.01 • Secure Digital I/O (SDIO) v3.0 • CE-ATA v1.1 • MMC v4.41 and eMMC v4.5, v4.51 • 1-bit and 4-bit bus width modes (8-bit mode not supported) ESP32-S31 SD/SDIO/MMC Host Controller can simultaneously support two SD/SDIO/MMC 4.41 cards, and supports one SD card operating at 1.8 V. Pin Assignment For the SD/SDIO/MMC host controller, Card 1 can use GPIO20–GPIO25 via IO MUX, and Card 2 can use GPIO35–GPIO40 via IO MUX. 5.2.2.11 LED PWM Controller (LEDC) The LED PWM Controller is a peripheral designed to generate PWM signals for LED control. It has specialized features such as automatic duty cycle fading. However, the LED PWM Controller can also be used to generate PWM signals for other purposes. Feature List • Two independent LED PWM controllers, each with eight independent PWM generator channels (16 channels in total) • Maximum PWM duty cycle resolution: 20 bits • Four independent timers per controller with 20-bit counters, fractional clock divider, and configurable overflow value • Adjustable phase of PWM signal output • PWM duty cycle dithering • Automatic duty cycle fading — gradual increase/decrease of a PWM’s duty cycle without interference from the processor. An interrupt will be generated upon fade completion • Up to 16 duty cycle ranges for each PWM generator to generate gamma curve signals; each range can be independently configured for fade direction (increase or decrease), fade amount (per-step duty change), fade count (number of steps per range), and fade frequency • PWM signal output in low-power mode (Light-sleep mode) • Event generation and task response related to the Event Task Matrix (ETM) peripheral Espressif Systems 32 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 5 Peripherals Pin Assignment The pins for the LED PWM controller can be chosen from any GPIOs via the GPIO Matrix. 5.2.2.12 Motor Control PWM (MCPWM) ESP32-S31 integrates an MCPWM that can be used to drive digital motors and smart light. Feature List • A clock divider (prescaler), three PWM timers, three PWM operators, an Event Task Matrix (ETM) module, a Fault Detection module, and a dedicated capture module. PWM timers are used to generate timing references. PWM operators generate desired waveform based on the timing references • A PWM operator can use the timing reference of any PWM timer • A PWM operator can use the same timing reference with other PWM operators • PWM operators can use different PWM timers’ values to produce independent PWM signals • PWM timers can be synchronized Pin Assignment The pins for the Motor Control PWM can be chosen from any GPIOs via the GPIO Matrix. 5.2.2.13 Remote Control Peripheral (RMT) The Remote Control Peripheral (RMT) supports four channels of infrared remote transmission and four channels of infrared remote reception. By controlling pulse waveform through software, it supports various infrared and other single wire protocols. Feature List • Eight channels: – TX channels 0–3 – RX channels 4–7 – Eight channels share a 384 x 32-bit RAM • The transmitter supports: – Normal TX mode – Wrap TX mode – Continuous TX mode – Modulation on TX pulses – Multiple channels transmitting data simultaneously (programmable) – GDMA access supported by TX channel 3 • The receiver supports: Espressif Systems 33 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 5 Peripherals – Normal RX mode – Wrap RX mode – RX filtering – Demodulation on RX pulses – GDMA access supported by RX channel 7 Pin Assignment The pins for the remote control peripheral can be chosen from any GPIOs via the GPIO Matrix. 5.2.2.14 Parallel IO Controller (PARLIO) ESP32-S31 contains a Parallel IO controller (PARLIO) capable of transferring data between external devices and internal memory on a parallel bus through General Direct Memory Access (GDMA). Feature List • Various clock sources: – Including external IO clock PAD_CLK_TX/RX and internal system clock XTAL_CLK, PLL_F160M_CLK, and RC_FAST_CLK – Maximum IO clock frequency of 40 MHz – Integer and fractional clock frequency division • 1/2/4/8/16-bit configurable data bus width • Full-duplex communication with 16-bit data bus width • Bit reversal when data bus width is 1/2/4-bit • RX unit for receiving IO parallel data, which supports: – Output clock gating – RX unit input and output clock inverse – Various receive modes – Configurable GDMA SUC EOF generation – Configurable IO pin of external enable signal • TX unit for sending IO parallel data, which supports: – Output clock gating – TX unit input and output clock inverse – Configurable TX EOF generation – Valid signal output – Configurable bus idle value Espressif Systems 34 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 5 Peripherals Pin Assignment The pins for the parallel IO controller can be chosen from any GPIOs via the GPIO Matrix. 5.2.2.15 BitScrambler The ESP32-S31 has an extensive amount of DMA-capable peripherals. These can move data from memory to an external device, and vice versa, without any interference from the CPU. This only works if the external device needs or emits the data in question in the same format as the software expects it: if not, the CPU needs to rewrite the format of the data. Examples include a need to swap bytes, reverse bytes, and shift the data left or right. Since bitwise operations can be relatively CPU-intensive and DMA is designed specifically to offload such work from the CPU, ESP32-S31 integrates two dedicated peripherals called BitScramblers. These modules are designed to transform data formats during transfers between memory and peripherals. One BitScrambler handles memory-to-peripheral (or memory-to-memory) transfers, while the other is dedicated to peripheral-to-memory transfers. While BitScramblers can handle the bitwise operations mentioned earlier, they are in fact flexible, programmable state machines capable of performing more advanced transformations as well. Feature List • Two BitScramblers, one for RX (peripheral-to-memory), one for TX (memory-to-peripheral) • Support for memory-to-memory transfers • Processing up to 32 bits per DMA clock period • Data path controlled by a BitScrambler program stored in instruction memory • Input registers able to read 0, 8, 16, or 32 bits per clock cycle • Output registers: – Able to write 0, 8, 16, or 32 bits per clock cycle – Data sources for output register bits: 64 bits of input data, two counters, LUT RAM data, data output of last cycle, comparators – With some restrictions, each of the 32 output register bits can come from any bit on the data sources • An 8 x 257-bit instruction memory for storing eight instructions, controlling control flow, and the data path • 2048 bytes of lookup table (LUT) memory, configurable as various word widths Pin Assignment The BitScrambler does not directly interact with IOs, so it has no pins assigned. 5.2.3 Analog Signal Processing This subsection describes components on the chip that sense and process real-world data. Espressif Systems 35 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 5 Peripherals 5.2.3.1 Touch Sensor (TOUCH) ESP32-S31 has 14 capacitive-sensing GPIOs, which detect variations induced by touching or approaching the GPIOs with a finger or other objects. The low-noise nature of the design and the high sensitivity of the circuit allow relatively small pads to be used. Arrays of pads can also be used, so that a larger area or more points can be detected. The touch sensing performance can be further enhanced by the waterproof design, detection of frequency hopping, and digital filtering feature. Feature List • Detection of 14 capacitive touch pins • Sampling triggered by software or dedicated hardware timer • Two sampling methods: – Pulses from the touch pins used as clock signals to count the sampling period – Pulses from the touch pins used as digital signals; sample the rising edge of the digital signal with the system clock to count the sampling period • Scan mode, supporting sequential sampling of multiple touch pins by configuring the Touch FSM. • Timeout mechanism to monitor channel abnormality • Frequency hopping to increase the anti-interference of detection • Proximity sensing mode with up to three configurable channels • Configuration of individual touch sensors to operate normally in sleep mode • Wake-up by touch sensor • Moisture resistance • Waterproof design Pin Assignment The touch sensor interface is multiplexed with GPIO6~GPIO19 pins. When the pins are configured for the analog function, the multiplexed digital functions are disabled. 5.2.3.2 Temperature Sensor (TSENS) ESP32-S31 provides a temperature sensor for real-time monitoring of temperature changes within the chip. The sensor converts analog voltage to digital values and provides compensation for temperature offsets. Feature List • Software-triggered temperature measurement, which once triggered, the sensor continuously measures temperature. Software can read the data at any time. • Hardware-triggered automatic temperature monitoring • Two automatic monitoring modes with interrupt generation • Configurable temperature offset based on the application scenario for improved accuracy Espressif Systems 36 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 5 Peripherals • Configurable temperature measurement range • Support for Event Task Matrix (ETM)-related events and tasks 5.2.3.3 ADC Controller (ADC) ESP32-S31 integrates two 12-bit successive approximation ADCs (SAR ADCs), each capable of measuring analog signals from up to eight pins. Feature List • 12-bit resolution • Analog inputs sampling from up to eight pins per ADC (16 pins in total) • One-shot sampling mode and multi-channel sampling mode • In multi-channel sampling mode: – Configurable channel sampling sequence – Two filters with configurable filter coefficients – Two threshold monitors that can trigger an interrupt when the filtered value is below a low threshold or above a high threshold – Continuous transfer of converted data to memory via GDMA interface • Support for several Event Task Matrix (ETM) related events and tasks Pin Assignment SAR ADC1 pins are multiplexed with GPIO42 ~ GPIO49; SAR ADC2 pins are multiplexed with GPIO50 ~ GPIO57. 5.2.3.4 DAC Controller (DAC) ESP32-S31 provides a digital-to-analog converter that converts digital signals into analog voltages and outputs them on two dedicated chip pads. The two channels connect to two pads respectively and can output independently without affecting each other. Feature List • Supports output value configuration by software via PDMA, or sine-wave output via an internal lookup table • Output voltage range: 0 V to 3.3 V • Supports maintaining output level in ultra-low-power mode Pin Assignment DAC uses dedicated pads and is supported only on GPIO4 (DAC channel 0) and GPIO5 (DAC channel 1). Espressif Systems 37 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 5 Peripherals 5.2.3.5 Analog Voltage Comparator ESP32-S31 includes one analog voltage comparator with four dedicated pads. Three of these pads can be selected to compare their voltages against the remaining pad. Alternatively, any of the three pads can be compared against an internally adjustable stable reference voltage. Feature List • Reference voltage selectable between internal reference and external reference • Internal reference voltage range: 0 ~ 0.7 * VDDPST • Internal reference voltage supports hysteresis • ETM support • Interrupt output when the measured voltage crosses the reference voltage Pin Assignment The analog voltagecomparator uses dedicated pads and is supported only on GPIO37, GPIO38, GPIO39, and GPIO40. Any of these pads can be configured as the measured-input pad or the reference-input pad. Espressif Systems 38 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 6 Electrical Characteristics 6 Electrical Characteristics 6.1 Absolute Maximum Ratings Stresses above those listed in Table 6-1 Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Table 6-2 Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Table 6-1. Absolute Maximum Ratings Symbol Parameter Min Max Unit VDD33 Power supply voltage –0.3 3.6 V 6.2 Recommended Operating Conditions Table 6-2. Recommended Operating Conditions Symbol Parameter Min Typ Max Unit VDD33 Power supply voltage 3.0 3.3 3.6 V I V DD Current delivered by external power supply 0.8 — — A T A Operating ambient temperature –40 — 85 °C 6.3 DC Characteristics (3.3 V, 25 °C) Table 6-3. DC Characteristics (3.3 V, 25 °C) Parameter Description Min Typ Max Unit C IN Pin capacitance — 2 — pF V IH High-level input voltage 0.75 × VDD 1 — VDD 1 + 0.3 V V IL Low-level input voltage –0.3 — 0.25 × VDD 1 V I IH High-level input current — — 50 nA I IL Low-level input current — — 50 nA V OH 2 High-level output voltage 0.8 × VDD 1 — — V V OL 2 Low-level output voltage — — 0.1 × VDD 1 V I OH High-level source current (VDD 1 = 3.3 V, V OH >= 2.64 V, PAD_DRIVER = 3) — 40 — mA I OL Low-level sink current (VDD 1 = 3.3 V, V OL = 0.495 V, PAD_DRIVER = 3) — 28 — mA R P U Internal weak pull-up resistor — 45 — kΩ R P D Internal weak pull-down resistor — 45 — kΩ Cont’d on next page Espressif Systems 39 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 6 Electrical Characteristics Table 6-3 – cont’d from previous page Parameter Description Min Typ Max Unit V IH_nRST Chip reset release voltage (CHIP_PU voltage is within the specified range) 0.75 × VDD 1 — VDD 1 + 0.3 V V IL_nRST Chip reset voltage (CHIP_PU voltage is within the specified range) –0.3 — 0.15 × VDD 1 V 1 VDD – voltage from a power pin of a respective power domain. 2 V OH and V OL are measured using high-impedance load. Espressif Systems 40 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 7 Module Schematics 7 Module Schematics This is the reference design of the module. IO6 IO7 IO8 IO9 IO10 IO11 IO12 IO35 IO13 IO37 IO38 IO39 IO40 IO42 IO43 IO44 IO45 IO46 IO47ANT IO48 IO49 VREF_TOUCH IO36 VREF_ADC TX0 RX0 IO34 IO33 USB_DP USB_DM IO61 IO60 IO53 IO52 IO51 IO50 XTAL_N XTAL_P SD_D2 SD_D3 SD_CLK SD_CMD IO14 IO15 IO16 IO17 IO18 IO19 SD_D0 SD_D1 EN IO57 IO56 IO55 IO54 IO0 IO1 IO2 IO3 IO4 IO5 SPICS SPID SPICLK SPIHD SPIWP SPIQ RF SPICLK SPICS SPIHD SPID SPIWP SPIQ RF1 RF_ANT EN IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IO9 IO10 IO11 IO12 IO13 IO14 IO15 IO16 IO17 IO18 IO19 SD_D0 SD_D1 SD_D2 SD_D3 SD_CLK SD_CMD USB_DP USB_DM IO33 IO34 IO35 IO36 IO37 IO39 IO40 IO38 IO42 IO43 IO44 IO45 IO46 IO47 IO48 IO49 IO50 IO51 IO52 IO53 IO54 IO55 IO56 IO57 TX0 RX0 IO60 IO61 VDD33 VDD33 GND GNDGNDGND GND GND VDD33 VDD33 GND GND GND GND GND VDD33 GND GND GND GNDGND GND GND VDD33 GND GND VDD33 VDD_SPI GNDGND GND VDD_LDO_1P8 VDD_PSRAM_1P8 GND GND VDD_SPI GND GND GNDGNDGNDGND GND VDD33 GND GND VDD33 GND The values of C3, L1, C4, C7, L2, C8, L5 and C9 vary with the actual PCB board. Single-ended 50ohm QFN80 1: 3.3V flash; 0: 1.8V flash; The values of C1 and C2 vary with the selection of the crystal. The value of L3 varies with the actual PCB board. L3 could be a resistor or inductor. NC: No component. ESP32-S31-WROOM-3 (Pin-out) C13 1uF C12 0.1uF R6 499 R5 0 C22 0.1uF C9 TBD U1 ESP32-S31 ANT 1 GPIO17 24 GPIO18 25 XTAL_32K_P/GPIO1 6 GPIO4 9 GPIO3 8 GPIO2 7 VDDA4 3 GPIO48 61 SDIO_DATA2 29 SPICLK 41 SPID 42 GPIO50 65 XTAL_N 78 XTAL_P 79 GND 81 VDD_LDO_1P8 35 GPIO49 62 VDDA3 2 CHIP_PU 4 XTAL_32K_N/GPIO0 5 GPIO5 10 GPIO6 12 GPIO7 13 GPIO8 14 GPIO14 21 GPIO15 22 GPIO16 23 SDIO_DATA0 27 SDIO_DATA1 28 GPIO33 46 GPIO34 47 GPIO37 50 GPIO38 51 GPIO51 66 MTDO 69 VDDA1 77 VDDPST_1 11 GPIO9 15 VREF_TOUCH 18 GPIO10 16 GPIO11 17 GPIO12 19 GPIO13 20 GPIO19 26 VDD_PSRAM_1P8_1 30 SDIO_DATA3 31 SDIO_CLK 32 SDIO_CMD 33 VDD_PSRAM_1P8_2 34 SPICS 36 SPIQ 37 SPIWP 38 VDD_SPI 39 SPIHD 40 VCCA/VDDPST_2 43 USB_DP 44 USB_DM 45 GPIO35 48 GPIO36 49 GPIO39 52 GPIO40 53 VDDPST_3 54 GPIO42 55 GPIO43 56 GPIO44 57 GPIO45 58 GPIO46 59 GPIO47 60 VREF_ADC 63 VDDPST_4 64 GPIO52 67 GPIO53 68 MTCK 70 MTDI 71 MTMS 72 U0TXD 73 U0RXD 74 GPIO60 75 GPIO61 76 VDDA2 80 C21 1uF R7 10K(NC) C15 10uF C17 0.1uF C2 TBD C25 0.1uF C8 TBD R1 0 C7 TBD R2 0 R9 0 R3 0 C14 0.1uF C6 10nF C24 0.1uF D1 ESD L2 TBD C3 TBD U2 FLASH VDD 8 GND 4 /CS 1 CLK 6 /HOLD 7 /WP 3 DO 2 DI 5 EPAD 9 ESP32-S31-WROOM-3 GND 1 3V3 3 EN 5 IO2 6 IO3 7 IO1 9 IO4 10 EPAD 95 GND 2 GND 99 GND 98 IO0 8 IO6 12 IO7 13 IO9 15 IO10 16 IO11 17 IO12 18 IO13 19 IO14 20 IO15 21 IO16 22 GND 96 IO17 23 IO18 24 IO19 25 SD_D0 27 SD_D1 28 SD_D2 29 SD_D3 30 SD_CLK 31 SD_CMD 32 NC 33 NC 34 NC 35 USB_DP 40 USB_DM 41 IO33 42 IO34 43 IO35 44 IO36 45 IO37 46 IO38 49 IO39 50 IO40 51 IO42 52 IO43 53 IO44 54 IO45 55 IO46 56 IO47 57 IO48 58 GND 72 IO49 59 IO50 60 IO51 61 IO52 62 IO53 63 IO54 64 IO55 65 IO56 66 RX0 69 IO57 67 TX0 68 IO60 70 IO61 71 GND 73 GND 74 GND 75 GND 76 GND 77 GND 78 GND 79 GND 80 GND 81 GND 82 GND 83 GND 84 GND 85 GND 86 GND 87 GND 88 GND 89 GND 90 NC 91 GND 92 GND 93 GND 94 3V3 4 IO5 11 IO8 14 GND 26 GND 47 GND 48 GND 97 NC 36 NC 37 NC 38 NC 39 R11 10K(NC) Y1 40MHz XIN 1 GND 2 XOUT 3 GND 4 C20 0.1uF R10 10K C16 1uF L4 2.0nH(0.1nH)_600mA L5 TBD R8 0 C1 TBD R4 0 C18 0.1uF L1 TBD ANT1 1 2 C23 0.1uF C19 0.1uF C5 1uF C4 TBD C11 0.47uF L3 TBD C10 10uF(NC) Figure 7-1. ESP32-S31-WROOM-3 Schematics Espressif Systems 41 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 8 Peripheral Schematics 8 Peripheral Schematics This is the typical application circuit of the module connected with peripheral components (for example, power supply, antenna, reset button, JTAG interface, and UART interface). IO35 IO36 IO37 IO38 IO39 IO40 IO42 IO43 IO44 IO45 IO46 IO47 IO48 IO49 IO50 IO51 IO52 IO53 IO54 IO55 IO56 IO57 IO61 IO60 RX0 TX0 USB_DP USB_DM USB_D+ USB_D- IO33 IO34 USB DBG D- USB DBG D+ TMS TDI TCK TDO IO3 IO2 IO4 IO5 IO1 IO0 EN IO1 IO0 IO6 IO7 IO8 IO9 IO10 IO11 IO12 IO13 IO14 IO15 IO16 IO17 IO18 IO19 SD_D0 SD_D1 SD_D2 SD_D3 SD_CLK SD_CMD VDD33 GND GND GND GND GND GND GND GND VDD33 GND GND GNDGND VDD33 GND GND X1: ESR = Max. 70 KΩ NC: No component. JP5 JTAG 1 1 2 2 3 3 4 4 R7 TBD C1 22uF R8 TBD C7 TBD R3 0(NC) JP3 Boot Option 1 1 2 2 X1 32.768KHz(NC) 2 1 JP4 UART 1 1 2 2 3 3 4 4 C4 0.1uF C6 12pF(NC) ESP32-S31-WROOM-3 U1 GND 1 3V3 3 EN 5 IO2 6 IO3 7 IO1 9 IO4 10 EPAD 95 GND 2 GND 99 GND 98 IO0 8 IO6 12 IO7 13 IO9 15 IO10 16 IO11 17 IO12 18 IO13 19 IO14 20 IO15 21 IO16 22 GND 96 IO17 23 IO18 24 IO19 25 SD_D0 27 SD_D1 28 SD_D2 29 SD_D3 30 SD_CLK 31 SD_CMD 32 NC 33 NC 34 NC 35 USB_DP 40 USB_DM 41 IO33 42 IO34 43 IO35 44 IO36 45 IO37 46 IO38 49 IO39 50 IO40 51 IO42 52 IO43 53 IO44 54 IO45 55 IO46 56 IO47 57 IO48 58 GND 72 IO49 59 IO50 60 IO51 61 IO52 62 IO53 63 IO54 64 IO55 65 IO56 66 RX0 69 IO57 67 TX0 68 IO60 70 IO61 71 GND 73 GND 74 GND 75 GND 76 GND 77 GND 78 GND 79 GND 80 GND 81 GND 82 GND 83 GND 84 GND 85 GND 86 GND 87 GND 88 GND 89 GND 90 NC 91 GND 92 GND 93 GND 94 3V3 4 IO5 11 IO8 14 GND 26 GND 47 GND 48 GND 97 NC 36 NC 37 NC 38 NC 39 C10 TBD R1 TBD C3 TBD R6 TBD JP2 USB 1 1 2 2 C2 0.1uF R9 TBD R4 0(NC) JP1 USB OTG 1 1 2 2 C5 12pF(NC) C8 TBD R5 NC C9 TBD SW1 R2 0 Figure 8-1. Peripheral Schematics • Soldering the EPAD to the ground of the base board is not a must, however, it can optimize thermal performance. If you choose to solder it, please apply the correct amount of soldering paste. Too much soldering paste may increase the gap between the module and the baseboard. As a result, the adhesion between other pins and the baseboard may be poor. • To ensure that the power supply to the ESP32-S31 chip is stable during power-up, it is advised to add an RC delay circuit at the EN pin. The recommended setting for the RC delay circuit is usually R = 10 kΩ and C = 1 µF. However, specific parameters should be adjusted based on the power-up timing of the module and the power-up and reset sequence timing of the chip. For ESP32-S31’s power-up and reset sequence timing diagram, please refer Section 4.5 Chip Power-up and Reset. Espressif Systems 42 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 9 Module Dimensions 9 Module Dimensions Top view Side view Unit: mm Bottom view Ø0.5 21 23 0.5 0.5 22±0.2 30±0.2 Antenna Area 1 Antenna Area 94 x 0.4 94 x 0.8 4 x 0.8 4 x 0.8 20.4 22.6 17.85 20.6 24 0.85 0.7 0.85 0.7 0.85 1.8 0.55 6.5 1.8 0.55 6.5 1.3 1.3 6 3.5±0.15 Figure 9-1. Physical Dimensions Espressif Systems 43 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 10 PCB Layout Recommendations 10 PCB Layout Recommendations 10.1 PCB Land Pattern This section provides the following resources for your reference: • Figures for recommended PCB land patterns with all the dimensions needed for PCB design. See Figure 10-1 Recommended PCB Land Pattern. Pin 1 Unit: mm : Pad Antenna Area 94 x 0.8 0.85 0.7 22.6 0.85 20.6 6.5 4 x 0.8 0.55 1.3 0.7 0.85 20.4 17.85 1.8 6.5 24 94 x 0.4 1.3 4 x 0.8 0.55 1.8 22 30 : Via for thermal pad Figure 10-1. Recommended PCB Land Pattern 10.2 Module Placement for PCB Design If module-on-board design is adopted, attention should be paid while positioning the module on the base board. The interference of the base board on the module’s antenna performance should be minimized. Espressif Systems 44 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 11 Product Handling 11 Product Handling 11.1 Storage Conditions The products sealed in moisture barrier bags (MBB) should be stored in a non-condensing atmospheric environment of < 40 °C and 90%RH. The module is rated at the moisture sensitivity level (MSL) of 3. After unpacking, the module must be soldered within 168 hours with the factory conditions 25±5 °C and 60%RH. If the above conditions are not met, the module needs to be baked. 11.2 Electrostatic Discharge (ESD) • Human body model (HBM): ±2000 V • Charged-device model (CDM): ±500 V 11.3 Reflow Profile Solder the module in a single reflow. 50 100 0 150 200 250 200 100 50 150 250 Time (s) 217 25 Preheating 150 – 200 °C 60 – 120 s Ramp-up 25 – 150 °C 60 – 90 s 1 – 3 °C/s Soldering ＞ 217 °C 60 – 90 s Peak temperature: 235 – 250 °C Peak time: 30 – 70 s Soldering time: ＞ 30 s Solder: Sn-Ag-Cu (SAC305) lead-free solder Temperature (°C) 180 230 Cooling ＜ 180 °C –5 ~ –1 °C/s Figure 11-1. Reflow Profile Espressif Systems 45 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY 11 Product Handling 11.4 Ultrasonic Vibration Avoid exposing Espressif modules to vibration from ultrasonic equipment, such as ultrasonic welders or ultrasonic cleaners. This vibration may induce resonance in the in-module crystal and lead to its malfunction or even failure. As a consequence, the module may stop working or its performance may deteriorate. Espressif Systems 46 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY Related Documentation and Resources Related Documentation and Resources Related Documentation • ESP32-S31 Series Datasheet- Specifications of the ESP32-S31 hardware. • Certificates https://espressif.com/en/support/documents/certificates • Documentation Updates and Update Notification Subscription https://espressif.com/en/support/download/documents Developer Zone • ESP-IDF Programming Guide for ESP32-S31 – Extensive documentation for the ESP-IDF development framework. • ESP-IDF and other development frameworks on GitHub. https://github.com/espressif • ESP32 BBS Forum – Engineer-to-Engineer (E2E) Community for Espressif products where you can post questions, share knowledge, explore ideas, and help solve problems with fellow engineers. https://esp32.com/ • ESP-FAQ – A summary document of frequently asked questions released by Espressif. https://espressif.com/projects/esp-faq/en/latest/index.html • The ESP Journal – Best Practices, Articles, and Notes from Espressif folks. https://blog.espressif.com/ • See the tabs SDKs and Demos, Apps, Tools, AT Firmware. https://espressif.com/en/support/download/sdks-demos Products • ESP32-S31 Series SoCs – Browse through all ESP32-S31 SoCs. https://espressif.com/en/products/socs?id=ESP32-S31 • ESP32-S31 Series Modules – Browse through all ESP32-S31-based modules. https://espressif.com/en/products/modules?id=ESP32-S31 • ESP32-S31 Series DevKits – Browse through all ESP32-S31-based devkits. https://espressif.com/en/products/devkits?id=ESP32-S31 • ESP Product Selector – Find an Espressif hardware product suitable for your needs by comparing or applying filters. https://products.espressif.com/#/product-selector?language=en Contact Us • See the tabs Sales Questions, Technical Enquiries, Circuit Schematic & PCB Design Review, Get Samples (Online stores), Become Our Supplier, Comments & Suggestions. https://espressif.com/en/contact-us/sales-questions Espressif Systems 47 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY Revision History Revision History Date Version Release notes 2026-05-21 v0.1 Draft Espressif Systems 48 Submit Documentation Feedback ESP32-S31-WROOM-3 Datasheet v0.1 PRELIMINARY Disclaimer and Copyright Notice Information in this document, including URL references, is subject to change without notice. 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