About This Document Table of Contents 1. Design Changes in Chip Revision v3.x1. Design Changes in Chip Revision v3.x 1.1. High-Performance CPU 1.2. RISC-V Trace Encoder 1.3. GDMA Controller 1.4. 2D-DMA Controller 1.5. System and Memory 1.6. GPIO Matrix and IO MUX 1.7. eFuse Controller 1.8. Reset and Clock 1.9. Interrupt Matrix 1.10. Low-power Management 1.11. Permission Control 1.12. System Registers 1.13. Brown-out Detector 1.14. AES Accelerator and External Memory Encryption and Decryption 1.15. ECC Accelerator and ECDSA Digital Signature Peripheral 1.16. HMAC Accelerator 1.17. Key Manager 1.18. Random Number Generator 1.19. JPEG Codec 1.20. Image Signal Processor 1.21. Pixel-Processing Accelerator 1.22. LCD and Camera Controller 1.23. H264 Encoder 1.24. MIPI DSI 1.25. I2S Controller 1.26. USB 2.0 High-Speed OTG 1.27. Parallel IO Controller 1.28. Touch Sensor 2. Impact on Customer Projects2. Impact on Customer Projects 2.1. Use Case 1: Hardware and Software Upgrade 2.1.1. Hardware Design Changes 2.1.2. Software Design Changes 3. Label Specification3. Label Specification 4. Ordering Information4. Ordering Information 5. Related Documents5. Related Documents ESP32-P4 Chip Revision v3.x User Guide v1.1 Related Product: ESP32-P4NRW16X ESP32-P4NRW32X www.espressif.com About This Document This document describes differences between chip revision v3.x and previous ESP32-P4 chip revisions. Release Notes Documentation Change Notification Espressif provides email notifications to keep customers updated on changes to technical documentation. Please subscribe at https://documentation.espressif.com/en/subscriptions. Certification Download certificates for Espressif products from https://www.espressif.com/en/support/ documents/certificates. Date Version Release Notes 2026.08 v1.1 Section Design Changes in Chip Revision v3.x: added eFuse Controller, System Registers, and MIPI DSI. Improved the formatting. 2026.03 v1.0 First release. Table of Contents 1. Design Changes in Chip Revision v3.x 1 1.1. High-Performance CPU 1 1.2. RISC-V Trace Encoder 2 1.3. GDMA Controller 2 1.4. 2D-DMA Controller 2 1.5. System and Memory 2 1.6. GPIO Matrix and IO MUX 2 1.7. eFuse Controller 2 1.8. Reset and Clock 3 1.9. Interrupt Matrix 3 1.10. Low-power Management 3 1.11. Permission Control 3 1.12. System Registers 3 1.13. Brown-out Detector 4 1.14. AES Accelerator and External Memory Encryption and Decryption 4 1.15. ECC Accelerator and ECDSA Digital Signature Peripheral 4 1.16. HMAC Accelerator 4 1.17. Key Manager 4 1.18. Random Number Generator 4 1.19. JPEG Codec 4 1.20. Image Signal Processor 4 1.21. Pixel-Processing Accelerator 5 1.22. LCD and Camera Controller 5 1.23. H264 Encoder 5 1.24. MIPI DSI 5 1.25. I2S Controller 6 1.26. USB 2.0 High-Speed OTG 6 1.27. Parallel IO Controller 6 1.28. Touch Sensor 6 2. Impact on Customer Projects 7 2.1. Use Case 1: Hardware and Software Upgrade 7 3. Label Specification 8 4. Ordering Information 9 5. Related Documents 10 1. Design Changes in Chip Revision v3.x Espressif has released ESP32-P4 chip revision v3.x that features wafer-level changes basing on previous ESP32-P4 chip revision v1.x. The design changes introduced on the ESP32-P4 chip revision v3.x are as below. The following bugs are fixed. For details, please refer to ESP32-P4 Series SoC Errata. [MSPI-749] Load Access Fault During Chip Power-on or Deep-Sleep Wake-up. [MSPI-750] PSRAM Unaligned DMA Read Operations May Return Old Data When Accessing Overlapping Addresses. [MSPI-751] Data Errors Caused by Asynchronous Timing Issues in the MSPI Address Overlap Detection Function When Read/Write Operations Overlap at Specific Frequencies. [ROM-764] Secure Boot Verification Failure Caused by Incorrect Buffer Address in ROM. [Analog-765] Output Regulators Cannot Generate a Reliable Supply When Peripheral Power Domain Is Off. [DMA-767] DMA Channel 0 Transaction ID Overlap Causes Permission Management Issue. [APM-560] Unauthorized AHB Access May Block Subsequent PSRAM or Flash Transactions. [ROM-770] Secure Download Mode Flash Power-On Failure. The following modules are updated. For details, please refer to the specific chapter in ESP32-P4 Technical Reference Manual. 1.1. High-Performance CPU Upgraded the HP system’s dual-core RISC-V processor, increasing the max frequency from 360 MHz to 400 MHz. Fixed EXT_ILL_CSR bit 0 not updating for FPU Load/Store and FPU CSR instructions. Improved CLIC CSR access latency and compliance. Fixed bugs in trace, trigger, and HW loop logic. Improved dynamic clock-gating to reduce power consumption. Increased PMP entry count to 32. Added support for Bitwise-Manipulation extension (Zb). Improved PMP lock bit behavior. Added support for interrupt delegation to user mode. • • • • • • • • • • • • • • • • • 1. Design Changes in Chip Revision v3.x Espressif 1 / 11 Submit Documentation Feedback 2026.08 Added core mode and interrupt delegation status signals to interrupt matrix. Updated PIE for saturation and rounding. Added pad_cpu_wakeup_event input port to CPU. Changed HW loop counter width to 24 bits. 1.2. RISC-V Trace Encoder Added TRACE_CORE_WAITI bit in TRACE_DATA_REG to indicate whether the HP CPU cores are in WFI (wait-for-interrupt) state. 1.3. GDMA Controller Updated GDMA-AXI to support interrupt response during circular linked-list switching. Updated arbitration scheme to resolve false arbitration issues. Added error response logging for GDMA-AHB transfers, including address, channel ID, peripheral ID, and access type. Added clock gating for each GDMA-AHB channel, with a register option to force the clock on. Added support for INCR4/8/16 burst types; registers remain backward compatible. Added clarification that GDMA-AHB supports memory-to-memory data transfer only on channels 1 and 2. 1.4. 2D-DMA Controller Expanded PPA block size to 32 × 32 and widened related registers. Increased channel count to 4 TX and 3 RX. Updated reorder logic to support JPEG output conversion from YUV444/422 to YUV420. 1.5. System and Memory Changed cached region mapping to start from the bottom of L2MEM rather than the top. 1.6. GPIO Matrix and IO MUX Added IO hold during Deep-sleep for all IOs. Routed EMAC PPS signal to GPIO matrix. Routed parallel TX_CS signal to GPIO matrix. 1.7. eFuse Controller Added a dedicated EFUSE_ECDSA_REG to configure and read back the eFuse block that stores the ECDSA key, separately for P-192, P-256, and P-384 (high and low blocks). • • • • • • • • • • • • • • • • • • • 1. Design Changes in Chip Revision v3.x Espressif 2 / 11 Submit Documentation Feedback 2026.08 1.8. Reset and Clock Added a new register HP_SYS_CLKRST_CPU_WAITI_CTRL0_REG. Added 160 MHz clock source to I2S. 1.9. Interrupt Matrix Enhanced Interrupt Matrix with interrupt remapping support, allowing user-mode delegated interrupts to be routed to the machine-mode interrupt port when the core runs in machine mode. Added core mode and delegate mode output signals from CPU to support remapping functionality. Added new peripheral interrupts. Added permission control to interrupt registers. 1.10. Low-power Management Added flash power quick discharge feature to enable faster ramp-up/down of the flash power supply, improving compatibility with a wider range of flash chips. Enabled wake-up via any interrupt when the TOP power domain remains powered during sleep; supported interrupts are configurable through a mask register located in the TOP domain. Added a power switch to fully power down the PUF memory. Optimized Light-sleep power consumption by adding a CPU power domain and updating memory retention modes. Enhanced power stability during Light-sleep using PVT monitoring to guard against power glitches. Removed debug probe port. 1.11. Permission Control Increased the number of configurable address ranges from 2 to 8 in PERI APM. Added permission control for TRNG. 1.12. System Registers Added HP_SYSTEM_USB_OTGHS_PHY_ST_REG to represent USB OTGHS PHY status. Added HP_SYSTEM_HP_CPU_WAKEUP_EVENT_REG to wake up HP CPU0 or HP CPU1. Added grouped HP-to-LP interrupt and wakeup control (GROUP0–3 enable, status, and wakeup registers) to route HP-domain peripheral events to the LP CPU and PMU. • • • • • • • • • • • • • • • • • 1. Design Changes in Chip Revision v3.x Espressif 3 / 11 Submit Documentation Feedback 2026.08 Added LP_SYSTEM_USBOTG20_LS_MODE to configure USB OTG2.0 Low-speed mode. Added LP_SYSTEM_HP_USB_OTGHS_PHY_CTRL_REG to control USB OTGHS PHY pull- up and pull-down signals. Added pad hold control: during sleep or reset, pads 0–56 can be held via LP_SYSTEM_PAD_RTC_HOLD_CTRL0_REG and LP_SYSTEM_PAD_RTC_HOLD_CTRL1_REG, and flash and PSRAM pads via LP_SYSTEM_DED_PAD_RTC_HOLD_CTRL_REG. Added LP_SYSTEM_DISCHARGE_REG to control discharge of LDO flash and LP PUF memory. 1.13. Brown-out Detector Modified the voltage threshold. 1.14. AES Accelerator and External Memory Encryption and Decryption Added the pseudo-round function to enhance resistance against DPA attacks. 1.15. ECC Accelerator and ECDSA Digital Signature Peripheral Added P-384 curve support. 1.16. HMAC Accelerator Added support for selecting key from key manager. 1.17. Key Manager Added support for HMAC and RSA_DS keys, and separated XTS keys into flash and PSRAM keys. 1.18. Random Number Generator Added separate RNG module. Added permission control bit for it in APM. 1.19. JPEG Codec Improved timing performance. Added one register to support extra color space. 1.20. Image Signal Processor Added BLC. • • • • • • • • • • • • • • 1. Design Changes in Chip Revision v3.x Espressif 4 / 11 Submit Documentation Feedback 2026.08 Added DPC. Added White Balance Gain (WBG). Updated AWB window (5 × 5 sub-windows). Added CROP. Updated CCM gain bit-width. Updated hue range from 0–255 to 0–359. Added shadow register. Enhanced the ISP CAM module to support HREF input functionality. Added RGB888-to-RGB565 and YUV422-to-YUV420 conversion before receiving pixel from MIPI CSI. Added 8-bit/16-bit byte swapping before receiving pixel from MIPI CSI. Added DMA flow control support in csi_bridge. 1.21. Pixel-Processing Accelerator Expanded SRM block size support up to 32 × 32. Added YUV422 and GRAY format support for SRM. Added YUV422/YUV420/GRAY support for BLEND input background and output. 1.22. LCD and Camera Controller Added byte swap support for CAM input. Updated CAM color mode conversion: removed YUV420 input support and changed conversion logic from RGB to YUV420. Increased LCD AFIFO depth to 32. 1.23. H264 Encoder Changed H264 core bitstream overflow status register into an interrupt source. Added support for multiple input color spaces in H264 core (also supported by H264 DMA). Added debug register. 1.24. MIPI DSI Updated PHY reference clock; added APLL as a new clock source. Enhanced color mode conversion with support for RGB888, RGB666, and RGB565 conversions. Added YUV420 format support. • • • • • • • • • • • • • • • • • • • • • • • 1. Design Changes in Chip Revision v3.x Espressif 5 / 11 Submit Documentation Feedback 2026.08 Added DPI clock source. Added support for grayscale images. 1.25. I2S Controller Added 160 MHz clock source. 1.26. USB 2.0 High-Speed OTG Updated configuration to meet application requirements. Added description: up to 8 non-periodic transactions and 16 periodic transactions per microframe. 1.27. Parallel IO Controller Added a separate VALID/CS signal. The CS signal no longer controls data transmission. 1.28. Touch Sensor Modified the touch active detection method. Fixed the bug for updating baseline by software. • • • • • • • • 1. Design Changes in Chip Revision v3.x Espressif 6 / 11 Submit Documentation Feedback 2026.08 2. Impact on Customer Projects This section is intended to help our customers to understand the impact of using chip revision v3.x in a new design or replacing older version SoC with chip revision v3.x in existing design. 2.1. Use Case 1: Hardware and Software Upgrade 2.1.1. Hardware Design Changes For chip revisions v3.0 and later versions, the pin 54 is changed from NC to VDD_HP_1. A 1 MΩ resistor has been removed from the USB_DP pin. Two 499 kΩ resistors and one 22 pF capacitor are added in the DCDC circuit. For details, please refer to the latest ESP32-P4 Hardware Design Guidelines. 2.1.2. Software Design Changes When using ESP32-P4 chip revision v3.x, you must upgrade ESP-IDF to v5.5.3 or later, or v6.0 or later, and rebuild the firmware. These ESP-IDF versions introduce a new configuration option in sdkconfig: CONFIG_ESP32P4_SELECTS_REV_LESS_V3 This option specifies which chip revision the compiled firmware targets: y: Targets v1.x chips n: Targets v3.x chips (default value) If you previously developed your project using an intermediate ESP-IDF version, your project configuration may already contain: CONFIG_ESP32P4_SELECTS_REV_LESS_V3=y This setting will cause the firmware to either fail to download to a v3.x chip, or fail to boot properly after flashing. If you encounter this issue, manually change the option to: CONFIG_ESP32P4_SELECTS_REV_LESS_V3=n Then rebuild the firmware. Chip revision v3.1 includes memory architecture adjustments and more than 50 hardware and register changes (including ISP, CPU, L2MEM, MSPI, security modules, etc.). Therefore, v1.x and v3.x chips cannot share the same firmware image. The target chip revision must be explicitly specified for compilation. If your product line includes both v1.x and v3.x chips, you must build separate firmware images for each revision. • • 2. Impact on Customer Projects Espressif 7 / 11 Submit Documentation Feedback 2026.08 3. Label Specification Figure 3-1. The label of ESP32-P4NRW16X Figure 3-2. The label of ESP32-P4NRW32X The figures above show the chip marking of chip revision v3.1: its manufacturing code is XGXX. For chip revision identification by chip marking, please refer to ESP32-P4 Series SoC Errata. 3. Label Specification Espressif 8 / 11 Submit Documentation Feedback 2026.08 4. Ordering Information For product ordering, please refer to: ESP Product Selector. 4. Ordering Information Espressif 9 / 11 Submit Documentation Feedback 2026.08 5. Related Documents ESP32-P4 Datasheet ESP32-P4 Technical Reference Manual ESP32-P4 Hardware Design Guidelines ESP32-P4 Series SoC Errata ESP32-P4 Development Board User Guide • • • • • 5. Related Documents Espressif 10 / 11 Submit Documentation Feedback 2026.08 Disclaimer and Copyright Notice Information in this document, including URL references, is subject to change without notice. ALL THIRD PARTY'S INFORMATION IN THIS DOCUMENT IS PROVIDED AS IS WITH NO WARRANTIES TO ITS AUTHENTICITY AND ACCURACY. NO WARRANTY IS PROVIDED TO THIS DOCUMENT FOR ITS MERCHANTABILITY, NON-INFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, NOR DOES ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE. All liability, including liability for infringement of any proprietary rights, relating to use of information in this document is disclaimed. No licenses express or implied, by estoppel or otherwise, to any intellectual property rights are granted herein. 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