I Microprocessor and Master1 High-Performance CPU1.1 Overview1.2 Features1.3 Terminology1.4 Address Map1.5 Configuration and Status Registers (CSRs)1.5.1 Register Summary1.5.2 Register Description1.6 RISC-V Standard ISA Extensions Support1.6.1 M Extension1.6.1.1 Overview1.6.1.2 Functional Description1.6.2 C Extension1.6.2.1 Overview1.6.2.2 Functional Description1.6.3 F Extension1.6.3.1 Overview1.6.3.2 Functional Description1.6.3.3 Initialization1.6.4 Zc (Z) Extension1.6.4.1 Overview1.6.4.2 Functional Description1.6.4.3 Zc Instructions1.6.4.4 Limitations1.6.5 A Extension1.6.5.1 Overview1.6.5.2 Functional Description1.6.5.3 Load-Reserve (LR.W) Instruction1.6.5.4 Store-Conditional (SC.W) Instruction1.6.5.5 AMO Instructions1.7 Custom Instruction Extensions1.7.1 Hardware Loop1.7.1.1 Overview1.7.1.2 Features1.7.1.3 Functional Description1.7.1.4 Instructions/Operations/Modes Supported in HWLP1.7.1.5 HWLP Constraints1.7.1.6 Register Summary1.7.1.7 Register Description1.7.1.8 HWLP Instructions1.7.2 Processor Instruction Extension1.7.2.1 Overview1.7.2.2 Functional Description1.7.2.3 Initialization, Context Switching, and Exceptions1.8 Memory-Mapped Registers1.8.1 Overview1.8.2 Features1.8.3 Functional Description1.9 Interrupt Controller1.9.1 Overview1.9.2 CLIC1.9.2.1 Overview1.9.2.2 CLIC CSRs1.9.2.3 Interrupt Mapping1.9.2.4 CLIC Parameters1.9.2.5 Interrupt Level and Priority Encoding1.9.2.6 CLIC Memory-Mapped Register Summary1.9.2.7 CLIC Memory-Mapped Register Description1.9.3 Core-Local Interrupts (CLINT)1.9.3.1 Overview1.9.3.2 Features1.9.3.3 Software Interrupt1.9.3.4 Timer Counter and Interrupt1.9.3.5 Register Summary1.9.3.6 Register Description1.10 Memory Protection Unit1.10.1 Standard Physical Memory Protection1.10.1.1 Overview1.10.1.2 Features1.10.1.3 Functional Description1.10.1.4 Register Summary1.10.1.5 Register Description1.10.2 Custom Physical Memory Attribute (PMA) Checker1.10.2.1 Overview1.10.2.2 Features1.10.2.3 Functional Description1.10.2.4 Register Summary1.10.2.5 Register Description1.11 Debug and Trace Support1.11.1 Debug1.11.1.1 Overview1.11.1.2 Features1.11.1.3 Functional Description1.11.1.4 JTAG Control1.11.1.5 Register Summary1.11.1.6 Register Description1.11.2 Debug Halt Groups1.11.2.1 Overview1.11.2.2 Features1.11.2.3 Functional Description1.11.2.4 Register Summary1.11.2.5 Register Description1.11.3 Hardware Trigger1.11.3.1 Overview1.11.3.2 Features1.11.3.3 Functional Description1.11.3.4 Trigger Execution Flow1.11.3.5 Register Summary1.11.3.6 Register Description1.11.4 Trace1.11.4.1 Overview1.11.4.2 Features1.11.4.3 Functional Description1.12 Performance1.12.1 Branch Prediction1.12.1.1 Overview1.12.1.2 Features1.12.1.3 Functional Description1.12.2 RAS1.12.2.1 Overview1.12.2.2 Features1.12.2.3 Functional Description1.12.3 Control Status Register for Performance Configuration1.13 Custom Features1.13.1 Bus Error Response1.13.1.1 Overview1.13.1.2 Functional Description1.13.1.3 Control Status Registers1.13.2 Dedicated IO1.13.2.1 Overview1.13.2.2 Features1.13.2.3 Functional Description1.13.2.4 Register Summary1.13.2.5 Register Description1.13.3 RunStall Support1.13.3.1 Overview1.13.3.2 Functional Description1.13.3.3 Register Summary1.13.4 Debug Assist Information1.13.5 Core Lock-up1.13.5.1 Overview1.13.5.2 Functional Description1.13.5.3 Register Summary1.13.5.4 Register Description2 RISC-V Trace Encoder (TRACE)2.1 Terminology2.2 Introduction2.3 Features2.4 Architectural Overview2.5 Functional Description2.5.1 Synchronization2.5.2 Address Mode2.5.3 Optional Sideband Signals2.5.4 Filtering2.5.5 Anchor Tag2.5.6 Memory Writing Mode2.5.7 Automatic Restart2.6 Encoder Output Packets2.6.1 Header2.6.2 Index2.6.3 Payload2.6.3.1 Format 3 Packets2.6.3.2 Format 2 Packets2.6.3.3 Format 1 Packets2.7 Interrupt2.8 Programming Procedures2.8.1 Encoder Option Configuration2.8.2 Filter Configuration2.8.3 Enable Encoder2.8.4 Disable Encoder2.8.5 Notify2.8.6 Decode Data Packets2.8.7 AHB Configuration2.8.8 Software Retention2.9 Register Summary2.10 Registers3 Low-Power CPU3.1 Overview3.2 Features3.3 Configuration and Status Registers (CSRs)3.3.1 Register Summary3.3.2 Registers3.4 Interrupts and Exceptions3.4.1 Interrupts3.4.2 Interrupt Handling3.4.3 Exceptions3.5 Debugging3.5.1 Features3.5.2 Functional Description3.5.3 Register Summary3.5.4 Registers3.6 Hardware Trigger3.6.1 Features3.6.2 Functional Description3.6.3 Trigger Execution Flow3.6.4 Register Summary3.6.5 Registers3.7 Performance Counter3.8 System Access3.8.1 Memory Access3.8.2 Peripheral Access3.9 Event Task Matrix Feature3.10 Sleep and Wake-Up Process3.10.1 Features3.10.2 Process3.10.3 Wake-Up Sources3.10.4 Sleep RejectionII System DMA4 GDMA Controller (GDMA-AHB, GDMA-AXI)4.1 Overview4.2 Features4.3 Architecture4.4 Functional Description4.4.1 Linked List4.4.2 Peripheral-to-Memory and Memory-to-Peripheral Data Transfer4.4.3 Memory-to-Memory Data Transfer4.4.4 Enabling GDMA4.4.5 Linked List Reading Process4.4.6 EOF4.4.7 Accessing Memory4.4.8 Arbitration4.4.9 CRC Calculation4.5 Event Task Matrix Feature4.6 Interrupts4.7 Programming Procedures4.7.1 Programming Procedures for GDMA's Transmit Channel4.7.2 Programming Procedures for GDMA's Receive Channel4.7.3 Programming Procedures for Memory-to-Memory Transfer4.7.4 Programming Procedures for Channel Priority and Weight4.7.5 Programming Procedures for CRC Calculation4.8 Register Summary4.8.1 GDMA-AHB Register Summary4.8.2 GDMA-AXI Register Summary4.9 Registers4.9.1 GDMA-AHB Registers4.9.2 GDMA-AXI Registers5 VDMA Controller (VDMA)5.1 Overview5.2 Terminology5.3 Features5.4 Architectural Overview5.5 Functional Description5.5.1 Transfer Hierarchy5.5.2 Arbitration Scheme5.5.2.1 Read Arbiter5.5.2.2 Write Arbiter5.5.3 Handshaking Interface5.5.4 Transfer Control5.5.4.1 Single-Block Transfer5.5.4.2 Multi-Block Transfer5.5.5 Flow Controller5.5.6 Channel Suspend and Resume5.5.7 Channel Disable5.5.7.1 Disabling a Suspended Channel Before Transfer Completion5.5.7.2 Disabling a Non-suspended Channel Before Transfer Completion5.5.8 Low-Power Technique5.5.8.1 Low-Power Technique for DMA Channels5.5.8.2 Low-Power Technique for Slave Bus Interface5.5.8.3 Low-Power Technique for AXI Master Interface Channels5.5.8.4 Global Low-Power Technique5.6 Interrupts5.7 Programming Procedures5.7.1 Common Programming Procedures5.7.2 Programming Procedures for Shadow-Register-Based Multi-Block Transfer5.7.3 Programming Procedures for Linked-List-Based Multi-Block Transfer5.7.4 Programming Procedures for Single-Block Transfer5.8 Register Summary5.9 Registers6 2D-DMA Controller (2D-DMA)6.1 Overview6.2 Features6.3 Architecture6.4 Functional Description6.4.1 Transfer Mode6.4.2 Linked List6.4.3 Padding in 2D-MOD1 Mode and DSCR-PORT Mode6.4.4 Peripheral-to-Memory and Memory-to-Peripheral Data Transfer6.4.5 Memory-to-Memory Data Transfer6.4.6 Macroblock Reordering6.4.6.1 Macroblock Reordering in TX Direction6.4.6.2 Macroblock Reordering in RX Direction6.4.7 Color Space Conversion6.4.8 Enabling 2D-DMA6.4.9 Linked List Reading Process6.4.10 EOF6.4.11 Accessing Memory6.4.12 Arbitration6.5 Event Task Matrix Feature6.6 Interrupts6.7 Programming Procedures6.7.1 General Configurations for 2D-DMA6.7.2 Mode-Specific Configurations for 2D-DMA6.7.3 Configurations for 2D-DMA's Transmit Channel6.7.4 Configurations for 2D-DMA's Receive Channel6.7.5 Configurations for Memory-to-Memory Transfer6.7.6 Configurations for Channel Priority and Weight6.7.7 Resetting 2D-DMA While it Runs6.8 Register Summary6.9 RegistersIII Memory Organization7 System and Memory7.1 Overview7.2 Features7.3 Functional Description7.3.1 Address Mapping7.3.2 Internal Memory7.3.3 External Memory7.3.3.1 External Memory Address Mapping7.3.3.2 Cache7.3.3.3 Cache Operations7.3.4 DMA Address Space7.3.5 Modules/Peripherals Address Mapping8 eFuse Controller (EFUSE)8.1 Overview8.2 Features8.3 Functional Description8.3.1 Structure8.3.1.1 [fielddesc:EFUSEWRDIS]EFUSE_WR_DIS8.3.1.2 [fielddesc:EFUSERDDIS]EFUSE_RD_DIS8.3.1.3 Data Storage8.3.2 Programming of Parameters8.3.3 Reading of Parameters by Users8.3.4 eFuse VDDQ Timing8.3.5 Parameters Used by Hardware Modules8.4 Interrupts8.5 Register Summary8.6 RegistersIV System Component9 GPIO Matrix and IO MUX9.1 Overview9.2 Features9.2.1 HP GPIO Matrix and HP IO MUX9.2.2 LP GPIO Matrix and LP IO MUX9.3 Architectural Overview9.4 Peripheral Input via GPIO Matrix9.4.1 Overview9.4.2 Signal Synchronization9.4.3 GPIO Filter9.4.4 Glitch Filter9.4.5 Simple GPIO Input9.4.6 GPIO Wakeup9.4.6.1 HP GPIO Wakeup9.4.6.2 LP GPIO Wakeup9.4.7 Programming Procedure9.4.7.1 HP GPIO Matrix9.4.7.2 LP GPIO Matrix9.5 Peripheral Output via GPIO Matrix9.5.1 Overview9.5.2 Simple GPIO Output9.5.3 Sigma Delta Modulated Output (SDM)9.5.3.1 Functional Description9.5.3.2 SDM Configuration9.5.4 Programming Procedure9.5.4.1 HP GPIO Matrix9.5.4.2 LP GPIO Matrix9.6 Direct Input and Output via IO MUX9.6.1 Overview9.6.2 Functional Description9.6.2.1 HP IO MUX9.6.2.2 LP IO MUX9.7 Analog Functions9.7.1 Overview9.7.2 Analog Functions9.8 Pin Functions in Light-sleep9.9 Pin Hold Feature9.10 Hysteresis Characteristics of GPIO Pins9.11 Power Supplies and Management of GPIO Pins9.11.1 Power Supplies of GPIO Pins9.11.2 Power Supply Management9.12 HP Peripheral Signal List9.13 LP Peripheral Signal List9.14 HP IO MUX Functions List9.15 LP IO MUX Functions List9.16 GPIO Pin Analog Functions List9.17 Event Task Matrix Function9.18 Interrupts9.19 Register Summary9.19.1 HP GPIO Matrix Register Summary9.19.2 HP IO MUX Register Summary9.19.3 GPIO EXT Register Summary9.19.4 LP GPIO Matrix Register Summary9.19.5 LP IO MUX Register Summary9.20 Registers9.20.1 HP GPIO Matrix Registers9.20.2 HP IO MUX Registers9.20.3 GPIO EXT Registers9.20.4 LP GPIO Matrix Registers9.20.5 LP IO MUX Registers10 Reset and Clock10.1 Reset10.1.1 Overview10.1.2 Architectural Overview10.1.3 Features10.1.4 Functional Description10.1.5 Peripheral Reset10.2 Clock10.2.1 Overview10.2.2 Architectural Overview10.2.3 Features10.2.4 Functional Description10.2.4.1 HP System Clock10.2.4.2 LP System Clock10.2.4.3 Peripheral Clocks10.3 Programming Procedures10.3.1 HP System Clock Configuration10.3.2 LP System Clock Configuration10.3.3 Peripheral Clock Reset and Configuration10.4 Register Summary10.4.1 Reset and Clock (HP_SYS_CLKRST) Register Summary10.4.2 LP Always on Clock and Reset (LP_CLKRST) Register Summary10.4.3 LP Peripheral Clock and Reset (LPPERI) Register Summary10.5 Registers10.5.1 Reset and Clock (HP_SYS_CLKRST) Registers10.5.2 LP Always on Clock and Reset (LP_CLKRST) Registers10.5.3 LP Peripheral Clock and Reset (LPPERI) Registers11 Chip Boot Control11.1 Overview11.2 Functional Description11.2.1 Default Configuration11.2.2 Boot Mode Control11.2.3 ROM Messages Printing Control11.2.4 JTAG Signal Source Control12 Interrupt Matrix12.1 Overview12.2 Interrupt Terminology in ESP32-P412.2.1 Interrupt12.2.2 Interrupt Signal/interrupt Source12.2.3 Interrupt Flow in ESP32-P412.3 Features12.4 Functional Description12.4.1 Peripheral Interrupt Sources12.4.2 Assign Peripheral Interrupt Source to HP CPU Interrupt12.4.2.1 Assign One Peripheral Interrupt Source (Source_Y) to HP CPUx12.4.2.2 Assign Multiple Peripheral Interrupt Sources (Source_Y) to HP CPUx12.4.2.3 Disable HP CPUx Peripheral Interrupt Source (Source_x)12.4.3 Query Current Interrupt Status of HP CPUx Peripheral Interrupt Source12.5 Register Summary12.5.1 HP CPU0 Interrupt Matrix Register Summary12.5.2 HP CPU1 Interrupt Matrix Register Summary12.6 Registers12.6.1 HP CPU0 Interrupt Matrix Registers12.6.2 HP CPU1 Interrupt Matrix Registers13 Event Task Matrix (ETM)13.1 Overview13.2 Features13.3 Functional Description13.3.1 Architecture13.3.2 Events13.3.3 Tasks13.3.4 Event and Task Status13.3.5 Timing Considerations13.3.6 Channel Control13.4 Register Summary13.5 Registers14 Low-Power Management14.1 Overview14.2 Terminology14.3 Features14.4 Functional Description14.4.1 Power Scheme14.4.1.1 Regulators14.4.1.2 Digital Power Domains14.4.1.3 Analog Power Domains14.4.1.4 Battery Power Domain14.4.2 PMU14.4.2.1 PMU Main State Machine14.4.2.2 Sleep/Wake-up Controller14.4.2.3 Analog Power Controller14.4.2.4 Digital Power Controller14.4.2.5 Clock Controller14.4.2.6 Backup Controller14.4.2.7 System Controller14.4.2.8 Battery Power Controller14.4.2.9 Output Regulator Control14.4.2.9.1 Regulator Features14.4.2.9.2 Regulator Configuration Examples14.4.2.9.3 Software Configuration Steps14.5 Power Modes14.6 Event Task Matrix Feature14.7 Interrupts14.8 Register Summary14.9 Registers15 System Timer15.1 Overview15.2 Features15.3 System Timer Structure15.4 Clock Source Selection15.5 Functional Description15.5.1 Counter15.5.2 Comparator and Alarm15.5.3 Event Task Matrix15.5.4 Synchronization Operation15.6 Interrupts15.7 Programming Procedure15.7.1 Read Current Count Value15.7.2 Configure a One-Time Alarm in Target Mode15.7.3 Configure Periodic Alarms in Period Mode15.7.4 Update After Light-sleep15.8 Register Summary15.9 Registers16 Timer Group (TIMG)16.1 Overview16.2 Features16.3 Functional Description16.3.1 16-bit Prescaler and Clock Selection16.3.2 54-bit Time-base Counter16.3.3 Alarm Generation16.3.4 Timer Reload16.3.5 Event Task Matrix Feature16.3.6 RTC_SLOW_CLK Frequency Calculation16.3.7 Interrupts16.4 Configuration and Usage16.4.1 Timer as a Simple Clock16.4.2 Timer as One-shot Alarm16.4.3 Timer as Periodic Alarm by APB16.4.4 Timer as Periodic Alarm by ETM16.4.5 RTC_SLOW_CLK Frequency Calculation16.5 Register Summary16.6 Registers17 Watchdog Timers (WDT)17.1 Overview17.2 Digital Watchdog Timers17.2.1 Features17.2.2 Functional Description17.2.2.1 Clock Source and 32-Bit Counter17.2.2.2 Stages and Timeout Actions17.2.2.3 Write Protection17.2.2.4 Flash Boot Protection17.3 Super Watchdog17.3.1 Features17.3.2 Super Watchdog Controller17.3.2.1 Structure17.3.2.2 Workflow17.4 Interrupts17.5 Register Summary17.6 Registers18 RTC Timer18.1 Introduction18.2 Feature List18.3 Functional Description18.4 Event Task Matrix Feature18.5 Interrupts18.6 Register Summary18.7 Registers19 Permission Control (PMS)19.1 Overview19.2 Features19.3 Functional Description19.3.1 Architecture19.3.2 Address Ranges and Permissions Management19.3.2.1 Address Ranges Managed by HP APM and LP APM19.3.2.2 Address Ranges Managed by DMA APM19.4 Programming Procedure19.4.1 Configuring Access Permissions for HP CPU0/119.4.2 Configuring Access Permissions for LP CPU19.4.3 Configuring Access Permission for DMA Masters19.5 Illegal Access and Interrupts19.6 Register Summary19.6.1 HP_DMA_PMS_REG19.6.2 HP_PERI_PMS_REG19.6.3 LP2HP_PERI_PMS_REG19.6.4 LP_PERI_PMS_REG19.6.5 HP2LP_PERI_PMS_REG19.7 Registers19.7.1 HP_DMA_PMS_REG19.7.2 HP_PERI_PMS_REG19.7.3 LP2HP_PERI_PMS_REG19.7.4 LP_PERI_PMS_REG19.7.5 HP2LP_PERI_PMS_REG20 System Registers (SYSREG)20.1 Overview20.2 Function Description20.2.1 HP System Registers20.2.1.1 External Memory Encryption/Decryption Configuration20.2.1.2 HP Peripherals Clock Configuration and Power Control20.2.1.3 HP Cache Clock and Reset Configuration20.2.1.4 HP SPM and HP L2MEM Clock Configuration20.2.1.5 HP SPM Parity Check Configuration20.2.1.6 HP L2MEM ECC Check Configuration20.2.1.7 BitScrambler Configuration20.2.1.8 Ethernet MAC Control20.2.1.9 USB OTG 2.0 Control20.2.1.10 CPU Control and Record20.2.1.11 HP GPIO Hold Control20.2.1.12 HP GPIO Output Control20.2.1.13 Illegal Access and Unauthorized Access20.2.1.14 HP CPU Bus Timeout Protection20.2.1.15 AXI Matrix20.2.1.16 Post Write20.2.2 LP System Registers20.2.2.1 LP Timer Stall Control20.2.2.2 Focused Ion Beam (FIB) Control20.2.2.3 Boot Mode20.2.2.4 LP CPU Control20.2.2.5 Reset Control20.2.2.6 Wakeup Control20.2.2.7 LPROM and LP SPM Clock Control20.2.2.8 Analog Voltage Comparator20.2.2.9 Illegal Access and Unauthorized Access20.2.2.10 LP Bus Timeout Protection20.2.2.11 RNG Control20.3 Interrupt20.4 Register Summary20.4.1 HP Register Summary20.4.2 ICM Register Summary20.4.3 LP Register Summary20.5 Registers20.5.1 HP Registers20.5.2 ICM Register20.5.3 LP Registers21 Debug Assistant21.1 Overview21.2 Features21.3 Functional Description21.3.1 Region Read/Write Monitoring21.3.2 SP Monitoring21.3.3 PC Logging21.3.4 CPU/DMA Bus Access Logging21.4 Interrupts21.5 Recommended Operation21.5.1 Region Monitoring and SP Monitoring Configuration21.5.2 PC Logging Configuration21.5.3 CPU/DMA Bus Access Logging Configuration21.5.3.1 HP CPU0/1 Bus Access Logging Configuration21.5.3.2 DMA Bus Access Logging Configuration21.6 Register Summary21.6.1 HP CPU Bus Logging Configuration Register Summary21.6.2 DMA Bus Logging Configuration Register Summary21.6.3 Summary of Other Registers21.7 Registers21.7.1 HP CPU Bus Logging Configuration Registers21.7.2 DMA Bus Logging Configuration Registers21.7.3 Other Registers22 LP Mailbox22.1 Overview22.2 Features22.3 Functional Description22.3.1 Message Registers22.3.2 Interrupts22.3.3 Inter-Core Communication22.4 Register Summary22.5 Registers23 Brown-out Detector23.1 Introduction23.2 Feature List23.3 Architectural Overview23.4 Functional Description23.5 Interrupts23.6 Programming Procedures23.7 Register Summary23.8 RegistersV Cryptography/Security Component24 AES Accelerator (AES)24.1 Introduction24.2 Features24.3 Clock and Reset24.4 AES Working Modes24.5 Typical AES Working Mode24.5.1 Key, Plaintext, and Ciphertext24.5.2 Endianness24.5.3 Operation Process 24.6 DMA-AES Working Mode24.6.1 Key, Plaintext, and Ciphertext24.6.2 Endianness24.6.3 Standard Incrementing Function24.6.4 Block Number24.6.5 Initialization Vector24.6.6 Block Operation Process24.6.7 GCM Operation Process24.7 GCM Algorithm24.7.1 Hash Subkey24.7.2 J024.7.3 Authentication Tag24.7.4 AAD Block Number24.7.5 Number of Effective Bits of Incomplete Blocks24.8 Interrupts24.9 Memory Summary24.10 Register Summary24.11 Registers25 ECC Accelerator (ECC)25.1 Introduction25.2 Features25.3 ECC Basics25.3.1 Elliptic Curve and Points on the Curves25.3.2 Affine Coordinates and Jacobian Coordinates25.3.3 Memory Blocks25.3.4 Data and Data Block25.3.5 Writing Data25.3.6 Reading Data25.3.7 Standard Calculation and Jacobian Calculation25.4 Function Description25.4.1 Key Size25.4.2 Working Modes25.4.2.1 Affine Point Multiplication (Affine Point Multi)25.4.2.2 Affine Point Verification (Affine Point Verif)25.4.2.3 Affine Point Verification + Affine Point Multiplication (Affine Point Verif + Multi)25.4.2.4 Jacobian Point Multiplication (Jacobian Point Multi)25.4.2.5 Point Addition (Point Add)25.4.2.6 Jacobian Point Verification (Jacobian Point Verif)25.4.2.7 Affine Point Verification + Jacobian Point Multiplication (Affine Point Verif + Jacobian Point Multi)25.4.2.8 Mod Addition (Mod Add)25.4.2.9 Mod Subtraction (Mod Sub)25.4.2.10 Mod Multiplication (Mod Multi)25.4.2.11 Mod Division (Mod Div)25.5 Clock and Reset25.6 Interrupts25.7 Programming Procedures25.8 Register Summary25.9 Registers26 HMAC Accelerator (HMAC)26.1 Main Features26.2 Functional Description26.2.1 Upstream Mode26.2.2 Downstream Mode - JTAG Enable Feature26.2.3 Downstream Mode - RSA_DS Key Derivation Feature26.2.4 HMAC eFuse Configuration26.2.5 HMAC Process (Detailed)26.2.5.1 Enable HMAC Module26.2.5.2 Configure HMAC Keys and Key Purposes26.2.5.3 Downstream Mode Process26.2.5.4 Upstream Mode Process26.3 HMAC Algorithm Details26.3.1 Padding Bits26.3.2 HMAC Algorithm Structure26.4 Register Summary26.5 Registers27 RSA Accelerator (RSA)27.1 Introduction27.2 Features27.3 Functional Description27.3.1 Definitions and Representations27.3.2 Large-Number Modular Exponentiation27.3.3 Large-Number Modular Multiplication27.3.4 Large-Number Multiplication27.3.5 Options for Additional Acceleration27.4 Interrupts27.5 Memory Summary27.6 Register Summary27.7 Registers28 SHA Accelerator (SHA)28.1 Introduction28.2 Features28.3 Working Modes28.4 Function Description28.4.1 Preprocessing28.4.1.1 Padding the Message28.4.1.2 Parsing the Message28.4.1.3 Setting the Initial Hash Value28.4.2 Hash Operation28.4.2.1 Typical SHA Mode Process28.4.2.2 DMA-SHA Mode Process28.4.3 Message Digest28.5 Interrupt28.6 Register Summary28.7 Registers29 RSA Digital Signature Peripheral (RSA_DS)29.1 Overview29.2 Features29.3 Functional Description29.3.1 Overview29.3.2 Private Key Operands29.3.3 Software Prerequisites29.3.4 RSA_DS Operation at the Hardware Level29.3.5 RSA_DS Operation at the Software Level29.4 Memory Summary29.5 Register Summary29.6 Registers30 ECDSA Digital Signature Peripheral (ECDSA_DS)30.1 Introduction30.2 Features30.3 ECDSA Basics30.3.1 Domain Parameters30.3.2 Key Generation30.3.3 Signature Generation30.3.4 Signature Verification30.4 Functional Description30.4.1 ECDSA_DS Working Modes30.4.2 Data and Data Block30.4.2.1 Writing Data30.4.2.2 Reading Data30.4.2.3 Padding the Message30.4.2.4 Parsing the Message30.4.3 Security Features30.4.3.1 State-Dependent Register Access Control30.4.3.2 Hardware Occupation30.5 Programming Procedures30.5.1 ECDSA_DS Process30.5.1.1 IDLE Stage30.5.1.2 PREP Stage30.5.1.3 LOAD Stage30.5.1.4 PROC Stage30.5.1.5 POST Stage30.5.1.6 ECDSA_DS SHA Interface30.5.2 Clocks and Resets30.5.3 Interrupts30.6 Memory Blocks30.7 Register Summary30.8 Registers31 External Memory Encryption and Decryption (XTS_AES)31.1 Overview31.2 Features31.3 Module Structure31.4 Functional Description31.4.1 XTS Algorithm31.4.2 Key31.4.3 Target Memory Space31.4.4 Data Writing31.4.5 Manual Encryption Block31.4.6 Auto Encryption Block31.4.7 Auto Decryption Block31.5 Software Process 31.6 Anti-DPA31.7 Register Summary31.8 Registers32 Random Number Generator (RNG)32.1 Introduction32.2 Feature List32.3 Functional Description32.4 Programming Procedure32.5 Register Summary32.6 RegistersVI Image and Voice Processing33 JPEG Codec33.1 Terminology33.2 Introduction33.3 Features33.4 Architectural Overview33.5 Functional Description33.5.1 JPEG Encoder33.5.1.1 Pause33.5.1.2 Color Space Conversion33.5.1.3 Configurable Quantization Coefficient Table33.5.1.4 Stuffed Zero Byte33.5.1.5 EOI Marker33.5.2 JPEG Decoder33.5.2.1 Multiple Chrominance Components33.5.2.2 Parsing RST Marker33.5.2.3 Configurable Quantization Coefficient Table33.5.2.4 Configurable Huffman Table33.5.2.5 Timeout Detection33.6 Interrupts33.7 Programming Procedures33.7.1 JPEG Encoder33.7.2 JPEG Decoder33.7.3 Reset33.8 Register Summary33.9 Registers34 Image Signal Processor (ISP)34.1 Introduction34.2 Terminology34.3 Feature List34.4 Architectural Overview34.5 Functional Description34.5.1 ISP_Header34.5.2 ISP_Pipeline34.5.2.1 Bayer Filter (BF)34.5.2.2 Lens Shading Correction (LSC)34.5.2.3 Demosaic34.5.2.4 Color Correction Matrix (CCM)34.5.2.5 Gamma Correction34.5.2.6 RGB2YUV34.5.2.7 Sharpen34.5.2.8 Contrast/Hue/Saturation/Luminance Adjustment (COLOR)34.5.2.9 YUV_Limit and YUV2RGB34.5.2.10 Automatic Exposure Statistics (AE)34.5.2.11 Automatic Focus Statistics (AF)34.5.2.12 Automatic White Balance Statistics (AWB)34.5.2.13 Histogram Statistics (HIST)34.5.3 ISP_Tail34.5.4 Sequence Control34.5.5 CSI_Bridge34.5.6 Color Mode and Byte Order34.5.6.1 Output Pixel Layout Format34.5.6.2 Byte Order34.6 Interrupts34.7 Programming Procedures34.7.1 ISP Clock Reset Configuration34.7.2 CSI_Bridge Configuration34.7.3 VDMA Configuration34.7.4 ISP General Configuration34.7.5 Enabling ISP for Image Capture from MIPI-CSI34.7.6 Enabling ISP for Image Capture from DVP34.7.7 Enabling ISP for Image Capture from VDMA34.7.8 LSC LUT Configuration34.7.9 AE Configuration34.7.10 AF Configuration34.7.11 AWB Configuration34.7.12 HIST Configuration34.7.13 ISP_Pipeline Module Update Configuration34.8 Register Summary34.8.1 ISP Register Summary34.8.2 MIPI CSI_Bridge Register Summary34.9 Registers34.9.1 ISP Registers34.9.2 MIPI CSI_Bridge Registers35 Pixel-Processing Accelerator (PPA)35.1 Overview35.2 Terminology35.3 Features35.4 Architectural Overview35.5 Functional Description35.5.1 PPA Color Spaces35.5.1.1 SRM Color Space35.5.1.2 BLEND Color Space35.5.2 PPA 2D-DMA Linked List Configuration35.5.2.1 SRM Special Configuration35.5.3 Scaling - Rotation - Mirroring (SRM)35.5.3.1 Basic Functionality35.5.3.2 Pixel Block Rearrangement35.5.4 Layer Blending (BLEND)35.5.4.1 Basic Functionality35.5.4.2 Filled Image Output35.6 Interrupts35.7 Programming Procedures35.7.1 PPA Clock Reset Configuration35.7.2 SRM Configuration35.7.3 BLEND CLUT Configuration35.7.4 BLEND Configuration35.7.5 BLEND Image Filling Configuration35.7.6 Error Handling35.8 Register Summary35.9 Registers36 LCD and Camera Controller (LCD_CAM)36.1 Overview36.2 Features36.3 Functional Description36.3.1 Block Diagram36.3.2 Signal Description36.3.3 LCD_CAM Module Clocks36.3.3.1 LCD Clock36.3.3.2 Camera Clock36.3.4 LCD_CAM Reset36.3.5 LCD_CAM Data Format Control36.3.5.1 LCD Data Format Control36.3.5.2 Camera Data Format Control36.3.6 YUV-RGB Data Format Conversion36.3.6.1 YUV Formats36.3.6.2 Format Conversion Configuration36.3.7 LCD_CAM Timing36.3.7.1 LCD Timing (RGB Format)36.3.7.2 LCD Timing (I8080/MOTO6800 Format)36.4 Interrupts36.5 Software Configuration Process36.5.1 Configure LCD (RGB Format) as TX Mode36.5.2 Configure LCD (I8080/MOTO6800 Format) as TX Mode36.5.3 Configure Camera as RX Mode36.6 Register Summary36.7 Registers37 H264 Encoder37.1 Overview37.2 Terminology37.3 Features37.4 Architecture37.5 Functional Description37.5.1 Encoder Algorithm Core (ENC_CORE)37.5.1.1 Architecture37.5.1.2 Quantization Result Decimation37.5.1.3 Motion Vector (MV) Merging37.5.1.4 MB Level Rate Control37.5.1.5 Region of Interest (ROI)37.5.2 H264 Dedicated DMA37.5.2.1 Architecture37.5.2.2 Linked List Descriptor37.5.2.3 Transfer Initialization37.5.2.4 Transfer Reset37.5.2.5 Channel Configuration37.6 Interrupts37.7 Programming Procedures37.7.1 GOP Mode37.7.2 Dual Stream Mode37.7.3 Soft Reset37.8 Register Summary37.8.1 H264 Encoder Register Summary37.8.2 H264 DMA Register Summary37.9 Registers37.9.1 H264 Encoder Registers37.9.2 H264 DMA Registers38 MIPI CSI38.1 Introduction38.2 Terminology38.3 Feature List38.4 Architectural Overview38.5 Functional Description38.5.1 Data Lane State38.5.2 MIPI RX D-PHY Operation38.5.2.1 No-Power State38.5.2.2 Shut-Down State38.5.2.3 AFE Initialization38.5.2.4 Control Mode38.5.2.5 High-Speed Data Reception Mode38.5.2.6 Escape Mode38.5.3 MIPI RX D-PHY Configuration38.5.3.1 MIPI RX D-PHY Programming Interface38.5.3.2 MIPI RX D-PHY Test Code38.5.4 Descrambler38.5.5 Error Management38.6 Interrupts38.7 Programming Procedures38.7.1 Start High-Speed Data Reception38.7.1.1 Clock and Reset38.7.1.2 MIPI RX D-PHY and MIPI Host Initialization38.7.2 Stop High-Speed Data Reception38.8 Register Summary38.9 Registers39 Voice Activity Detection (VAD)39.1 Introduction39.2 Feature List39.3 Architectural Overview39.4 Functional Description39.4.1 Algorithm Parameter Configuration39.4.2 Wake-up Source Configuration39.5 Interrupts39.6 Programming Procedure39.6.1 Automatic Operation Mode39.6.2 Manual Operation Mode39.7 Register Summary39.8 RegistersVII Connectivity Interface40 UART Controller (UART)40.1 Overview40.2 Features40.3 UART Structure40.4 Functional Description40.4.1 Clock and Reset40.4.2 UART FIFO40.4.3 Baud Rate Generation and Detection40.4.3.1 Baud Rate Generation40.4.3.2 Baud Rate Detection40.4.4 UART Data Frame40.4.5 AT_CMD Character Structure40.4.6 RS48540.4.6.1 Driver Control40.4.6.2 Turnaround Delay40.4.6.3 Bus Snooping40.4.7 IrDA40.4.8 Wakeup40.4.9 Flow Control40.4.9.1 Hardware Flow Control40.4.9.2 Software Flow Control40.4.10 GDMA Mode40.4.11 Interrupts40.5 Programming Procedures40.5.1 Register Type40.5.2 Detailed Steps40.5.2.1 Initializing UARTn40.5.2.2 Configuring UARTn Communication40.5.2.3 Enabling UARTn40.6 Register Summary40.6.1 UART Register Summary40.6.2 LP UART Register Summary40.6.3 UHCI Register Summary40.7 Registers40.7.1 UART Registers40.7.2 LP UART Registers40.7.3 UHCI Registers41 SPI Controller (SPI)41.1 Overview41.2 Glossary41.3 Features41.4 Architectural Overview41.5 Functional Description41.5.1 Data Modes41.5.2 Introduction to Bus Signals41.5.3 Bit Read/Write Order Control41.5.4 Unaligned Byte Transfer41.5.5 Transfer Types41.5.6 CPU-Controlled Data Transfer41.5.6.1 CPU-Controlled Master Transfer41.5.6.2 CPU-Controlled Slave Transfer41.5.7 DMA-Controlled Data Transfer41.5.7.1 DMA Configuration41.5.7.2 DMA TX/RX Buffer Length Control41.5.8 Data Flow Control (Take GP-SPI as an Example)41.5.8.1 GP-SPI Functional Blocks41.5.8.2 Data Flow Control as Master41.5.8.3 Data Flow Control as Slave41.5.9 GP-SPI as a Master41.5.9.1 State Machine41.5.9.2 Register Configuration for State and Bit Mode Control41.5.9.3 Full-Duplex Communication (1-bit Mode Only)41.5.9.4 Half-Duplex Communication (1/2/4/(8)-bit Mode)41.5.9.5 DMA-Controlled Configurable Segmented Transfer41.5.10 GP-SPI Works as a Slave41.5.10.1 Configurable Communication Formats41.5.10.2 CMD Values Supported in Half-Duplex Communication41.5.10.3 Slave Single Transfer and Slave Segmented Transfer41.5.10.4 Configuration of Slave Single Transfer41.5.10.5 Configuration of Slave Segmented Transfer in Half-Duplex41.5.10.6 Configuration of Slave Segmented Transfer in Full-Duplex41.6 CS Setup Time and Hold Time Control41.7 Clock Control41.7.1 GP-SPI Clock Control41.7.2 LP-SPI Clock Control41.7.3 Clock Phase and Polarity41.7.4 Clock Control as Master41.7.5 Clock Control as Slave41.8 GP-SPI Timing Compensation41.9 LP-SPI Wake-Up41.10 Differences Among LP-SPI, GP-SPI2, and GP-SPI341.10.1 Feature Differences41.10.2 Register Differences41.10.3 Interrupt Differences41.11 Interrupt41.11.1 Interrupt Description41.11.2 Interrupts Used in Master and in Slave (Take GP-SPI as an Example)41.12 Register Summary41.12.1 GP-SPI2 Register Summary41.12.2 GP-SPI3 Register Summary41.12.3 LP-SPI Register Summary41.13 Register41.13.1 GP-SPI2 Register41.13.2 GP-SPI3 Register41.13.3 LP-SPI Register42 I2C Controller (I2C)42.1 Overview42.2 Features42.3 I2C Architecture42.4 Functional Description42.4.1 Clock Configuration42.4.2 SCL and SDA Noise Filtering42.4.3 SCL Clock Stretching42.4.4 Generating SCL Pulses in Idle State42.4.5 Synchronization42.4.6 Open-Drain Output42.4.7 Timing Parameter Configuration42.4.8 Timeout Control42.4.9 Command Configuration42.4.10 TX/RX RAM Data Storage42.4.11 Data Conversion42.4.12 Addressing Mode42.4.13 R/W Bit Check in 10-bit Addressing Mode42.4.14 To Start the I2C Controller42.5 Functional Differences Between LP_I2C and I2C42.6 Programming Example42.6.1 I2C master Writes to I2C slave with a 7-bit Address in One Command Sequence42.6.1.1 Introduction42.6.1.2 Configuration Example42.6.2 I2C master Writes to I2C slave with a 10-bit Address in One Command Sequence42.6.2.1 Introduction42.6.2.2 Configuration Example42.6.3 I2C master Writes to I2C slave with Two 7-bit Addresses in One Command Sequence42.6.3.1 Introduction42.6.3.2 Configuration Example42.6.4 I2C master Writes to I2C slave with a 7-bit Address in Multiple Command Sequences42.6.4.1 Introduction42.6.4.2 Configuration Example42.6.5 I2C master Reads I2C slave with a 7-bit Address in One Command Sequence42.6.5.1 Introduction42.6.5.2 Configuration Example42.6.6 I2C master Reads I2C slave with a 10-bit Address in One Command Sequence42.6.6.1 Introduction42.6.6.2 Configuration Example42.6.7 I2C master Reads I2C slave with Two 7-bit Addresses in One Command Sequence42.6.7.1 Introduction42.6.7.2 Configuration Example42.6.8 I2C master Reads I2C slave with a 7-bit Address in Multiple Command Sequences42.6.8.1 Introduction42.6.8.2 Configuration Example42.7 Interrupts42.8 Register Summary42.8.1 I2C Register Summary42.8.2 LP_I2C Register Summary42.9 Registers42.9.1 I2C Registers42.9.2 LP_I2C Registers43 Analog I2C Controller43.1 Introduction43.2 Feature List43.3 Architectural Overview43.4 Functional Description43.5 Programming Procedures43.6 Register Summary43.7 Registers44 I2S Controller (I2S)44.1 Overview44.2 Terminology44.3 Features44.4 System Architecture44.5 Supported Audio Standards44.5.1 TDM Philips Standard44.5.2 TDM MSB Alignment Standard44.5.3 TDM PCM Standard44.5.4 PDM Standard44.6 I2S TX/RX Clock44.7 I2S Reset44.8 I2S Master/Slave Mode44.8.1 Master/Slave TX Mode44.8.2 Master/Slave RX Mode44.9 Transmitting Data44.9.1 Data Format Control44.9.1.1 Bit Width Control of Channel Valid Data44.9.1.2 Endian Control of Channel Valid Data44.9.1.3 A-law/-law Compression and Decompression44.9.1.4 Bit Width Control of Channel TX Data44.9.1.5 Bit Order Control of Channel Data44.9.2 Channel Mode Control44.9.2.1 TDM TX Mode44.9.2.2 PDM TX Mode44.9.3 Synchronous Counter44.10 Receiving Data44.10.1 Channel Mode Control44.10.1.1 TDM RX Mode44.10.1.2 PDM RX Mode44.10.2 Data Format Control44.10.2.1 Bit Order Control of Channel Data44.10.2.2 Bit Width Control of Channel Storage (Valid) Data44.10.2.3 Bit Width Control of Channel RX Data44.10.2.4 Endian Control of Channel Storage Data44.10.2.5 A-law/-law Compression and Decompression44.11 Event Task Matrix Feature44.12 I2S Interrupts44.13 Software Configuration Process44.13.1 Configure I2S as TX Mode44.13.2 Configure I2S as RX Mode44.14 Register Summary44.15 Registers45 LP I2S Controller45.1 Introduction45.2 Feature List45.3 Architectural Overview45.4 Supported Audio Standards45.4.1 TDM Philips Standard45.4.2 TDM MSB Alignment Standard45.4.3 TDM PCM Standard45.4.4 PDM Standard45.5 RX Clock45.6 Reset45.7 Master/Slave RX Mode45.8 Receiving Data45.8.1 Channel Mode Control45.8.1.1 TDM RX Mode45.8.1.2 PDM RX Mode45.8.2 Data Format Control45.8.2.1 Bit Order Control of Channel Data45.8.2.2 Bit Width Control of Channel RX Data45.8.2.3 Bit Width Control of Channel RX Data45.8.2.4 Endian Control of Channel Storage Data45.8.3 Internal Memory45.9 Interrupts45.10 Register Summary45.11 Registers46 Pulse Count Controller (PCNT)46.1 Introduction46.2 Feature List46.3 Architectural Overview46.4 Functional Description46.5 Interrupts46.6 Programming Procedures46.6.1 Channel 0 Incrementing Independently46.6.2 Channel 0 Decrementing Independently46.6.3 Channel 0 and Channel 1 Incrementing Together46.7 Register Summary46.8 Registers47 USB 2.0 High-Speed OTG47.1 Overview47.2 Glossary47.3 Features47.3.1 General Features47.3.2 Device Mode Features47.3.3 Host Mode Features47.4 Functional Description47.4.1 Controller Core and Interfaces47.4.2 Memory Layout47.4.2.1 Control & Status Registers (CSRs)47.4.2.2 FIFO Access47.4.3 FIFO and Queue Organization47.4.3.1 Host Mode FIFOs and Queues47.4.3.2 Device Mode FIFOs47.4.4 Interrupt Hierarchy47.4.5 DMA Modes and Slave Mode47.4.5.1 Slave Mode47.4.5.2 Buffer DMA Mode47.4.5.3 Scatter/Gather DMA Mode47.4.6 Transaction and Transfer Level Operation47.4.6.1 Transaction and Transfer Level Operation in DMA Mode47.4.6.2 Transaction and Transfer Level Operation in Slave Mode47.4.7 OTG47.5 Registers48 USB 2.0 Full-Speed OTG 48.1 Overview48.2 Glossary48.3 Features48.3.1 General Features48.3.2 Device Mode Features48.3.3 Host Mode Features48.4 Functional Description48.4.1 Controller Core and Interfaces48.4.2 Memory Layout48.4.2.1 Control & Status Registers (CSRs)48.4.2.2 FIFO Access48.4.3 FIFO and Queue Organization48.4.3.1 Host Mode FIFOs and Queues48.4.3.2 Device Mode FIFOs48.4.4 Interrupt Hierarchy48.4.5 Slave Mode and DMA Modes48.4.5.1 Slave Mode48.4.5.2 Buffer DMA Mode48.4.5.3 Scatter/Gather DMA Mode48.4.6 Transaction and Transfer Level Operation48.4.6.1 Transaction and Transfer Level Operation in DMA Mode48.4.6.2 Transaction and Transfer Level Operation in Slave Mode48.5 OTG48.5.1 OTG Interface48.5.2 ID Pin Detection48.5.3 Session Request Protocol (SRP)48.5.3.1 A-Device SRP48.5.3.2 B-Device SRP48.5.4 Host Negotiation Protocol (HNP)48.5.4.1 A-Device HNP48.5.4.2 B-Device HNP48.6 Registers49 USB Serial/JTAG Controller (USB_SERIAL_JTAG)49.1 Overview49.2 Features49.3 Functional Description49.3.1 CDC-ACM USB Interface Functional Description49.3.2 CDC-ACM Firmware Interface Functional Description49.3.3 USB-to-JTAG Interface: JTAG Command Processor49.3.4 USB-to-JTAG Interface: CMD_REP Usage Example49.3.5 USB-to-JTAG Interface: Response Capture Unit49.3.6 USB-to-JTAG Interface: Control Transfer Requests49.4 Recommended Operation49.5 Interrupts49.6 Register Summary49.7 Registers50 Ethernet Media Access Controller (EMAC)50.1 Overview50.2 Features50.3 Ethernet MAC Architecture50.4 Functional Description50.4.1 EMAC_CORE50.4.1.1 Transmission50.4.1.2 Reception50.4.2 EMAC_MTL (MAC Transaction Layer)50.4.3 EMAC_DMA50.4.3.1 Transmit Descriptors50.4.3.2 Receive Descriptors50.4.4 PHY Interface50.4.4.1 Media Independent Interface: MII50.4.4.2 Reduced Media Independent Interface: RMII50.4.4.3 Station Management Agent (SMA) Interface50.4.5 MAC Address Filtering50.4.5.1 Unicast Destination Address Filtering50.4.5.2 Multicast Destination Address Filtering50.4.5.3 Broadcast Address Filter50.4.5.4 Unicast Source Address Filter50.4.5.5 Inverse Filtering Operation50.4.6 Energy Efficient Ethernet (EEE) 50.4.6.1 Transmission50.4.6.2 Reception50.4.7 Source Address, VLAN, and CRC Control50.4.7.1 Source Address Control50.4.7.2 VLAN Control50.4.7.3 CRC Control50.4.8 Time Stamp50.4.8.1 Transmit Path50.4.8.2 Receive Path50.4.9 Remote Wakeup50.4.10 Good Transmitted and Received Frames50.5 Programming Procedures50.5.1 MAC System Layer Configuration50.5.2 EMAC Initial Configuration50.5.3 Starting Transmission50.5.4 Starting Reception50.5.5 TX Entering and Exiting the LPI State50.5.6 RX Entering and Exiting the LPI State50.6 Interrupts50.7 Register Summary50.8 Registers51 Two-Wire Automotive Interface (TWAI)51.1 Features51.2 Protocol Overview51.2.1 TWAI Properties51.2.2 TWAI Messages51.2.2.1 Data Frames and Remote Frames51.2.2.2 Error and Overload Frames51.2.2.3 Interframe Space51.2.3 TWAI Errors51.2.3.1 Error Types51.2.3.2 Error States51.2.3.3 Error State Transition51.2.3.4 Error Counter Rules51.2.4 TWAI Bit Timing51.2.4.1 Nominal Bit51.2.4.2 Hard Synchronization and Resynchronization51.3 Architectural Overview51.3.1 Bit Timing Logic51.3.2 Bit Stream Processor51.3.3 Acceptance Filter51.3.4 Receive FIFO51.3.5 Error Management Logic51.3.6 Registers Block51.4 Functional Description51.4.1 Modes51.4.1.1 Reset Mode51.4.1.2 Operation Mode51.4.2 Bit Timing51.4.3 Transmit and Receive Buffers51.4.3.1 Overview of Buffers51.4.3.2 Frame Information51.4.3.3 Frame Identifier51.4.3.4 Frame Data51.4.4 Receive FIFO and Data Overruns51.4.5 Acceptance Filter51.4.5.1 Single-Filter Mode51.4.5.2 Dual-Filter Mode51.4.6 Error Management51.4.6.1 Error Warning Limit51.4.6.2 Error Passive51.4.6.3 Bus-Off and Bus-Off Recovery51.4.7 Error Code Capture51.4.8 Arbitration Lost Capture51.4.9 Transceiver Auto-Standby51.5 Interrupts51.6 Register Summary51.7 Registers52 SD/MMC Host Controller (SDHOST)52.1 Overview52.2 Features52.3 SD/MMC External Interface Signals52.4 Functional Description52.4.1 SD/MMC Host Controller Architecture52.4.1.1 Bus Interface Unit (BIU)52.4.1.2 Card Interface Unit (CIU)52.4.2 Command Path52.4.3 Data Path52.4.3.1 Data Transmit52.4.3.2 Data Receive52.5 Software Restrictions for CIU Operations52.6 RAM for Receiving and Transmitting Data52.6.1 TX RAM Module52.6.2 RX RAM Module52.7 DMA Linked List52.8 DMA Descriptor Format52.9 Programming Procedures52.9.1 Initializing Registers52.9.2 Sending Commands52.9.3 Initializing DMA52.9.4 Initializing DMA Transmission52.9.5 Initializing DMA Reception52.10 Clock Phase Selection52.11 Interrupt52.12 Register Summary52.13 Registers53 LED PWM Controller (LEDC)53.1 Overview53.2 Features53.3 Architectural Overview53.4 Functional Description53.4.1 Timers53.4.1.1 Clock Source53.4.1.2 Clock Divider Configuration53.4.1.3 20-Bit Counter53.4.2 PWM Generators53.4.3 Duty Cycle Fading53.4.3.1 Linear Duty Cycle Fading53.4.3.2 Gamma Curve Fading53.4.3.3 Suspend and Resume Duty Cycle Fading53.4.4 Event Task Matrix Feature53.5 Interrupts53.6 Programming Procedures53.7 Memory Blocks53.8 Register Summary53.9 Registers54 Motor Control PWM (MCPWM)54.1 Overview54.2 Features54.3 Modules54.3.1 Overview54.3.1.1 Timer Module54.3.1.2 Operator Module54.3.1.3 Capture Module54.3.1.4 ETM Module54.3.2 PWM Timer Module54.3.2.1 Configurations of the PWM Timer Module54.3.2.2 PWM Timer's Working Modes and Timing Event Generation54.3.2.3 Shadow Register of PWM Timer54.3.2.4 PWM Timer Synchronization and Phase Locking54.3.3 PWM Operator Module54.3.3.1 PWM Generator Module54.3.3.2 Dead Time Generator Module54.3.3.3 PWM Carrier Module54.3.3.4 Fault Detection Module54.3.4 Capture Module54.3.4.1 Introduction54.3.4.2 Capture Timer54.3.4.3 Capture Channel54.3.5 ETM Module54.3.5.1 Overview54.3.5.2 MCPWM-Related ETM Events54.3.5.3 MCPWM-Related ETM Tasks54.4 Interrupts54.5 Register Summary54.6 Registers55 Remote Control Peripheral (RMT)55.1 Overview55.2 Features55.3 Functional Description55.3.1 Architecture55.3.2 RAM55.3.2.1 Structure of RAM55.3.2.2 Use of RAM55.3.2.3 RAM Access55.3.3 Clock55.3.4 Transmitter55.3.4.1 Normal TX Mode55.3.4.2 Wrap TX Mode55.3.4.3 TX Modulation55.3.4.4 Continuous TX Mode55.3.4.5 Simultaneous TX Mode55.3.5 Receiver55.3.5.1 Normal RX Mode55.3.5.2 Wrap RX Mode55.3.5.3 RX Filtering55.3.5.4 RX Demodulation55.3.6 Configuration Update55.4 Interrupts55.5 Register Summary55.6 Registers56 Parallel IO Controller (PARLIO)56.1 Introduction56.2 Glossary56.3 Features56.4 Architectural Overview56.5 Functional Description56.5.1 Clock Generator56.5.2 Clock & Reset Restriction56.5.3 Master-Slave Mode56.5.4 Receive Modes of the RX Unit56.5.4.1 Level Enable Mode56.5.4.2 Pulse Enable Mode56.5.4.3 Software Enable Mode56.5.5 RX Unit GDMA SUC EOF Generation56.5.6 TX Unit EOF Generation56.5.7 RX Unit Timeout56.5.8 Output Clock Gating of TX Unit56.5.9 Valid Signal Output of TX Unit 56.5.10 Bus Idle Value of TX Unit56.5.11 Data Transfer in a Single Frame56.5.12 Bit Reversal in One Byte56.6 Interrupts56.7 Programming Procedures56.7.1 Data Receiving Operation Process56.7.2 Data Transmitting Operation Process56.8 Application Examples56.8.1 Co-working with SPI56.8.2 Co-working with I2S56.8.3 Co-working with LCD56.9 Register Summary56.10 Registers57 BitScrambler57.1 Introduction57.2 Feature List57.3 Architectural Overview57.3.1 Data Path57.3.2 Control Path57.4 Functional Description57.4.1 Instructions57.4.2 Configuration Registers57.5 Programming Procedures57.6 Register Summary57.7 RegistersVIII Analog Signal Processing58 Touch Sensor (TOUCH)58.1 Terminology58.2 Feature List58.3 Architectural Overview58.3.1 Touch Panel58.3.2 Capacitive Touch Pin58.3.3 Touch Sensor58.4 Functional Description58.4.1 Touch FSM58.4.2 Sampled Signal Preprocessing58.4.2.1 Measurement Process58.4.2.2 Trigger Source of Measurement58.4.2.3 Scan Mode58.4.2.4 Frequency Hopping58.4.3 Touch Detection58.4.3.1 Sampled Value58.4.3.2 Hardware Touch Detection58.4.4 Proximity Mode58.4.5 Sleep Mode58.4.6 Moisture Tolerance58.4.7 Water Rejection58.5 Interrupts58.6 Register Summary58.6.1 Interrupt and Status Register Summary58.6.2 Configuration Register Summary58.7 Registers58.7.1 Interrupt and Status Registers58.7.2 Configuration Registers59 Temperature Sensor (TSENS)59.1 Overview59.2 Features59.3 Architecture59.4 Functional Description59.4.1 Temperature Sensor Power Up59.4.2 Temperature Sensor Clock59.4.3 Wake-Up Modes for Automatic Temperature Monitoring59.4.4 Temperature Measurement Range and Offset59.4.5 Data Conversion59.5 Event Task Matrix Feature59.6 Interrupts59.7 Programming Procedure59.8 Register Summary59.9 Registers60 ADC Controller (ADC)60.1 Overview60.2 Terminology60.3 Features60.4 Architecture60.5 Functional Description60.5.1 SAR ADC Power Up60.5.2 SAR ADC Channels60.5.3 SAR ADC Clock60.5.4 SAR ADC Conversion and Attenuation60.5.5 HP ADC FSM60.5.6 HP ADC Pattern Table60.5.7 HP ADC Pattern Configuration Example for Multi-channel Sampling60.5.8 Dual HP ADC Sampling Control60.5.9 HP ADC Filters60.5.10 HP ADC Threshold Monitors60.5.11 HP ADC GDMA Support60.5.12 LP ADC Wake-Up Modes for Automatic Monitoring60.6 Event Task Matrix Feature60.7 Interrupts60.8 Programming Procedure60.8.1 HP ADC Multi-Channel Sampling Mode60.8.2 LP ADC One-shot Sampling Mode60.8.3 LP ADC Automatic Monitoring60.9 Register Summary60.9.1 HP ADC Register Summary60.9.2 LP ADC Register Summary60.10 Registers60.10.1 HP ADC Registers60.10.2 LP ADC Registers61 Analog Voltage Comparator61.1 Introduction61.2 Feature List61.3 Architectural Overview61.4 Functional Description61.5 Event Task Matrix Feature61.6 Interrupts61.7 Programming ProceduresIX AppendixRelated Documentation and ResourcesGlossaryAbbreviations for PeripheralsAbbreviations Related to RegistersAccess Types for RegistersProgramming Reserved Register FieldIntroductionProgramming Reserved Register FieldInterrupt Configuration RegistersRevision History
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HP GPIO matrixHP IOMUX0 (FUNC)2 (FUNC) GPIOSYNCMCU_SELGPIO_FUNCy_IN_SEL1 (FUNC)63Constant 1 inputConstant 0 input62012GPIO0_inGPIO1_inGPIO2_inGPIO54_in54GPIOX_inXGPIO_FUNCy_IN_INV_SELsig_in_func[y]GPIO_SIGy_IN_SEL0(FUNC)HP Peripheral Signal Y1(GPIO)0 1 GPIO_FUNCx_OUT_SELsignal0_outsignal2_outsignal255_outGPIO_OUT_DATA_bit_x012255256GPIOx_outsignal1_outPeripheral Signal YMCU_SEL1(FUNC)0(FUNC)2(FUNC)01GPIO_FUNCX_OUT_INV_SEL222 HP peripheral inputsPADbufOEIEWPUWPDPin X supplied byVDD_IO_0, VDD_FLASHIO, VDD_IO_4~VDD_IO_6253Pin X supplied byVDD_LPPADbufOEIEWPUWPD3232 HP peripheral outputs GPIOFilter14Peripheral Signal Y’VDD_IO_0, VDD_FLASHIO, VDD_IO_4~VDD_IO_6 power domainVDD_LP power domain GlitchFilter0 1 GPIOSD_FILTER_CH0~7_INPUT_IO_NUM == X01MUX_SEL6LP GPIO matrixLP IOMUX0 ( FUNC)2 ( FUNC)MCU_SELGPIO_FUNCy_IN_SEL1 ( FUNC)24~31Constant 1 inputConstant 0 input16~23012GPIO0_inGPIO1_inGPIO2_inGPIO15_in15GPIOX_inXGPIO_FUNCy_IN_INV_SELsig_in_func[y]GPIO_SIGy_IN_SEL0(FUNC)LP Peripheral Signal Y1(GPIO)0 1 GPIO_FUNCx_OUT_SELsignal0_outsignal2_outsignal31_outGPIO_OUT_DATA_bit_x0123132GPIOx_outsignal1_outPeripheral Signal YMCU_SEL1(FUNC)0(FUNC)2(FUNC)01GPIO_FUNCX_OUT_INV_SEL14 LP peripheral inputs14 LP peripheral outputs Peripheral Signal Y’ GPIOFilterCININC7 fi •
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31 2827 2524 23 2019 1716 15 1211 98 7 43 10Reset fi fi
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Digital Core Low Power CoreCPU0 PeripheralsDigital GPIOHP Core ResetSystem ResetHP CPU1 ResetChip ResetANALOGDigital SystemESP32-P4CPU1HP CPU0 ResetLP CPULPPeripheralsLPAONLP CPU ResetLP Core Reset fi •
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XTALPLLMUXRCXTAL_PXTAL_NXTAL_CLKCPLL_CLK (400MHz)RC_FAST_CLKDIVROOT_CLKDIV DIV DIVCPU_CLK (MAX 400MHz) SYS_CLK (MAX 200MHz)MEM_CLK (MAX 200MHz)APB_CLK (MAX 100MHz)PLL DIVMPLL_CLK (500MHz) PLL_F50M_CLKDIVPLL_F25M_CLKPLL DIVSPLL_CLK (480MHz) PLL_F240M_CLKDIVPLL_F160M_CLKDIVPLL_F120M_CLKDIVPLL_F80M_CLKDIVPLL_F20M_CLKMUXXTAL_CLKRC_FAST_CLKPLL_FxxM_CLKICG DIVPERI_XXM_CLKTypical HP Peripheral Clock GenerationMUXXTAL32K_CLKRC_SLOW_CLKMUXPLLXTAL_CLKRC_FAST_CLKPLL_LP_CLKXTAL32K_PXTAL32K_NOSC_SLOW_CLKDIVXTAL_CLK XTAL_D2_CLKMUXMUXLP_DYN_SLOW_CLKLP_DYN_FAST_CLKLP_SLOW_CLKLP_FAST_CLKMUXLP_FAST_CLKXTAL_D2_CLKPLL_LP_CLKICGPERI_XXM_CLKTypical LP Peripheral Clock GenerationXTALRCOSCDIVLP_PERI_CLK fi •
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ETM channelChannel nEventsTasks MUXDEMUXSOC_ETM_CHn_EVT_ID SOC_ETM_CHn_TASK_IDSOC_ETM_CH_ENABLEnSOC_ETM_CH_DISABLEnSOC_ETM_CH_ENABLEDn fi fi fifi fi fi fi
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