I Microprocessor and Master1 High-Performance CPU1.1 Overview1.2 Features1.3 Terminology1.4 Address Map1.5 Configuration and Status Registers (CSRs)1.5.1 Register Summary1.5.2 Register Description1.6 RISC-V Standard ISA Extensions Support1.6.1 M Extension1.6.1.1 Overview1.6.1.2 Functional Description1.6.2 C Extension1.6.2.1 Overview1.6.2.2 Functional Description1.6.3 F Extension1.6.3.1 Overview1.6.3.2 Functional Description1.6.3.3 Initialization1.6.4 Zc (Z) Extension1.6.4.1 Overview1.6.4.2 Functional Description1.6.4.3 Zc Instructions1.6.4.4 Limitations1.6.5 A Extension1.6.5.1 Overview1.6.5.2 Functional Description1.6.5.3 Load-Reserve (LR.W) Instruction1.6.5.4 Store-Conditional (SC.W) Instruction1.6.5.5 AMO Instructions1.7 Custom Instruction Extensions1.7.1 Hardware Loop1.7.1.1 Overview1.7.1.2 Features1.7.1.3 Functional Description1.7.1.4 Instructions/Operations/Modes Supported in HWLP1.7.1.5 HWLP Constraints1.7.1.6 Register Summary1.7.1.7 Register Description1.7.1.8 HWLP Instructions1.7.2 Processor Instruction Extension1.7.2.1 Overview1.7.2.2 Functional Description1.7.2.3 Initialization, Context Switching, and Exceptions1.8 Memory-Mapped Registers1.8.1 Overview1.8.2 Features1.8.3 Functional Description1.9 Interrupt Controller1.9.1 Overview1.9.2 CLIC1.9.2.1 Overview1.9.2.2 CLIC CSRs1.9.2.3 Interrupt Mapping1.9.2.4 CLIC Parameters1.9.2.5 Interrupt Level and Priority Encoding1.9.2.6 CLIC Memory-Mapped Register Summary1.9.2.7 CLIC Memory-Mapped Register Description1.9.3 Core-Local Interrupts (CLINT)1.9.3.1 Overview1.9.3.2 Features1.9.3.3 Software Interrupt1.9.3.4 Timer Counter and Interrupt1.9.3.5 Register Summary1.9.3.6 Register Description1.10 Memory Protection Unit1.10.1 Standard Physical Memory Protection1.10.1.1 Overview1.10.1.2 Features1.10.1.3 Functional Description1.10.1.4 Register Summary1.10.1.5 Register Description1.10.2 Custom Physical Memory Attribute (PMA) Checker1.10.2.1 Overview1.10.2.2 Features1.10.2.3 Functional Description1.10.2.4 Register Summary1.10.2.5 Register Description1.11 Debug and Trace Support1.11.1 Debug1.11.1.1 Overview1.11.1.2 Features1.11.1.3 Functional Description1.11.1.4 JTAG Control1.11.1.5 Register Summary1.11.1.6 Register Description1.11.2 Debug Halt Groups1.11.2.1 Overview1.11.2.2 Features1.11.2.3 Functional Description1.11.2.4 Register Summary1.11.2.5 Register Description1.11.3 Hardware Trigger1.11.3.1 Overview1.11.3.2 Features1.11.3.3 Functional Description1.11.3.4 Trigger Execution Flow1.11.3.5 Register Summary1.11.3.6 Register Description1.11.4 Trace1.11.4.1 Overview1.11.4.2 Features1.11.4.3 Functional Description1.12 Performance1.12.1 Branch Prediction1.12.1.1 Overview1.12.1.2 Features1.12.1.3 Functional Description1.12.2 RAS1.12.2.1 Overview1.12.2.2 Features1.12.2.3 Functional Description1.12.3 Control Status Register for Performance Configuration1.13 Custom Features1.13.1 Bus Error Response1.13.1.1 Overview1.13.1.2 Functional Description1.13.1.3 Control Status Registers1.13.2 Dedicated IO1.13.2.1 Overview1.13.2.2 Features1.13.2.3 Functional Description1.13.2.4 Register Summary1.13.2.5 Register Description1.13.3 RunStall Support1.13.3.1 Overview1.13.3.2 Functional Description1.13.3.3 Register Summary1.13.4 Debug Assist Information1.13.5 Core Lock-up1.13.5.1 Overview1.13.5.2 Functional Description1.13.5.3 Register Summary1.13.5.4 Register Description2 RISC-V Trace Encoder (TRACE)2.1 Terminology2.2 Introduction2.3 Features2.4 Architectural Overview2.5 Functional Description2.5.1 Synchronization2.5.2 Address Mode2.5.3 Optional Sideband Signals2.5.4 Filtering2.5.5 Anchor Tag2.5.6 Memory Writing Mode2.5.7 Automatic Restart2.6 Encoder Output Packets2.6.1 Header2.6.2 Index2.6.3 Payload2.6.3.1 Format 3 Packets2.6.3.2 Format 2 Packets2.6.3.3 Format 1 Packets2.7 Interrupt2.8 Programming Procedures2.8.1 Encoder Option Configuration2.8.2 Filter Configuration2.8.3 Enable Encoder2.8.4 Disable Encoder2.8.5 Notify2.8.6 Decode Data Packets2.8.7 AHB Configuration2.8.8 Software Retention2.9 Register Summary2.10 Registers3 Low-Power CPU3.1 Overview3.2 Features3.3 Configuration and Status Registers (CSRs)3.3.1 Register Summary3.3.2 Registers3.4 Interrupts and Exceptions3.4.1 Interrupts3.4.2 Interrupt Handling3.4.3 Exceptions3.5 Debugging3.5.1 Features3.5.2 Functional Description3.5.3 Register Summary3.5.4 Registers3.6 Hardware Trigger3.6.1 Features3.6.2 Functional Description3.6.3 Trigger Execution Flow3.6.4 Register Summary3.6.5 Registers3.7 Performance Counter3.8 System Access3.8.1 Memory Access3.8.2 Peripheral Access3.9 Event Task Matrix Feature3.10 Sleep and Wake-Up Process3.10.1 Features3.10.2 Process3.10.3 Wake-Up Sources3.10.4 Sleep RejectionII System DMA4 GDMA Controller (GDMA-AHB, GDMA-AXI)4.1 Overview4.2 Features4.3 Architecture4.4 Functional Description4.4.1 Linked List4.4.2 Peripheral-to-Memory and Memory-to-Peripheral Data Transfer4.4.3 Memory-to-Memory Data Transfer4.4.4 Enabling GDMA4.4.5 Linked List Reading Process4.4.6 EOF4.4.7 Accessing Memory4.4.8 Arbitration4.4.9 CRC Calculation4.5 Event Task Matrix Feature4.6 Interrupts4.7 Programming Procedures4.7.1 Programming Procedures for GDMA's Transmit Channel4.7.2 Programming Procedures for GDMA's Receive Channel4.7.3 Programming Procedures for Memory-to-Memory Transfer4.7.4 Programming Procedures for Channel Priority and Weight4.7.5 Programming Procedures for CRC Calculation4.8 Register Summary4.8.1 GDMA-AHB Register Summary4.8.2 GDMA-AXI Register Summary4.9 Registers4.9.1 GDMA-AHB Registers4.9.2 GDMA-AXI Registers5 VDMA Controller (VDMA)5.1 Overview5.2 Terminology5.3 Features5.4 Architectural Overview5.5 Functional Description5.5.1 Transfer Hierarchy5.5.2 Arbitration Scheme5.5.2.1 Read Arbiter5.5.2.2 Write Arbiter5.5.3 Handshaking Interface5.5.4 Transfer Control5.5.4.1 Single-Block Transfer5.5.4.2 Multi-Block Transfer5.5.5 Flow Controller5.5.6 Channel Suspend and Resume5.5.7 Channel Disable5.5.7.1 Disabling a Suspended Channel Before Transfer Completion5.5.7.2 Disabling a Non-suspended Channel Before Transfer Completion5.5.8 Low-Power Technique5.5.8.1 Low-Power Technique for DMA Channels5.5.8.2 Low-Power Technique for Slave Bus Interface5.5.8.3 Low-Power Technique for AXI Master Interface Channels5.5.8.4 Global Low-Power Technique5.6 Interrupts5.7 Programming Procedures5.7.1 Common Programming Procedures5.7.2 Programming Procedures for Shadow-Register-Based Multi-Block Transfer5.7.3 Programming Procedures for Linked-List-Based Multi-Block Transfer5.7.4 Programming Procedures for Single-Block Transfer5.8 Register Summary5.9 Registers6 2D-DMA Controller (2D-DMA)6.1 Overview6.2 Features6.3 Architecture6.4 Functional Description6.4.1 Transfer Mode6.4.2 Linked List6.4.3 Padding in 2D-MOD1 Mode and DSCR-PORT Mode6.4.4 Peripheral-to-Memory and Memory-to-Peripheral Data Transfer6.4.5 Memory-to-Memory Data Transfer6.4.6 Macroblock Reordering6.4.6.1 Macroblock Reordering in TX Direction6.4.6.2 Macroblock Reordering in RX Direction6.4.7 Color Space Conversion6.4.8 Enabling 2D-DMA6.4.9 Linked List Reading Process6.4.10 EOF6.4.11 Accessing Memory6.4.12 Arbitration6.5 Event Task Matrix Feature6.6 Interrupts6.7 Programming Procedures6.7.1 General Configurations for 2D-DMA6.7.2 Mode-Specific Configurations for 2D-DMA6.7.3 Configurations for 2D-DMA's Transmit Channel6.7.4 Configurations for 2D-DMA's Receive Channel6.7.5 Configurations for Memory-to-Memory Transfer6.7.6 Configurations for Channel Priority and Weight6.7.7 Resetting 2D-DMA While it Runs6.8 Register Summary6.9 RegistersIII Memory Organization7 System and Memory7.1 Overview7.2 Features7.3 Functional Description7.3.1 Address Mapping7.3.2 Internal Memory7.3.3 External Memory7.3.3.1 External Memory Address Mapping7.3.3.2 Cache7.3.3.3 Cache Operations7.3.4 DMA Address Space7.3.5 Modules/Peripherals Address Mapping8 eFuse Controller (EFUSE)8.1 Overview8.2 Features8.3 Functional Description8.3.1 Structure8.3.1.1 [fielddesc:EFUSEWRDIS]EFUSE_WR_DIS8.3.1.2 [fielddesc:EFUSERDDIS]EFUSE_RD_DIS8.3.1.3 Data Storage8.3.2 Programming of Parameters8.3.3 Reading of Parameters by Users8.3.4 eFuse VDDQ Timing8.3.5 Parameters Used by Hardware Modules8.4 Interrupts8.5 Register Summary8.6 RegistersIV System Component9 GPIO Matrix and IO MUX9.1 Overview9.2 Features9.2.1 HP GPIO Matrix and HP IO MUX9.2.2 LP GPIO Matrix and LP IO MUX9.3 Architectural Overview9.4 Peripheral Input via GPIO Matrix9.4.1 Overview9.4.2 Signal Synchronization9.4.3 GPIO Filter9.4.4 Glitch Filter9.4.5 Simple GPIO Input9.4.6 GPIO Wakeup9.4.6.1 HP GPIO Wakeup9.4.6.2 LP GPIO Wakeup9.4.7 Programming Procedure9.4.7.1 HP GPIO Matrix9.4.7.2 LP GPIO Matrix9.5 Peripheral Output via GPIO Matrix9.5.1 Overview9.5.2 Simple GPIO Output9.5.3 Sigma Delta Modulated Output (SDM)9.5.3.1 Functional Description9.5.3.2 SDM Configuration9.5.4 Programming Procedure9.5.4.1 HP GPIO Matrix9.5.4.2 LP GPIO Matrix9.6 Direct Input and Output via IO MUX9.6.1 Overview9.6.2 Functional Description9.6.2.1 HP IO MUX9.6.2.2 LP IO MUX9.7 Analog Functions9.7.1 Overview9.7.2 Analog Functions9.8 Pin Functions in Light-sleep9.9 Pin Hold Feature9.10 Hysteresis Characteristics of GPIO Pins9.11 Power Supplies and Management of GPIO Pins9.11.1 Power Supplies of GPIO Pins9.11.2 Power Supply Management9.12 HP Peripheral Signal List9.13 LP Peripheral Signal List9.14 HP IO MUX Functions List9.15 LP IO MUX Functions List9.16 GPIO Pin Analog Functions List9.17 Event Task Matrix Function9.18 Interrupts9.19 Register Summary9.19.1 HP GPIO Matrix Register Summary9.19.2 HP IO MUX Register Summary9.19.3 GPIO EXT Register Summary9.19.4 LP GPIO Matrix Register Summary9.19.5 LP IO MUX Register Summary9.20 Registers9.20.1 HP GPIO Matrix Registers9.20.2 HP IO MUX Registers9.20.3 GPIO EXT Registers9.20.4 LP GPIO Matrix Registers9.20.5 LP IO MUX Registers10 Reset and Clock10.1 Reset10.1.1 Overview10.1.2 Architectural Overview10.1.3 Features10.1.4 Functional Description10.1.5 Peripheral Reset10.2 Clock10.2.1 Overview10.2.2 Architectural Overview10.2.3 Features10.2.4 Functional Description10.2.4.1 HP System Clock10.2.4.2 LP System Clock10.2.4.3 Peripheral Clocks10.3 Programming Procedures10.3.1 HP System Clock Configuration10.3.2 LP System Clock Configuration10.3.3 Peripheral Clock Reset and Configuration10.4 Register Summary10.4.1 Reset and Clock (HP_SYS_CLKRST) Register Summary10.4.2 LP Always on Clock and Reset (LP_CLKRST) Register Summary10.4.3 LP Peripheral Clock and Reset (LPPERI) Register Summary10.5 Registers10.5.1 Reset and Clock (HP_SYS_CLKRST) Registers10.5.2 LP Always on Clock and Reset (LP_CLKRST) Registers10.5.3 LP Peripheral Clock and Reset (LPPERI) Registers11 Chip Boot Control11.1 Overview11.2 Functional Description11.2.1 Default Configuration11.2.2 Boot Mode Control11.2.3 ROM Messages Printing Control11.2.4 JTAG Signal Source Control12 Interrupt Matrix12.1 Overview12.2 Interrupt Terminology in ESP32-P412.2.1 Interrupt12.2.2 Interrupt Signal/interrupt Source12.2.3 Interrupt Flow in ESP32-P412.3 Features12.4 Functional Description12.4.1 Peripheral Interrupt Sources12.4.2 Assign Peripheral Interrupt Source to HP CPU Interrupt12.4.2.1 Assign One Peripheral Interrupt Source (Source_Y) to HP CPUx12.4.2.2 Assign Multiple Peripheral Interrupt Sources (Source_Y) to HP CPUx12.4.2.3 Disable HP CPUx Peripheral Interrupt Source (Source_x)12.4.3 Query Current Interrupt Status of HP CPUx Peripheral Interrupt Source12.5 Register Summary12.5.1 HP CPU0 Interrupt Matrix Register Summary12.5.2 HP CPU1 Interrupt Matrix Register Summary12.6 Registers12.6.1 HP CPU0 Interrupt Matrix Registers12.6.2 HP CPU1 Interrupt Matrix Registers13 Event Task Matrix (ETM)13.1 Overview13.2 Features13.3 Functional Description13.3.1 Architecture13.3.2 Events13.3.3 Tasks13.3.4 Event and Task Status13.3.5 Timing Considerations13.3.6 Channel Control13.4 Register Summary13.5 Registers14 Low-Power Management14.1 Overview14.2 Terminology14.3 Features14.4 Functional Description14.4.1 Power Scheme14.4.1.1 Regulators14.4.1.2 Digital Power Domains14.4.1.3 Analog Power Domains14.4.1.4 Battery Power Domain14.4.2 PMU14.4.2.1 PMU Main State Machine14.4.2.2 Sleep/Wake-up Controller14.4.2.3 Analog Power Controller14.4.2.4 Digital Power Controller14.4.2.5 Clock Controller14.4.2.6 Backup Controller14.4.2.7 System Controller14.4.2.8 Battery Power Controller14.4.2.9 Output Regulator Control14.5 Power Modes14.6 Event Task Matrix Feature14.7 Interrupts14.8 Register Summary14.9 Registers15 System Timer15.1 Overview15.2 Features15.3 System Timer Structure15.4 Clock Source Selection15.5 Functional Description15.5.1 Counter15.5.2 Comparator and Alarm15.5.3 Event Task Matrix15.5.4 Synchronization Operation15.6 Interrupts15.7 Programming Procedure15.7.1 Read Current Count Value15.7.2 Configure a One-Time Alarm in Target Mode15.7.3 Configure Periodic Alarms in Period Mode15.7.4 Update After Light-sleep15.8 Register Summary15.9 Registers16 Timer Group (TIMG)16.1 Overview16.2 Features16.3 Functional Description16.3.1 16-bit Prescaler and Clock Selection16.3.2 54-bit Time-base Counter16.3.3 Alarm Generation16.3.4 Timer Reload16.3.5 Event Task Matrix Feature16.3.6 RTC_SLOW_CLK Frequency Calculation16.3.7 Interrupts16.4 Configuration and Usage16.4.1 Timer as a Simple Clock16.4.2 Timer as One-shot Alarm16.4.3 Timer as Periodic Alarm by APB16.4.4 Timer as Periodic Alarm by ETM16.4.5 RTC_SLOW_CLK Frequency Calculation16.5 Register Summary16.6 Registers17 Watchdog Timers (WDT)17.1 Overview17.2 Digital Watchdog Timers17.2.1 Features17.2.2 Functional Description17.2.2.1 Clock Source and 32-Bit Counter17.2.2.2 Stages and Timeout Actions17.2.2.3 Write Protection17.2.2.4 Flash Boot Protection17.3 Super Watchdog17.3.1 Features17.3.2 Super Watchdog Controller17.3.2.1 Structure17.3.2.2 Workflow17.4 Interrupts17.5 Register Summary17.6 Registers18 RTC Timer18.1 Introduction18.2 Feature List18.3 Functional Description18.4 Event Task Matrix Feature18.5 Interrupts18.6 Register Summary18.7 Registers19 Permission Control (PMS)19.1 Overview19.2 Features19.3 Functional Description19.3.1 Architecture19.3.2 Address Ranges and Permissions Management19.3.2.1 Address Ranges Managed by HP APM and LP APM19.3.2.2 Address Ranges Managed by DMA APM19.4 Programming Procedure19.4.1 Configuring Access Permissions for HP CPU0/119.4.2 Configuring Access Permissions for LP CPU19.4.3 Configuring Access Permission for DMA Masters19.5 Illegal Access and Interrupts19.6 Register Summary19.6.1 HP_DMA_PMS_REG19.6.2 HP_PERI_PMS_REG19.6.3 LP2HP_PERI_PMS_REG19.6.4 LP_PERI_PMS_REG19.6.5 HP2LP_PERI_PMS_REG19.7 Registers19.7.1 HP_DMA_PMS_REG19.7.2 HP_PERI_PMS_REG19.7.3 LP2HP_PERI_PMS_REG19.7.4 LP_PERI_PMS_REG19.7.5 HP2LP_PERI_PMS_REG20 System Registers (SYSREG)20.1 Overview20.2 Function Description20.2.1 HP System Registers20.2.1.1 External Memory Encryption/Decryption Configuration20.2.1.2 HP Peripherals Clock Configuration and Power Control20.2.1.3 HP Cache Clock and Reset Configuration20.2.1.4 HP SPM and HP L2MEM Clock Configuration20.2.1.5 HP SPM Parity Check Configuration20.2.1.6 HP L2MEM ECC Check Configuration20.2.1.7 BitScrambler Configuration20.2.1.8 Ethernet MAC Control20.2.1.9 USB OTG 2.0 Control20.2.1.10 CPU Control and Record20.2.1.11 HP GPIO Hold Control20.2.1.12 HP GPIO Output Control20.2.1.13 Illegal Access and Unauthorized Access20.2.1.14 HP CPU Bus Timeout Protection20.2.1.15 AXI Matrix20.2.1.16 Post Write20.2.2 LP System Registers20.2.2.1 LP Timer Stall Control20.2.2.2 Focused Ion Beam (FIB) Control20.2.2.3 Boot Mode20.2.2.4 LP CPU Control20.2.2.5 Reset Control20.2.2.6 Wakeup Control20.2.2.7 LPROM and LP SPM Clock Control20.2.2.8 Analog Voltage Comparator20.2.2.9 Illegal Access and Unauthorized Access20.2.2.10 LP Bus Timeout Protection20.2.2.11 RNG Control20.3 Interrupt20.4 Register Summary20.4.1 HP Register Summary20.4.2 ICM Register Summary20.4.3 LP Register Summary20.5 Registers20.5.1 HP Registers20.5.2 ICM Register20.5.3 LP Registers21 Debug Assistant21.1 Overview21.2 Features21.3 Functional Description21.3.1 Region Read/Write Monitoring21.3.2 SP Monitoring21.3.3 PC Logging21.3.4 CPU/DMA Bus Access Logging21.4 Interrupts21.5 Recommended Operation21.5.1 Region Monitoring and SP Monitoring Configuration21.5.2 PC Logging Configuration21.5.3 CPU/DMA Bus Access Logging Configuration21.5.3.1 HP CPU0/1 Bus Access Logging Configuration21.5.3.2 DMA Bus Access Logging Configuration21.6 Register Summary21.6.1 HP CPU Bus Logging Configuration Register Summary21.6.2 DMA Bus Logging Configuration Register Summary21.6.3 Summary of Other Registers21.7 Registers21.7.1 HP CPU Bus Logging Configuration Registers21.7.2 DMA Bus Logging Configuration Registers21.7.3 Other Registers22 LP Mailbox22.1 Overview22.2 Features22.3 Functional Description22.3.1 Message Registers22.3.2 Interrupts22.3.3 Inter-Core Communication22.4 Register Summary22.5 Registers23 Brown-out Detector23.1 Introduction23.2 Feature List23.3 Architectural Overview23.4 Functional Description23.5 Interrupts23.6 Programming Procedures23.7 Register Summary23.8 RegistersV Cryptography/Security Component24 AES Accelerator (AES)24.1 Introduction24.2 Features24.3 Clock and Reset24.4 AES Working Modes24.5 Typical AES Working Mode24.5.1 Key, Plaintext, and Ciphertext24.5.2 Endianness24.5.3 Operation Process 24.6 DMA-AES Working Mode24.6.1 Key, Plaintext, and Ciphertext24.6.2 Endianness24.6.3 Standard Incrementing Function24.6.4 Block Number24.6.5 Initialization Vector24.6.6 Block Operation Process24.6.7 GCM Operation Process24.7 GCM Algorithm24.7.1 Hash Subkey24.7.2 J024.7.3 Authentication Tag24.7.4 AAD Block Number24.7.5 Number of Effective Bits of Incomplete Blocks24.8 Interrupts24.9 Memory Summary24.10 Register Summary24.11 Registers25 ECC Accelerator (ECC)25.1 Introduction25.2 Features25.3 ECC Basics25.3.1 Elliptic Curve and Points on the Curves25.3.2 Affine Coordinates and Jacobian Coordinates25.3.3 Memory Blocks25.3.4 Data and Data Block25.3.5 Writing Data25.3.6 Reading Data25.3.7 Standard Calculation and Jacobian Calculation25.4 Function Description25.4.1 Key Size25.4.2 Working Modes25.4.2.1 Affine Point Multiplication (Affine Point Multi)25.4.2.2 Affine Point Verification (Affine Point Verif)25.4.2.3 Affine Point Verification + Affine Point Multiplication (Affine Point Verif + Multi)25.4.2.4 Jacobian Point Multiplication (Jacobian Point Multi)25.4.2.5 Point Addition (Point Add)25.4.2.6 Jacobian Point Verification (Jacobian Point Verif)25.4.2.7 Affine Point Verification + Jacobian Point Multiplication (Affine Point Verif + Jacobian Point Multi)25.4.2.8 Mod Addition (Mod Add)25.4.2.9 Mod Subtraction (Mod Sub)25.4.2.10 Mod Multiplication (Mod Multi)25.4.2.11 Mod Division (Mod Div)25.5 Clock and Reset25.6 Interrupts25.7 Programming Procedures25.8 Register Summary25.9 Registers26 HMAC Accelerator (HMAC)26.1 Main Features26.2 Functional Description26.2.1 Upstream Mode26.2.2 Downstream Mode - JTAG Enable Feature26.2.3 Downstream Mode - Digital Signature Algorithm and Key Derivation Feature26.2.4 HMAC eFuse Configuration26.2.5 HMAC Process (Detailed)26.2.5.1 Enable HMAC Module26.2.5.2 Configure HMAC Keys and Key Purposes26.2.5.3 Downstream Mode Process26.2.5.4 Upstream Mode Process26.3 HMAC Algorithm Details26.3.1 Padding Bits26.3.2 HMAC Algorithm Structure26.4 Register Summary26.5 Registers27 RSA Accelerator (RSA)27.1 Introduction27.2 Features27.3 Functional Description27.3.1 Definitions and Representations27.3.2 Large-Number Modular Exponentiation27.3.3 Large-Number Modular Multiplication27.3.4 Large-Number Multiplication27.3.5 Options for Additional Acceleration27.4 Interrupts27.5 Memory Summary27.6 Register Summary27.7 Registers28 SHA Accelerator (SHA)28.1 Introduction28.2 Features28.3 Working Modes28.4 Function Description28.4.1 Preprocessing28.4.1.1 Padding the Message28.4.1.2 Parsing the Message28.4.1.3 Setting the Initial Hash Value28.4.2 Hash Operation28.4.2.1 Typical SHA Mode Process28.4.2.2 DMA-SHA Mode Process28.4.3 Message Digest28.5 Interrupt28.6 Register Summary28.7 Registers29 Digital Signature Algorithm (DSA)29.1 Overview29.2 Features29.3 Functional Description29.3.1 Overview29.3.2 Private Key Operands29.3.3 Software Prerequisites29.3.4 DSA Operation at the Hardware Level29.3.5 DSA Operation at the Software Level29.4 Memory Summary29.5 Register Summary29.6 Registers30 Elliptic Curve Digital Signature Algorithm (ECDSA)30.1 Introduction30.2 Features30.3 ECDSA Basics30.3.1 Domain Parameters30.3.2 Key Generation30.3.3 Signature Generation30.3.4 Signature Verification30.4 Functional Description30.4.1 ECDSA Working Modes30.4.2 Data and Data Block30.4.2.1 Writing Data30.4.2.2 Reading Data30.4.2.3 Padding the Message30.4.2.4 Parsing the Message30.4.3 Security Features30.4.3.1 State-Dependent Register Access Control30.4.3.2 Hardware Occupation30.5 Programming Procedures30.5.1 ECDSA Process30.5.1.1 IDLE Stage30.5.1.2 PREP Stage30.5.1.3 LOAD Stage30.5.1.4 PROC Stage30.5.1.5 POST Stage30.5.1.6 ECDSA SHA Interface30.5.2 Clocks and Resets30.5.3 Interrupts30.6 Memory Blocks30.7 Register Summary30.8 Registers31 External Memory Encryption and Decryption (XTS_AES)31.1 Overview31.2 Features31.3 Module Structure31.4 Functional Description31.4.1 XTS Algorithm31.4.2 Key31.4.3 Target Memory Space31.4.4 Data Writing31.4.5 Manual Encryption Block31.4.6 Auto Encryption Block31.4.7 Auto Decryption Block31.5 Software Process 31.6 Anti-DPA31.7 Register Summary31.8 Registers32 Random Number Generator (RNG)32.1 Introduction32.2 Feature List32.3 Functional Description32.4 Programming Procedure32.5 Register Summary32.6 RegistersVI Image and Voice Processing33 JPEG Codec33.1 Terminology33.2 Introduction33.3 Features33.4 Architectural Overview33.5 Functional Description33.5.1 JPEG Encoder33.5.1.1 Pause33.5.1.2 Color Space Conversion33.5.1.3 Configurable Quantization Coefficient Table33.5.1.4 Stuffed Zero Byte33.5.1.5 EOI Marker33.5.2 JPEG Decoder33.5.2.1 Multiple Chrominance Components33.5.2.2 Parsing RST Marker33.5.2.3 Configurable Quantization Coefficient Table33.5.2.4 Configurable Huffman Table33.5.2.5 Timeout Detection33.6 Interrupts33.7 Programming Procedures33.7.1 JPEG Encoder33.7.2 JPEG Decoder33.7.3 Reset33.8 Register Summary33.9 Registers34 Image Signal Processor (ISP)34.1 Introduction34.2 Terminology34.3 Feature List34.4 Architectural Overview34.5 Functional Description34.5.1 ISP_Header34.5.2 ISP_Pipeline34.5.2.1 Bayer Filter (BF)34.5.2.2 Lens Shading Correction (LSC)34.5.2.3 Demosaic34.5.2.4 Color Correction Matrix (CCM)34.5.2.5 Gamma Correction34.5.2.6 RGB2YUV34.5.2.7 Sharpen34.5.2.8 Contrast/Hue/Saturation/Luminance Adjustment (COLOR)34.5.2.9 YUV_Limit and YUV2RGB34.5.2.10 Automatic Exposure Statistics (AE)34.5.2.11 Automatic Focus Statistics (AF)34.5.2.12 Automatic White Balance Statistics (AWB)34.5.2.13 Histogram Statistics (HIST)34.5.3 ISP_Tail34.5.4 Sequence Control34.5.5 CSI_Bridge34.5.6 Color Mode and Byte Order34.5.6.1 Output Pixel Layout Format34.5.6.2 Byte Order34.6 Interrupts34.7 Programming Procedures34.7.1 ISP Clock Reset Configuration34.7.2 CSI_Bridge Configuration34.7.3 VDMA Configuration34.7.4 ISP General Configuration34.7.5 Enabling ISP for Image Capture from MIPI-CSI34.7.6 Enabling ISP for Image Capture from DVP34.7.7 Enabling ISP for Image Capture from VDMA34.7.8 LSC LUT Configuration34.7.9 AE Configuration34.7.10 AF Configuration34.7.11 AWB Configuration34.7.12 HIST Configuration34.7.13 ISP_Pipeline Module Update Configuration34.8 Register Summary34.8.1 ISP Register Summary34.8.2 MIPI CSI_Bridge Register Summary34.9 Registers34.9.1 ISP Registers34.9.2 MIPI CSI_Bridge Registers35 Pixel-Processing Accelerator (PPA)35.1 Overview35.2 Terminology35.3 Features35.4 Architectural Overview35.5 Functional Description35.5.1 PPA Color Spaces35.5.1.1 SRM Color Space35.5.1.2 BLEND Color Space35.5.2 PPA 2D-DMA Linked List Configuration35.5.2.1 SRM Special Configuration35.5.3 Scaling - Rotation - Mirroring (SRM)35.5.3.1 Basic Functionality35.5.3.2 Pixel Block Rearrangement35.5.4 Layer Blending (BLEND)35.5.4.1 Basic Functionality35.5.4.2 Filled Image Output35.6 Interrupts35.7 Programming Procedures35.7.1 PPA Clock Reset Configuration35.7.2 SRM Configuration35.7.3 BLEND CLUT Configuration35.7.4 BLEND Configuration35.7.5 BLEND Image Filling Configuration35.7.6 Error Handling35.8 Register Summary35.9 Registers36 LCD and Camera Controller (LCD_CAM)36.1 Overview36.2 Features36.3 Functional Description36.3.1 Block Diagram36.3.2 Signal Description36.3.3 LCD_CAM Module Clocks36.3.3.1 LCD Clock36.3.3.2 Camera Clock36.3.4 LCD_CAM Reset36.3.5 LCD_CAM Data Format Control36.3.5.1 LCD Data Format Control36.3.5.2 Camera Data Format Control36.3.6 YUV-RGB Data Format Conversion36.3.6.1 YUV Formats36.3.6.2 Format Conversion Configuration36.3.7 LCD_CAM Timing36.3.7.1 LCD Timing (RGB Format)36.3.7.2 LCD Timing (I8080/MOTO6800 Format)36.4 Interrupts36.5 Software Configuration Process36.5.1 Configure LCD (RGB Format) as TX Mode36.5.2 Configure LCD (I8080/MOTO6800 Format) as TX Mode36.5.3 Configure Camera as RX Mode36.6 Register Summary36.7 Registers37 H264 Encoder37.1 Overview37.2 Terminology37.3 Features37.4 Architecture37.5 Functional Description37.5.1 Encoder Algorithm Core (ENC_CORE)37.5.1.1 Architecture37.5.1.2 Quantization Result Decimation37.5.1.3 Motion Vector (MV) Merging37.5.1.4 MB Level Rate Control37.5.1.5 Region of Interest (ROI)37.5.2 H264 Dedicated DMA37.5.2.1 Architecture37.5.2.2 Linked List Descriptor37.5.2.3 Transfer Initialization37.5.2.4 Transfer Reset37.5.2.5 Channel Configuration37.6 Interrupts37.7 Programming Procedures37.7.1 GOP Mode37.7.2 Dual Stream Mode37.7.3 Soft Reset37.8 Register Summary37.8.1 H264 Encoder Register Summary37.8.2 H264 DMA Register Summary37.9 Registers37.9.1 H264 Encoder Registers37.9.2 H264 DMA Registers38 MIPI CSI38.1 Introduction38.2 Terminology38.3 Feature List38.4 Architectural Overview38.5 Functional Description38.5.1 Data Lane State38.5.2 MIPI RX D-PHY Operation38.5.2.1 No-Power State38.5.2.2 Shut-Down State38.5.2.3 AFE Initialization38.5.2.4 Control Mode38.5.2.5 High-Speed Data Reception Mode38.5.2.6 Escape Mode38.5.3 MIPI RX D-PHY Configuration38.5.3.1 MIPI RX D-PHY Programming Interface38.5.3.2 MIPI RX D-PHY Test Code38.5.4 Descrambler38.5.5 Error Management38.6 Interrupts38.7 Programming Procedures38.7.1 Start High-Speed Data Reception38.7.1.1 Clock and Reset38.7.1.2 MIPI RX D-PHY and MIPI Host Initialization38.7.2 Stop High-Speed Data Reception38.8 Register Summary38.9 Registers39 Voice Activity Detection (VAD)39.1 Introduction39.2 Feature List39.3 Architectural Overview39.4 Functional Description39.4.1 Algorithm Parameter Configuration39.4.2 Wake-up Source Configuration39.5 Interrupts39.6 Programming Procedure39.6.1 Automatic Operation Mode39.6.2 Manual Operation Mode39.7 Register Summary39.8 RegistersVII Connectivity Interface40 UART Controller (UART)40.1 Overview40.2 Features40.3 UART Structure40.4 Functional Description40.4.1 Clock and Reset40.4.2 UART FIFO40.4.3 Baud Rate Generation and Detection40.4.3.1 Baud Rate Generation40.4.3.2 Baud Rate Detection40.4.4 UART Data Frame40.4.5 AT_CMD Character Structure40.4.6 RS48540.4.6.1 Driver Control40.4.6.2 Turnaround Delay40.4.6.3 Bus Snooping40.4.7 IrDA40.4.8 Wakeup40.4.9 Flow Control40.4.9.1 Hardware Flow Control40.4.9.2 Software Flow Control40.4.10 GDMA Mode40.4.11 Interrupts40.5 Programming Procedures40.5.1 Register Type40.5.2 Detailed Steps40.5.2.1 Initializing UARTn40.5.2.2 Configuring UARTn Communication40.5.2.3 Enabling UARTn40.6 Register Summary40.6.1 UART Register Summary40.6.2 LP UART Register Summary40.6.3 UHCI Register Summary40.7 Registers40.7.1 UART Registers40.7.2 LP UART Registers40.7.3 UHCI Registers41 SPI Controller (SPI)41.1 Overview41.2 Glossary41.3 Features41.4 Architectural Overview41.5 Functional Description41.5.1 Data Modes41.5.2 Introduction to Bus Signals41.5.3 Bit Read/Write Order Control41.5.4 Unaligned Byte Transfer41.5.5 Transfer Types41.5.6 CPU-Controlled Data Transfer41.5.6.1 CPU-Controlled Master Transfer41.5.6.2 CPU-Controlled Slave Transfer41.5.7 DMA-Controlled Data Transfer41.5.7.1 DMA Configuration41.5.7.2 DMA TX/RX Buffer Length Control41.5.8 Data Flow Control (Take GP-SPI as an Example)41.5.8.1 GP-SPI Functional Blocks41.5.8.2 Data Flow Control as Master41.5.8.3 Data Flow Control as Slave41.5.9 GP-SPI as a Master41.5.9.1 State Machine41.5.9.2 Register Configuration for State and Bit Mode Control41.5.9.3 Full-Duplex Communication (1-bit Mode Only)41.5.9.4 Half-Duplex Communication (1/2/4/(8)-bit Mode)41.5.9.5 DMA-Controlled Configurable Segmented Transfer41.5.10 GP-SPI Works as a Slave41.5.10.1 Configurable Communication Formats41.5.10.2 CMD Values Supported in Half-Duplex Communication41.5.10.3 Slave Single Transfer and Slave Segmented Transfer41.5.10.4 Configuration of Slave Single Transfer41.5.10.5 Configuration of Slave Segmented Transfer in Half-Duplex41.5.10.6 Configuration of Slave Segmented Transfer in Full-Duplex41.6 CS Setup Time and Hold Time Control41.7 Clock Control41.7.1 GP-SPI Clock Control41.7.2 LP-SPI Clock Control41.7.3 Clock Phase and Polarity41.7.4 Clock Control as Master41.7.5 Clock Control as Slave41.8 GP-SPI Timing Compensation41.9 LP-SPI Wake-Up41.10 Differences Among LP-SPI, GP-SPI2, and GP-SPI341.10.1 Feature Differences41.10.2 Register Differences41.10.3 Interrupt Differences41.11 Interrupt41.11.1 Interrupt Description41.11.2 Interrupts Used in Master and in Slave (Take GP-SPI as an Example)41.12 Register Summary41.12.1 GP-SPI2 Register Summary41.12.2 GP-SPI3 Register Summary41.12.3 LP-SPI Register Summary41.13 Register41.13.1 GP-SPI2 Register41.13.2 GP-SPI3 Register41.13.3 LP-SPI Register42 I2C Controller (I2C)42.1 Overview42.2 Features42.3 I2C Architecture42.4 Functional Description42.4.1 Clock Configuration42.4.2 SCL and SDA Noise Filtering42.4.3 SCL Clock Stretching42.4.4 Generating SCL Pulses in Idle State42.4.5 Synchronization42.4.6 Open-Drain Output42.4.7 Timing Parameter Configuration42.4.8 Timeout Control42.4.9 Command Configuration42.4.10 TX/RX RAM Data Storage42.4.11 Data Conversion42.4.12 Addressing Mode42.4.13 R/W Bit Check in 10-bit Addressing Mode42.4.14 To Start the I2C Controller42.5 Functional Differences Between LP_I2C and I2C42.6 Programming Example42.6.1 I2C master Writes to I2C slave with a 7-bit Address in One Command Sequence42.6.1.1 Introduction42.6.1.2 Configuration Example42.6.2 I2C master Writes to I2C slave with a 10-bit Address in One Command Sequence42.6.2.1 Introduction42.6.2.2 Configuration Example42.6.3 I2C master Writes to I2C slave with Two 7-bit Addresses in One Command Sequence42.6.3.1 Introduction42.6.3.2 Configuration Example42.6.4 I2C master Writes to I2C slave with a 7-bit Address in Multiple Command Sequences42.6.4.1 Introduction42.6.4.2 Configuration Example42.6.5 I2C master Reads I2C slave with a 7-bit Address in One Command Sequence42.6.5.1 Introduction42.6.5.2 Configuration Example42.6.6 I2C master Reads I2C slave with a 10-bit Address in One Command Sequence42.6.6.1 Introduction42.6.6.2 Configuration Example42.6.7 I2C master Reads I2C slave with Two 7-bit Addresses in One Command Sequence42.6.7.1 Introduction42.6.7.2 Configuration Example42.6.8 I2C master Reads I2C slave with a 7-bit Address in Multiple Command Sequences42.6.8.1 Introduction42.6.8.2 Configuration Example42.7 Interrupts42.8 Register Summary42.8.1 I2C Register Summary42.8.2 LP_I2C Register Summary42.9 Registers42.9.1 I2C Registers42.9.2 LP_I2C Registers43 Analog I2C Controller43.1 Introduction43.2 Feature List43.3 Architectural Overview43.4 Functional Description43.5 Programming Procedures43.6 Register Summary43.7 Registers44 I2S Controller (I2S)44.1 Overview44.2 Terminology44.3 Features44.4 System Architecture44.5 Supported Audio Standards44.5.1 TDM Philips Standard44.5.2 TDM MSB Alignment Standard44.5.3 TDM PCM Standard44.5.4 PDM Standard44.6 I2S TX/RX Clock44.7 I2S Reset44.8 I2S Master/Slave Mode44.8.1 Master/Slave TX Mode44.8.2 Master/Slave RX Mode44.9 Transmitting Data44.9.1 Data Format Control44.9.1.1 Bit Width Control of Channel Valid Data44.9.1.2 Endian Control of Channel Valid Data44.9.1.3 A-law/-law Compression and Decompression44.9.1.4 Bit Width Control of Channel TX Data44.9.1.5 Bit Order Control of Channel Data44.9.2 Channel Mode Control44.9.2.1 TDM TX Mode44.9.2.2 PDM TX Mode44.9.3 Synchronous Counter44.10 Receiving Data44.10.1 Channel Mode Control44.10.1.1 TDM RX Mode44.10.1.2 PDM RX Mode44.10.2 Data Format Control44.10.2.1 Bit Order Control of Channel Data44.10.2.2 Bit Width Control of Channel Storage (Valid) Data44.10.2.3 Bit Width Control of Channel RX Data44.10.2.4 Endian Control of Channel Storage Data44.10.2.5 A-law/-law Compression and Decompression44.11 Event Task Matrix Feature44.12 I2S Interrupts44.13 Software Configuration Process44.13.1 Configure I2S as TX Mode44.13.2 Configure I2S as RX Mode44.14 Register Summary44.15 Registers45 LP I2S Controller45.1 Introduction45.2 Feature List45.3 Architectural Overview45.4 Supported Audio Standards45.4.1 TDM Philips Standard45.4.2 TDM MSB Alignment Standard45.4.3 TDM PCM Standard45.4.4 PDM Standard45.5 RX Clock45.6 Reset45.7 Master/Slave RX Mode45.8 Receiving Data45.8.1 Channel Mode Control45.8.1.1 TDM RX Mode45.8.1.2 PDM RX Mode45.8.2 Data Format Control45.8.2.1 Bit Order Control of Channel Data45.8.2.2 Bit Width Control of Channel RX Data45.8.2.3 Bit Width Control of Channel RX Data45.8.2.4 Endian Control of Channel Storage Data45.8.3 Internal Memory45.9 Interrupts45.10 Register Summary45.11 Registers46 Pulse Count Controller (PCNT)46.1 Introduction46.2 Feature List46.3 Architectural Overview46.4 Functional Description46.5 Interrupts46.6 Programming Procedures46.6.1 Channel 0 Incrementing Independently46.6.2 Channel 0 Decrementing Independently46.6.3 Channel 0 and Channel 1 Incrementing Together46.7 Register Summary46.8 Registers47 USB 2.0 High-Speed OTG47.1 Overview47.2 Glossary47.3 Features47.3.1 General Features47.3.2 Device Mode Features47.3.3 Host Mode Features47.4 Functional Description47.4.1 Controller Core and Interfaces47.4.2 Memory Layout47.4.2.1 Control & Status Registers (CSRs)47.4.2.2 FIFO Access47.4.3 FIFO and Queue Organization47.4.3.1 Host Mode FIFOs and Queues47.4.3.2 Device Mode FIFOs47.4.4 Interrupt Hierarchy47.4.5 DMA Modes and Slave Mode47.4.5.1 Slave Mode47.4.5.2 Buffer DMA Mode47.4.5.3 Scatter/Gather DMA Mode47.4.6 Transaction and Transfer Level Operation47.4.6.1 Transaction and Transfer Level Operation in DMA Mode47.4.6.2 Transaction and Transfer Level Operation in Slave Mode47.4.7 OTG47.5 Registers48 USB 2.0 Full-Speed OTG 48.1 Overview48.2 Glossary48.3 Features48.3.1 General Features48.3.2 Device Mode Features48.3.3 Host Mode Features48.4 Functional Description48.4.1 Controller Core and Interfaces48.4.2 Memory Layout48.4.2.1 Control & Status Registers (CSRs)48.4.2.2 FIFO Access48.4.3 FIFO and Queue Organization48.4.3.1 Host Mode FIFOs and Queues48.4.3.2 Device Mode FIFOs48.4.4 Interrupt Hierarchy48.4.5 Slave Mode and DMA Modes48.4.5.1 Slave Mode48.4.5.2 Buffer DMA Mode48.4.5.3 Scatter/Gather DMA Mode48.4.6 Transaction and Transfer Level Operation48.4.6.1 Transaction and Transfer Level Operation in DMA Mode48.4.6.2 Transaction and Transfer Level Operation in Slave Mode48.5 OTG48.5.1 OTG Interface48.5.2 ID Pin Detection48.5.3 Session Request Protocol (SRP)48.5.3.1 A-Device SRP48.5.3.2 B-Device SRP48.5.4 Host Negotiation Protocol (HNP)48.5.4.1 A-Device HNP48.5.4.2 B-Device HNP48.6 Registers49 USB Serial/JTAG Controller (USB_SERIAL_JTAG)49.1 Overview49.2 Features49.3 Functional Description49.3.1 CDC-ACM USB Interface Functional Description49.3.2 CDC-ACM Firmware Interface Functional Description49.3.3 USB-to-JTAG Interface: JTAG Command Processor49.3.4 USB-to-JTAG Interface: CMD_REP Usage Example49.3.5 USB-to-JTAG Interface: Response Capture Unit49.3.6 USB-to-JTAG Interface: Control Transfer Requests49.4 Recommended Operation49.5 Interrupts49.6 Register Summary49.7 Registers50 Ethernet Media Access Controller (EMAC)50.1 Overview50.2 Features50.3 Ethernet MAC Architecture50.4 Functional Description50.4.1 EMAC_CORE50.4.1.1 Transmission50.4.1.2 Reception50.4.2 EMAC_MTL (MAC Transaction Layer)50.4.3 EMAC_DMA50.4.3.1 Transmit Descriptors50.4.3.2 Receive Descriptors50.4.4 PHY Interface50.4.4.1 Media Independent Interface: MII50.4.4.2 Reduced Media Independent Interface: RMII50.4.4.3 Station Management Agent (SMA) Interface50.4.5 MAC Address Filtering50.4.5.1 Unicast Destination Address Filtering50.4.5.2 Multicast Destination Address Filtering50.4.5.3 Broadcast Address Filter50.4.5.4 Unicast Source Address Filter50.4.5.5 Inverse Filtering Operation50.4.6 Energy Efficient Ethernet (EEE) 50.4.6.1 Transmission50.4.6.2 Reception50.4.7 Source Address, VLAN, and CRC Control50.4.7.1 Source Address Control50.4.7.2 VLAN Control50.4.7.3 CRC Control50.4.8 Time Stamp50.4.8.1 Transmit Path50.4.8.2 Receive Path50.4.9 Remote Wakeup50.4.10 Good Transmitted and Received Frames50.5 Programming Procedures50.5.1 MAC System Layer Configuration50.5.2 EMAC Initial Configuration50.5.3 Starting Transmission50.5.4 Starting Reception50.5.5 TX Entering and Exiting the LPI State50.5.6 RX Entering and Exiting the LPI State50.6 Interrupts50.7 Register Summary50.8 Registers51 Two-Wire Automotive Interface (TWAI)51.1 Features51.2 Protocol Overview51.2.1 TWAI Properties51.2.2 TWAI Messages51.2.2.1 Data Frames and Remote Frames51.2.2.2 Error and Overload Frames51.2.2.3 Interframe Space51.2.3 TWAI Errors51.2.3.1 Error Types51.2.3.2 Error States51.2.3.3 Error State Transition51.2.3.4 Error Counter Rules51.2.4 TWAI Bit Timing51.2.4.1 Nominal Bit51.2.4.2 Hard Synchronization and Resynchronization51.3 Architectural Overview51.3.1 Bit Timing Logic51.3.2 Bit Stream Processor51.3.3 Acceptance Filter51.3.4 Receive FIFO51.3.5 Error Management Logic51.3.6 Registers Block51.4 Functional Description51.4.1 Modes51.4.1.1 Reset Mode51.4.1.2 Operation Mode51.4.2 Bit Timing51.4.3 Transmit and Receive Buffers51.4.3.1 Overview of Buffers51.4.3.2 Frame Information51.4.3.3 Frame Identifier51.4.3.4 Frame Data51.4.4 Receive FIFO and Data Overruns51.4.5 Acceptance Filter51.4.5.1 Single-Filter Mode51.4.5.2 Dual-Filter Mode51.4.6 Error Management51.4.6.1 Error Warning Limit51.4.6.2 Error Passive51.4.6.3 Bus-Off and Bus-Off Recovery51.4.7 Error Code Capture51.4.8 Arbitration Lost Capture51.4.9 Transceiver Auto-Standby51.5 Interrupts51.6 Register Summary51.7 Registers52 SD/MMC Host Controller (SDHOST)52.1 Overview52.2 Features52.3 SD/MMC External Interface Signals52.4 Functional Description52.4.1 SD/MMC Host Controller Architecture52.4.1.1 Bus Interface Unit (BIU)52.4.1.2 Card Interface Unit (CIU)52.4.2 Command Path52.4.3 Data Path52.4.3.1 Data Transmit52.4.3.2 Data Receive52.5 Software Restrictions for CIU Operations52.6 RAM for Receiving and Transmitting Data52.6.1 TX RAM Module52.6.2 RX RAM Module52.7 DMA Linked List52.8 DMA Descriptor Format52.9 Programming Procedures52.9.1 Initializing Registers52.9.2 Sending Commands52.9.3 Initializing DMA52.9.4 Initializing DMA Transmission52.9.5 Initializing DMA Reception52.10 Clock Phase Selection52.11 Interrupt52.12 Register Summary52.13 Registers53 LED PWM Controller (LEDC)53.1 Overview53.2 Features53.3 Architectural Overview53.4 Functional Description53.4.1 Timers53.4.1.1 Clock Source53.4.1.2 Clock Divider Configuration53.4.1.3 20-Bit Counter53.4.2 PWM Generators53.4.3 Duty Cycle Fading53.4.3.1 Linear Duty Cycle Fading53.4.3.2 Gamma Curve Fading53.4.3.3 Suspend and Resume Duty Cycle Fading53.4.4 Event Task Matrix Feature53.5 Interrupts53.6 Programming Procedures53.7 Memory Blocks53.8 Register Summary53.9 Registers54 Motor Control PWM (MCPWM)54.1 Overview54.2 Features54.3 Modules54.3.1 Overview54.3.1.1 Timer Module54.3.1.2 Operator Module54.3.1.3 Capture Module54.3.1.4 ETM Module54.3.2 PWM Timer Module54.3.2.1 Configurations of the PWM Timer Module54.3.2.2 PWM Timer's Working Modes and Timing Event Generation54.3.2.3 Shadow Register of PWM Timer54.3.2.4 PWM Timer Synchronization and Phase Locking54.3.3 PWM Operator Module54.3.3.1 PWM Generator Module54.3.3.2 Dead Time Generator Module54.3.3.3 PWM Carrier Module54.3.3.4 Fault Detection Module54.3.4 Capture Module54.3.4.1 Introduction54.3.4.2 Capture Timer54.3.4.3 Capture Channel54.3.5 ETM Module54.3.5.1 Overview54.3.5.2 MCPWM-Related ETM Events54.3.5.3 MCPWM-Related ETM Tasks54.4 Interrupts54.5 Register Summary54.6 Registers55 Remote Control Peripheral (RMT)55.1 Overview55.2 Features55.3 Functional Description55.3.1 Architecture55.3.2 RAM55.3.2.1 Structure of RAM55.3.2.2 Use of RAM55.3.2.3 RAM Access55.3.3 Clock55.3.4 Transmitter55.3.4.1 Normal TX Mode55.3.4.2 Wrap TX Mode55.3.4.3 TX Modulation55.3.4.4 Continuous TX Mode55.3.4.5 Simultaneous TX Mode55.3.5 Receiver55.3.5.1 Normal RX Mode55.3.5.2 Wrap RX Mode55.3.5.3 RX Filtering55.3.5.4 RX Demodulation55.3.6 Configuration Update55.4 Interrupts55.5 Register Summary55.6 Registers56 Parallel IO Controller (PARLIO)56.1 Introduction56.2 Glossary56.3 Features56.4 Architectural Overview56.5 Functional Description56.5.1 Clock Generator56.5.2 Clock & Reset Restriction56.5.3 Master-Slave Mode56.5.4 Receive Modes of the RX Unit56.5.4.1 Level Enable Mode56.5.4.2 Pulse Enable Mode56.5.4.3 Software Enable Mode56.5.5 RX Unit GDMA SUC EOF Generation56.5.6 TX Unit EOF Generation56.5.7 RX Unit Timeout56.5.8 Output Clock Gating of TX Unit56.5.9 Valid Signal Output of TX Unit 56.5.10 Bus Idle Value of TX Unit56.5.11 Data Transfer in a Single Frame56.5.12 Bit Reversal in One Byte56.6 Interrupts56.7 Programming Procedures56.7.1 Data Receiving Operation Process56.7.2 Data Transmitting Operation Process56.8 Application Examples56.8.1 Co-working with SPI56.8.2 Co-working with I2S56.8.3 Co-working with LCD56.9 Register Summary56.10 Registers57 BitScrambler57.1 Introduction57.2 Feature List57.3 Architectural Overview57.3.1 Data Path57.3.2 Control Path57.4 Functional Description57.4.1 Instructions57.4.2 Configuration Registers57.5 Programming Procedures57.6 Register Summary57.7 RegistersVIII Analog Signal Processing58 Touch Sensor (TOUCH)58.1 Terminology58.2 Feature List58.3 Architectural Overview58.3.1 Touch Panel58.3.2 Capacitive Touch Pin58.3.3 Touch Sensor58.4 Functional Description58.4.1 Touch FSM58.4.2 Sampled Signal Preprocessing58.4.2.1 Measurement Process58.4.2.2 Trigger Source of Measurement58.4.2.3 Scan Mode58.4.2.4 Frequency Hopping58.4.3 Touch Detection58.4.3.1 Sampled Value58.4.3.2 Hardware Touch Detection58.4.4 Proximity Mode58.4.5 Sleep Mode58.4.6 Moisture Tolerance58.4.7 Water Rejection58.5 Interrupts58.6 Register Summary58.6.1 Interrupt and Status Register Summary58.6.2 Configuration Register Summary58.7 Registers58.7.1 Interrupt and Status Registers58.7.2 Configuration Registers59 Temperature Sensor (TSENS)59.1 Overview59.2 Features59.3 Architecture59.4 Functional Description59.4.1 Temperature Sensor Power Up59.4.2 Temperature Sensor Clock59.4.3 Wake-Up Modes for Automatic Temperature Monitoring59.4.4 Temperature Measurement Range and Offset59.4.5 Data Conversion59.5 Event Task Matrix Feature59.6 Interrupts59.7 Programming Procedure59.8 Register Summary59.9 Registers60 ADC Controller (ADC)60.1 Overview60.2 Terminology60.3 Features60.4 Architecture60.5 Functional Description60.5.1 SAR ADC Power Up60.5.2 SAR ADC Channels60.5.3 SAR ADC Clock60.5.4 SAR ADC Conversion and Attenuation60.5.5 HP ADC FSM60.5.6 HP ADC Pattern Table60.5.7 HP ADC Pattern Configuration Example for Multi-channel Sampling60.5.8 Dual HP ADC Sampling Control60.5.9 HP ADC Filters60.5.10 HP ADC Threshold Monitors60.5.11 HP ADC GDMA Support60.5.12 LP ADC Wake-Up Modes for Automatic Monitoring60.6 Event Task Matrix Feature60.7 Interrupts60.8 Programming Procedure60.8.1 HP ADC Multi-Channel Sampling Mode60.8.2 LP ADC One-shot Sampling Mode60.8.3 LP ADC Automatic Monitoring60.9 Register Summary60.9.1 HP ADC Register Summary60.9.2 LP ADC Register Summary60.10 Registers60.10.1 HP ADC Registers60.10.2 LP ADC Registers61 Analog Voltage Comparator61.1 Introduction61.2 Feature List61.3 Architectural Overview61.4 Functional Description61.5 Event Task Matrix Feature61.6 Interrupts61.7 Programming ProceduresIX AppendixRelated Documentation and ResourcesGlossaryAbbreviations for PeripheralsAbbreviations Related to RegistersAccess Types for RegistersProgramming Reserved Register FieldIntroductionProgramming Reserved Register FieldInterrupt Configuration RegistersRevision History
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HP GPIO matrixHP IOMUX0 (FUNC)2 (FUNC) GPIOSYNCMCU_SELGPIO_FUNCy_IN_SEL1 (FUNC)63Constant 1 inputConstant 0 input62012GPIO0_inGPIO1_inGPIO2_inGPIO54_in54GPIOX_inXGPIO_FUNCy_IN_INV_SELsig_in_func[y]GPIO_SIGy_IN_SEL0(FUNC)HP Peripheral Signal Y1(GPIO)0 1 GPIO_FUNCx_OUT_SELsignal0_outsignal2_outsignal255_outGPIO_OUT_DATA_bit_x012255256GPIOx_outsignal1_outPeripheral Signal YMCU_SEL1(FUNC)0(FUNC)2(FUNC)01GPIO_FUNCX_OUT_INV_SEL222 HP peripheral inputsPADbufOEIEWPUWPDPin X supplied byVDD_IO_0, VDD_FLASHIO, VDD_IO_4~VDD_IO_6253Pin X supplied byVDD_LPPADbufOEIEWPUWPD3232 HP peripheral outputs GPIOFilter14Peripheral Signal Y’VDD_IO_0, VDD_FLASHIO, VDD_IO_4~VDD_IO_6 power domainVDD_LP power domain GlitchFilter0 1 GPIOSD_FILTER_CH0~7_INPUT_IO_NUM == X01MUX_SEL6LP GPIO matrixLP IOMUX0 ( FUNC)2 ( FUNC)MCU_SELGPIO_FUNCy_IN_SEL1 ( FUNC)24~31Constant 1 inputConstant 0 input16~23012GPIO0_inGPIO1_inGPIO2_inGPIO15_in15GPIOX_inXGPIO_FUNCy_IN_INV_SELsig_in_func[y]GPIO_SIGy_IN_SEL0(FUNC)LP Peripheral Signal Y1(GPIO)0 1 GPIO_FUNCx_OUT_SELsignal0_outsignal2_outsignal31_outGPIO_OUT_DATA_bit_x0123132GPIOx_outsignal1_outPeripheral Signal YMCU_SEL1(FUNC)0(FUNC)2(FUNC)01GPIO_FUNCX_OUT_INV_SEL14 LP peripheral inputs14 LP peripheral outputs Peripheral Signal Y’ GPIOFilterCININC7 fi •
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Digital Core Low Power CoreCPU0 PeripheralsDigital GPIOHP Core ResetSystem ResetHP CPU1 ResetChip ResetANALOGDigital SystemESP32-P4CPU1HP CPU0 ResetLP CPULPPeripheralsLPAONLP CPU ResetLP Core Reset fi •
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XTALPLLMUXRCXTAL_PXTAL_NXTAL_CLKCPLL_CLK (400MHz)RC_FAST_CLKDIVROOT_CLKDIV DIV DIVCPU_CLK (MAX 400MHz) SYS_CLK (MAX 200MHz)MEM_CLK (MAX 200MHz)APB_CLK (MAX 100MHz)PLL DIVMPLL_CLK (500MHz) PLL_F50M_CLKDIVPLL_F25M_CLKPLL DIVSPLL_CLK (480MHz) PLL_F240M_CLKDIVPLL_F160M_CLKDIVPLL_F120M_CLKDIVPLL_F80M_CLKDIVPLL_F20M_CLKMUXXTAL_CLKRC_FAST_CLKPLL_FxxM_CLKICG DIVPERI_XXM_CLKTypical HP Peripheral Clock GenerationMUXXTAL32K_CLKRC_SLOW_CLKMUXPLLXTAL_CLKRC_FAST_CLKPLL_LP_CLKXTAL32K_PXTAL32K_NOSC_SLOW_CLKDIVXTAL_CLK XTAL_D2_CLKMUXMUXLP_DYN_SLOW_CLKLP_DYN_FAST_CLKLP_SLOW_CLKLP_FAST_CLKMUXLP_FAST_CLKXTAL_D2_CLKPLL_LP_CLKICGPERI_XXM_CLKTypical LP Peripheral Clock GenerationXTALRCOSCDIVLP_PERI_CLK fi •
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ETM channelChannel nEventsTasks MUXDEMUXSOC_ETM_CHn_EVT_ID SOC_ETM_CHn_TASK_IDSOC_ETM_CH_ENABLEnSOC_ETM_CH_DISABLEnSOC_ETM_CH_ENABLEDn fi fi fifi fi fi fi
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31 1211109876 5 43210Reset fi fi fl fi fi fi fi
fi fi fi fi
31 29282726252423222120191817161514131211109876543210Reset fi fi fi fi fi
fi fi fi fi fi fi fl fi
fi fi fi fi fi fi fi
fi fi fi fi fi fi fi
313029282726252423222120191817161514131211109876543210Reset fi fi fi fi fi fi
fi fi fi fi fi fi fi
fi fi fi fi fi fi fi
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31 543210Reset fi fi fi fi fi fi
31 0Reset 31 10Reset fi
31 1211109876 5 43210Reset fi fi fl fi fi fi fi
fi fi fi fi
31 29282726252423222120191817161514131211109876543210Reset fi fi fi fi fi fi
fi fi fi fi fi fl fi fi
fi fi fi fi fi fi fi
fi fi fi fi fi fi
313029282726252423222120191817161514131211109876543210Reset fi fi fi fi fi fi
fi fi fi fi fi fi fi
fi fi fi fi fi fi fi
fi fi fi fi fi fi fi
fi fi fi
31 543210Reset fi fi fi fi fi fi
31 0Reset 31 10Reset fi
31 222120191817161514131211109876543210Reset fi fi fi fi fi fi
fi fi fi fi fi fi fi
fi fi fi fi fi fi fi
fi 31 2 1 0Reset fi 31 2 1 0Reset fi
31 109 87 65 43 21 0Reset fi fi fi fi fi
fi 31 0Reset 31 10Reset fi
31 2423222120191817161514131211109876543210Reset fi fi fi fi fi
fi fi fi fi fi fi fi
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fi fi fi
31 2423222120191817161514131211109876543210Reset fi fi fi fi fi
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fi fi fi fi fi • • • fi • • • fi
fi fi • • • • fi fi • • • fi fi fi • • • fi fl fi • • fi • • • fi
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fi 31 0Reset 31 10Reset fi
31 10Reset 31 10Reset 31 10Reset
31 10Reset 31 30 0Reset
31 30 0Reset 31 30 0Reset
31 30 0Reset 31 6543210Reset
31 6543210Reset
31 6543210Reset
31 6543210Reset
31 654 3 210Reset fi fi fi fi
31 654 3 210Reset fi fi fi 31 10Reset fi
31 10Reset fi 31 10Reset fi
31 210Reset
31 43210Reset fi fi fi fi
31 0Reset fi 31 98 0Reset fi
31 3210Reset fl
31 3210Reset 31 3210Reset
31 3210Reset 31 10Reset
31 30 0Reset 31 30 0Reset
31 30 0Reset
31 6543210Reset fi fi fi fi fi fi
31 2524 222120 0Reset
31 272625 17161514 0Reset fl 31 10Reset fi
31 43 0Reset fi 31 43 0Reset fi 31 2625 0Reset fi fl
31 10Reset fi 31 1312 0Reset
31 65 0Reset fi 31 21 0Reset fi
31 54 10Reset fi fi fi 31 10Reset fi
31 1716 10Reset fi fi 31 1716 10Reset fi fi
31 1716 10Reset fi fi 31 3210Reset fi fi
31 10Reset fi
31 87 43 0Reset fi fi
31 43210Reset fi fi fi fi
31 3210Reset fi fi fi
31 3210Reset fi fi fi
31 2423 16 15 10Reset fi fi 31 210Reset fi fi
31 43210Reset fi fi fi fi
31 21 0Reset fi
31 87654 210Reset fi fl fi fi
31 0Reset 31 0Reset
31 2524 23 21201918171615 14 10Reset fi fi fi fi
fi fi fi 31 10Reset fi
31 131211109876543210Reset fi fi fi fi fi
fi fi
31 3210Reset fi fi 31 10Reset fi
31 10Reset fi 31 210Reset fi fi
31 10Reset 31 32 0Reset fi
31 0Reset fi 31 98 0Reset fi
fi 31 0Reset 31 10Reset fi
31 121110 76 43 0Reset 31 0Reset
31 10987 0Reset fi
31 0Reset
31 1098 7 54 0Reset
31 3210Reset 31 3210Reset
31 3210Reset 31 3210Reset
31 2423 2120 1817 1514 12 11 65 3 2 0Reset fi fi fi fi fi
31 2827 2423 2019 1615 1211 87 43 0Reset fi fi fi fi fi fi fi fi
31 2827 2423 2019 1615 1211 87 43 0Reset fi fi fi fi fi fi fi fi 31 1312 0Reset fi fi
fi 31 0Reset
31302928 2120 14 13 121110 3210Reset fi fi fi fi
fi fi
31 10Reset fi 31 210Reset fi fi
31 0Reset fi 31 8765 4 0Reset fi fi
31432 10Reset fi 31 5432 0Reset fi fi fi
31 5432 0Reset fi fi fi 31 0Reset fi
31 0Reset fi 31 0Reset fi 31 0Reset fi
31 24 23 1615 8 7 0Reset fi fi fi fi
31 2322 181716 10Reset fi fi fi fi
31 1716 10Reset fi fi 31 1716 10Reset fi fi
31 0Reset
31 7654 0Reset
31 0Reset 31 0Reset 31 0Reset
31 7654 0Reset 31 0Reset
31 76543210Reset
31 76543210Reset
31 76543210Reset
31 76543210Reset
31 32 0Reset fi 31 2928 16 15 1098 10Reset fi fi fi
• fi • fi • • fi fi fi
fl fi fi fi fi • • • • • • •
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fi fi fi fi fi fi fi fi fl fi fi fi fi fi
fi fi fi fi fi fi fi fi fi fi fi fi fi
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fi fi fi fi 31 109 87 543 0Reset fi fi fi fi fi fi
fi fi fi 31 0Reset fi
31 43 0Reset fi fi fi fi fi fi fi fi fi 31 0Reset fi
31 0Reset fi 31 0Reset fi 31 0Reset fi
31 0Reset 31 10Reset fi
31 210Reset fl fl fl fi fl 31 10Reset fi
31 2827 0Reset
fi 31 543 0Reset fi fi fi fi fi fi
31 987 10Reset fi fi 31 0Reset fi
31 43 0Reset fi fi fi fi fi fi fi fi fi 31 0Reset fi
31 0Reset fi 31 0Reset fi 31 0Reset fi
31 0Reset 31 10Reset fi
31 210Reset fl fl fl fi fl 31 10Reset fi
31 2827 0Reset
31 109876543210Reset fi fi fi fi fi
fi fi fi fi fi
31 0Reset fi 31 0Reset fi
31 0Reset fi 31 0Reset fi
31 0Reset fi 31 0Reset fi
31 0Reset fi 31 0Reset fi 31 0Reset
31 0Reset 31 0Reset fi 31 0Reset fi
31 0Reset
31 109876543210Reset
31 109876543210Reset
31 109876543210Reset
31 210Reset fi fi 31 0Reset
31 0Reset 31 0Reset
31210Reset
31 109876543210Reset fi fi fi fi fi
fi fi fi fi fi
31 0Reset fi 31 0Reset fi
31 0Reset fi 31 0Reset fi
31 0Reset fi 31 0Reset fi
31 0Reset fi 31 0Reset fi 31 0Reset
31 0Reset 31 0Reset fi 31 0Reset fi
31 0Reset
31 109876543210Reset
31 109876543210Reset
31 109876543210Reset
31 210Reset fi fi 31 0Reset
31 0Reset 31 0Reset
31 210Reset 31 10Reset fi
31 2827 0Reset
fi • • •
Message0Message1Message15...LP_INTR_CtrlAPB...HP_INTR_CtrlLP MailBoxBUSHP CPUHP CPULP CPUMB_LP_INTRMB_HP_INTRLP_INTR_MAPINTR_Matrixcore0_intr_vectorcore1_intr_vectorlpcore_intr_vector • •
• • • • • fi • fi fi
fi fi
31 0Reset 31 0Reset 31 0Reset 31 0Reset
31 0Reset 31 0Reset 31 0Reset 31 0Reset
31 0Reset 31 0Reset 31 0Reset 31 0Reset
31 0Reset 31 0Reset 31 0Reset 31 0Reset
31 10Reset fi
31 161514131211109876543210Reset
31 161514131211109876543210Reset
31 161514131211109876543210Reset
31 161514131211109876543210Reset
31 161514131211109876543210Reset
31 161514131211109876543210Reset
31 161514131211109876543210Reset
31 161514131211109876543210Reset
fi fl fi • • fi fi fi • fi • fi
AnalogBrown Out&&LP_ANA_BOD_MODE1_RESET_ENAbod_mode1_reset_enbrownout cntinvLP_ANA_BOD_MODE0_INTR_ENALP_ANA_BOD_MODE0_CNT_CLRcmp0cmp1LP_ANA_BOD_MODE0_RESET_WAITLP_ANA_BOD_MODE0_INTR_WAIT&&||bod_mode0_reset_en&&LP_ANA_BOD_MODE0_CLOSE_FLASH_ENAbod_mode0_intbod_mode0_close_flashrtc_bod_sys_resrt_enDigitalLP_ANA_BOD_SOURCE_ENA1RTC_VGOOD_VBAT1RTC_VGOOD_VDDA[1][2]PMU_BOD_BAT_SOURCE_SEL01LP_ANA_BOD_MODE0_RESET_ENA • fi • fi • fi fi • fl fl • • fi
• fi fi fi • fi fi fi • fi fi fi
vdd_cntLP_ANA_VDDBAT_UNDERVOLTAGE_TARGETbod_sourcevdd_undervolatge_flag1 2 3 4 5 6 7LP_ANA_VDDBAT_UNDERVOLTAGE_INTLP_ANA_VDDBAT_UPVOLTAGE_INTLP_ANA_VDDBAT_UPVOLTAGE_TARGET fi fl fl fl fl fl fl
• • fi • fi • fi • fi • fi fi fi fi • fi fi fi fi • fi
fi 3130292827 1817 876 5 0Reset fi fl fi fi fi fi fi
31 2726 25 24 1918 17 16 1110 9 8 0Reset fl fl fl fi
31 2221 1211 10 10Reset fi fi
31 2221 1211 10 10Reset fi fi
3130292827 26 0Reset
3130292827 26 0Reset
3130292827 26 0Reset fi fi fi fi fi
3130292827 26 0Reset fi fi fi fi fi
fi • •
• fi • fi fi fi
• • • • fi fi 12
fi
fi fi fi fi fi 1 2 fi fi fi
fi fi fi
fi • •
X Y X X = X1||X2|| · · · ||Xn−1||Xn X1, X2, · · · , Xn−1 Xn = 0 X X 0 < <= 127 fi X∗n X∗n= Xn||0128− X X1||X2|| · · · ||Xn−1||X∗n X||0128− • •
32 128 32 128 P C P C · · · fi fi fi • • fi • • fi • • •
fi • • fi • • • • • H J0 T0
AAD C P 232 AAD C P 232 H AAD
32 J0 P C J0 T0 T0 t fi T fi H fi H K0128 fi H fi fi J0J0 J0 fi J0 fi fi t 1 <= t <= 128• t = 128 T0 fi fi • 1 <= t < 128 t fi T0 tT0 t fi T0 4 5 t
AAD P C T0 fi• fi C C • C • fi
fi fi fi fi fi
fi 31 0Reset 31 0Reset 31 0Reset
31 32 0Reset fi 31 10Reset fi
31 32 0Reset fi 31 0Reset 31 10Reset fi 32 128
31 0Reset 31 76 0Reset 31 10Reset fi
31 21 0Reset 31 10Reset fi
31 10Reset fi 31 10Reset fi 31 10Reset fi
• fi • • fi y2=x3+ax+bp• p • a b p• (x, y) fi
• fi y2= x3+ ax + b p• Y2= X3+ aXZ4+ bZ6 p fi (x, y) (X, Y, Z)• fi x = X/Z2 py = Y /Z3 p• fi X = xY = yZ = 1 D[255 : 0] D[n][31 : 0](n = 0, 1, · · · , 7) fiD[255 : 0] = D[7][31 : 0], D[6][31 : 0], D[5][31 : 0], D[4][31 : 0], D[3][31 : 0], D[2][31 : 0], D[1][31 : 0], D[0][31 : 0] fi D[n][31 : 0](n = 0, 1, · · · , 7) 4 × n • D[0]
• D[1] • · · ·• D[7] fi D[n][31 : 0](n = 0, 1, · · · , 7) 4 × n • D[0] • D[1] • · · ·• D[7] fi fi fi fi fi fi fi fi fi fi
fi fi fi fi fi fi fi fi fi fi Q = (Qx, Qy) = (Jx, Jy, Jz) = k · (Px, Py)• (Qx, Qy) fi • (Jx, Jy, Jz) • Px Py k • Qx Qy fi fi fi fi fi (Px, Py) • Px Py • fi
fi fi fi fi fi fi (Px, Py) Q = (Qx, Qy) = (Jx, Jy, Jz) = k · (Px, Py)• (Qx, Qy) fi • (Jx, Jy, Jz) • Px Py k • fi Qx Qy Jx Jy Jz Q = (Qx, Qy, Qz) = k · (Px, Py, 1)• (Qx, Qy, Qz) • • Px Py k • Qx Qy Qz R = (Rx, Ry) = (Jx, Jy, Jz) = (Px, Py, 1) + (Qx, Qy, Qz)• (Rx, Ry) fi • (Jx, Jy, Jz) • • Px Py Qx Qy Qz
• Rx Ry Jx Jy Jz fi fi (Qx, Qy, Qz) • (Qx, Qy, Qz) • Qx Qy Qz • fi fi fi fi fi fi (Px, Py) Q = (Qx, Qy, Qz) = k · (Px, Py, 1)• (Qx, Qy, Qz) • • Px Py k • fi Qx Qy Qz R = A + B N• fi •
R = A − B N• fi • R = A · B N• fi • R = A · B−1 N• fi •
fi fi fi • • • • fi fi fi
fi
fi fi
fi 31 10Reset 31 10Reset
31 10Reset 31 10Reset
313029 28 87 43210Reset fi fi fi fi fi fi fi fi fi
fi fi fi fi fi 31 2827 0Reset
• • • • fl fi fi fi
• • • • • fi
fi fi y y (y − 4) (y−4) fi fi
fi fi fi fi m fi fi fi
n >= 0 • fi • fi • • fi
fl m k k fim + 1 + k≡448(mod512) m fi fi
0 0 0 fi
fi fi fi fi fi
fi 31 10Reset fi 31 10Reset fi fi fi fi
31 10Reset 31 10Reset fi 3110Reset fi
31 10Reset fi 31 10Reset fi
31 10Reset fi 31 10Reset 31 10Reset fi
31 43 0Reset fi 31 32 0Reset fi fi 31 0Reset 31 0Reset
31 10Reset fi 31 10Reset 31 10Reset fi
31 0Reset 31 3029 0Reset
fi fl • • • • • fi
fi N = 32 × n fi b b = 232 b n =N32Z = (Zn−1Zn−2· · · Z0)bX = (Xn−1Xn−2· · · X0)bY = (Yn−1Yn−2· · · Y0)bM = (Mn−1Mn−2· · · M0)br = (rn−1rn−2· · · r0)b Zn−1· · · Z0 Xn−1· · · X0 Yn−1· · · Y0 Mn−1· · · M0 rn−1· · · r0 b Zn−1 Xn−1 Yn−1 Mn−1 rn−1 fi Z X Y M Z0 X0 Y0 M0 r0 fi fi R = bn r r = R2 M M′ M′= − M−1 b M−1 M Z = XY M X Y M r M′ N = 32 × n n ∈ {1, 2, 3, . . . , 128} Z X Y M r N M′ fi fi (N32− 1)
M′ fi Xi Yi Mi ri i ∈ {0, 1, . . . , n − 1} b fi fi Zi i ∈ {0, 1, . . . , n − 1} Xi ri Z = X × Y M r M′ N = 32 × n n ∈ {1, 2, 3, . . . , 128} fi fi (N32− 1) M′ Xi Yi Mi ri i ∈ {0, 1, . . . , n − 1} b fi fi
Zi i ∈ {0, 1, . . . , n − 1} Xi Yi Mi M′ ri Z = X × Y Z X Y N= 32×n n∈ {1,2,3, . . . ,64} ˆN Z2×N (ˆN32−1) (N16−1) Xi Yi ∈ {0, 1, . . . , n − 1} b fi n N32 Xi i ∈ {0, 1, . . . , n − 1} i Yi i ∈ {0, 1, . . . , n − 1} i n + i 4 × (n + i) Zi i ∈ {0, 1, . . . , ˆn − 1} ˆn 2 × n Xi Yi fi fi
fi fi fi Z = XY M fi Y fi Y Y = (eYN−1eYN−2· · ·eYt+1eYteYt−1· · ·eY0)2• N Y •eYt •eYN−1eYN−2 eYt+1 • eYt−1eYt−2 eY0 m tm eYt−1eYt−2, · · · ,eY0 t − m fi • fi eYi i > α α fi α N α t eYN−1eYN−2 eYt+1 α t Z = XY M • fi Y fi • Z = XY M• N
• Y • X M • α fi Z = XY M 174.7 × 106 1.023 × 106 0.546 × 106 0.540 × 106 • fi • fi • fi • fi
fi fi fi fi fi
fi 31 0Reset M′ 31 76 0Reset fi 31 10Reset fi
31 10Reset fi 31 10Reset fi 31 10Reset
31 10Reset fi 31 10Reset fi 31 1211 0Reset fi fi fi
31 10Reset 31 10Reset 31 10Reset 31 3029 0Reset
fi • • • • • • fi
fi fi fi fi fi fi fi fi
M m M • k k m + 1 + k ≡ 448 mod m • k k m + 1 + k ≡ 896 mod m N • N M(1) M(2) M(N) fi i (i)0 (i)1 (i)15 (i)0 (i)1 (i)15 • N fi i (i)0 (i)1 (i)15 fi fi (i)0 fi fi (i)15
(0) t t tt t t fi t• 1 <= t <= 9 tlength = 7′h48 tstring 8′h30 + 8′ht01′b1 23′b0 t0= t t0 tstring 32′h38800000• 10 <= t <= 99 tlength = 7′h50 tstring 8′h30 + 8′ht18′h30 + 8′ht01′b1 15′b0 t0= t10 t1= t/10 t0 t1 tstring 32′h35368000• 100 <= t < 512 tlength = 7′h58 tstring 8′h30 + 8′ht28′h30 + 8′ht18′h30 + 8′ht01′b1 7′b0 t0= t10 t1= ( t/10) 10 t2= t/100 t0 t1 t2 tstring 32′h32333180
M fi • fi • 1• fi fi • fi 2 • 3 • • •
• fi 1• • • 3 • • • • fi •
• • fi • fi fi fi • M • fi • • •
• • fi fi fi • M • • • •
fi fi fi t roundup(t/32) • fi • • • • fi
• fi fi
fi fi
fi 31 32 0Reset fi 31 0Reset fi 31 76 0Reset fi
31 65 0Reset fi 31 10Reset 31 10Reset 31 10Reset
31 10Reset 31 10Reset 31 10Reset 31 10Reset
31 3029 0Reset 31 0Reset 31 0Reset
• • • Z = XY M Z X Y M fl DSAKEY HMACKEY X Z fi
• s s • xs s s x x s x [Y ]4096 8 [x]t (s − t) s fi [ x ]s 8= 0000010116= 0000010100000000 16= 0000000000000101 8= 0001001116= 0001001100000000 16= 0000000000010011• Y M r M′ Y M Y M r M′ C C C Z = XY M N = 32 × x x ∈ {1, 2, 3, . . . , 128} Z X Y M r N M′ fl
fi C • Y M fi [L]32=N32− 1 [L]32 32 [HM ACKEY ]256 [DSA KEY ]256 DSAKEY [HMACKEY ]256 1256 [IV ]128 • r M′ M • Y M r [Y ]4096 [M ]4096 [r]4096 Y M r • [MD]256 [Y ]4096||[M]4096||[r]4096||[M′]32||[L]32||[IV ]128• [P ]12672 [Y ]4096||[M]4096||[r]4096||[Box]384 [Box]384 [MD]256||[M′]32||[L]32||[β]64) [β]64 []64 [β]64 P • C [C]12672 [P ]12672 [DSAKEY ]256 [IV ]128 C C [C]12672[bY ]4096||[cM]4096||[br]4096||[dBox]384 [bY ]4096 [cM]4096 [br]4096 [dBox]384
C [Y ]4096 [M ]4096 [r]4096 [Box]384 C X IV C P C DSAKEY IV IV [IV ]128 fi [DSA KEY ]256 HMACKEY [DSA KEY ]256 [HMACKEY ]256 P [Y ]4096 [M ]4096 [r]4096 [M′]32 [L]32 [β]64 • [CALCM D]256[CALCMD]256 [MD]256 [CALCMD]256 [MD]256 • [β]64 [β]64 X Y M r M′ XY M fi L Z Z = XY M C X IV DSA KEY HM ACKEY C X IV
DSA KEY • • DSAKEY fi IV IV X Xii ∈ {0, 1, . . . , n − 1} n =N32 b fi fi X N C C • bYii ∈ {0, 1, . . . , 127} • cMii ∈ {0, 1, . . . , 127} • brii ∈ {0, 1, . . . , 127} • dBoxii ∈ {0, 1, . . . , 11} b fi • Z• Z • Z
• Z Zii ∈ {0, 1, . . . , n − 1} n =N32 Z
r
fi IV IV IV IV DSAKEY
fi 31 0Reset IV 31 10Reset fi 31 10Reset fi
31 10Reset fi 31 10Reset 31 43 0Reset fi DSAKEY
31 210Reset 31 3029 0Reset
fi fi fi fi • fi• fi • fi • fi fi fi fi • p fi fi fi fi fi a b G
n G • fi fi fi• p• fi a b• G n • d n • • Q Q = dG • Q Qx Qy m e e z z Ln e Ln n k n n x y kG
r x n r k s k−1 (z + d ∗ r) n s k r s m r s fi fi fi Q m r s e e z z Ln e Ln n fi r s n n r s u1= z ∗ s−1 n u2= r ∗ s−1 n (x1, y1) = u1∗ G + u2∗ Q G Q r = x1 n r x1 n fi fi fi
fi D[255 : 0] D[n][31 : 0](n = 0, 1, · · · , 7) fiD[255 : 0] = D[7][31 : 0], D[6][31 : 0], D[5][31 : 0], D[4][31 : 0], D[3][31 : 0], D[2][31 : 0], D[1][31 : 0], D[0][31 : 0] fi D[n][31 : 0] 4 × n • D[0] • D[1]
• · · ·• D[7] fi D[n][31 : 0] 4 × n • D[0] • D[1] • · · ·• D[7] M LM M LA LA LM+ 1 + LA≡ 448 mod LM N M(1) M(2) M(N)
fi fi • • • • • • fi
IDLEPOSTPREPLOADPROC fi d fi fi fi fi fi z fi fi
z • z z • z fi r s Qx Qy fi fi z • 1• fi
• fi 2 • • • fi • fi fi fi fi • fi
fi fi fi fi
• • • fi fi
fi 31 54321 0Reset fi fi z 31 210Reset fi fi fi
31 10Reset fi 31 210Reset
31 210Reset 31 210Reset 31 210Reset
31 21 0Reset 31 210Reset k k k k k k k
31 32 0Reset fi 31 10Reset fi fi 31 10Reset fi
31 10Reset 31 2827 0Reset
fi fl fi fl • • • • fi • fi
ManualEncryptionAutoDecryptionSystemRegisterExternal MemoryEncryption/DecryptioneFuseControllerEFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPTEFUSE_SPI_BOOT_CRYPT_CNTBoot ModeHP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPTHP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPTHP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPTAutoEncryptionKeyHP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT fl fi fl • • • •
fi Key Key Key Key fi• A A KeyA • B B KeyB • C C KeyC fi Key A B C Key A BC Key KeyA KeyB KeyCABCKey Key KeyA||KeyB KeyA||0256 0256||KeyB KeyC 0256• • • 0256 • ||
fi fi • ty pe fl fl • size • baseaddr size baseaddrsize == 0 fl fl fi fi fi tweak tweak type ∗ 230 baseaddr tweak fi address fi offset address64 n offset4 n size offset
offset offset fi fl • • Key fi •
• • Key • fi • • • Key •
fi • type • baseaddr• size32 fi baseaddr size Key fl • fi • fi fi • fi selectreg = regddpaen = ef usedpa en =
regantidpalevel = ef useanti dpa level = • fi AntiDP Alevel = selectreg ? (regantidpal evel) : (efusedpaen ∗ ef useantidpalevel) AntiDP Alevel AntiDP Alevel • fi AntiDP AenabledincalcD = selectreg ? regddpaen : efusedpaen AntiDP Alevel AntiDP AenabledincalcD AntiDP Alevel • fi selectreg regantidpalevel • fi
fi fi fi fi
fi 31 0Reset fi 32 21 0Reset fi
31 10Reset fi fl fl 31 3029 0Reset fi
31 5432 0Reset fi fi fi fi fi fi 31 10Reset fi
31 10Reset fi 31 10Reset fi 31 21 0Reset
31 3029 0Reset
fi • • SAR ADCRandomNumberGeneratorRC_FAST_CLK Random bit seeds Random bit seeds XOR LPSYSREG_RNG_DATA_REG
• • • fi
fi 31 0Reset
fi
fi fi fi
fi fi fi fi fi
fi • • fl • • • •
• fi fi • • • • • • • fi fi • • • fi
• • • • fi • fi fi • • fi fi fi • • • fi • fi • • fi fi
fi • • Y = (0.299 ∗ R) + (0.587 ∗ G) + (0.114 ∗ B)U = (−0.1687 ∗ R) + (−0.3313 ∗ G) + (0.5 ∗ B) + 128V = (0.5 ∗ R) + (−0. 4187 ∗ G) + (−0.0813 ∗ B) + 128 fi fi • • • fi fi fi fi fi
fi • • fi fi • fi fi • fi fi fi 0 1 2 3 4 5 6 78 9 10 11 12 13 14 1556 57 58 59 60 61 62 63 fi fi fi • fi fi fi fi fi fi fi fi fi fi • fi fi fi fi fi fi fi fi • • fi fi
fi fi fi • • fi • •
fi fi
fi fi fi fi fi fi fi fi fi fi fi • fi fi • fi • fi fi fi fi fi fi
• • • fi • • fi fi • fi fi fi • fi fi fi • fi
fi fi • fi fi fi fi • 2JP EGDECODET IMEOUT T HRES− 1 • 2JP EGDECODET IMEOUT T HRES− 1 fi • fi
• • • • fi • fi • fi • fi • fi • fi • fi • • • • • • • • fi
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• • fi • fi • fi • fi • fi • fi fi fi fi • • fi • fi • fi • fi • fi • fi fi fi
fi • • fi • fi • fi • fi • fi • • • fi • fi fi • • • fi
fi • • • • • • • fi fi • • fi • • fi • • fi fi • fi • fi
fi fi fi • • fi • fi • fi fi • • fi • fi • fi fi fi fi • fi • fi fi fi
• fi • fi • • • fi • fi fi • • • fi fi • • • • •
• fi fi fi fi fi • • • • • • fi fi fi • • •
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fi fi fi fi fi fi fi fi fi
fi 3130 2928272625242322 17161514 1312 1110 98765 43210Reset fi fi fi fi fi fi
fi fi fi fi fi fi fi fi fi fi fi fi 2JP EGDECODET IMEOUT T HRES− 1
fi fi fi fi fi fi fi fi
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31 0Reset fi fi 31 0Reset fi fi 31 0Reset fi fi
31 0Reset fi fi 31302928 2726 252423 1615 0Reset fi fi fi fi fi fi fi
31 2423 1615 1211 87 0Reset fi fi fi fi fi 31 2423 1615 1211 87 0Reset fi fi fi fi fi
31 2423 1615 1211 87 0Reset fi fi fi fi fi 31 2423 1615 1211 87 0Reset fi fi fi fi fi
31 1615 1211 87 43 0Reset fi fi fi fi 31 252423222120191817161514131211109876543210Reset
31 252423222120191817161514131211109876543210Reset
31 252423222120191817161514131211109876543210Reset
31 252423222120191817161514131211109876543210Reset
31 0Reset fi
31 0Reset fi 31 0Reset fi 310Reset fi
31 0Reset fi 31 0Reset fi 31 0Reset fi
31 0Reset fi 31 0Reset fi 31 0Reset fi
31 0Reset fi 31 0Reset fi 31 30 0Reset fi
31 2827 0Reset
• • • • CSI HOSTISPAXI-DMACfrom mipi camerafrom dvp camerafrom axi-dmacaxi infhandshakehandshaketo axi-dmacCSI_Bridge fi
fi fi fi fi • • • • • fi
BF LSC Demosaic CCM Gamma RGB2YUV SHARP COLORYUV LimitYUV2RGBAE AFAWB HISTAXI to IDI32GATEfrom mipi csifrom axi-dmacISP_PipelineDVP to IDI32from dvpISP_HeaderCSI_BridgeImage Interface 32 to 64ISP to Image Interface 64ISP_TailAXI-DMAChandshakeAXI-DMAChandshaketo axi-dmacISP_PipelineBLC • fi • • • • fi • fi fi fi
fi fi fi fi fi gain = ref lum/actlum fi fi gain = gain0 + (gain1 − gain0)/(539 − 511) ∗ (543 − 511) fi fi fi • • • fi
fi fi ISP LSCXT ABLESIZE = fix((linewidth − 1)/2/32) + 2 f ix() ISP LSCXT ABLESIZE = fix((1920 − 1)/2/32) + 2 = 29 + 2 = 31 fi fi fi fi R′G′B′=RR RG RBGR GG GBBR BG BB×RGB fi fi fi ISP GAMMARX(n) = log2(X(n) − X(n − 1)) fi X(0F ) = 2ISP GAMMARX0F+ X(0E) − 1 fi fi
XX00 Xn-1 X0FX0EXn......YY00Yn-1YnY0EY0FREG_GAMMA_Xn = log2(Xn-Xn-1)REG_GAMMA_XF = log2(X0F-X0E+1) fi fi • • fi • fi fi
fi fi 00 01 02 03 0410 11 12 13 1420 21 22 23 2430 31 32 33 3440 41 42 43 44(X_START, Y_START)X_BSIZEY_BSIZE fi
fi fi fi • • • fi fi R/G B/G fi fi fi fi fi fi
fi • fi• fi• fl fi • fi • fi n fi fi n
• • byte_orderISP_BYTE_ENDIAN_ORDERImage Interface 32 to 64ISP to Image Interface 64ISP_Header ISP_PipelineCSI_BridgeImage Interface 64 to system memoryCSI_BRIG_BYTE_ENDIAN_ORDERISP_TailISPImage Interface 32BYTE 3 BYTE 2 BYTE 1 BYTE 0BYTE 7 BYTE 6 BYTE 5 BYTE 4Image Interface 32ISP_BYTE_ENDIAN_ORDER = 1BYTE 0 BYTE 1 BYTE 2 BYTE 3BYTE 4 BYTE 5 BYTE 6 BYTE 7BYTE 0 BYTE 1 BYTE 2 BYTE 3BYTE 4 BYTE 5 BYTE 6 BYTE 7Image Interface 64Image Interface 32 to 64BYTE 7 BYTE 6 BYTE 5 BYTE 4BYTE 3 BYTE 2 BYTE 1 BYTE 0CSI_BRIG_BYTE_ENDIAN_ORDER = 1bit 0bit 31bit 63 bit 0bit 0bit 63bit 0bit 31
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31302928 27 26 2423 1211 0Reset fi fi fi fi fi fi 31 2625 1312 0Reset fi fi
31 2625 1312 0Reset fi fi 31 2625 1312 0Reset fi fi 31 2625 1312 0Reset fi fi
31 1312 0Reset fi 31 252423 1615 87 0Reset fi fi fi fi fi fi fi
31 65 0Reset fi 31 2827 2423 2019 1615 1211 87 43 0Reset fi fi fi fi fi fi fi fi
31 43 0Reset fi 31 171615 1211 0Reset fi fi fi 31 0Reset fi
31 54 0Reset fi fix((linenumber − 1)/2/32) + 2 fix() 31 252423 1615 87 0Reset fi fi fi fi fi fi fi
31 65 0Reset fi 31 43210Reset fi fi fi fi fi
31 2423 1615 87 0Reset fi fi fi fi 31 2423 1615 87 0Reset fi fi fi fi
31 2423 1615 87 0Reset fi fi fi fi 31 2423 1615 87 0Reset fi fi fi fi
31 2423 1615 87 0Reset fi fi fi fi 31 2423 1615 87 0Reset fi fi fi fi
31 2423 1615 87 0Reset fi fi fi fi 31 2423 1615 87 0Reset fi fi fi fi
31 2423 1615 87 0Reset fi fi fi fi 31 2423 1615 87 0Reset fi fi fi fi
31 2423 1615 87 0Reset fi fi fi fi 31 2423 1615 87 0Reset fi fi fi fi
31 2423 2120 1817 1514 1211 98 65 32 0Reset fi fi fi fi fi fi fi fi fi
31 2423 2120 1817 1514 1211 98 65 32 0Reset fi fi fi fi fi fi fi fi fi
31 2423 2120 1817 1514 1211 98 65 32 0Reset fi fi fi fi fi fi fi fi fi
31 2423 2120 1817 1514 1211 98 65 32 0Reset fi fi fi fi fi fi fi fi fi
31 2423 2120 1817 1514 1211 98 65 32 0Reset fi fi fi fi fi fi fi fi fi
31 2423 2120 1817 1514 1211 98 65 32 0Reset fi fi fi fi fi fi fi fi fi 31 210Reset fi fi
3122211615870Reset fi fi fi 31 2221 1110 0Reset fi fi 31 2221 1110 0Reset fi fi
31 1716 0Reset fi 31 2019 0Reset fi 31 2423 1615 87 0Reset fi fi fi fi fi fi fi fi
31 1514 109 54 0Reset fi fi fi fi fi fi 31 1514 109 54 0Reset fi fi fi fi fi fi
31 1514 109 54 0Reset fi fi fi fi fi fi
31 252423 1615 87 0Reset fi fi fi fi fi fi fi 31 87 0Reset
31 2019 87 210Reset fi fi fi fi fi fi fi
31 30 2221 0Reset fi fi fi 31 43210Reset fi fi fi fi fi fi
31 151413 1110987 210Reset fi fi fi fi fi fi fi fi fi fi fi
31 2423 16 15 1211 8 7 54 3 10Reset fi fi fi fi fi fi 31 0Reset fi
31 3029 0Reset fi 31 1615 0Reset fi 31 2827 16 15 1211 0Reset fi fi
31 2827 16 15 1211 0Reset fi fi 31 2827 16 15 1211 0Reset fi fi 31 2827 16 15 1211 0Reset fi fi
31 2827 16 15 1211 0Reset fi fi 31 2827 16 15 1211 0Reset fi fi 31 54 3 21 0Reset fi fi
31 2827 16 15 1211 0Reset fi fi 31 2827 16 15 1211 0Reset fi fi 31 2625 16 15 109 0Reset fi fi fi fi
31 2625 16 15 109 0Reset fi fi fi fi 31 2625 16 15 109 0Reset fi fi fi fi
31 2423 1615 87 0Reset fi fi 360 ∗ (ISP COLORHUE/256) fi fi 31 32 0Reset fi
31 2423 1615 87 0Reset fi fi fi 31 2827 16 15 1211 0Reset fi fi 31 2524 16 15 98 0Reset fi fi
31 2423 1615 87 0Reset fi fi fi fi 31 2423 1615 87 0Reset fi fi fi fi 31 2423 1615 87 0Reset fi fi fi fi
31 2423 1615 87 0Reset fi fi fi 31 2423 1615 87 0Reset fi fi fi fi
31 2423 1615 87 0Reset fi fi fi fi 31 2423 1615 87 0Reset fi fi fi fi
31 2423 1615 87 0Reset fi fi fi fi 31 2423 1615 87 0Reset fi fi fi fi
31 2423 1615 87 0Reset fi fi fi fi 31 87 0Reset fi
31 210Reset fi fi 31 0Reset fi fi 31 2423 1615 87 0Reset
31 2423 1615 87 0Reset 31 2423 1615 87 0Reset 31 2423 1615 87 0Reset
31 2423 1615 87 0Reset 31 2423 1615 87 0Reset 31 24 23 0Reset
31 3029 0Reset 31 3029 0Reset 31 3029 0Reset 31 2827 0Reset
31 2827 0Reset 31 2827 0Reset 31 2423 0Reset 31 0Reset
31 0Reset 31 0Reset 31 1716 0Reset 31 1716 0Reset
31 1716 0Reset 31 1716 0Reset 31 1716 0Reset 31 1716 0Reset
31 1716 0Reset 31 1716 0Reset 31 1716 0Reset 31 1716 0Reset
31 1716 0Reset 31 1716 0Reset 31 1716 0Reset 31 1716 0Reset
31 1716 0Reset 31 1716 0Reset
31 29282726252423222120191817 16 15141312111098 7 6543210Reset
31 29282726252423222120191817 16 15141312111098 7 6543210Reset
31 29282726252423222120191816 16 15141312111098 7 6543210Reset
31 29282726252423222120191816 16 15141312111098 7 6543210Reset
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31 1615 0Reset fi 31 1312 0Reset fi 31 1413 8 7 65 0Reset fi fi
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SRM BLEND2D-DMASRM input SRM output BLEND0 input BLEND outputPPAaxi_infBLEND1 input •
• fi fi fi fi fi Addr Gento 2D-DMASRM Coordinate CalculationFIFO0FIFO1Bilinear InterpolationRXColor ModeConvertfrom 2D-DMAARGB8888TXFIFOReorder CTRLTX CTRLAddr Gento 2D-DMAto 2D-DMASRMCLUTCTRLCLUTCLUTCLUTCTRLfrom 2D-DMAfrom 2D-DMAAPBAPBRXColor ModeConvertRXColor ModeConvertBLENDCoreARGB8888ARGB8888TXFIFO TX CTRLto 2D-DMABLEND fi
fi
fi fi RGBswapYUV2RGBAlpha processARGB8888RGB888RAW Alpha Alphabyteswap fifi • • fi fi fi fi 255-RAWPPA_SRM_RX_FIX_ALPHAPPA_SRM_RX_ALPHA_INVRAW Alpha10X01100011PPA_SRM_RX_ALPHA_MOD fi fi fi
fi fi fi fi fi fi • Y U Vfull Y UVlimit Ylimit=220256Yfull+ 16 Ulimit=225256Ufull+ 16 Vlimit=225256Vfull+ 16• Y U Vlimit R =298256Ylimit+409256Vlimit−56906256 G =298256Ylimit−100256Ulimit−208256Vlimit+34707256 B =298256Ylimit+516256Ulimit−70836256• Y U Vlimit R =298256Ylimit+459256Vlimit−63367256 G =298256Ylimit−55256Ulimit−136256Vlimit+19681256 B =298256Ylimit+541256Ulimit−73918256 fi fi fi fi • Y U Vlimit Y UVfull Yfull=298256Ylimit+4768256 Ufull=291256Ulimit+4550256 Vfull=291256Vlimit+4550256• Y U Vlimit
Ylimit=4096256+66256R +129256G +25256B Ulimit=32768256−38256R −74256G +112256B Vlimit=32768256+112256R −94256G −18256B• Y U Vlimit Ylimit=4096256+47256R +157256G +16256B Ulimit=32768256−26256R −86256G +112256B Vlimit=32768256+112256R −102256G −10256B fi fi fi fi fi fi fi • •
fi fi owner eof 2DEN err_eof hb vbHA VApbyte31 30 29 28 27 14 13 0X YmodReservedBuffer address pointerNext descriptor address fi fi
fi fi fi fi fi fi fi Xmiddle Ymiddle fi Xtarget Ytarget fi • •
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31 2423 1615 87 0Reset fi fi fi 31 0Reset fi fi
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31 302928272625 2423 2019 1211 87 0Reset fi fi fi fi fi fi fi fi
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fl • • • • •
• • • • • • Async RX FIFO(8 * 16-bit)Async TX FIFO(8 * 16-bit)GDMALCD_Clock GeneratorPLL_F160M_CLKCAM_CLKI/OsyncLCD_Data_out[23:0]CAM_Data_in[15:0]RXTXTX_FIFORX_FIFOCamera_Ctrl(8/16-bit mode)Camera RXCAM_VSYNCCAM_DECAM_HSYNCCAM_PCLKLCD_VSYNCLCD_HSYNCLCD_PCLKLCD_DELCD_Ctrl(8/16/24-bit mode)LCD_PCLKCAM_CLKLCD_CDCAM_Clock GeneratorXTAL_CLKLCD TXAPLL_CLKXTAL_CLKAPLL_CLKPLL_F160M_CLKRGB/YUVConverterRGB/YUVConverterLCD_CS fl fi • • •
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312423222019 18170Reset 31 0Reset
31 0Reset 31 0Reset 31 0Reset
31 0Reset 31 109 0Reset 31 87 0Reset
31 0Reset 31 2928 0Reset
31 2019 181716 15 1312 8765 210Reset
31 242322 2019 1817 0Reset 31 0Reset
31 0Reset 31 0Reset 31 0Reset
31 0Reset 31 109 0Reset 31 87 0Reset
31 0Reset 31 2928 0Reset
31 2019 181716 15 1312 8765 210Reset
31 242322 2019 1817 0Reset 31 0Reset
31 0Reset 31 0Reset 31 0Reset
31 0Reset 31 109 0Reset 31 87 0Reset
31 0Reset 31 2928 0Reset
31 2019 181716 15 1312 8765 210Reset
31 242322 2019 1817 0Reset 31 0Reset
31 0Reset 31 0Reset 31 0Reset
31 0Reset 31 109 0Reset 31 87 0Reset
31 0Reset 3129280Reset
31 76 210Reset 31 432 0Reset
31 109 0Reset 31 87 0Reset 31 0Reset
31 2928 0Reset 31 2625 2221 1918 1514 1211 87 43 0Reset
31 2625 2221 1918 1514 1211 87 43 0Reset 31 2322 0Reset
31 2120 0Reset 31 1110 0Reset 31 1716 0Reset
31 0Reset
fi fi fi fi fi fi fi fi fi
fi fi • fi • fi• • • • • • fi fi
• • fi fi • • fi MIPIImageSensorMIPIRXD-PHYPipelinePHYAdaptationLayerPacketAnalyzerDescramblerDescrambler...Register BankTest Code InterfaceISPAPBError ManagementMIPI CSI-2 HOSTCP/CND0P/D0ND1P/D1NMIPI CSIImageInterfacePPI Interface
fi • • → → → → → → → → → →
HS diff swing (e.g. 200mV)HS common level(e.g. 200mV)Minimum LP-RX Low thresholdMax LP-RX HighLow-Power signaling level (e.g. 1.2V)
No PowerNo-PowerShut-DownAFE InitializationControl ModeHigh-Speed ModeEscape ModeUltra Low-Power StateINITIALIZATIONACTIVE STATE fi fi fi fi fi fi
fi fi fi
fi fi
LP-11 LP-01 LP-00Enable HS ReceiversHS-0Sync Sequence00011101Start of ReceptionPayload Data LP-00 LP-11HS-TrailerEnd of ReceptionDisable HSReceivers
STOP STATELP-11LP Receiver enabledEscape mode sequence LP-10, LP-00, LP-01, LP-00ULPS commandULPS LP-00 LP receiver enabledLP-10 LP receiver enabledSTOP STATELP-11Escape mode sequence LP-10, LP-00ULPS LP-00LP Receiver enabled fi fi fi fi • • fifi fi •
• fi fi fi CSI_HOST_PHY_TESTCLRCSI_HOST_PHY_TESTENCSI_HOST_PHY_TESTCLKCSI_HOST_PHY_TESTDIN[7:0]CSI_HOST_PHY_TESTDOUT[7:0]Test Code A Test Data A1Monitor DataDefault Test Code 0x00Monitor DataDefault Test Code AMonitor DataBased on Test Data A1Test Code B Test Data B1 Test Data B2Monitor DataDefault Test Code BMonitor DataBased on Test Code B10x00Monitor DataBased on Test Code B2TEST INF CLEAR TEST INF INACTIVESETTINGTEST CODESETTINGTEST DATASETTINGTEST CODESETTING TEST DATAPLACING TESTINF INACTIVE fi
fi fi • • • • • fl
G(x) = x16+ x5+ x4+ x3+ 1 fi
fi fi
AND31 30 ... 1 0group 0 interruptsource 0ANDgroup 0 interruptsource 1ANDgroup 0 interruptsource 30ANDgroup 0 interruptsource 31...AND31 30 ... 1 0CSI_HOST_INT_FORCE_CSI_HOST_INT_ST_ANDANDANDANDAND...31 30 ... 1 0CSI_HOST_INT_MSK_AND31 30 ... 1 0group 31 interruptsource 0ANDgroup 31 interruptsource 1ANDgroup 31 interruptsource 30ANDgroup 31 interruptsource 31...AND31 30 ... 1 0CSI_HOST_INT_FORCE_CSI_HOST_INT_ST_ANDANDANDANDAND...31 30 ... 1 0CSI_HOST_INT_MSK_Clear on read accessClear on read access31 30 ... 1 0CSI_HOST_INT_ST_MAINCSI_INTRAND...
• • • • • • • • • fi fi •
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fi 31 0Reset 31 32 0Reset fi
31 10Reset fi fi 31 10Reset fi
31 10Reset fi 31 181716 15 210Reset
31 210Reset fi fi 31 171615 87 0Reset fi fi
31 10Reset fi 31 1615 0Reset fi
31 1716 15 876543210Reset
31 210Reset 31 210Reset fi
31 210Reset fi 31 210Reset
31 210Reset fi fi
31 210Reset fi fi
31 181716 15 210Reset
31 181716 15 210Reset fi fi
31 181716 15 210Reset fi fi 31 161514131211109876543210Reset
31 161514131211109876543210Reset fi 31 161514131211109876543210Reset fi
31 161514131211109876543210Reset 31 161514131211109876543210Reset fi
31 161514131211109876543210Reset fi 31 161514131211109876543210Reset
31 161514131211109876543210Reset fi 31 161514131211109876543210Reset fi
31 161514131211109876543210Reset 31 161514131211109876543210Reset fi
31 161514131211109876543210Reset fi 31 161514131211109876543210Reset
31 161514131211109876543210Reset fi 31 161514131211109876543210Reset fi
31 161514131211109876543210Reset 31 161514131211109876543210Reset fi
31 161514131211109876543210Reset fi 31 1716 15 210Reset
fi • • • • fi • fi • • •
CPUData and Address BusVADESP32-P4 VAD Figure 1-1EnergyLP I2SMemoryLP I2SFFTLTSDVAD status signals fl fi fi fi fi fi fi fi fi
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fi 31 3210Reset fi fi fi 31 210Reset
31 2524 1615 0Reset fi fi 3130 2423 1615 1110 43 0Reset fi fi fi fi fi
31 1615 87 0Reset
fl fi fi
fl Tx_FIFO Tx_FIFO_CtrlGDMATx_FSMHardware Flow ControlSoftware Flow ControlStart_DetectBaudrate_Detect 1 0 Wakeup_CtrlUART_TXD_INV ... DividerUART0Rx_FIFOUART0 Tx_FIFOfifo_rdata fifo_rd Rx_FIFO Rx_FIFO_Ctrl Rx_FSMfifo_wdata fifo_wr APB_CLK Clock sourceUART_RXD_INV wake_upUART_LOOPBACKtxd_out rtsn_out ctsn_inCLOCK...apb_rdataTransmitterReceiverClock sourceRAMapb_wdataXTAL_CLKRC_FAST_CLKPLL_F80M_CLKCTSRTSConfigurationregisters AHB_CLK Clock sourceAPB_CLK DomainAHB_CLK DomainUART_FCLK DomainUART_SCLK Domain rxd_in fi fi
fi fi fi fi fl fl fl fi fi • • •
fi fi fi fi fi UART CLKDIV +UART CLKDIV F RAG16 fi IN P U T F REQUART CLKDIV +UART CLKDIV F RAG16 694 +716= 694. 4375
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UART_LOOPBACK 1 0 Comparatorrts_int UART_RX_FLOW_EN1 0 UART_SW_RTS cts_intUART_RTS_INVrtsn_outUART_CTS_INVctsn_inUART_LOOPBACK 1 0 DE Control Logic UART_RS485_EN1 0 UART_SW_DTR UART_DTR_INVdtrn_outUART_DSR_INVdsrn_in UART_RXFIFO_CNTUART_RX_FLOW_THRHD fl fl fi • fi •
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fi 31 87 0Reset 31 1211 210Reset fi fi fl fi
31 20191817161514131211109876543210Reset
31 20191817161514131211109876543210Reset
31 20191817161514131211109876543210Reset
31 20191817161514131211109876543210Reset
31 2423 20 19 1211 0Reset fi fi 31 987 0Reset fi fi fi fi
31 24232221201918171615141312111098765 43 210Reset fi fi fi fi fi fi fi fi
fi fi fi fi fi fl fi fi fi fi fl
fi fi fi fi fl fi fi
31 2221201918171615 87 0Reset fi fi fi fi fi fi fi fl fi
31 987 0Reset fi fl fi 31 2423 1615 87 0Reset fi fi fi fi 31 87 0Reset fi
31 2827 2625 2120 1817 109 0Reset fi fi fi fi fi
31 232221201918171615 87 0Reset fi fl fi fl fi fi fl fi fl fi fi fi fi
31 1615 87 0Reset fi fl fi fl 31 87 0Reset fi fi 31 2019 109 0Reset fi fi
31 109 6543210Reset fi fi fi fi fi fi fi
31 282726252423 0Reset fi fi 313029 28 2423 16151413 12 87 0Reset
31 1716 987 0Reset 31 1716 987 0Reset 31 87 43 0Reset
31 43210Reset 31 1615 0Reset fi fi
31 1615 0Reset fi 31 1615 0Reset fi 31 1615 87 0Reset fi fi
31 1211 0Reset 31 1211 0Reset 31 1211 0Reset
31 1211 0Reset 31 109 0Reset 31 0Reset
31 10Reset fi 31 0Reset fi
fi 31 87 0Reset 31 1211 210Reset fi fi fl fi
31 201918 17 1514131211109876543210Reset
31 201918 17 1514131211109876543210Reset
31201918 171514131211109876543210Reset
31 201918 17 1514131211109876543210Reset
31 2423 20 19 1211 0Reset fi fi 31 987 0Reset fi fi fi fi
31 2423222120191817161514131211 765 43 210Reset fi fi fi fi fi fi fi
fi fl fi fi fi fl fi fi fi fl fi fi
31 2221201918171615 11 10 87 3 2 0Reset fi fi fi fi fi fi fi fl fi
31 987 3 2 0Reset fi fl fi 31 2423 1615 87 0Reset fi fi fi fi 31 87 0Reset fi
31 2827 2625 2120 1817 13 12 109 0Reset fi fi fi fi fi
31 232221201918171615 87 0Reset fi fl fi fl fi fi fl fi fl fi fi fi fi
31 1615 11 10 87 3 2 0Reset fi fl fi fl 31 87 0Reset fi fi
31 2019 109 0Reset fi fi 31 282726252423 0Reset fi fi
313029 28 2423 19 18 16151413 12 87 3 2 0Reset 31171612 11873 20Reset
31 1716 12 11 87 3 2 0Reset 31 87 43 0Reset
31 43210Reset 31 1615 0Reset fi fi
31 1615 0Reset fi 31 1615 0Reset fi 31 1615 87 0Reset fi fi
31 0Reset 31 10Reset fi 31 0Reset fi
fi 31 13121110987654 210Reset fi fi fi
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31 9876543210Reset fi fi fi fi fi fi
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31 876543210Reset fi fi fi fl fi fl fi fi
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31 242322 2019 121110 87 0Reset fi fi fi fi fi fi
31 432 0Reset fi fl fi
31 876 432 0Reset fi fi fi fi
31 0Reset 31 0Reset 31 0Reset
31 0Reset 31 0Reset 310Reset
31 0Reset 31 0Reset 31 0Reset
31 0Reset 31 0Reset 31 0Reset
31 0Reset 31 0Reset 31 2423 1615 87 0Reset fi fi fi fi
31 2423 1615 87 0Reset fi fi fi fi fi 31 2423 1615 87 0Reset fi fl fi fi fi
31 2423 1615 87 0Reset fi fl fi fi fi 31 1312 0Reset fi
31 9876543210Reset
31 9876543210Reset
31 9876543210Reset
31 9876543210Reset
31 65 32 0Reset 31320Reset 31 0Reset
31 0Reset
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fi fi fi (SP ICSSET U P T IM E + 1) × TSP ICLK>= 4 × (TAHBCLK+ T clkspimst)fi fi fi fi fi fi
fi fi • • fi fi fi fi fi
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31 252423 22 1817 0Reset fi fi fi fi fi 31 0Reset fi fi
3130292827262524 23 18171615141312 11 109876543 2 10Reset fi fi fi fi fi fi fi fi fi fi fi fi fi
fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi
fi fi fi fi fi fi fi fi fi fi fi fi fi fi
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31 2726 2221 1716 15 87 0Reset fi fi fi fi fi fi fi fi fi fi fi
31 2827 26 1615 0Reset fi fi fi fi fi
31 2726 2524 23222120191817161514 13 11109876543 2 0Reset fi fi fi fi fi fi fi fi fi fi fi fi
fi fi fi fi fi fi fi fi fi fi fi fi fi fi
fi fi fi fi fi fi fi fi fi fi fi fi fi fi 31 1817 0Reset fi fi fi
313029 28 252423 22 2019181716 15 1312 76543210Reset fi fi fi fi fi fi fi fi fi fi fi fi
fi fi fi ∼ fi fi fi fi fi fi fi fi fi fi
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3130292827 26 2221201918 17 210Reset fi fi fi
fi fi fi fi fi fi fi fi fi
31 30292827262522 21 201912111098 743210Reset fi fi fi fi fi fi fi
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31 2625 1817 0Reset fi fi fi
31 30 2221 1817 1211 65 0Reset fi fi fi fi fi fl fl fl fi fi f fi fi fi fi fi
31 3210Reset fi
31 171615 1413 1211 109 87 65 43 21 0Reset fi fi fi fi fi fi
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31 1615 1413 1211 109 87 65 43 21 0Reset fi fi fi fi fi fi fi fi
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31 9876543210Reset fi fi fi fi fi fi fi fi fi fi fi fi fi fi
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31 2120191817161514131211109876543210Reset
31 2120191817161514131211109876543210Reset
31 2120191817161514131211109876543210Reset
31 2120191817161514131211109876543210Reset
31 2120191817161514131211109876543210Reset
31 0Reset
31 0Reset 31 0Reset 31 0Reset 31 0Reset
31 0Reset 31 0Reset 31 0Reset 31 0Reset
31 0Reset 31 0Reset 31 0Reset 31 0Reset
31 0Reset 31 0Reset 31 0Reset 31 2827 0Reset
fi 31252423 220Reset fi fi fi 31 0Reset fi
3130292827262524 23 1817 16 141312 11 109876543 2 10Reset fi fi fi fi fi fi fi fi
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31 2726 2221 1716 15 87 0Reset fi fi fi fi fi fi fi
31 2827 26 1615 0Reset fi fi fi
31 2726 2524 232221201918 17 161514 13 109876543 2 0Reset fi fi fi fi fi fi fi
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31 1817 0Reset fi fi
313029 28 2423 22 109 76 5 3210Reset fi fi fi fi fi ∼ fi fi fi
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3130292827 26 2221201918 17 210Reset fi fi fi
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31 3029282726 25201912111098 743210Reset fi fi fi fi fi fi
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31 2625 1817 0Reset fi fi fi
31 30 2221 1817 1211 65 0Reset fi fi fi fi fi fl fl fl fi f fi fi 31 3210Reset fi
31 1716 15 87 65 43 21 0Reset fi fi fi fi
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31 87 65 43 21 0Reset fi fi fi fi
31 43210Reset fi fi fi fi
31 2120191817161514131211109876543210Reset
31 2120191817161514131211109876543210Reset
31 2120191817161514131211109876543210Reset
31 2120191817161514131211109876543210Reset
31 2120191817161514131211109876543210Reset
31 0Reset 31 0Reset
31 0Reset 31 0Reset 31 0Reset 31 0Reset
31 0Reset 31 0Reset 31 0Reset 31 0Reset
31 0Reset 31 0Reset 31 0Reset 31 0Reset
31 0Reset 31 0Reset 31 2827 0Reset fi
31 252423 22 0Reset fi fi fi 31 0Reset fi
3130292827262524 23 1817 16 1098765 4 10Reset fi fi fi fi fi fi fi
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31 2726 2221 1716 15 87 0Reset fi fi fi fi fi fi fi
31 2827 26 1615 0Reset fi fi fi
31 272625 24 201918 17 43 2 0Reset fi fi fi fi fi fi fi fi fi
31 1817 0Reset fi
313029 28 2423 22 109 76 5 10Reset fi fi fi fi fi fi
313029 28 0Reset fi fi fi fi fi fi
31 201918171615 1110 87 0Reset fi fi fi ∼ ∼ fi fi fi fi fi
31 2423 1615 87 0Reset fi fi fi fi
31 282726 25 121110 9 4321 0Reset fi fi fi fi fi fi fi
31 2625 1817 0Reset fi fi fi
31 30 2221 1817 1211 65 0Reset fi fi fi fi fl fl fl fi f fi fi 31 3210Reset fi
31 1716 15 87 65 43 21 0Reset fi fi fi
31 87 65 43 21 0Reset fi fi 31 43210Reset fi fi
31 212019181716151413121110 9 0Reset
31 212019181716151413121110 9 0Reset
31 212019181716151413121110 9 0Reset
31 212019181716151413121110 9 0Reset
31 21201918171615 14 13121110 9 0Reset
31 0Reset 31 0Reset 31 0Reset 31 0Reset
31 0Reset 31 0Reset 31 0Reset 31 0Reset
31 0Reset 31 0Reset 31 0Reset 31 0Reset
31 0Reset 31 0Reset 31 0Reset 31 0Reset
31 2827 0Reset
fi R/W R/W fi R/W • • • • • • • fi•
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fi fi fi fi fi fi tLOW= ( I2CSCLLOW P ERIOD + 1) · TI2CSCLK tHIGH= ( I2CSCLHIGHP ERIOD + 1) · TI2CSCLK tSU :ST A= ( I2CSCLRST ART SET U P T IME + 1) · TI2CSCLK tHD:ST A= ( I2CSCLST ART HOLDT IM E + 1) · TI2CSCLK tr= ( I2CSCLW AIT HIGHP ERIOD + 1) · TI2CSCLK tSU :ST O= ( I2CSCLST OP SET UP T IM E + 1) · TI2CSCLK tBUF= ( I2CSCLST OP HOLDT IME + 1) · TI2CSCLK tHD:DAT= ( I2CSDAHOLDT IME + 1) · TI2CSCLK tSU :DAT= ( I2CSCLLOW P ERIOD − I2CSDAHOLDT IME) · TI2CSCLK •
fi fi fi fi fscl=f fi • fi fi fifI2CSCLKfSC L> 20 3 × fI2CSCLK≤ ( I2CSDAHOLDT IME − 4) × fAP BCLK
fi fi I2CSCLST T OI2C 22 I2CSCLMAIN ST T OI2C 22 I2CT IMEO U T V ALUE fi fi • • fi
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fi 31 98 0Reset fi 31 98 0Reset fi
31 98 0Reset fi 31 1615 98 0Reset fi fi
31 98 0Reset fi 31 98 0Reset fi 31 98 0Reset fi
31 98 0Reset fi 31 54 0Reset fi 31 54 0Reset fi
31 1514131211109876543210Reset fi fi fi fi fi fi fi fi fi fi fi fi
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31 1514131211109 54 0Reset fi fi fi fi fi fi fi fl fl
31 10987 43 0Reset fi fi fi fi fi fi fi fi
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31 14131211109 0Reset fi fi fi fi fi
3130 282726 2423 18 17 1615 1413 8 7 6543210Reset fi
31 3029 22 21 2019 1514 109 54 0Reset
31 87 0Reset 31 191817161514131211109876543210Reset
31 191817161514131211109876543210Reset
31 191817161514131211109876543210Reset
31 191817161514131211109876543210Reset
31 3014130Reset fi 31 30 1413 0Reset fi
31 30 1413 0Reset fi 31 30 1413 0Reset fi
31 30 1413 0Reset fi 31 30 1413 0Reset fi
31 30 1413 0Reset fi 31 30 1413 0Reset fi 31 0Reset
31 0Reset fi 31 0Reset fi 31 98 0Reset fi
31 98 0Reset fi 31 98 0Reset fi
31 1615 98 0Reset fi fi 31 98 0Reset fi
31 98 0Reset fi 31 98 0Reset fi
31 98 0Reset fi 31 54 0Reset fi 31 54 0Reset fi
31 12111098765432 1 0Reset fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi
31 654 0Reset fi fi
31 15141312111098 543 0Reset fi fi fi fi fi fi fi fi fi fi fl fl
31 10987 43 0Reset fi fi fi fi fi fi fi fi 31 8765 10Reset fi fi
3130 282726 242322 18 17 1312 8 7 543 2 10Reset
31 1918 151413 1098 543 0Reset 31 87 0Reset
31 161514131211109876543210Reset
31 161514131211109876543210Reset
31 161514131211109876543210Reset
31 161514131211109876543210Reset
31 30 1413 0Reset fi
31 30 1413 0Reset fi 31 30 1413 0Reset fi
31 30 1413 0Reset fi 31 30 1413 0Reset fi
31 30 1413 0Reset fi 31 30 1413 0Reset fi
31 30 1413 0Reset fi 31 0Reset 31 0Reset fi fi
31 0Reset fi fi
fi fi fi fi fi • fi • fi • fi • fi • fi • fi • • • • •
fi I2C0_MSTI2C1_MSTAnalog ModuleI2C signalMUXI2C0 signalI2C1 signal8 group of I2C busConfigurationRegistersANA_I2C • fi fi • fi • fi fi fi
SDASDA_SIDE_GUARDSCL_PULSE_DURSDA_SIDE_GUARDdata_phase1SDA_SIDE_GUARDSCL_PULSE_DURSDA_SIDE_GUARDdata_phase2SCL fi fi fi fi • • fi • fi • fi •
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31 262524 0Reset fi fi 31 2423 0Reset fi fi
311110650Reset fi fi 31 1110 65 0Reset fi fi
31 292827 0Reset
fl fi fi µ µ fi
fi fi fi • • • • •
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CPUGDMAData and Address BusA-law/μ-lawDecompressClock GeneratorXTAL_CLKBCKI2Sn_TX/RX_CLKI/OSyncI2SnA-law/μ-lawCompressAPLL_CLKI2Sn_MCLK_inRX UnitTDM RXRX FIFOTX FIFOPDM RXI2SnO_SD_outI2SnI_SD_in I2SnO_BCK_in/ I2SnO_BCK_out I2SnO_WS_in/ I2SnO_WS_outI2Sn_MCLK_out I2SnI_WS_in/ I2SnI_WS_out I2SnI_BCK_in/ I2SnI_BCK_outRXTXPDM-to-PCMConverter*TX UnitTDM TXPDM TXPCM-to-PDMConverter* • • •
fi • • •
fi fi fi fi fi fi fi fi
fi fi fi
Left RightLeft RightWS(LRCK)SD(SDOUT)Left RightLeft RightRightLeftLeft RightRightLeftLeft RightRightLeftLeft Right • • • XTAL_CLKI2SnO_BCK_outI2Sn_TX_CLKHP_SYS_CLKRST_I2Sn_TX_CLK_SRC_SEL01N +ba1MO1APLL_CLK2I2Sn_MCLK_inI2SnI_BCK_outI2Sn_RX_CLK1N +ba1MI01HP_SYS_CLKRST_I2Sn_MST_CLK_SELI2Sn_MCLK_outHP_SYS_CLKRST_I2Sn_RX_CLK_SRC_SELXTAL_CLK01APLL_CLK2I2Sn_MCLK_in f
ff=f + • • • • <=2 = 0 = floor([]) − 1 = = • >2 = 1 = floor([ ]) − 1 = = fi fi f=f = + 1 fi f=f = + 1
• fi • f f • • fi fi fi • • • fi •
fi • fi fi • fi fi fi fi
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µ µ fi fi • • fi • • • µ• µ fi • fi fi fi fi • • •
• •
• • fi fi • • • • fi Data_0 Data_0 Data_2 Data_2 Data_2 Data_5I2S_TX_TDM_CHAN_NUM = 5; I2S_TX_CHAN_EQUAL = 1; I2S_TX_TDM_CHAN0_EN = 1; I2S_TX_TDM_CHAN1_EN = 0; I2S_TX_TDM_CHAN2_EN = 1; I2S_TX_TDM_CHAN3_EN = 0; I2S_TX_TDM_CHAN4_EN = 0; I2S_TX_TDM_CHAN5_EN = 1;Channel0Channel1Channel2Channel3Channel4Channel5 fi fi fi
fi fi • fi 1 2 fi• fi
f f=f = × f f= × fi fi fi • • • • fi
Left LeftLeftData (Left) = Data (Right)Left RightWS(LRCK)SD(SDOUT)LeftI2S_TX_CHAN_MOD = 2; I2S_TX_WS_IDLE_POL = 1; fl • fl• fl• •
fi fi fi • • • • fi
fi fi • fi f f=f = × fi • fi fi • • • •
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µ µ fi fi • • fi • • • µ• µ • • • • • • • •
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fi fi fi fi fi fi fi fi fi fi fi fi fi fi
fi 31 43210Reset 31 43210Reset
31 43210Reset 31 43210Reset
31 2726 21201918171615141211 1098765 43210Reset fi fi fi fi fi fi fi fi
fi fi fi fi µ µ fi fi fi
fi fi fi fi fi fi fi fi
31 2726 1918 14 13 98 0Reset fi fi fi fi
31 2928 262524 212019 18 0Reset fi fi fi fi fi fi
31 2019 161514131211109876543210Reset fi fi fi 31 1211 0Reset fi fi
313029 2726 2120191817161514131211 109876543210Reset fi fi fi fi fi fi fi
fi fi fi fi fi µ µ fi fi fi fi
fi fi fi fi fi fi fi fi fi fi
31 2726 1918 14 13 98 0Reset fi fi fi fi
31 26252423222120 1918 1716 1514 1312 54 10Reset fi fi fi fi 31 26 31 2625 2322 209 0Reset fi
31 212019 161514131211109876543210Reset fi fi fi
31 3029 28 27 2625 24 23 2221 20 19 1817 16 15 1413 12 11 109 8 7 65 4 3 21 0Reset fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi
31 3029 28 27 2625 24 23 2221 20 19 1817 16 15 65 4 3 21 0Reset fi fi fi fi fi fi fi fi fi fi fi
31 121110 87 0Reset fi fi I2SLCF IF OT IMEOU T SHIF T fi 31 0Reset fi
31 10Reset 31 2019 109 0Reset fi fi
3130 0Reset fi fi 3130 0Reset fi fi 31 10Reset fi
31 2827 0Reset
fi • • • • fi •
• • • • • • • CPUData and Address BusClock GeneratorLP_FAST_CLKBCKLP_I2S_RX_CLKI/OSyncLP I2SXTAL_D2_CLKPLL_LP_CLKRX UnitTDM RXRX FIFOPDM RXLP_I2SI_SD_inLP_I2S_MCLK_out LP_I2SI_WS_in/ LP_I2SI_WS_out LP_I2SI_BCK_in/ LP_I2SI_BCK_outRXPDM-to-PCMConverterLP I2SMemoryVAD fi • fi •
• fi • • • fi
fi fi fi fi fi
fi fi fi Left RightLeft RightWS(LRCK)SD(SDOUT)Left RightLeft RightRightLeftLeft RightRightLeftLeft RightRightLeftLeft Right
• fi • • LP_I2SI_BCK_outLP_I2S_RX_CLK1N +ba1MILP_I2S_MCLK_outLPPERI_LP_I2S_RX_CLK_SELLP_FAST_CLK01XTAL_D2_CLK2PLL_LP_CLK f ff=f + • • • • <=2 = 0 = floor([]) − 1 = = • >2 = 1 = floor([ ]) − 1 = = fi fi
f=f = + 1 fi f f fi fi • • fi fi • fi fi
• fi fi fi fi • • • •
fi fi fi • fi f f=f = × fi • fi fi • •
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fi fi fi fi fi fi fi fi
fi 31 1716 98 0Reset fi fi
31 2120191817161514 13 12 109876543210Reset fi fi fi
fi fi fi fi fi fi fi fi fi fi
fi fi fi fi
31 302928 2423 1817 1312 76 0Reset fi fi fi fi fi fi fi fi fi fi fi
31 2019 16 15 210Reset fi fi fi 31 1211 0Reset fi
31 2928 262524 212019 18 0Reset fi fi fi fi fi fi fi fi
31 6543210Reset
31 6543210Reset
31 6543210Reset
31 6543210Reset
31 3029 28 27 2625 24 23 2221 20 19 1817 16 15 21 0Reset fi fi fi fi fi fi fi fi fi
31 121110 87 0Reset fi fi LP I2SLCF IF OT IM EOU T SHIF T fi 31 0Reset fi
31 43210Reset fi fi fi fi 31 2827 0Reset
fi fi • • • • fi
• fi • fAP BCLK2
• fi • fi • fi
fi fi fi fi • • • • fi fi fi fi fi •
fi fi fi fi • fi • fi •
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31 1615 0Reset fi fi 31 1615 0Reset fi fi
31 1716 15 876543210Reset fi 31 1615 0Reset
31 7654321 0Reset
31 43210Reset 31 43210Reset 31 43210Reset
31 43210Reset 31 0Reset
fi fi • fi • fi fi fl
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MAC PushMAC PopMAC PopMAC PopRX DataRX starting address fixed to 0USB_RXFEEPRX FIFO ControlAHB PopTX FIFO #0 DataUSB_NPTXFSTADDRUSB_NPTXFDEPTX FIFO #0 ControlAHB PushTX FIFO #1 DataTX FIFO #1 ControlAHB PushUSB_INEP2TXFSTADDR...TX FIFO #n DataUSB_INEPnTXFDEPTX FIFO #n ControlAHB Push...USB_INEPnTXFSTADDRUSB_INEP1TXFDEPUSB_INEP1TXFSTADDR • • fi fi
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fi • •
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USBController CoreCPU InterfaceDMA InterfaceCPUMemoryUSB 2.0 Full-Speed InterfaceData FIFORAM InterfaceSPRAMUSB 2.0 Full-SpeedSerial TransceiverUSB External ModuleAPB Interface • • • • fi •
• fi • fi fi
• fi • fi • • • • fi
• • • fi • • fi
MAC PushMAC PopMAC PopMAC PopRX DataRX starting address fixed to 0USB_RXFEEPRX FIFO ControlAHB PopTX FIFO #0 DataUSB_NPTXFSTADDRUSB_NPTXFDEPTX FIFO #0 ControlAHB PushTX FIFO #1 DataTX FIFO #1 ControlAHB PushUSB_INEP2TXFSTADDR...TX FIFO #n DataUSB_INEPnTXFDEPTX FIFO #n ControlAHB Push...USB_INEPnTXFSTADDRUSB_INEP1TXFDEPUSB_INEP1TXFSTADDR • • fi fi
USB_HCINTn_REG (0-7)USB_HCINTMSKn_REG (0-7)USB_HAINT_REGUSB_HAINTMSK_REG[7:0]USB_HPRT_REGUSB_DIEPINTn & USB_DOEPINTn (0-6)USB_DIEPMSK & USB_DOEPMSK_REG (Common)22:16OUT EPUSB_DAINTMSK_REGUSB_DAINT_REG6:0IN EP313029282726252423222120191817:10 98 7:3210USB_GINTSTS_REGInterrupt SourcesGOTGINTRegisterUSB_GINTMSK_REGANDORUSB_GLBLINTRMSKInterrupt Signal • • • • •
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• • • fl fi • • repetitioncount = (R1 × 2 + R0) × (4cmdrepcount) fi (0 × 2 + 1) × (40) = 1
(1 × 2 + 0) × (40) = 2 (0 × 2 + 0) × (41) = 0 (1 × 2 + 1) × (42) = 48 fi fi fl fl •
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fi 31 87 0Reset
31 3210Reset fi
31 161514131211109876 54 3210Reset fi fi fi fi fi fi
fi fi fi fi fi fi fi
31 76543210Reset fi fi fi fi
31 10Reset fi 31 210Reset fi fi
31 3210Reset fi 31 0Reset fi
31 2423 1615 87 0Reset fi fi fi 31 10Reset fi fi
31 6543210Reset fi fi fi fi
31 161514131211109876543210Reset
31 161514131211109876543210Reset
31 161514131211109876543210Reset
31 161514131211109876543210Reset
31 1098765 4321 0Reset fi fi
31 1110 0Reset 31 1615 98 21 0Reset
31 1615 98 21 0Reset 31 1615 98 21 0Reset
31 1615 98 21 0Reset 31 1615 98 21 0Reset −
31 2322 1615 98 21 0Reset − 31 1615 98 21 0Reset −
31 0Reset 31 2423 1615 87 0Reset
31 10Reset 31 0Reset
ESP32-P4 • • • • fi • • • •
fl fl fl • • • • • • fl fi fi fi fi • • • • fi • • • • fi • • • • • fl •
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310Reset fi fi 31 0Reset fi fi 31 0Reset fi fi
31302928 27 2625 2322 2019 1716151413 12 11109876543210Reset fi fl fi
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31 27262524 23 212019 1716 141312 1110 987654 3210Reset fi fi fl fi fl fl fi
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31 1716151413 12 11109876543210Reset fl fl
31 29fl28fl27 17fl1615 0Resetfl fl fl fl fl fl fl fl fl fl fl fl fl fl
31 87 0Reset fi 31 10Reset fi 31 0Reset fi
31 0Reset fi 31 0Reset fi 31 0Reset fi
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31 1615 1110 65 210Reset fi fi fi fi fi fi fi 31 1615 0Reset fi
31 16 15 8765 43210Reset fi fi fi fi fi fi fi fi fi fi fi fi fl
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31 1918171615 0Reset fi fi fi fi fi fi fi fi fi fi
31 262524232221 201918 1716 15 109 876 5432 10Reset fl
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31 0Reset fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi
31 30 29 28 24 23 109 8 765 4 3210Reset fi fi fi fi fi fi fi
31 2019181716 15 10987 43210Reset fi fi fi
31 26 25 16 15 0Reset fi fi fi
31 11109 8 53 2 0Reset 31 11109 8 43 2 0Reset 31 30 1615 0Reset fi fi fi fi
31 0Reset fi fi fi fi 313029 24 23 1615 0Reset fi fi fi fi fi fi fi fi fi fi
31 0Reset fi fi fi 313029 24 23 1615 0Reset fi fi fi fi fi fi fi fi fi fi
31 0Reset fi fi fi 313029 24 23 1615 0Reset fi fi fi fi fi fi fi fi fi fi
31 0Reset fi fi fi 313029 24 23 1615 0Reset fi fi fi fi fi fi fi fi fi fi fi fi
31 0Reset fi fi fi fi 313029 24 23 1615 0Reset fi fi fi fi fi fi fi fi fi fi
31 0Reset fi fi fi 313029 24 23 1615 0Reset fi fi fi fi fi fi fi fi fi fi
31 0Reset fi fi fi 313029 24 23 1615 0Reset fi fi fi fi fi fi fi fi fi fi
31 0Reset fi fi fi 313029 24 23 1615 0Reset fi fi fi fi fi fi fi fi fi fi
31 0Reset fi fi fi 31 1716 15 54 3 10Reset 31 1716 15 1413 0Reset fi fi fi fi
31 201918 17 1615 0Reset fi fi fi fi
31 1918 17 1615141312111098 7 6543210Reset fi fi fi fi fi fi
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31 87 0Reset fi 31 0Reset 3130 0Reset 31 0Reset fi
3130 0Reset fi fi 31 0Reset fi 31 0Reset fi
3130 0Reset fi 31 1615 0Reset fi fi fl
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fi fi • • • fi fi fi fi fi • fi fi fi T q CLK T q CLK • SJW SJW fi SJW fi
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fi fi fi fi fi 12334444 fi fi fi fi fi fi fi fi fi fi fi 12222
fi fi fi fi fi fi 122 fi fi fi fi fi fi fi fi fi fi fi
fi fi fi fi • fi • fi • • fi fi fi fi fi fi fi
message bitacceptance code bitacceptance mask bit1 = accepted0 = not acceptedORXNORAND fi fi fi fi fi fi fi fi fi fi • • fi fi fi fi fi fi fi fi fi fi • fi
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fi 11233333• • •
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31 1615 1413 0Reset fi fi 31 876 43 0Reset fi fi fi
31 87 0Reset fi 31 987 0Reset fi fi
31 210Reset fi fi 31 10Reset fi
31 0Reset fi 31 0Reset fi
31 9876543210Reset
31 54 0Reset
31 87 654 0Reset 31 87 0Reset fl
31 87 0Reset fl 31 76 0Reset
31 9876543210Reset
31 9876543210Reset 31 87 0Reset fi fi fi
31 87 0Reset fi fi fi 31 87 0Reset fi fi fi 31 87 0Reset fi fi fi
31 87 0Reset fi fi fi 31 87 0Reset fi fi fi 31 87 0Reset fi fi fi
31 87 0Reset fi fi fi 31 87 0Reset fi 31 87 0Reset fi
31 87 0Reset fi 31 87 0Reset fi 31 87 0Reset fi
31 0Reset 31 1615 0Reset fi 31 10Reset fi
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fi 31 2423 1615 87 0Reset fi fi fi fi
31 43 0Reset fi 31 1817 16 15 21 0Reset fi fi
31 87 0Reset fi fi 31 1817 16 15 21 0Reset fi fi
31 1615 0Reset fi 31 0Reset fi fi 31 0Reset fi
31302928 27 2423222120 1615141312111098765 0Reset fi fi fi fi fi fi fi fi
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3130 282726 16 15 1211 0Reset fi fi fi fl fi
31 2423 0Reset fi fi 31 0Reset fi fi
31 1817 16 15 21 0Reset fi fi 31 21 0Reset fi
31 1110 87 6 210Reset fi fi fi fi fi
31 0Reset fi fi 31 0Reset fi
31 16 15 210Reset fi fi fi fi 31 21 0Reset fi
31 43 0Reset fi 31 232221 20 0Reset fi fi
31 2120 1514 98 3 2 0Reset fi fi fi
31 1817 1615 0Reset
31 1817 1615 0Reset
31 1817 1615 0Reset
31 1716 1312 1098 7 6543210Reset fi fi fi fi fi
31 1098 7 6543210Reset
31 0Reset 31 0Reset 31 0Reset
31 0Reset 31 3029 1716 1110987 43210Reset fi fi
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31 21 0Reset 31 21 0Reset 31 0Reset
31 0Reset 31 0Reset 31 0Reset
31 0Reset
• • • • • • • fi • •
fi fi fl fi
fi fi fi fi • • • fi fi = A +B256• fi • fi • • •
fi fi fi fi fi fi fl fi fi fi 2− 1 fl fl fi fi fl fi fi fl fi fl fl fi
fl fi fi fi fi fl fi fi fi fi f=f · 2 = 2ff· 1023 +255256 fi
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31 17161514 54321 0Reset fi fi fi fi fi fi fi fl fl fi
fi 31 2019 0Reset fi fi 31 2524 0Reset fi
31 30 0Reset fi fi 31 272625242322 54 0Reset fi fi fi fi fi fi fi
31 7654 0Reset fi fi fi
313029282726252423222120191817161514131211109876543210Reset fi fi fi fi fi
313029282726252423222120191817161514131211109876543210Reset fi fi fi fi fi fi
31 2423222120191817161514131211109876543210Reset fi fi fi 31 2019 0Reset fi
31 30 10987654321 0Reset fi fi 31 2524 0Reset 31 2019 0Reset
31 2019 0Reset 31 20191817161514131211109876543210Reset fi fi
31 20191817161514131211109876543210Reset 31 20191817161514131211109876543210Reset
31 20191817161514131211109876543210Reset 31 2827 0Reset fi
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fl fi fi fi fi fi fi fi fi Duty = (P eriod − A) ÷ P eriod fi
P eriod = (M CP W M T IMERP ERIOD + 1) × TP T clk
P eriod = (M CP W M T IMERP ERIOD + 1) × TP T clk
P eriod = (2 × MCP W M T IM ERP ERIOD) × TP T clk
fi fi P eriod = (2 × MCP W M T IM ERP ERIOD) × TP T clk
fi fi • •
fi fi fi fi fi fi
fi • • • fi • fi fi
fi fi fi fi
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fi F ED = MCP W MDT F ED × TDT cl kRED = MCP W M DT RED × TDT cl k
fi• • fi • • fi fi fi fi fi
fi fi T1stpulse=TP W Mclk× 8 × (M CP W M CARRIERP RESCALE + 1) × (MCP W MCARRIEROSHT W T H + 1)• TP MW clk • (M CP W M CARRIEROSHT W T H + 1) fi • (M CP W M CARRIERP RESCALE + 1) fi fi fi Duty = M CP W M CARRIERDU T Y ÷ 8
fi • • • • • • •
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fi 31 87 0Reset fi 31 2625 2423 87 0Reset fi fi fi
31 54 32 0Reset fi fi
31 212019 43 210Reset fi fi fi fi fi
31 171615 0Reset 31 12111098 65 32 0Reset fi fi
31 65 43 21 0Reset fi
31 10987 43 0Reset fi fi fi fi fi fi fi fi
31 1615 0Reset fi 31 1615 0Reset fi
31 109 76 43 0Reset fi fi fi
31 1615 141312 11109 87 65 0Reset fi fi fi fi
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31 2423 2221 2019 1817 1615 1413 1211 109 87 65 43 21 0Reset fi fi fi fi
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31 2423 2221 2019 1817 1615 1413 1211 109 87 65 43 21 0Reset fi fi fi fi fi
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31 181716151413121110987 43 0Reset fi fi fi fi fi fi fi fi fi fi fi fi fi
fi fi fi fi fi fi fi 31 1615 0Reset fi 31 1615 0Reset fi
31 14131211 87 54 10Reset fi fi fi fi fi fi fi
31 2423 2221 2019 1817 1615 1413 1211 109 876543210Reset fi fi fi fi fi fi fi fi
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31 5432 10Reset fi fi fi fi
31 210Reset 31 9876543210Reset fi fi fi
31 654 210Reset fi fi fi fi
31 0Reset fi 31 13121110 32 10Reset fi fi fi fi fi
31 0Reset 31 3210Reset
31 876543210Reset fi fi fi fi fi
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31 3029282726252423222120191817161514131211109876543210Reset
31 3029282726252423222120191817161514131211109876543210Reset
31 3029282726252423222120191817161514131211109876543210Reset
31 3029282726252423222120191817161514131211109876543210Reset
31 3029282726252423222120191817161514131211109876543210Reset fi fi fi fi fi fi
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31 6543210Reset fi fi
31 222120191817161514131211109876543210Reset fi fi fi fi fi fi
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31 1615 0Reset fi 31 1615 0Reset fi 31 10Reset fi
3128270Reset
fi • • • •
• fi Same as TX Channel nRMT_REF_CNT_RST_CHnRMT_DIV_CNT_CHnmem_rdatanRMT_CARRIER_EN_CHnRMT_CONTI_MODE_CHnRMT_TX_LIM_CHnRMT_TX_WRAP_EN_CHnTX Channel nblock2...block3block7block1block0RAM RMT_MEM_SIZE_CHn/mRMT_MEM_RD_RST_CHnRMT_MEM_WR_RST_CHmTX Channel 0mem_wdatarmt_sclkmem_rdnmem_wr4clk_divCarrier_GeneratorRMT_IDLE_OUT_EN_CHnsig_outRMT_CARRIER_HIGH_CHnRMT_CARRIER_LOW_CHnRMT_CARRIER_OUT_LV_CHnModulator0 1 CK Div Counter CLRFSMtx_enFlip_FlopDENRMT_IDLE_OUT_LV_CHn1 0 ComparatorperiodlevelDetect_Edge 0 1 1 0DemodulatorFilter RMT_CARRIER_EN_CH4RMT_CARRIER_HIGH_THRES_CH4RMT_CARRIER_LOW_THRES_CH4RMT_CARRIER_OUT_LV_CH4Receiverrmt_sclk RMT_RX_FILTER_EN_CH4CK Div Counter CLRFSMrx_enHP_SYS_CLKRST_RMT_CLK_DIV_NUMERATORHP_SYS_CLKRST_RMT_CLK_DIV_DENOMINATORHP_SYS_CLKRST_RMT_CLK_DIV_NUMFrac Divider(8 bits)PLL_F80M_CLK RC_FAST_CLK Clock2 10 XTAL_CLK HP_SYS_CLKRST_RMT_CLK_SRC_SEL HP_SYS_CLKRST_RMT_CLK_ENAPB BUSSame as RX Channel 4RX Channel msig _inclk_divTransmittermem_wrmmem_rdata0mem_rd0RMT_RX_FILTER_THRES_CH4RX Channel 4GDMA TX INFGDMA RX INFModulator • • • •
• • fi 3 × Tapbclk+ 5 × Trmtsclk< period × Tclkdiv(1) period × Tclkdiv • (3×Tapbclk+ 5×Trmtsclk)• × Tclkdiv (215− 1)× Trmtsclk×
fi • • fi fi fl fi fi fl fi • • fi • •
fi fi fi fi fi fi fi fi
fi fi • fi • fi fi fi fi • •
• fi • fi 6 × Tapbclk+ 12 × Trmtsclk< period × Tclkdiv(2) fi fi fi • • fi fi
fi fi fi fi fi fi fi fi fi • • fi fi fi fi fi fi
fi fi • • • • • fi
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fi fi fi fi fi fi fi fi fi fi fi fi fi fi
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fi 31 0Reset 31 0Reset
31 2625242322212019 1615 876543210Reset fi fi fi fi fi fi fi fi fi fi
fi fi fi fi fi fi fi fi fi
31 30292827 242322 87 0Reset fi fi fi fi fi fi fi fi
31 1615141312 543210Reset fi fi fi fi fi fi fi fi fi
31 1615 0Reset fi fi 31 30 272625 2423 1817 1211 43210Reset fi fi
31 876543210Reset fi fi
31 27262524 222120 11109 0Reset fl
31 2827262524 222120 11109 0Reset fi fi fi fl
31 3029282726252423222120191817161514131211109876543210Reset
31 3029282726252423222120191817161514131211109876543210Reset
31 3029282726252423222120191817161514131211109876543210Reset
31 3029282726252423222120191817161514131211109876543210Reset
31 1615 0Reset fi fi
31 2221201918 98 0Reset fi fi fi fi fi
31 543210Reset fi fi 31 98 0Reset fi 31 2827 0Reset
fl fi fi
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RegisterGroupClockGeneratorXTAL_CLKPLL_F160M_CLKRC_FASK_CLKRX FIFOControl//TX FIFOControl//IOBus////RX FIFO_infTX FIFO_infRX FIFOTX FIFORXDPAD_CLK_RXPAD_CLK_TXCLK_TX_outTXDAXIPARLIO//CLK_TXCLK_RX//GDMA_push_inf//GDMA_pop_infGDMAClock DomainsCLK_RX_outRX CoreAPBTX Core fi fi fi
fi fi (28− 1) fi fi fi (28− 1) PLL_F160M_CLKXTAL_CLKRC_FAST_CLK PAD_CLK_RXDIVCLK_RX_inINVCLK_RX_out DIVCLK_TX_inCLK_TX_outINVHP_SYS_CLKRST_PARLIO_TX_CLK_SRC_SELRX_INV_OTX_INV_OClock GeneratorHP_SYS_CLKRST_PARLIO_RX_CLK_SRC_SELGateGateRX_Gate_EnTX_Gate_EnINVCLK_RX CLK_TXINVRX_INV_ITX_INV_I0123PLL_F160M_CLKXTAL_CLKRC_FAST_CLK PAD_CLK_TX0123 fi
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fi fi fi fi SW_ENABLE/Valid data/ Mode DescriptionSub-mode
fi • fi fi fi • fi fi • fi fi fi • fi fi fi fi (216− 1) fi fi
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31 292827 9 8 0Reset fi fi fi
31302928 1312 11 0Reset fi fi fi fi fi 31 30 0Reset fi
31 292827 9 8 0Reset fi fi fi 31 30 0Reset fi
313029 1413 12 0Reset fi fi fi fi fi 3130 29 0Reset fi fi
31 30 0Reset fi fi 31 30 0Reset 31 3210Reset
31 3210Reset 31 3210Reset
31 3210Reset 31 1312 8 7 0Reset 31 13 12 0Reset
31 1312 6 5 0Reset 3130 29 0Reset fi fi
3130 29 0Reset fi fi 31 30 0Reset 31 2827 0Reset
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31 76 32 0Reset fi fi 31 0Reset fi fi
31 1312 1110 0Reset fi fi fi 31 0Reset fi fi
31 1312 1110 0Reset fi fi fi 31 0Reset fi fi
31 1615 0Reset fi 31 1615 0Reset fi
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313029 16 15 543210Reset fi
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31 2827 0Reset
fi fi • • • • fi • • • fi
• fi • • • • fi• • ChipProtective coverSubstrateElectrodeC Touch panel fi
fi fi fi fi
FrequencyMode 0 DBIAS 0DRV_HS 0DRV_LS 0DRES_LPF 0DCAP_LPF 0DCAP_DRV 0BUF_DRVEN_CALFrequencyMode 1DBIAS 1DRV_HS 1DRV_LS 1DRES_LPF 1DCAP_LPF 1DCAP_DRV 1BUF_DRVEN_CALFrequencyMode 2DBIAS 2DRV_HS 2DRV_LS 2DRES_LPF 2DCAP_LPF 2DCAP_DRV 2BUF_DRVEN_CALFREQ_SCAN_CNT_LIMIT012TouchSensor 1 TOUCH_XPD 1TOUCH_START 1EN_BUF 1TOUCH_OUT 1TouchPanel 1TouchSensor 2 TOUCH_XPD 2TOUCH_START 2EN_BUF 2TOUCH_OUT 2TouchPanel 2(……)TouchSensor 14TOUCH_XPD 14TOUCH_START 14EN_BUF 14TOUCH_OUT 14TouchPanel 14 fi fi Ω Ω Ω Ω fi
fi CPUTouch Sensor 1xpd 1start 1out 1xpd 2start 2out 2Xpd 14Start 14out 14(...)touch_xpdtouch_starttouch_outwakeupTimer SoftwareSCAN_CTRL WORK_UNITinterruptDBIAS DRV_HS DRV_LS DRES_LPF DCAP_LPF DCAP_DRV BUF_DRVDCAP_CALEN_CALTouch Sensor 2DBIAS DRV_HS DRV_LS DRES_LPF DCAP_LPF DCAP_DRV BUF_DRVDCAP_CALEN_CALTouchSensor 14DBIAS DRV_HS DRV_LS DRES_LPF DCAP_LPF DCAP_DRV BUF_DRVDCAP_CALEN_CALtouch_work_starttouch_work_doneFilterSCAN_CURtouch_meas_outupdate_cur_datatouch_filter_donetouch_filter_startfreq_cntTouch FSM
• • • fi fi fi fi • fl TOUCH_OUTDIVdiv_num = LP_ANA_DIV_NUM[2:1]10AON_FAST_CLKLP_ANA_DIV_NUM[0]10LP_ANA_TOUCH_OUT_SELTOUCH_OUT_DIVCLK GATELP_ANA_TOUCH_OUT_GATEtouch_clktouch_data fi fi fi fi fi •
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Touch 1Touch 2Touch 3StartTouch 14…Sleep. . .Freq 0 Freq 1 Freq 2 Freq 0 Freq 1 Freq 2 Freq 0 Freq 1 Freq 2 SleepFreq 0 Freq 1 Freq 2 Freq 0 Freq 1 Freq 2 SleepFreq 0 Freq 1 Freq 2 Sleep fi fi • • • • • • fi • fi •
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31 2019 161514 0Reset 31 2322 1918 1615 0Reset touchsmoothdata < benchmark − passivenoisethreshold
31 2322 1918 1615 0Reset touchsmoothdata < benchmark − passivenoisethreshold 31 2423 1615 87 0Reset
31 2524 2322 1817 1312 98 76 0Reset 31 3029 1514 0Reset
31 30 2827 0Reset fi fi fi 31 3029 2019 109 0Reset fi fi fi
31 1716 210Reset fi fi fi fi
31 3029 282726 232221 6 5 0Reset fi fi fi fi fi fi
31 2827262524 2221 1918 16 15 0Reset fi fi fi fi fi fi fi fi fi fi fi fi fi
31 3029 2019 109 0Reset fi fi fi
31 2928 2120 171615 1312 98 76 54 32 100Reset fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi
313029 15 14 0Reset fi fi fi 31 171615 0Reset fi
31 2120 171615 0Reset fi fi 31 1615 0Reset fi fi
31 161514 0Reset 3113121187430Reset fi fi fi fi fi fi fi fi
31 2322 1817 1312 98 76 0Reset fi fi fi fi Ω Ω Ω Ω fi fi fi fi fi fi
31 1110 432 0Reset fi fi fi
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3130 0Reset fi
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Tsens_data MonitorTsens Ctrl & DetectAnalog DigitalHW TimerTsens_data[7:0]sync_moduleTsens_data_apb[7:0]Monitor_triggerover_threshold_apbTsens_pu_apbTsens_puover_threshold • • • • •
fi • fi fi fi V ALUE T V ALU E T = 0.4386 ∗ V ALUE27.88 ∗ of f set20.52 of f set • •
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31 151413 1211 0Reset fi fi fi 31 10Reset
31 10Reset 31 10Reset
31 10Reset 31 10Reset
31 10Reset
313029 28 2221 14 13 87 0Reset fi fi fi 31 1615 0Reset fi fi
LP ADC1ControllerHP DomainLP DomainAnalog Domain...HP ADC1ControllerLP ADC2Controller...inputsinputsSAR ADC1SAR ADC2HP ADC2Controller fi fi • •
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31 2928 26 25 0Reset fi fi fi k fi k fi k k k k k k fi fi fi k fi 31 2423 0Reset fi 31 2423 0Reset fi
31 2423 0Reset fi 31 2423 0Reset fi 31 2423 0Reset fi
31 2423 0Reset fi 31 2423 0Reset fi 31 2423 0Reset fi
31 30 2423 1918 14 13 0Reset fi fi fi fi fi fi 3130 1817 54 0Reset fi fi fi
3130 1817 54 0Reset fi fi fi 3130 29 2827 26 0Reset fi fi fi fi
313029282726 25 0Reset 313029282726 25 0Reset
313029282726 25 0Reset 313029282726 25 0Reset
3130 29 1615 0Reset fi fi fl fi fi 3130 0Reset fi
31 302928 27 87 0Reset fi fi fi
3130 1918171615 0Reset fi fi fi fi
31 30 0Reset fi 31 0Reset fi
31302928 27 26 87 0Reset fi fi fi
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31 30 0Reset fi 310Reset fi
31 43 21 0Reset fi fi
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313029 28 2625 14 13 1211 0Reset fi fi fi
313029 28 2625 14 13 1211 0Reset fi fi fi 31 10Reset
31 1716 10Reset fi fi fi 31 1716 10Reset fi fi fi
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