Product OverviewFeaturesApplications1 ESP32-C6 Series Comparison1.1 Nomenclature1.2 Comparison1.3 Chip Revision2 Pins2.1 Pin Layout2.2 Pin Overview2.3 IO Pins2.3.1 IO MUX Pin Functions2.3.2 LP IO MUX Functions2.3.3 Analog Functions2.3.4 Restrictions for GPIOs and LP GPIOs2.3.5 Peripheral Pin Assignment2.4 Analog Pins2.5 Power Supply2.5.1 Power Pins2.5.2 Power Scheme2.5.3 Chip Power-up and Reset2.6 Pin Mapping Between Chip and Flash3 Boot Configurations3.1 Chip Boot Mode Control3.2 SDIO Sampling and Driving Clock Edge Control3.3 ROM Messages Printing Control3.4 JTAG Signal Source Control4 Functional Description4.1 System4.1.1 Microprocessor and Master4.1.1.1 High-Performance CPU4.1.1.2 RISC-V Trace Encoder4.1.1.3 Low-Power CPU4.1.1.4 GDMA Controller4.1.2 Memory Organization4.1.2.1 Internal Memory4.1.2.2 External Memory4.1.2.3 eFuse Controller4.1.3 System Components4.1.3.1 IO MUX and GPIO Matrix4.1.3.2 Reset4.1.3.3 Clock4.1.3.4 Interrupt Matrix4.1.3.5 Event Task Matrix4.1.3.6 System Timer4.1.3.7 Power Management Unit4.1.3.8 Timer Group4.1.3.9 Watchdog Timers4.1.3.10 Permission Control4.1.3.11 System Registers4.1.3.12 Debug Assistant4.1.4 Cryptography and Security Component4.1.4.1 AES Accelerator4.1.4.2 ECC Accelerator4.1.4.3 HMAC Accelerator4.1.4.4 RSA Accelerator4.1.4.5 SHA Accelerator4.1.4.6 Digital Signature4.1.4.7 External Memory Encryption and Decryption4.1.4.8 Random Number Generator4.2 Peripherals4.2.1 Connectivity Interface4.2.1.1 UART Controller4.2.1.2 SPI Controller4.2.1.3 I2C Controller4.2.1.4 I2S Controller4.2.1.5 Pulse Count Controller4.2.1.6 USB Serial/JTAG Controller4.2.1.7 Two-wire Automotive Interface4.2.1.8 SDIO Slave Controller 4.2.1.9 LED PWM Controller4.2.1.10 Motor Control PWM4.2.1.11 Remote Control Peripheral4.2.1.12 Parallel IO Controller4.2.2 Analog Signal Processing4.2.2.1 SAR ADC4.2.2.2 Temperature Sensor4.3 Wireless Communication4.3.1 Radio4.3.1.1 2.4 GHz Receiver4.3.1.2 2.4 GHz Transmitter4.3.1.3 Clock Generator4.3.2 Wi-Fi4.3.2.1 Wi-Fi Radio and Baseband4.3.2.2 Wi-Fi MAC4.3.2.3 Networking Features4.3.3 Bluetooth LE4.3.3.1 Bluetooth LE PHY4.3.3.2 Bluetooth LE Link Controller4.3.4 802.15.44.3.4.1 802.15.4 PHY4.3.4.2 802.15.4 MAC5 Electrical Characteristics5.1 Absolute Maximum Ratings5.2 Recommended Operating Conditions5.3 VDD_SPI Output Characteristics5.4 DC Characteristics (3.3 V, 25 °C)5.5 ADC Characteristics5.6 Current Consumption Characteristics5.6.1 Current Consumption in Active Mode5.6.2 Current Consumption in Other Modes5.7 Memory Specifications5.8 Reliability6 RF Characteristics6.1 Wi-Fi Radio6.1.1 Wi-Fi RF Transmitter (TX) Characteristics6.1.2 Wi-Fi RF Receiver (RX) Characteristics6.2 Bluetooth 5 (LE) Radio6.2.1 Bluetooth LE RF Transmitter (TX) Characteristics6.2.2 Bluetooth LE RF Receiver (RX) Characteristics6.3 802.15.4 Radio6.3.1 802.15.4 RF Transmitter (TX) Characteristics6.3.2 802.15.4 RF Receiver (RX) Characteristics7 PackagingESP32-C6 Consolidated Pin OverviewDatasheet VersioningGlossaryRelated Documentation and ResourcesRevision History ESP32-C6 SeriesDatasheet Version 1.4Ultra-low-power SoC with RISC-V single-core microprocessor2.4 GHz Wi-Fi 6 (802.11ax), Bluetooth®5 (LE), Zigbee and Thread (802.15.4)Optional flash in the chip’s package30 or 22 GPIOs, rich set of peripheralsQFN40 (5×5 mm) or QFN32 (5×5 mm) packageIncluding:ESP32-C6ESP32-C6FH4ESP32-C6FH8www.espressif.com Product OverviewThe ESP32-C6 SoC (System on Chip) supports Wi-Fi 6 in 2.4 GHz band, Bluetooth 5, Zigbee 3.0 and Thread1.3. It consists of a high-performance (HP) 32-bit RISC-V processor, an low-power (LP) 32-bit RISC-V processor,wireless baseband and MAC (Wi-Fi, Bluetooth LE, and 802.15.4), RF module, and numerous peripherals. Wi-Fi,Bluetooth and 802.15.4 coexist with each other and share the same antenna.The functional block diagram of the SoC is shown below.CPU SystemWireless MAC and BasebandWi-Fi MAC Wi-Fi BasebandBluetooth LE Link ControllerBluetooth LE Baseband2.4 GHz Balun + Switch2.4 GHz Receiver2.4 GHz TransmitterRF SynthesizerRFSecurityHP RISC-V32-bitMicroprocessorJTAGCachePeripherals Espressif’s ESP32-C6 Wi-Fi + Bluetooth® Low Energy + 802.15.4 SoCSRAMMCPWMGPIOUARTTWAI®General-Purpose TimersI2SI2CPCNTLED PWMUSB Serial/JTAGSPIRMTADCSystem TimerLP IOTemperature SensorLP MemoryRTC Watchdog TimerPower Management UnitPower ManagementDigital SignatureAESHMAC⚙⚙⚙Modules having power in specific power modes:ActiveActive and Modem-sleepActive, Modem-sleep, Light-sleep; optional in Light-sleep⚙GDMAETM⚙SDIO 2.0 Slave802.15.4Baseband802.15.4MACRSASHA⚙ ⚙ECC⚙BrownoutDetectorLP UARTLP I2CLP RISC-V32-bitMicroprocessorAll modesROMPARLIOeFuse ControllerMain System Watchdog TimersSuper Watchdog⚙⚙⚙⚙⚙⚙⚙⚙⚙⚙⚙⚙⚙⚙⚙⚙⚙⚙⚙⚙RNGClock Glitch FilterTEEController⚙⚙ ⚙Flash EncryptionSecure Boot⚙APM⚙⚙optional in Deep-sleep⚙⚙⚙⚙ESP32-C6 Functional Block DiagramFor more information on power consumption, see Section 4.1.3.7 Power Management Unit.Espressif Systems 2Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 FeaturesWi-Fi• 1T1R in 2.4 GHz band• Operating frequency: 2412 ~ 2484 MHz• Data rate up to 150 Mbps• IEEE 802.11ax-compliant– 20 MHz-only non-AP mode– MCS0 ~MCS9– Uplink and downlink OFDMA, especiallysuitable for simultaneous connections inhigh-density environments– Downlink MU-MIMO (multi-user, multipleinput, multiple output) to increase networkcapacity– Beamformee that improves signal quality– Channel quality indication (CQI)– DCM (dual carrier modulation) to improvelink robustness– Spatial reuse to maximize paralleltransmissions– Target wake time (TWT) that optimizespower saving mechanisms• Fully compatible with IEEE 802.11b/g/n protocol– 20 MHz and 40 MHz bandwidth– MCS0 ~MCS7– Wi-Fi Multimedia (WMM)– TX/RX A-MPDU, TX/RX A-MSDU– Immediate Block ACK– Fragmentation and defragmentation– Transmit opportunity (TXOP)– Automatic Beacon monitoring (hardwareTSF)– Four virtual Wi-Fi interfaces– Simultaneous support for Infrastructure BSSin Station mode, SoftAP mode, Station +SoftAP mode, and promiscuous modeNote that when ESP32-C6 scans in Stationmode, the SoftAP channel will change alongwith the Station channel– Antenna diversity– 802.11mc FTMBluetooth®• Bluetooth LE: Bluetooth 5.3 certified• Bluetooth mesh• High power mode with up to 20 dBmtransmission power• Speed: 125 Kbps, 500 Kbps, 1 Mbps, 2 Mbps• Advertising extensions• Multiple advertisement sets• Channel selection algorithm #2• LE power control• Internal co-existence mechanism between Wi-Fiand Bluetooth to share the same antennaIEEE 802.15.4• Compliant with IEEE 802.15.4-2015 protocol• OQPSK PHY in 2.4 GHz band• Data rate: 250 Kbps• Thread 1.3• Zigbee 3.0CPU and Memory• HP RISC-V processor:– Clock speed: up to 160 MHz– Four stage pipeline– CoreMark®score: 496.66 CoreMark; 3.10CoreMark/MHz (160 MHz)Espressif Systems 3Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 • LP RISC-V processor:– Clock speed: up to 20 MHz– Two stage pipeline• General DMA controller, with 3 transmit channelsand 3 receive channels• L1 cache: 32 KB• ROM: 320 KB• HP SRAM: 512 KB• LP SRAM: 16 KB• 4096-bit eFuse memory, up to 1792 bits forusers• Supported SPI protocols: SPI, Dual SPI, QuadSPI, QPI interfaces that allow connection to flashand other SPI devices off the chip’s package• Flash controller with cache is supported• Flash in-Circuit Programming (ICP) is supportedPeripherals• 30 GPIOs (QFN40), or 22 GPIOs (QFN32)– 5 strapping GPIOs– 6 GPIOs needed for off-package flash• Connectivity interfaces:– Two UARTs– Low-power (LP) UART– Two SPI ports for communication with flash– General purpose SPI port– I2C– Low-power (LP) I2C– I2S– Pulse count controller– USB Serial/JTAG controller– Two TWAI®controllers, compatible with ISO11898-1 (CAN Specification 2.0)– SDIO slave controller– LED PWM controller, up to 6 channels– Motor Control PWM (MCPWM)– Remote control peripheral (TX/RX)– Parallel IO interface (PARLIO)– Event task matrix (ETM)• Analog signal processing:– 12-bit SAR ADC, up to 7 channels– Temperature sensor• Timers:– 52-bit system timer– Two 54-bit general-purpose timers– Three digital watchdog timers– Analog watchdog timerPower Management• Fine-resolution power control, including clockfrequency, duty cycle, Wi-Fi operating modes,and individual internal component control• Four power modes designed for typicalscenarios: Active, Modem-sleep, Light-sleep,Deep-sleep• Power consumption in Deep-sleep mode is 7 µA• Low-power (LP) memory remains powered on inDeep-sleep modeSecurity• Secure boot - permission control on accessinginternal and external memory• Flash encryption - memory encryption anddecryption• Trusted execution environment (TEE) controllerand access permission management (APM)• Cryptographic hardware acceleration:– AES-128/256 (FIPS PUB 197)– ECC– HMAC– RSAEspressif Systems 4Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 – SHA (FIPS PUB 180-4)– Digital signature• External Memory Encryption and Decryption(XTS_AES)• Random Number Generator (RNG)RF Module• Antenna switches, RF balun, power amplifier,low-noise receive amplifier• Up to +21 dBm of power for an 802.11btransmission• Up to +19.5 dBm of power for an 802.11axtransmission• Up to -106 dBm of sensitivity for Bluetooth LEreceiver (125 Kbps)ApplicationsWith low power consumption, ESP32-C6 is an ideal choice for IoT devices in the following areas:• Smart Home• Industrial Automation• Health Care• Consumer Electronics• Smart Agriculture• POS Machines• Service Robot• Audio Devices• Generic Low-power IoT Sensor Hubs• Generic Low-power IoT Data LoggersEspressif Systems 5Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 ContentsNote:Check the link or the QR code to make sure that you use the latest version of this document:https://www.espressif.com/documentation/esp32-c6_datasheet_en.pdfContentsProduct Overview 2Features 3Applications 51 ESP32-C6 Series Comparison 131.1 Nomenclature 131.2 Comparison 131.3 Chip Revision 132 Pins 142.1 Pin Layout 142.2 Pin Overview 162.3 IO Pins 192.3.1 IO MUX Pin Functions 192.3.2 LP IO MUX Functions 222.3.3 Analog Functions 232.3.4 Restrictions for GPIOs and LP GPIOs 242.3.5 Peripheral Pin Assignment 252.4 Analog Pins 282.5 Power Supply 292.5.1 Power Pins 292.5.2 Power Scheme 292.5.3 Chip Power-up and Reset 302.6 Pin Mapping Between Chip and Flash 323 Boot Configurations 333.1 Chip Boot Mode Control 343.2 SDIO Sampling and Driving Clock Edge Control 353.3 ROM Messages Printing Control 353.4 JTAG Signal Source Control 364 Functional Description 374.1 System 374.1.1 Microprocessor and Master 374.1.1.1 High-Performance CPU 374.1.1.2 RISC-V Trace Encoder 37Espressif Systems 6Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 Contents4.1.1.3 Low-Power CPU 384.1.1.4 GDMA Controller 384.1.2 Memory Organization 394.1.2.1 Internal Memory 404.1.2.2 External Memory 404.1.2.3 eFuse Controller 404.1.3 System Components 414.1.3.1 IO MUX and GPIO Matrix 414.1.3.2 Reset 414.1.3.3 Clock 424.1.3.4 Interrupt Matrix 424.1.3.5 Event Task Matrix 434.1.3.6 System Timer 434.1.3.7 Power Management Unit 434.1.3.8 Timer Group 444.1.3.9 Watchdog Timers 444.1.3.10 Permission Control 454.1.3.11 System Registers 454.1.3.12 Debug Assistant 464.1.4 Cryptography and Security Component 464.1.4.1 AES Accelerator 464.1.4.2 ECC Accelerator 474.1.4.3 HMAC Accelerator 474.1.4.4 RSA Accelerator 474.1.4.5 SHA Accelerator 484.1.4.6 Digital Signature 484.1.4.7 External Memory Encryption and Decryption 484.1.4.8 Random Number Generator 494.2 Peripherals 504.2.1 Connectivity Interface 504.2.1.1 UART Controller 504.2.1.2 SPI Controller 504.2.1.3 I2C Controller 514.2.1.4 I2S Controller 524.2.1.5 Pulse Count Controller 524.2.1.6 USB Serial/JTAG Controller 534.2.1.7 Two-wire Automotive Interface 534.2.1.8 SDIO Slave Controller 544.2.1.9 LED PWM Controller 554.2.1.10 Motor Control PWM 554.2.1.11 Remote Control Peripheral 564.2.1.12 Parallel IO Controller 574.2.2 Analog Signal Processing 574.2.2.1 SAR ADC 574.2.2.2 Temperature Sensor 584.3 Wireless Communication 59Espressif Systems 7Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 Contents4.3.1 Radio 594.3.1.1 2.4 GHz Receiver 594.3.1.2 2.4 GHz Transmitter 594.3.1.3 Clock Generator 594.3.2 Wi-Fi 604.3.2.1 Wi-Fi Radio and Baseband 604.3.2.2 Wi-Fi MAC 604.3.2.3 Networking Features 624.3.3 Bluetooth LE 624.3.3.1 Bluetooth LE PHY 624.3.3.2 Bluetooth LE Link Controller 624.3.4 802.15.4 634.3.4.1 802.15.4 PHY 634.3.4.2 802.15.4 MAC 635 Electrical Characteristics 645.1 Absolute Maximum Ratings 645.2 Recommended Operating Conditions 645.3 VDD_SPI Output Characteristics 655.4 DC Characteristics (3.3 V, 25 °C) 655.5 ADC Characteristics 655.6 Current Consumption Characteristics 665.6.1 Current Consumption in Active Mode 665.6.2 Current Consumption in Other Modes 675.7 Memory Specifications 685.8 Reliability 686 RF Characteristics 706.1 Wi-Fi Radio 706.1.1 Wi-Fi RF Transmitter (TX) Characteristics 706.1.2 Wi-Fi RF Receiver (RX) Characteristics 716.2 Bluetooth 5 (LE) Radio 736.2.1 Bluetooth LE RF Transmitter (TX) Characteristics 736.2.2 Bluetooth LE RF Receiver (RX) Characteristics 756.3 802.15.4 Radio 776.3.1 802.15.4 RF Transmitter (TX) Characteristics 776.3.2 802.15.4 RF Receiver (RX) Characteristics 777 Packaging 78ESP32-C6 Consolidated Pin Overview 79Datasheet Versioning 81Glossary 82Espressif Systems 8Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 ContentsRelated Documentation and Resources 83Revision History 84Espressif Systems 9Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 List of TablesList of Tables1-1 ESP32-C6 Series Comparison 132-1 QFN40 Pin Overview 162-2 QFN32 Pin Overview 172-3 Peripheral Signals Routed via IO MUX 192-4 QFN40 IO MUX Pin Functions 202-5 QFN32 IO MUX Pin Functions 212-6 LP Peripheral Signals Routed via LP IO MUX 222-7 LP IO MUX Functions 222-8 Analog Signals Routed to Analog Functions 232-9 Analog Functions 232-10 QFN40 Peripheral Pin Assignment 262-11 QFN32 Peripheral Pin Assignment 272-12 Analog Pins 282-13 Power Pins 292-14 Voltage Regulators 292-15 Description of Timing Parameters for Power-up and Reset 312-16 Pin Mapping Between QFN40 Chip and Flash 323-1 Default Configuration of Strapping Pins 333-2 Description of Timing Parameters for the Strapping Pins 343-3 Chip Boot Mode Control 343-4 SDIO Input Sampling Edge/Output Driving Edge Control 353-5 UART0 ROM Message Printing Control 353-6 USB Serial/JTAG ROM Message Printing Control 363-7 JTAG Signal Source Control 365-1 Absolute Maximum Ratings 645-2 Recommended Operating Conditions 645-3 VDD_SPI Internal and Output Characteristics 655-4 DC Characteristics (3.3 V, 25 °C) 655-5 ADC Characteristics 665-6 ADC Calibration Results 665-7 Current Consumption for Wi-Fi (2.4 GHz) in Active Mode 665-8 Current Consumption for Bluetooth LE in Active Mode 675-9 Current Consumption for 802.15.4 in Active Mode 675-10 Current Consumption in Modem-sleep Mode 675-11 Current Consumption in Low-Power Modes 685-12 Flash Specifications 685-13 Reliability Qualifications 686-1 Wi-Fi RF Characteristics 706-2 TX Power with Spectral Mask and EVM Meeting 802.11 Standards 706-3 TX EVM Test1706-4 RX Sensitivity 716-5 Maximum RX Level 726-6 RX Adjacent Channel Rejection 72Espressif Systems 10Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 List of Tables6-7 Bluetooth LE RF Characteristics 736-8 Bluetooth LE - Transmitter Characteristics - 1 Mbps 736-9 Bluetooth LE - Transmitter Characteristics - 2 Mbps 736-10 Bluetooth LE - Transmitter Characteristics - 125 Kbps 746-11 Bluetooth LE - Transmitter Characteristics - 500 Kbps 746-12 Bluetooth LE - Receiver Characteristics - 1 Mbps 756-13 Bluetooth LE - Receiver Characteristics - 2 Mbps 756-14 Bluetooth LE - Receiver Characteristics - 125 Kbps 766-15 Bluetooth LE - Receiver Characteristics - 500 Kbps 766-16 802.15.4 RF Characteristics 776-17 802.15.4 Transmitter Characteristics - 250 Kbps 776-18 802.15.4 Receiver Characteristics - 250 Kbps 777-1 QFN40 Pin Overview 797-2 QFN32 Pin Overview 80Espressif Systems 11Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 List of FiguresList of Figures1-1 ESP32-C6 Series Nomenclature 132-1 ESP32-C6 Pin Layout (QFN40, Top View) 142-2 ESP32-C6 Pin Layout (QFN32, Top View) 152-3 ESP32-C6 Power Scheme 302-4 Visualization of Timing Parameters for Power-up and Reset 303-1 Visualization of Timing Parameters for the Strapping Pins 344-1 Address Mapping Structure 397-1 QFN40 (5×5 mm) Package 787-2 QFN32 (5×5 mm) Package 78Espressif Systems 12Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 1 ESP32-C6 Series Comparison1 ESP32-C6 Series Comparison1.1 NomenclatureESP32-C6FHxChip seriesIn-package flashFlash temperatureH: High temperatureN: Normal temperatureFlash Figure 1-1. ESP32-C6 Series Nomenclature1.2 ComparisonTable 1-1. ESP32-C6 Series ComparisonPart Number1In-Package Flash Ambient Temp.2Package Chip RevisionESP32-C6 —3–40 ∼ 105 °C QFN40 (5×5 mm) v0.0/v0.1/v0.2ESP32-C6FH4 4 MB (Quad SPI)4, 5–40 ∼ 105 °C QFN32 (5×5 mm) v0.0/v0.1/v0.2ESP32-C6FH8 8 MB (Quad SPI)4, 5–40 ∼ 105 °C QFN32 (5×5 mm) v0.0/v0.1/v0.21For details on chip marking and packing, see Section 7 Packaging.2Ambient temperature specifies the recommended temperature range of the environment immediatelyoutside an Espressif chip.3Can connect a flash outside the chip package. For details, see Section 4.1.2.2 External Memory.4For details about SPI modes, see Section 2.6 Pin Mapping Between Chip and Flash.5For information about in-package flash, see also Section 4.1.2.1 Internal Memory. By default, the SPIflash on the chip operates at a maximum clock frequency of 80 MHz and does not support the autosuspend feature. If you have a requirement for a higher flash clock frequency of 120 MHz or if youneed the flash auto suspend feature, please contact us.1.3 Chip RevisionAs shown in Table 1-1 ESP32-C6 Series Comparison, ESP32-C6 now has multiple chip revisions available on themarket using the same part number.For chip revision identification, ESP-IDF release that supports a specific chip revision, and errors fixed in eachchip revision, please refer to ESP32-C6 Series SoC Errata.Espressif Systems 13Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 2 Pins2 Pins2.1 Pin Layout12345678910SPICS0GPIO13GPIO12GPIO11GPIO10GPIO9GPIO8MTDOMTCKMTDIMTMSGPIO3GPIO2XTAL_32K_NXTAL_32K_PVDDPST1CHIP_PUVDDA3P3VDDA3P3ANTVDDA2XTAL_NVDDA1SDIO_DATA3SDIO_DATA2SDIO_DATA1SDIO_DATA0SDIO_CLKSDIO_CMDXTAL_PU0RXDU0TXDVDDPST2SPIDSPICLKVDD_SPISPIWPSPIQSPIHD1112131415161718192030292827262524232221GPIO1540393837363534333231ESP32-C641 GNDFigure 2-1. ESP32-C6 Pin Layout (QFN40, Top View)Espressif Systems 14Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 2 Pins12345678MTMSGPIO3GPIO12GPIO9GPIO8MTDOMTCKMTDIGPIO2XTAL_32K_NXTAL_32K_PVDDPST1CHIP_PUVDDA3P3VDDA3P3ANTVDDA2XTAL_NVDDA1SDIO_DATA3SDIO_DATA2SDIO_DATA1SDIO_DATA0XTAL_PU0RXDU0TXDVDDPST2GPIO14GPIO13SDIO_CMDSDIO_CLK1112131415169102221201918172423GPIO153231302928272625ESP32-C633 GNDFigure 2-2. ESP32-C6 Pin Layout (QFN32, Top View)Espressif Systems 15Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 2 Pins2.2 Pin OverviewThe ESP32-C6 chip integrates multiple peripherals that require communication with the outside world. To keepthe chip package size reasonably small, the number of available pins has to be limited. So the only way to routeall the incoming and outgoing signals is through pin multiplexing. Pin muxing is controlled via softwareprogrammable registers (see ESP32-C6 Technical Reference Manual > Chapter IO MUX and GPIO Matrix).All in all, the ESP32-C6 chip has the following types of pins:• IO pins with the following predefined sets of functions to choose from:– Each IO pin has predefined IO MUX functions – see Table 2-4 QFN40 IO MUX Pin Functions or Table2-5 QFN32 IO MUX Pin Functions– Some IO pins have predefined LP IO MUX functions – see Table 2-7 LP IO MUX Functions– Some IO pins have predefined analog functions – see Table 2-9 Analog FunctionsPredefined functions means that each IO pin has a set of direct connections to certain signals from on-chipperipherals. During run-time, the user can configure which peripheral signal from a predefined set toconnect to a certain pin at a certain time via memory mapped registers.• Analog pins that have exclusively-dedicated analog functions – see Table 2-12 Analog Pins• Power pins that supply power to the chip components and non-power pins – see Table 2-13 Power PinsTable 2-1 QFN40 Pin Overview or Table 2-2 QFN32 Pin Overview gives an overview of all the pins. For moreinformation, see the respective sections for each pin type below, or ESP32-C6 Consolidated Pin Overview.Table 2-1. QFN40 Pin OverviewPin Pin Pin Pin Providing Pin Settings4-6Pin Function Sets1No. Name Type Power2, 3At Reset After Reset IO MUX LP IO MUX Analog1 ANT Analog2 VDDA3P3 Power3 VDDA3P3 Power4 CHIP_PU Analog VDDPST15 VDDPST1 Power6 XTAL_32K_P IO VDDPST1 IO MUX LP IO MUX Analog7 XTAL_32K_N IO VDDPST1 IO MUX LP IO MUX Analog8 GPIO2 IO VDDPST1 IE IE IO MUX LP IO MUX Analog9 GPIO3 IO VDDPST1 IE IE IO MUX LP IO MUX Analog10 MTMS IO VDDPST1 IE IE IO MUX LP IO MUX Analog11 MTDI IO VDDPST1 IE IE IO MUX LP IO MUX Analog12 MTCK IO VDDPST1 IE, WPU5IO MUX LP IO MUX Analog13 MTDO IO VDDPST1 IE IO MUX LP IO MUX14 GPIO8 IO VDDPST2 IE IE IO MUX15 GPIO9 IO VDDPST2 IE, WPU IE, WPU IO MUX16 GPIO10 IO VDDPST2 IE IO MUX17 GPIO11 IO VDDPST2 IE IO MUX18 GPIO12 IO VDDPST2 IE IO MUX Analog19 GPIO13 IO VDDPST2 USB_PU IE, USB_PU IO MUX AnalogCont’d on next pageEspressif Systems 16Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 2 PinsTable 2-1 – cont’d from previous pagePin Pin Pin Pin Providing Pin Settings4-6Pin Function Sets1No. Name Type Power2, 3At Reset After Reset IO MUX LP IO MUX Analog20 SPICS0 IO VDD_SPI WPU IE, WPU IO MUX21 SPIQ IO VDD_SPI WPU IE, WPU IO MUX22 SPIWP IO VDD_SPI WPU IE, WPU IO MUX23 VDD_SPI Power/IO — IO MUX Analog24 SPIHD IO VDD_SPI WPU IE, WPU IO MUX25 SPICLK IO VDD_SPI WPU IE, WPU IO MUX26 SPID IO VDD_SPI WPU IE, WPU IO MUX27 GPIO15 IO VDDPST2 IE IE IO MUX28 VDDPST2 Power29 U0TXD IO VDDPST2 WPU6IO MUX30 U0RXD IO VDDPST2 IE, WPU IO MUX31 SDIO_CMD IO VDDPST2 WPU IE IO MUX32 SDIO_CLK IO VDDPST2 WPU IE IO MUX33 SDIO_DATA0 IO VDDPST2 WPU IE IO MUX34 SDIO_DATA1 IO VDDPST2 WPU IE IO MUX35 SDIO_DATA2 IO VDDPST2 WPU IE IO MUX36 SDIO_DATA3 IO VDDPST2 WPU IE IO MUX37 VDDA1 Power38 XTAL_N Analog39 XTAL_P Analog40 VDDA2 Power41 GND PowerTable 2-2. QFN32 Pin OverviewPin Pin Pin Pin Providing Pin Settings4-6Pin Function Sets1No. Name Type Power2, 3At Reset After Reset IO MUX LP IO MUX Analog1 ANT Analog2 VDDA3P3 Power3 VDDA3P3 Power4 CHIP_PU Analog VDDPST15 VDDPST1 Power6 XTAL_32K_P IO VDDPST1 IO MUX LP IO MUX Analog7 XTAL_32K_N IO VDDPST1 IO MUX LP IO MUX Analog8 GPIO2 IO VDDPST1 IE IE IO MUX LP IO MUX Analog9 GPIO3 IO VDDPST1 IE IE IO MUX LP IO MUX Analog10 MTMS IO VDDPST1 IE IE IO MUX LP IO MUX Analog11 MTDI IO VDDPST1 IE IE IO MUX LP IO MUX Analog12 MTCK IO VDDPST1 IE, WPU5IO MUX LP IO MUX Analog13 MTDO IO VDDPST1 IE IO MUX LP IO MUX14 GPIO8 IO VDDPST2 IE IE IO MUX15 GPIO9 IO VDDPST2 IE, WPU IE, WPU IO MUX16 GPIO12 IO VDDPST2 IE IO MUX Analog17 GPIO13 IO VDDPST2 USB_PU IE, USB_PU IO MUX AnalogCont’d on next pageEspressif Systems 17Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 2 PinsTable 2-2 – cont’d from previous pagePin Pin Pin Pin Providing Pin Settings4-6Pin Function Sets1No. Name Type Power2, 3At Reset After Reset IO MUX LP IO MUX Analog18 GPIO14 IO VDDPST2 IE IO MUX19 GPIO15 IO VDDPST2 IE IE IO MUX20 VDDPST2 Power21 U0TXD IO VDDPST2 WPU6IO MUX22 U0RXD IO VDDPST2 IE, WPU IO MUX23 SDIO_CMD IO VDDPST2 WPU IE IO MUX24 SDIO_CLK IO VDDPST2 WPU IE IO MUX25 SDIO_DATA0 IO VDDPST2 WPU IE IO MUX26 SDIO_DATA1 IO VDDPST2 WPU IE IO MUX27 SDIO_DATA2 IO VDDPST2 WPU IE IO MUX28 SDIO_DATA3 IO VDDPST2 WPU IE IO MUX29 VDDA1 Power30 XTAL_N Analog31 XTAL_P Analog32 VDDA2 Power33 GND Power1. Bold marks the pin function set in which a pin has its default function in the default boot mode. See Section 3.1 Chip Boot ModeControl.2. In column Pin Providing Power, regarding pins powered by VDD_SPI:• Power actually comes from the internal power rail supplying power to VDD_SPI. For details, see Section 2.5.2 Power Scheme.3. Except for GPIO12 and GPIO13 whose default drive strength is 40 mA, the default drive strength for all the other pins is 20 mA.4. ColumnPin Settingsshows predefined settings at reset and after reset with the following abbreviations:• IE – input enabled• WPU – internal weak pull-up resistor enabled• WPD – internal weak pull-down resistor enabled• USB_PU – USB pull-up resistor enabled– By default, the USB function is enabled for USB pins (i.e., GPIO12 and GPIO13), and the pin pull-up is decided by theUSB pull-up resistor. The USB pull-up resistor is controlled by USB_SERIAL_JTAG_DP/DM_PULLUP and the pull-upvalue is controlled by USB_SERIAL_JTAG_PULLUP_VALUE. For details, see ESP32-C6 Technical Reference Manual >Chapter USB Serial/JTAG Controller).– When the USB function is disabled, USB pins are used as regular GPIOs. At reset, GPIO13’s internal weak pull-up resistoris disabled by default. After reset, GPIO13’s internal weak pull-up resistor is enabled by default. A pin’s internal weakpull-up and pull-down resistors are configurable by IO_MUX_FUN_WPU/WPD. For details, seeESP32-C6 Technical Reference Manual > Chapter IO MUX and GPIO Matrix.5. Depends on the value of EFUSE_DIS_PAD_JTAG• 0 - default value. Input enabled, and internal weak pull-up resistor enabled (IE & WPU)• 1 - input enabled (IE)6. Output enabledEspressif Systems 18Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 2 Pins2.3 IO Pins2.3.1 IO MUX Pin FunctionsThe IO MUX allows multiple input/output signals to be connected to a single input/output pin. Each IO pin ofESP32-C6 can be connected to one of the three signals (IO MUX functions, i.e. F0-F2), as listed in Table 2-4QFN40 IO MUX Pin Functions and Table 2-5 QFN32 IO MUX Pin Functions.Among the three sets of signals:• Some are routed via the GPIO Matrix (GPIO0, GPIO1, etc.), which incorporates internal signal routingcircuitry for mapping signals programmatically. It gives the pin access to almost any peripheral signals.However, the flexibility of programmatic mapping comes at a cost as it might affect the latency of routedsignals. For details about connecting to peripheral signals via GPIO Matrix, seeESP32-C6 Technical Reference Manual > Chapter IO MUX and GPIO Matrix.• Some are directly routed from certain peripherals (U0TXD, MTCK, etc.), including UART0, JTAG, SPI0/1,SPI2, and SDIO - see Table 2-3 Peripheral Signals Routed via IO MUX.Table 2-3. Peripheral Signals Routed via IO MUXPin Function Signal DescriptionU0TXD Transmit dataUART0 interfaceU0RXD Receive dataMTCK Test clockJTAG interface for debuggingMTDO Test Data OutMTDI Test Data InMTMS Test Mode SelectSPIQ Master in, slave out3.3 V SPI0/1 interface for connection to in-package or off-package flashvia the SPI bus. It supports 1-, 2-, 4-line SPI modes. See also Section 2.6Pin Mapping Between Chip and FlashSPID Master out, slave inSPIHD HoldSPIWP Write protectSPICLK ClockSPICS0 Chip selectFSPIQ Master in, slave outSPI2 interface for fast SPI connection. It supports 1-, 2-, 4-line SPI modesFSPID Master out, slave inFSPIHD HoldFSPIWP Write protectFSPICLK ClockFSPICS… Chip selectSDIO_CMD CommandSDIO interfaceSDIO_CLK ClockSDIO_DATA… DataTable 2-4 QFN40 IO MUX Pin Functions or Table 2-5 QFN32 IO MUX Pin Functions shows the IO MUX functions ofIO pins.Espressif Systems 19Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 2 PinsTable 2-4. QFN40 IO MUX Pin FunctionsPin IO MUX / IO MUX Function1, 2, 3No.GPIOName2F0 Type3F1 Type F2 Type6 GPIO0 GPIO0 I/O/T GPIO0 I/O/T7 GPIO1 GPIO1 I/O/T GPIO1 I/O/T8 GPIO2 GPIO2 I/O/T GPIO2 I/O/T FSPIQ I1/O/T9 GPIO3 GPIO3 I/O/T GPIO3 I/O/T10 GPIO4 MTMS I1 GPIO4 I/O/T FSPIHD I1/O/T11 GPIO5 MTDI I1 GPIO5 I/O/T FSPIWP I1/O/T12 GPIO6 MTCK I1 GPIO6 I/O/T FSPICLK I1/O/T13 GPIO7 MTDO O/T GPIO7 I/O/T FSPID I1/O/T14 GPIO8 GPIO8 I/O/T GPIO8 I/O/T15 GPIO9 GPIO9 I/O/T GPIO9 I/O/T16 GPIO10 GPIO10 I/O/T GPIO10 I/O/T17 GPIO11 GPIO11 I/O/T GPIO11 I/O/T18 GPIO12 GPIO12 I/O/T GPIO12 I/O/T19 GPIO13 GPIO13 I/O/T GPIO13 I/O/T20 GPIO24 SPICS0 O/T GPIO24 I/O/T21 GPIO25 SPIQ I1/O/T GPIO25 I/O/T22 GPIO26 SPIWP I1/O/T GPIO26 I/O/T23 GPIO27 GPIO27 I/O/T GPIO27 I/O/T24 GPIO28 SPIHD I1/O/T GPIO28 I/O/T25 GPIO29 SPICLK O/T GPIO29 I/O/T26 GPIO30 SPID I1/O/T GPIO30 I/O/T27 GPIO15 GPIO15 I/O/T GPIO15 I/O/T29 GPIO16 U0TXD O GPIO16 I/O/T FSPICS0 I1/O/T30 GPIO17 U0RXD I1 GPIO17 I/O/T FSPICS1 O/T31 GPIO18 SDIO_CMD I1/O/T GPIO18 I/O/T FSPICS2 O/T32 GPIO19 SDIO_CLK I1 GPIO19 I/O/T FSPICS3 O/T33 GPIO20 SDIO_DATA0 I1/O/T GPIO20 I/O/T FSPICS4 O/T34 GPIO21 SDIO_DATA1 I1/O/T GPIO21 I/O/T FSPICS5 O/T35 GPIO22 SDIO_DATA2 I1/O/T GPIO22 I/O/T36 GPIO23 SDIO_DATA3 I1/O/T GPIO23 I/O/T1Bold marks the default pin functions in the default boot mode. See Section 3.1 ChipBoot Mode Control.2Regarding highlighted cells, see Section 2.3.4 Restrictions for GPIOs and LP GPIOs.3Each IO MUX function (Fn, n = 0 ~ 2) is associated with a type. The description of typeis as follows:• I – input. O – output. T – high impedance.• I1 – input; if the pin is assigned a function other than Fn, the input signal of Fn isalways 1.• I0 – input; if the pin is assigned a function other than Fn, the input signal of Fn isalways0.Espressif Systems 20Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 2 PinsTable 2-5. QFN32 IO MUX Pin FunctionsPin IO MUX / IO MUX Function1, 2, 3No.GPIOName2F0 Type3F1 Type F2 Type6 GPIO0 GPIO0 I/O/T GPIO0 I/O/T7 GPIO1 GPIO1 I/O/T GPIO1 I/O/T8 GPIO2 GPIO2 I/O/T GPIO2 I/O/T FSPIQ I1/O/T9 GPIO3 GPIO3 I/O/T GPIO3 I/O/T10 GPIO4 MTMS I1 GPIO4 I/O/T FSPIHD I1/O/T11 GPIO5 MTDI I1 GPIO5 I/O/T FSPIWP I1/O/T12 GPIO6 MTCK I1 GPIO6 I/O/T FSPICLK I1/O/T13 GPIO7 MTDO O/T GPIO7 I/O/T FSPID I1/O/T14 GPIO8 GPIO8 I/O/T GPIO8 I/O/T15 GPIO9 GPIO9 I/O/T GPIO9 I/O/T16 GPIO12 GPIO12 I/O/T GPIO12 I/O/T17 GPIO13 GPIO13 I/O/T GPIO13 I/O/T18 GPIO14 GPIO14 I/O/T GPIO14 I/O/T19 GPIO15 GPIO15 I/O/T GPIO15 I/O/T21 GPIO16 U0TXD O GPIO16 I/O/T FSPICS0 I1/O/T22 GPIO17 U0RXD I1 GPIO17 I/O/T FSPICS1 O/T23 GPIO18 SDIO_CMD I1/O/T GPIO18 I/O/T FSPICS2 O/T24 GPIO19 SDIO_CLK I1 GPIO19 I/O/T FSPICS3 O/T25 GPIO20 SDIO_DATA0 I1/O/T GPIO20 I/O/T FSPICS4 O/T26 GPIO21 SDIO_DATA1 I1/O/T GPIO21 I/O/T FSPICS5 O/T27 GPIO22 SDIO_DATA2 I1/O/T GPIO22 I/O/T28 GPIO23 SDIO_DATA3 I1/O/T GPIO23 I/O/T1Boldmarks the default pin functions in the default boot mode. See Section3.1 ChipBoot Mode Control.2Regarding highlighted cells, see Section 2.3.4 Restrictions for GPIOs and LP GPIOs.3Each IO MUX function (Fn, n = 0 ~ 2) is associated with a type. The description of typeis as follows:• I – input. O – output. T – high impedance.• I1 – input; if the pin is assigned a function other than Fn, the input signal of Fn isalways 1.• I0 – input; if the pin is assigned a function other than Fn, the input signal of Fn isalways 0.Espressif Systems 21Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 2 Pins2.3.2 LP IO MUX FunctionsWhen the chip is in Deep-sleep mode, the IO MUX described in Section 2.3.1 IO MUX Pin Functions will not work.That is where the LP IO MUX comes in. It allows multiple input/output signals to be a single input/output pin inDeep-sleep mode, as the pin is connected to the LP system and powered by VDDPST1.LP IO pins can be assigned to LP functions. They can• Either work as LP GPIOs (LP_GPIO0, LP_GPIO1, etc.), connected to the LP CPU• Or connect to LP peripheral signals (LP_I2C_SDA, LP_I2C_SCL, etc.) - see Table 2-6 LP PeripheralSignals Routed via LP IO MUXTable 2-6. LP Peripheral Signals Routed via LP IO MUXPin Function Signal DescriptionLP_I2C_SDA Serial dataLP I2C interfaceLP_I2C_SCL Serial clockLP_UART_RXD ReceiveLP UART interfaceLP_UART_TXD TransmitLP_UART_RTSN Request to sendLP_UART_CTSN Clear to sendLP_UART_DTRN Data set readyLP_UART_DSRN Data terminal readyTable 2-7 LP IO MUX Functions shows the LP functions of LP IO pins.Table 2-7. LP IO MUX FunctionsPin LP IO LP IO MUX FunctionNo. Name1, 2, 3F0 F16 LP_GPIO0 LP_GPIO0 LP_UART_DTRN7 LP_GPIO1 LP_GPIO1 LP_UART_DSRN8 LP_GPIO2 LP_GPIO2 LP_UART_RTSN9 LP_GPIO3 LP_GPIO3 LP_UART_CTSN10 LP_GPIO4 LP_GPIO4 LP_UART_RXD11 LP_GPIO5 LP_GPIO5 LP_UART_TXD12 LP_GPIO6 LP_GPIO6 LP_I2C_SDA13 LP_GPIO7 LP_GPIO7 LP_I2C_SCL1Bold marks the default pin functions in the default bootmode. See Section 3.1 Chip Boot Mode Control.2This column lists the LP GPIO names, since LP func-tions are configured with LP GPIO registers that use LPGPIO numbering.3Regarding highlighted cells, see Section 2.3.4 Restric-tions for GPIOs and LP GPIOs.Espressif Systems 22Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 2 Pins2.3.3 Analog FunctionsSome IO pins also have analog functions, for analog peripherals (such as ADC) in any power mode. Internalanalog signals are routed to these analog functions, see Table 2-8 Analog Signals Routed to AnalogFunctions.Table 2-8. Analog Signals Routed to Analog FunctionsPin Function Signal DescriptionADC1_CH… ADC1 channel … signal ADC1 interfaceXTAL_32K_N Negative clock signal 32 kHz external clock input/output connectedto ESP32-C6’s crystal or oscillatorXTAL_32K_P Positive clock signalUSB_D- Data -USB Serial/JTAG functionUSB_D+ Data +Table 2-9 Analog Functions shows the analog functions of IO pins.Table 2-9. Analog FunctionsQFN40 QFN32 Analog Analog Function2Pin No. Pin No. IO Name1, 2F0 F16 6 GPIO0 XTAL_32K_P ADC1_CH07 7 GPIO1 XTAL_32K_N ADC1_CH18 8 GPIO2 ADC1_CH29 9 GPIO3 ADC1_CH310 10 GPIO4 ADC1_CH411 11 GPIO5 ADC1_CH512 12 GPIO6 ADC1_CH618 16 GPIO12 USB_D-19 17 GPIO13 USB_D+23 — GPIO27 VDD_SPI1Bold marks the default pin functions in the default boot mode. SeeSection 3.1 Chip Boot Mode Control.2Regarding highlighted cells, see Section 2.3.4 Restrictions for GPIOsand LP GPIOs.Espressif Systems 23Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 2 Pins2.3.4 Restrictions for GPIOs and LP GPIOsAll IO pins of ESP32-C6 have GPIO and some have LP GPIO pin functions. However, the IO pins are multiplexedand can be configured for different purposes based on the requirements. Some IOs have restrictions for usage. Itis essential to consider the multiplexed nature and the limitations when using these IO pins.In tables of this chapter, some pin functions are highlighted in red or yellow . These functions indicate pins thatrequire extra caution when used as GPIO / GPIO :• IO Pins – allocated for communication with flash and NOT recommended for other uses. For details, seeSection 2.6 Pin Mapping Between Chip and Flash.• IO Pins – have one of the following important functions:– Strapping pins – need to be at certain logic levels at startup. See Section 3 Boot Configurations.Note:Strapping pins are highlighted by Pin Name or configurations At Reset, instead of the pin functions.– USB_D+/- – by default, connected to the USB Serial/JTAG Controller. To function as GPIOs, thesepins need to be reconfigured.– JTAG interface – often used for debugging. See Table 2-4 QFN40 IO MUX Pin Functions or Table 2-5QFN32 IO MUX Pin Functions. To free these pins up, the pin functions USB_D+/- of the USBSerial/JTAG Controller can be used instead. See also Section 3.4 JTAG Signal Source Control.– UART0 interface – often used for debugging. See Table 2-4 QFN40 IO MUX Pin Functions or Table2-5 QFN32 IO MUX Pin Functions.– VDD_SPI – the power supply pin for off-package flash by default, and can only be used as a GPIO pinif the flash is powered by an external power supply.For more information about assigning pins, please see Section 2.3.5 Peripheral Pin Assignment and ESP32-C6Consolidated Pin Overview.Espressif Systems 24Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 2 Pins2.3.5 Peripheral Pin AssignmentTable 2-10 QFN40 Peripheral Pin Assignment and Table 2-11 QFN32 Peripheral Pin Assignment highlight whichpins can be assigned to each peripheral interface according to the following priorities:• Priority 1 (P1) : Fixed pins connected directly to peripheral signals via IO MUX or RTC IO MUX.If a peripheral interface does not have priority 1 pins, such as UART1, it can be assigned to any GPIO pinsfrom priority 2 to priority 4.• Any GPIO pins mapping to peripheral signals via GPIO Matrix, can be priority 2, 3, or 4:– Priority 2 (P2) : GPIO pins can be freely used without restrictions.– Priority 3 (P3) : GPIO pins should be used with caution, as they may conflict with the followingimportant functions described in Section 2.3.4 Restrictions for GPIOs and LP GPIOs:* GPIO4, GPIO5, GPIO8, GPIO9, GPIO15 : Strapping pins.* GPIO12, GPIO13 : USB Serial/JTAG interface.* GPIO4, GPIO5, GPIO6, GPIO7 : JTAG interface.* GPIO16, GPIO17 : UART0 interface.* GPIO27 : The VDD_SPI pin. The power supply pin for off-package flash by default, and can onlybe reconfigured as a GPIO pin if the flash is powered by an external power supply.– Priority 4 (P4) : GPIO pins already allocated or not recommended for use, as described in Section2.3.4 Restrictions for GPIOs and LP GPIOs:* GPIO24, GPIO25, GPIO26, GPIO28, GPIO29, GPIO30 : SPI0/1 interface recommended for theoff-package flash.If a peripheral interface does not have priority 2 to 4 pins, such as USB Serial/JTAG, it means it can beassigned only to priority 1 pins.Note:• For details about which peripheral signals are connected to IO MUX or LP IO MUX pins, please refer to Section2.3.1 IO MUX Pin Functions or Section 2-7 LP IO MUX Functions.• For details about which peripheral signals can be assigned to GPIO pins, please refer toESP32-C6 Technical Reference Manual > Chapter IO MUX and GPIO Matrix > Section Peripheral Signal List.Espressif Systems 25Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 2 PinsTable 2-10. QFN40 Peripheral Pin AssignmentPin No. Pin Name USB Serial/JTAG1JTAG SDIO Slave LP UART LP I2C ADC UART02SPI0/12SPI22UART1 I2C I2S PCNT TWAI LED PWM MCPWM RMT PARLIO1 ANT2 VDDA3P33 VDDA3P34 CHIP_PU5 VDDPST16 XTAL_32K_P LP_UART_DTRN (P1) ADC1_CH0 (P1) GPIO0 (P2) GPIO0 (P2) GPIO0 (P2) GPIO0 (P2) GPIO0 (P2) GPIO0 (P2) GPIO0 (P2) GPIO0 (P2) GPIO0 (P2) GPIO0 (P2) GPIO0 (P2) GPIO0 (P2)7 XTAL_32K_N LP_UART_DSRN (P1) ADC1_CH1 (P1) GPIO1 (P2) GPIO1 (P2) GPIO1 (P2) GPIO1 (P2) GPIO1 (P2) GPIO1 (P2) GPIO1 (P2) GPIO1 (P2) GPIO1 (P2) GPIO1 (P2) GPIO1 (P2) GPIO1 (P2)8 GPIO2 LP_UART_RTSN (P1) ADC1_CH2 (P1) GPIO2 (P2) GPIO2 (P2) FSPIQ (P1) GPIO2 (P2) GPIO2 (P2) GPIO2 (P2) GPIO2 (P2) GPIO2 (P2) GPIO2 (P2) GPIO2 (P2) GPIO2 (P2) GPIO2 (P2)9 GPIO3 LP_UART_CTSN (P1) ADC1_CH3 (P1) GPIO3 (P2) GPIO3 (P2) GPIO3 (P2) GPIO3 (P2) GPIO3 (P2) GPIO3 (P2) GPIO3 (P2) GPIO3 (P2) GPIO3 (P2) GPIO3 (P2) GPIO3 (P2) GPIO3 (P2)10 MTMS MTMS (P1) LP_UART_RXD (P1) ADC1_CH4 (P1) GPIO4 (P3) GPIO4 (P3) FSPIHD (P1) GPIO4 (P3) GPIO4 (P3) GPIO4 (P3) GPIO4 (P3) GPIO4 (P3) GPIO4 (P3) GPIO4 (P3) GPIO4 (P3) GPIO4 (P3)11 MTDI MTDI (P1) LP_UART_TXD (P1) ADC1_CH5 (P1) GPIO5 (P3) GPIO5 (P3) FSPIWP (P1) GPIO5 (P3) GPIO5 (P3) GPIO5 (P3) GPIO5 (P3) GPIO5 (P3) GPIO5 (P3) GPIO5 (P3) GPIO5 (P3) GPIO5 (P3)12 MTCK MTCK (P1) LP_I2C_SDA (P1) ADC1_CH6 (P1) GPIO6 (P3) GPIO6 (P3) FSPICLK (P1) GPIO6 (P3) GPIO6 (P3) GPIO6 (P3) GPIO6 (P3) GPIO6 (P3) GPIO6 (P3) GPIO6 (P3) GPIO6 (P3) GPIO6 (P3)13 MTDO MTDO (P1) LP_I2C_SCL (P1) GPIO7 (P3) GPIO7 (P3) FSPID (P1) GPIO7 (P3) GPIO7 (P3) GPIO7 (P3) GPIO7 (P3) GPIO7 (P3) GPIO7 (P3) GPIO7 (P3) GPIO7 (P3) GPIO7 (P3)14 GPIO8 GPIO8 (P3) GPIO8 (P3) GPIO8 (P3) GPIO8 (P3) GPIO8 (P3) GPIO8 (P3) GPIO8 (P3) GPIO8 (P3) GPIO8 (P3) GPIO8 (P3) GPIO8 (P3) GPIO8 (P3)15 GPIO9 GPIO9 (P3) GPIO9 (P3) GPIO9 (P3) GPIO9 (P3) GPIO9 (P3) GPIO9 (P3) GPIO9 (P3) GPIO9 (P3) GPIO9 (P3) GPIO9 (P3) GPIO9 (P3) GPIO9 (P3)16 GPIO10 GPIO10 (P2) GPIO10 (P2) GPIO10 (P2) GPIO10 (P2) GPIO10 (P2) GPIO10 (P2) GPIO10 (P2) GPIO10 (P2) GPIO10 (P2) GPIO10 (P2) GPIO10 (P2) GPIO10 (P2)17 GPIO11 GPIO11 (P2) GPIO11 (P2) GPIO11 (P2) GPIO11 (P2) GPIO11 (P2) GPIO11 (P2) GPIO11 (P2) GPIO11 (P2) GPIO11 (P2) GPIO11 (P2) GPIO11 (P2) GPIO11 (P2)18 GPIO12 USB_D- (P1) GPIO12 (P3) GPIO12 (P3) GPIO12 (P3) GPIO12 (P3) GPIO12 (P3) GPIO12 (P3) GPIO12 (P3) GPIO12 (P3) GPIO12 (P3) GPIO12 (P3) GPIO12 (P3) GPIO12 (P3)19 GPIO13 USB_D+ (P1) GPIO13 (P3) GPIO13 (P3) GPIO13 (P3) GPIO13 (P3) GPIO13 (P3) GPIO13 (P3) GPIO13 (P3) GPIO13 (P3) GPIO13 (P3) GPIO13 (P3) GPIO13 (P3) GPIO13 (P3)20 SPICS0 GPIO24 (P4) SPICS0 (P1) GPIO24 (P4) GPIO24 (P4) GPIO24 (P4) GPIO24 (P4) GPIO24 (P4) GPIO24 (P4) GPIO24 (P4) GPIO24 (P4) GPIO24 (P4) GPIO24 (P4)21 SPIQ GPIO25 (P4) SPIQ (P1) GPIO25 (P4) GPIO25 (P4) GPIO25 (P4) GPIO25 (P4) GPIO25 (P4) GPIO25 (P4) GPIO25 (P4) GPIO25 (P4) GPIO25 (P4) GPIO25 (P4)22 SPIWP GPIO26 (P4) SPIWP (P1) GPIO26 (P4) GPIO26 (P4) GPIO26 (P4) GPIO26 (P4) GPIO26 (P4) GPIO26 (P4) GPIO26 (P4) GPIO26 (P4) GPIO26 (P4) GPIO26 (P4)23 VDD_SPI GPIO27 (P3) GPIO27 (P3) GPIO27 (P3) GPIO27 (P3) GPIO27 (P3) GPIO27 (P3) GPIO27 (P3) GPIO27 (P3) GPIO27 (P3) GPIO27 (P3) GPIO27 (P3) GPIO27 (P3)24 SPIHD GPIO28 (P4) SPIHD (P1) GPIO28 (P4) GPIO28 (P4) GPIO28 (P4) GPIO28 (P4) GPIO28 (P4) GPIO28 (P4) GPIO28 (P4) GPIO28 (P4) GPIO28 (P4) GPIO28 (P4)25 SPICLK GPIO29 (P4) SPICLK (P1) GPIO29 (P4) GPIO29 (P4) GPIO29 (P4) GPIO29 (P4) GPIO29 (P4) GPIO29 (P4) GPIO29 (P4) GPIO29 (P4) GPIO29 (P4) GPIO29 (P4)26 SPID GPIO30 (P4) SPID (P1) GPIO30 (P4) GPIO30 (P4) GPIO30 (P4) GPIO30 (P4) GPIO30 (P4) GPIO30 (P4) GPIO30 (P4) GPIO30 (P4) GPIO30 (P4) GPIO30 (P4)27 GPIO15 GPIO15 (P3) GPIO15 (P3) GPIO15 (P3) GPIO15 (P3) GPIO15 (P3) GPIO15 (P3) GPIO15 (P3) GPIO15 (P3) GPIO15 (P3) GPIO15 (P3) GPIO15 (P3) GPIO15 (P3)28 VDDPST229 U0TXD U0TXD (P1) GPIO16 (P3) FSPICS0 (P1) GPIO16 (P3) GPIO16 (P3) GPIO16 (P3) GPIO16 (P3) GPIO16 (P3) GPIO16 (P3) GPIO16 (P3) GPIO16 (P3) GPIO16 (P3)30 U0RXD U0RXD (P1) GPIO17 (P3) FSPICS1 (P1) GPIO17 (P3) GPIO17 (P3) GPIO17 (P3) GPIO17 (P3) GPIO17 (P3) GPIO17 (P3) GPIO17 (P3) GPIO17 (P3) GPIO17 (P3)31 SDIO_CMD SDIO_CMD (P1) GPIO18 (P2) GPIO18 (P2) FSPICS2 (P1) GPIO18 (P2) GPIO18 (P2) GPIO18 (P2) GPIO18 (P2) GPIO18 (P2) GPIO18 (P2) GPIO18 (P2) GPIO18 (P2) GPIO18 (P2)32 SDIO_CLK SDIO_CLK (P1) GPIO19 (P2) GPIO19 (P2) FSPICS3 (P1) GPIO19 (P2) GPIO19 (P2) GPIO19 (P2) GPIO19 (P2) GPIO19 (P2) GPIO19 (P2) GPIO19 (P2) GPIO19 (P2) GPIO19 (P2)33 SDIO_DATA0 SDIO_DATA0 (P1) GPIO20 (P2) GPIO20 (P2) FSPICS4 (P1) GPIO20 (P2) GPIO20 (P2) GPIO20 (P2) GPIO20 (P2) GPIO20 (P2) GPIO20 (P2) GPIO20 (P2) GPIO20 (P2) GPIO20 (P2)34 SDIO_DATA1 SDIO_DATA1 (P1) GPIO21 (P2) GPIO21 (P2) FSPICS5 (P1) GPIO21 (P2) GPIO21 (P2) GPIO21 (P2) GPIO21 (P2) GPIO21 (P2) GPIO21 (P2) GPIO21 (P2) GPIO21 (P2) GPIO21 (P2)35 SDIO_DATA2 SDIO_DATA2 (P1) GPIO22 (P2) GPIO22 (P2) GPIO22 (P2) GPIO22 (P2) GPIO22 (P2) GPIO22 (P2) GPIO22 (P2) GPIO22 (P2) GPIO22 (P2) GPIO22 (P2) GPIO22 (P2) GPIO22 (P2)36 SDIO_DATA3 SDIO_DATA3 (P1) GPIO23 (P2) GPIO23 (P2) GPIO23 (P2) GPIO23 (P2) GPIO23 (P2) GPIO23 (P2) GPIO23 (P2) GPIO23 (P2) GPIO23 (P2) GPIO23 (P2) GPIO23 (P2) GPIO23 (P2)37 VDDA138 XTAL_N39 XTAL_P40 VDDA241 GND1For USB Serial/JTAG, the USB_D- and USB_D+ can be swapped by configuring the USB_SERIAL_JTAG_EXCHG_PINS bit according to ESP32-C6 Technical Reference Manual.2Signals of UART0, SPI0/1, and SPI2 interfaces can be mapped to any GPIO pins through the GPIO Matrix, regardless of whether they are directly routed to fixed pins via IO MUX.Espressif Systems 26Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 2 PinsTable 2-11. QFN32 Peripheral Pin AssignmentPin No. Pin Name USB Serial/JTAG1JTAG SDIO Slave LP UART LP I2C ADC UART02SPI22UART1 I2C I2S PCNT TWAI LED PWM MCPWM RMT PARLIO1 ANT2 VDDA3P33 VDDA3P34 CHIP_PU5 VDDPST16 XTAL_32K_P LP_UART_DTRN (P1) ADC1_CH0 (P1) GPIO0 (P2) GPIO0 (P2) GPIO0 (P2) GPIO0 (P2) GPIO0 (P2) GPIO0 (P2) GPIO0 (P2) GPIO0 (P2) GPIO0 (P2) GPIO0 (P2) GPIO0 (P2)7 XTAL_32K_N LP_UART_DSRN (P1) ADC1_CH1 (P1) GPIO1 (P2) GPIO1 (P2) GPIO1 (P2) GPIO1 (P2) GPIO1 (P2) GPIO1 (P2) GPIO1 (P2) GPIO1 (P2) GPIO1 (P2) GPIO1 (P2) GPIO1 (P2)8 GPIO2 LP_UART_RTSN (P1) ADC1_CH2 (P1) GPIO2 (P2) FSPIQ (P1) GPIO2 (P2) GPIO2 (P2) GPIO2 (P2) GPIO2 (P2) GPIO2 (P2) GPIO2 (P2) GPIO2 (P2) GPIO2 (P2) GPIO2 (P2)9 GPIO3 LP_UART_CTSN (P1) ADC1_CH3 (P1) GPIO3 (P2) GPIO1 (P2) GPIO3 (P2) GPIO3 (P2) GPIO3 (P2) GPIO3 (P2) GPIO3 (P2) GPIO3 (P2) GPIO3 (P2) GPIO3 (P2) GPIO3 (P2)10 MTMS MTMS (P1) LP_UART_RXD (P1) ADC1_CH4 (P1) GPIO4 (P3) FSPIHD (P1) GPIO4 (P3) GPIO4 (P3) GPIO4 (P3) GPIO4 (P3) GPIO4 (P3) GPIO4 (P3) GPIO4 (P3) GPIO4 (P3) GPIO4 (P3)11 MTDI MTDI (P1) LP_UART_TXD (P1) ADC1_CH5 (P1) GPIO5 (P3) FSPIWP (P1) GPIO5 (P3) GPIO5 (P3) GPIO5 (P3) GPIO5 (P3) GPIO5 (P3) GPIO5 (P3) GPIO5 (P3) GPIO5 (P3) GPIO5 (P3)12 MTCK MTCK (P1) LP_I2C_SDA (P1) ADC1_CH6 (P1) GPIO6 (P3) FSPICLK (P1) GPIO6 (P3) GPIO6 (P3) GPIO6 (P3) GPIO6 (P3) GPIO6 (P3) GPIO6 (P3) GPIO6 (P3) GPIO6 (P3) GPIO6 (P3)13 MTDO MTDO (P1) LP_I2C_SCL (P1) GPIO7 (P3) FSPID (P1) GPIO7 (P3) GPIO7 (P3) GPIO7 (P3) GPIO7 (P3) GPIO7 (P3) GPIO7 (P3) GPIO7 (P3) GPIO7 (P3) GPIO7 (P3)14 GPIO8 GPIO8 (P3) GPIO8 (P3) GPIO8 (P3) GPIO8 (P3) GPIO8 (P3) GPIO8 (P3) GPIO8 (P3) GPIO8 (P3) GPIO8 (P3) GPIO8 (P3) GPIO8 (P3)15 GPIO9 GPIO9 (P3) GPIO9 (P3) GPIO9 (P3) GPIO9 (P3) GPIO9 (P3) GPIO9 (P3) GPIO9 (P3) GPIO9 (P3) GPIO9 (P3) GPIO9 (P3) GPIO9 (P3)16 GPIO12 USB_D- (P1) GPIO12 (P3) GPIO12 (P3) GPIO12 (P3) GPIO12 (P3) GPIO12 (P3) GPIO12 (P3) GPIO12 (P3) GPIO12 (P3) GPIO12 (P3) GPIO12 (P3) GPIO12 (P3)17 GPIO13 USB_D+ (P1) GPIO13 (P3) GPIO13 (P3) GPIO13 (P3) GPIO13 (P3) GPIO13 (P3) GPIO13 (P3) GPIO13 (P3) GPIO13 (P3) GPIO13 (P3) GPIO13 (P3) GPIO13 (P3)18 GPIO14 GPIO14 (P2) GPIO14 (P2) GPIO14 (P2) GPIO14 (P2) GPIO14 (P2) GPIO14 (P2) GPIO14 (P2) GPIO14 (P2) GPIO14 (P2) GPIO14 (P2) GPIO14 (P2)19 GPIO15 GPIO15 (P3) GPIO15 (P3) GPIO15 (P3) GPIO15 (P3) GPIO15 (P3) GPIO15 (P3) GPIO15 (P3) GPIO15 (P3) GPIO15 (P3) GPIO15 (P3) GPIO15 (P3)20 VDDPST221 U0TXD U0TXD (P1) FSPICS0 (P1) GPIO16 (P3) GPIO16 (P3) GPIO16 (P3) GPIO16 (P3) GPIO16 (P3) GPIO16 (P3) GPIO16 (P3) GPIO16 (P3) GPIO16 (P3)22 U0RXD U0RXD (P1) FSPICS1 (P1) GPIO17 (P3) GPIO17 (P3) GPIO17 (P3) GPIO17 (P3) GPIO17 (P3) GPIO17 (P3) GPIO17 (P3) GPIO17 (P3) GPIO17 (P3)23 SDIO_CMD SDIO_CMD (P1) GPIO18 (P2) FSPICS2 (P1) GPIO18 (P2) GPIO18 (P2) GPIO18 (P2) GPIO18 (P2) GPIO18 (P2) GPIO18 (P2) GPIO18 (P2) GPIO18 (P2) GPIO18 (P2)24 SDIO_CLK SDIO_CLK (P1) GPIO19 (P2) FSPICS3 (P1) GPIO19 (P2) GPIO19 (P2) GPIO19 (P2) GPIO19 (P2) GPIO19 (P2) GPIO19 (P2) GPIO19 (P2) GPIO19 (P2) GPIO19 (P2)25 SDIO_DATA0 SDIO_DATA0 (P1) GPIO20 (P2) FSPICS4 (P1) GPIO20 (P2) GPIO20 (P2) GPIO20 (P2) GPIO20 (P2) GPIO20 (P2) GPIO20 (P2) GPIO20 (P2) GPIO20 (P2) GPIO20 (P2)26 SDIO_DATA1 SDIO_DATA1 (P1) GPIO21 (P2) FSPICS5 (P1) GPIO21 (P2) GPIO21 (P2) GPIO21 (P2) GPIO21 (P2) GPIO21 (P2) GPIO21 (P2) GPIO21 (P2) GPIO21 (P2) GPIO21 (P2)27 SDIO_DATA2 SDIO_DATA2 (P1) GPIO22 (P2) GPIO22 (P2) GPIO22 (P2) GPIO22 (P2) GPIO22 (P2) GPIO22 (P2) GPIO22 (P2) GPIO22 (P2) GPIO22 (P2) GPIO22 (P2) GPIO22 (P2)28 SDIO_DATA3 SDIO_DATA3 (P1) GPIO23 (P2) GPIO23 (P2) GPIO23 (P2) GPIO23 (P2) GPIO23 (P2) GPIO23 (P2) GPIO23 (P2) GPIO23 (P2) GPIO23 (P2) GPIO23 (P2) GPIO23 (P2)29 VDDA130 XTAL_N31 XTAL_P32 VDDA233 GND1For USB Serial/JTAG, the USB_D- and USB_D+ can be swapped by configuring the USB_SERIAL_JTAG_EXCHG_PINS bit according to ESP32-C6 Technical Reference Manual.2Signals of UART0 and SPI2 interfaces can be mapped to any GPIO pins through the GPIO Matrix, regardless of whether they are directly routed to fixed pins via IO MUX.3SPI0/1 interface connected to the in-package flash is not available on QFN32 chips.Espressif Systems 27Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 2 Pins2.4 Analog PinsTable 2-12. Analog PinsQFN40 QFN32 Pin Pin PinPin No. Pin No. Name Type Function1 1 ANT I/O RF input and output4 4 CHIP_PU —High: on, enables the chip (powered up).Low: off, disables the chip (powered down).Note: Do not leave the CHIP_PU pin floating.38 30 XTAL_N — External clock input/output connected to chip’s crystal oroscillator. P/N means differential clock positive/negative.39 31 XTAL_P —Espressif Systems 28Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 2 Pins2.5 Power Supply2.5.1 Power PinsThe chip is powered via the power pins described in Table 2-13 Power Pins.Table 2-13. Power PinsQFN40 QFN32 Pin Power Supply1,2Pin No. Pin No. Name Direction Power Domain / Other IO Pins2 2 VDDA3P3 Input Analog power domain3 3 VDDA3P3 Input Analog power domain5 5 VDDPST1 Input LP digital and part of analog pin power domains LP IO323—VDD_SPIInput In-package flash (backup power line)Output In-package flash and off-package flash28 20 VDDPST2 Input HP digital power domain HP IO37 29 VDDA1 Input Analog power domain40 32 VDDA2 Input Analog power domain41 33 GND — External ground connection1See in conjunction with Section 2.5.2 Power Scheme.2For recommended and maximum voltage and current, see Section 5.1 Absolute Maximum Ratings and Section5.2 Recommended Operating Conditions.3LP IO pins are those powered by VDDPST1 and so on, as shown in Figure 2-3 ESP32-C6 Power Scheme. Seealso Table 2-1 QFN40 Pin Overview or Table 2-2 QFN32 Pin Overview > Column Pin Providing Power.2.5.2 Power SchemeThe power scheme is shown in Figure 2-3 ESP32-C6 Power Scheme.The components on the chip are powered via voltage regulators.Table 2-14. Voltage RegulatorsVoltage Regulator Output Power SupplyHP 1.1 V HP power domainLP 1.1 V LP power domainEspressif Systems 29Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 2 PinsLPVoltageRegulatorHPVoltageRegulatorLP SystemHPSystemVDD_PST1 VDD_PST2VDDA1 VDDA2AnalogVDD_SPILP IOHP IORSPIFigure 2-3. ESP32-C6 Power Scheme2.5.3 Chip Power-up and ResetOnce the power is supplied to the chip, its power rails need a short time to stabilize. After that, CHIP_PU – thepin used for power-up and reset – is pulled high to activate the chip. For information on CHIP_PU as well aspower-up and reset timing, see Figure 2-4 and Table 2-15.VIL_nRSTtST BLtRST2.8 VVDDA3P3,VDDPST1,VDDPST2,VDDA1,VDDA2CHIP_PUFigure 2-4. Visualization of Timing Parameters for Power-up and ResetEspressif Systems 30Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 2 PinsTable 2-15. Description of Timing Parameters for Power-up and ResetParameter Description Min (µs)tST BLTime reserved for the power rails of VDDA3P3, VDDPST1, VD-DPST2, VDDA1 and VDDA2 to stabilize before the CHIP_PU pinis pulled high to activate the chip50tRSTTime reserved for CHIP_PU to stay below VIL_nRSTto reset thechip (see Table 5-4)50Espressif Systems 31Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 2 Pins2.6 Pin Mapping Between Chip and FlashTable 2-16 lists the pin mapping between the chip and off-package flash for all SPI modes.For chip variants with in-package flash (namely variants in QFN32 package, see Table 1-1 ESP32-C6 SeriesComparison), the pins allocated for communication with in-package flash are not routed out, but you can takeTable 2-16 as a reference.For more information on SPI controllers, see also Section 4.2.1.2 SPI Controller.Notice:Do not use the pins connected to flash for any other purposes.Table 2-16. Pin Mapping Between QFN40 Chip and FlashQFN40 Pin Name Single SPI Dual SPI Quad SPI / QPIPin No. Flash Flash Flash25 SPICLK CLK CLK CLK20 SPICS0 CS# CS# CS#26 SPID MOSI SIO0 SIO021 SPIQ MISO SIO1 SIO122 SPIWP WP# SIO224 SPIHD HOLD# SIO31SIO: Serial Data Input and OutputEspressif Systems 32Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 3 Boot Configurations3 Boot ConfigurationsThe chip allows for configuring the following boot parameters through strapping pins and eFuse parameters atpower-up or a hardware reset, without microcontroller interaction.• Chip boot mode– Strapping pin: GPIO8 and GPIO9• SDIO Sampling and Driving Clock Edge– Strapping pin: MTMS and MTDI• ROM message printing– Strapping pin: GPIO8– eFuse parameter: EFUSE_UART_PRINT_CONTROL andEFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT• JTAG signal source– Strapping pin: GPIO15– eFuse parameter: EFUSE_DIS_PAD_JTAG, EFUSE_DIS_USB_JTAG, andEFUSE_JTAG_SEL_ENABLEThe default values of all the above eFuse parameters are 0, which means that they are not burnt. Given thateFuse is one-time programmable, once programmed to 1, it can never be reverted to 0. For how to programeFuse parameters, please refer to ESP32-C6 Technical Reference Manual > Chapter eFuse Controller.The default values of the strapping pins, namely the logic levels, are determined by pins’ internal weakpull-up/pull-down resistors at reset if the pins are not connected to any circuit, or connected to an externalhigh-impedance circuit.Table 3-1. Default Configuration of Strapping PinsStrapping Pin Default Configuration Bit ValueMTMS Floating –MTDI Floating –GPIO8 Floating –GPIO9 Weak pull-up 1GPIO15 Floating –To change the bit values, the strapping pins should be connected to external pull-down/pull-up resistances. If theESP32-C6 is used as a device by a host MCU, the strapping pin voltage levels can also be controlled by the hostMCU.All strapping pins have latches. At Chip Reset, the latches sample the bit values of their respective strapping pinsand store them until the chip is powered down or shut down. The states of latches cannot be changed in anyother way. It makes the strapping pin values available during the entire chip operation, and the pins are freed upto be used as regular IO pins after reset. For details on Chip Reset, see ESP32-C6 Technical Reference Manual >Chapter Reset and Clock.Espressif Systems 33Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 3 Boot ConfigurationsThe timing of signals connected to the strapping pins should adhere to the setup time and hold time specificationsin Table 3-2 and Figure 3-1.Table 3-2. Description of Timing Parameters for the Strapping PinsParameter Description Min (ms)tSUSetup time is the time reserved for the power rails to stabilize beforethe CHIP_PU pin is pulled high to activate the chip.0tHHold time is the time reserved for the chip to read the strapping pinvalues after CHIP_PU is already high and before these pins startoperating as regular IO pins.3Strapping pinVIH_nRSTVIHtSUtHCHIP_PUFigure 3-1. Visualization of Timing Parameters for the Strapping Pins3.1 Chip Boot Mode ControlGPIO8 and GPIO9 control the boot mode after the reset is released. See Table 3-3 Chip Boot ModeControl.Table 3-3. Chip Boot Mode ControlBoot Mode GPIO8 GPIO9SPI boot mode Any value 1Joint download boot mode21 01Bold marks the default value and configuration.2Joint Download Boot mode supports the followingdownload methods:• USB-Serial-JTAG Download Boot• UART Download Boot• SDIO Download BootEspressif Systems 34Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 3 Boot Configurations3.2 SDIO Sampling and Driving Clock Edge ControlThe strapping pin MTMS and MTDI can be used to decide on which clock edge to sample signals and driveoutput lines. See Table 3-4 SDIO Input Sampling Edge/Output Driving Edge Control.Table 3-4. SDIO Input Sampling Edge/Output Driving Edge ControlEdge behavior MTMS MTDIFalling edge sampling, falling edge output 0 0Falling edge sampling, rising edge output 0 1Rising edge sampling, falling edge output 1 0Rising edge sampling, rising edge output 1 11MTMS and MTDI are floating by default, so above are notdefault configurations.3.3 ROM Messages Printing ControlDuring the boot process, ROM message printing is enabled if LP_AON_STORE4_REG[0] is 0 (default), anddisabled if LP_AON_STORE4_REG[0] is 1. When ROM message printing is enabled, the messages can beprinted to:• (Default) UART0 and USB Serial/JTAG controller• USB Serial/JTAG controller• UART0EFUSE_UART_PRINT_CONTROL and GPIO8 control ROM messages printing to UART0 as shown in Table 3-5UART0 ROM Message Printing Control.Table 3-5. UART0 ROM Message Printing ControlUART0 ROM Code Printing EFUSE_UART_PRINT_CONTROL GPIO8Enabled0 Ignored1 02 1Disabled1 12 03 Ignored1Bold marks the default value and configuration.EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT controls the printing to USB Serial/JTAG controller as shown inTable 3-6 USB Serial/JTAG ROM Message Printing Control.Espressif Systems 35Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 3 Boot ConfigurationsTable 3-6. USB Serial/JTAG ROM Message Printing ControlUSB Serial/JTAGROM CodePrintingEFUSE_DIS_USB_SERIAL_JTAG2EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINTEnabled 0 0Disabled0 11 Ignored1Bold marks the default value and configuration.2EFUSE_DIS_USB_SERIAL_JTAG controls whether to disable USB Serial/JTAG.3.4 JTAG Signal Source ControlThe strapping pin GPIO15 can be used to control the source of JTAG signals during the early boot process. Thispin does not have any internal pull resistors and the strapping value must be controlled by the external circuit thatcannot be in a high impedance state.As Table 3-7 JTAG Signal Source Control shows, GPIO15 is used in combination with EFUSE_DIS_PAD_JTAG,EFUSE_DIS_USB_JTAG and EFUSE_JTAG_SEL_ENABLE.Table 3-7. JTAG Signal Source ControlJTAG Signal Source EFUSE_DIS_PAD_JTAG EFUSE_DIS_USB_JTAG EFUSE_JTAG_SEL_ENABLE GPIO15USB Serial/JTAG Controller0 0 0 Ignored0 0 1 11 0 Ignored IgnoredJTAG pins20 0 1 00 1 Ignored IgnoredJTAG is disabled 1 1 Ignored Ignored1Bold marks the default value and configuration.2JTAG pins refer to MTDI, MTCK, MTMS, and MTDO.Espressif Systems 36Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 4 Functional Description4 Functional Description4.1 SystemThis section describes the core of the chip’s operation, covering its microprocessor, memory organization,system components, and security features.4.1.1 Microprocessor and MasterThis subsection describes the core processing units within the chip and their capabilities.4.1.1.1 High-Performance CPUThe ESP-RISC-V CPU (HP CPU) is a high-performance 32-bit core based on the RISC-V instruction setarchitecture (ISA) comprising base integer (I), multiplication/division (M), atomic (A) and compressed (C) standardextensions.Feature List• Four-stage pipeline that supports an operating clock frequency up to 160 MHz• RV32IMAC ISA (instruction set architecture)• Compatible with RISC-V ISA Manual Volume I: Unprivileged ISA Version 2.2 and RISC-V ISA Manual,Volume II: Privileged Architecture, Version 1.10• Zero wait cycle access to on-chip SRAM and Cache for program and data access over IRAM/DRAMinterface• Branch target buffer (BTB) with static branch prediction• User (U) mode support along with interrupt delegation• Interrupt controller with up to 28 external vectored interrupts for both M and U modes with 16programmable priority and threshold levels• Core local interrupts (CLINT) dedicated for each privilege mode• Debug module (DM) compliant with the specification RISC-V External Debug Support Version 0.13 withexternal debugger support over an industry-standard JTAG/USB port• Support for instruction trace, see Section 4.1.1.2 RISC-V Trace Encoder• Hardware trigger compliant to the specification RISC-V External Debug Support Version 0.13 with up to 4breakpoints/watchpoints• Physical memory protection (PMP) and attributes (PMA) for up to 16 configurable regionsFor details, see ESP32-C6 Technical Reference Manual > Chapter High-Performance CPU.4.1.1.2 RISC-V Trace EncoderThe RISC-V Trace Encoder in the ESP32-C6 chip provides a way to capture detailed trace information from theHigh-Performance CPU’s execution, enabling deeper analysis and optimization of the system. It connects to theEspressif Systems 37Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 4 Functional DescriptionHP CPU’s instruction trace interface and compresses the information into smaller packets, which are then storedin internal SRAM.Feature List• Compatible with RISC-V Processor Trace Version 1.0• Synchronization packets sent every few clock cycles or packets• Zero bytes as anchor tags to identify boundaries between data packets• Configurable memory writing mode: loop mode or non-loop mode• Trace lost status to indicate packet loss• Automatic restart after packet lossFor details, see ESP32-C6 Technical Reference Manual > Chapter RISC-V Trace Encoder (TRACE).4.1.1.3 Low-Power CPUThe ESP32-C6 Low-Power CPU (LP CPU) is a 32-bit processor based on the RISC-V ISA comprising integer (I),multiplication/division (M), atomic (A), and compressed (C) standard extensions. It is designed for ultra-low powerconsumption and is capable of staying powered on during Deep-sleep mode when the HP CPU is powereddown.Feature List• Two-stage pipeline that supports a clock frequency of up to 20 MHz• RV32IMAC ISA (instruction set architecture)• 19 vector interrupts• Debug module compliant with RISC-V External Debug Support Version 0.13 with external debuggersupport over an industry-standard JTAG/USB port• Hardware trigger compliant with RISC-V External Debug Support Version 0.13 with up to 2breakpoints/watchpoints• 32-bit AHB system bus for peripheral and memory access• Core performance metric events• Able to wake up the HP CPU and send an interrupt to it• Access to HP memory and LP memory• Access to the entire peripheral address spaceFor details, see ESP32-C6 Technical Reference Manual > Chapter Low-Power CPU.4.1.1.4 GDMA ControllerThe GDMA Controller is a General Direct Memory Access (GDMA) controller that allows peripheral-to-memory,memory-to-peripheral, and memory-to-memory data transfer with the CPU’s intervention. The GDMA has sixEspressif Systems 38Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 4 Functional Descriptionindependent channels, three transmit and three receive. These channels are shared by peripherals with theGDMA feature, such as SPI2, UHCI (UART0/UART1), I2S, AES, SHA, ADC, and PARLIO.Feature List• Programmable length of data to be transferred in bytes• Linked list of descriptors for efficient data transfer management• INCR burst transfer when accessing internal RAM for improved performance• Access to an address space of up to 384 KB in internal RAM• Software-configurable selection of peripheral requesting service• Fixed-priority and round-robin channel arbitration schemes for managing bandwidth• Support for Event Task MatrixFor details, see ESP32-C6 Technical Reference Manual > Chapter GDMA Controller (DMA).4.1.2 Memory OrganizationThis subsection describes the memory arrangement to explain how data is stored, accessed, and managed forefficient operation.Figure 4-1 illustrates the address mapping structure of ESP32-C6.Figure 4-1. Address Mapping StructureEspressif Systems 39Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 4 Functional Description4.1.2.1 Internal MemoryThe internal memory of ESP32-C6 refers to the memory integrated on the chip die or in the chip package,including ROM, SRAM, eFuse, and flash.Feature List• 320 KB of ROM for booting and core functions• 512 KB of high-performance SRAM (HP SRAM) for data and instructions• 16 KB of low-power SRAM (LP SRAM) that can be accessed by HP CPU or LP CPU. It can retain data inDeep-sleep mode• 4096-bit eFuse memory, with 1792 bits available for users. See also Section 4.1.2.3 eFuse Controller• In-package flash– See flash size in Chapter 1 ESP32-C6 Series Comparison– For specifications, refer to Section 5.7 Memory Specifications.For details, see ESP32-C6 Technical Reference Manual > Chapter System and Memory.4.1.2.2 External MemoryESP32-C6 allows connection to memories outside the chip’s package via the SPI, Dual SPI, Quad SPI, and QPIinterfaces.Feature List• Support connection to off-package flash of 16 MB at most– Support hardware encryption/decryption based on XTS-AES– Up to 16 MB of CPU instruction memory space can map into flash as individual blocks of 64 KB.32-bit fetch is supported– Up to 16 MB of CPU data memory space can map into flash as individual blocks of 64 KB. 8-bit,16-bit and 32-bit reads are supported• External memory accessed via a 32 KB read-only cache– Four-way set associative– 32-byte cache block– Critical word first and early restartFor details, see ESP32-C6 Technical Reference Manual > Chapter System and Memory.4.1.2.3 eFuse ControllerThe eFuse memory is a one-time programmable memory that stores parameters and user data, and the eFusecontroller of ESP32-C6 is used to program and read this eFuse memory.Espressif Systems 40Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 4 Functional DescriptionFeature List• Configure write protection for some blocks• Configure read protection for some blocks• Various hardware encoding schemes against data corruptionFor details, see ESP32-C6 Technical Reference Manual > ChaptereFuse Controller.4.1.3 System ComponentsThis subsection describes the essential components that contribute to the overall functionality and control of thesystem.4.1.3.1 IO MUX and GPIO MatrixThe IO MUX and GPIO Matrix in the ESP32-C6 chip provide flexible routing of peripheral input and output signalsto the GPIO pins. These peripherals enhance the functionality and performance of the chip by allowing theconfiguration of I/O, support for multiplexing, and signal synchronization for peripheral inputs.Feature List• 30 or 22 GPIO pins for general-purpose I/O or connection to internal peripheral signals• GPIO matrix:– Routing 85 peripheral input and 93 output signals to any GPIO pin– Signal synchronization for peripheral inputs based on IO MUX operating clock– GPIO Filter hardware for input signal filtering– Glitch Filter hardware for second time filtering on input signal– Sigma delta modulated (SDM) output• IO MUX for directly connecting certain digital signals (SPI, JTAG, UART) to pins• LP IO MUX for controlling eight LP GPIO pins (GPIO0 ~ GPIO7) used by peripherals in the LP system• Support for Event Task MatrixFor details, see ESP32-C6 Technical Reference Manual > Chapter IO MUX and GPIO Matrix.4.1.3.2 ResetThe ESP32-C6 chip provides four types of reset that occur at different levels, namely CPU Reset, Core Reset,System Reset, and Chip Reset. Except for Chip Reset, all reset types preserve the data stored in internalmemory.Feature List• Four types of reset:– CPU Reset – Resets the CPU coreEspressif Systems 41Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 4 Functional Description– Core Reset – Resets the whole digital system except for the LP system– System reset – Resets the whole digital system, including the LP system– Chip reset – Resets the whole chip• Reset trigger:– Directly by hardware– Via software by configuring the corresponding registers of the CPU• Support for retrieving reset causeFor details, see ESP32-C6 Technical Reference Manual > Chapter Reset and Clock.4.1.3.3 ClockThe ESP32-C6 chip has clocks sourced from oscillators, RC circuits, and PLL circuits, which are then processedby dividers or selectors. The clocks can be classified into high speed clocks for devices working at higherfrequencies and slow speed clocks for low-power systems and some peripherals.Feature List• High speed clocks for HP system– 40 MHz external crystal clockNote:The chip cannot operate without the external crystal clock.– 480 MHz internal PLL clock• Slow speed clocks for LP system and some peripherals working in low-power mode– 32 kHz external crystal clock– Internal fast RC oscillator with adjustable frequency (17.5 MHz by default)– 136 kHz Internal slow RC oscillator– External slow clock input through XTAL_32K_P (32 kHz by default)For details, see ESP32-C6 Technical Reference Manual > Chapter Reset and Clock.4.1.3.4 Interrupt MatrixThe Interrupt Matrix in the ESP32-C6 chip routes interrupt requests generated by various peripherals to CPUinterrupts.Feature List• 77 peripheral interrupt sources accepted as input• 31 CPU peripheral interrupts generated to CPU as output• Current interrupt status query of peripheral interrupt sourcesEspressif Systems 42Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 4 Functional Description• Multiple interrupt sources mapping to a single CPU interrupt (i.e., shared interrupts)For details, see ESP32-C6 Technical Reference Manual > Chapter Interrupt Matrix.4.1.3.5 Event Task MatrixThe Event Task Matrix (ETM) allows events from any specified peripheral to be mapped to tasks of any specifiedperipheral, enabling peripherals to execute specified tasks without CPU intervention. Peripherals supporting ETMinclude GPIO, LED PWM, general-purpose timers, RTC Timer, system timer, MCPWM, temperature sensor, ADC,I2S, LP CPU, GDMA, and PMU.Feature List• 50 channels that can be enabled and configured independently• Receive 124 events from multiple peripherals• Generate 130 tasks for multiple peripheralsFor details, see ESP32-C6 Technical Reference Manual > Chapter Event Task Matrix.4.1.3.6 System TimerThe System Timer (SYSTIMER) in the ESP32-C6 chip is a 52-bit timer that can be used to generate tickinterrupts for the operating system or as a general timer to generate periodic or one-time interrupts.Feature List• Two 52-bit counters and three 52-bit comparators• 52-bit alarm values and 26-bit alarm periods• Two modes to generate alarms: target mode and period mode• Three comparators generating three independent interrupts based on configured alarm value or alarmperiod• Ability to load back sleep time recorded by RTC timer via software after Deep-sleep or Light-sleep• Counters can be stalled if the CPU is stalled or in OCD mode• Real-time alarm eventsFor details, see ESP32-C6 Technical Reference Manual > Chapter System Timer.4.1.3.7 Power Management UnitThe ESP32-C6 has an advanced Power Management Unit (PMU). It can be flexibly configured to power updifferent power domains of the chip to achieve the best balance between chip performance, power consumption,and wakeup latency.The integrated LP CPU allow the ESP32-C6 to operate in Deep-sleep mode with most of the power domainsturned off, thus achieving extremely low-power consumption.Configuring the PMU is a complex procedure. To simplify power management for typical scenarios, there are thefollowing predefined power modes that power up different combinations of power domains:Espressif Systems 43Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 4 Functional Description• Active mode – The HP CPU, RF circuits, and all peripherals are on. The chip can process data, receive,transmit, and listen.• Modem-sleep mode – The HP CPU is on, but the clock frequency can be reduced. The wirelessconnections can be configured to remain active as RF circuits are periodically switched on when required.• Light-sleep mode – The HP CPU stops running, and can be optionally powered on. The LP peripherals,as well as the LP CPU can be woken up periodically by the timer. The chip can be woken up via all wakeup mechanisms: MAC, SDIO host, RTC timer, or external interrupts. Wireless connections can remainactive. Some groups of digital peripherals can be optionally powered off.• Deep-sleep mode – Only the LP system is powered on. Wireless connection data is stored in LP memory.For modules powered on in each power mode, see Figure ESP32-C6 Functional Block Diagram.For power consumption in different power modes, see Section 5.6 Current Consumption Characteristics.For details, see ESP32-C6 Technical Reference Manual > Chapter Low-Power Management.4.1.3.8 Timer GroupThe Timer Group (TIMG) in the ESP32-C6 chip can be used to precisely time an interval, trigger an interrupt aftera particular interval (periodically and aperiodically), or act as a hardware clock. ESP32-C6 has two timer groups,each consisting of one general-purpose timer and one Main System Watchdog Timer.Feature List• 16-bit prescaler• 54-bit auto-reload-capable up-down counter• Able to read real-time value of the time-base counter• Halt, resume, and disable the time-base counter• Programmable alarm generation• Timer value reload (auto-reload at an alarm or a software-controlled instant reload)• RTC slow clock frequency calculation• Real-time alarm events• Level interrupt generation• Support for several ETM tasks and eventsFor details, see ESP32-C6 Technical Reference Manual > Chapter Timer Group (TIMG).4.1.3.9 Watchdog TimersThe Watchdog Timers (WDT) in ESP32-C6 are used to detect and recover from malfunctions. The chip containsthree digital watchdog timers: one in each of the two timer groups (MWDT) and one in the RTC Module (RWDT).Additionally, there is one analog watchdog timer called the Super watchdog (SWD) that helps prevent the systemfrom operating in a sub-optimal state.Espressif Systems 44Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 4 Functional DescriptionFeature List• Digital watchdog timers:– Four stages, each with a separately programmable timeout value and timeout action– Timeout actions: Interrupt, CPU reset, core reset, system reset (RWDT only)– Flash boot protection under SPI Boot mode at stage 0– Write protection that makes WDT register read only unless unlocked– 32-bit timeout counter• Analog watchdog timer：– Timeout period slightly less than one second– Timeout actions: Interrupt, system resetFor details, see ESP32-C6 Technical Reference Manual > Chapter Watchdog Timers.4.1.3.10 Permission ControlThe Permission Control module in ESP32-C6 is responsible for managing access permissions to memory andperipheral registers. It consists of two parts: PMP (Physical Memory Protection) and APM (Access PermissionManagement).Feature List• Access permission management for ROM, HP memory, HP peripheral, LP memory, and LP peripheraladdress spaces• APM supports each master (such as DMA) to select one of the four security modes• Access permission configuration for up to 16 address ranges• Interrupt function and exception information recordFor details, see ESP32-C6 Technical Reference Manual > Chapter Permission Control (PMS).4.1.3.11 System RegistersThe System Registers in the ESP32-C6 chip are used to configure various auxiliary chip features.Feature List• Control External memory encryption and decryption• Control HP core/LP core debugging• Control Bus timeout protectionFor details, see ESP32-C6 Technical Reference Manual > Chapter System Registers (HP_SYSREG).Espressif Systems 45Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 4 Functional Description4.1.3.12 Debug AssistantThe Debug Assistant provides a set of functions to help locate bugs and issues during software debugging. Itoffers various monitoring capabilities and logging features to assist in identifying and resolving software errorsefficiently.Feature List• Read/write monitoring: Monitor whether the HP CPU bus reads from or writes to a specified memoryaddress space• Stack pointer (SP) monitoring: Prevent stack overflow or erroneous push/pop operations violation willtrigger an interrupt.• Program counter (PC) logging: Record PC value. The developer can get the last PC value at the mostrecent HP CPU reset• Bus access logging: Record information about bus access when the HP CPU, LP CPU, or DMA writes aspecified valueFor details, see ESP32-C6 Technical Reference Manual > Chapter Debug Assistant (ASSIST_DEBUG).4.1.4 Cryptography and Security ComponentThis subsection describes the security features incorporated into the chip, which safeguard data andoperations.4.1.4.1 AES AcceleratorESP32-C6 integrates an Advanced Encryption Standard (AES) accelerator, which is a hardware device thatspeeds up computation using AES algorithm significantly, compared to AES algorithms implemented solely insoftware. The AES accelerator integrated in ESP32-C6 has two working modes, which are Typical AES andDMA-AES.Feature List• Typical AES working mode– AES-128/AES-256 encryption and decryption• DMA-AES working mode– AES-128/AES-256 encryption and decryption– Block cipher mode* ECB (Electronic Codebook)* CBC (Cipher Block Chaining)* OFB (Output Feedback)* CTR (Counter)* CFB8 (8-bit Cipher Feedback)Espressif Systems 46Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 4 Functional Description* CFB128 (128-bit Cipher Feedback)– Interrupt on completion of computationFor details, see ESP32-C6 Technical Reference Manual > Chapter AES Accelerator (AES).4.1.4.2 ECC AcceleratorThe ECC Accelerator accelerates calculations based on the Elliptic Curve Cryptography (ECC) algorithm andECC-derived algorithms like ECDSA, which offers the advantages of smaller public keys compared to RSAcryptography with equivalent security.Feature List• Supports two different elliptic curves (P-192 and P-256)• Six working modes that supports Base Point Verification, Base Point Multiplication, Jacobian PointVerification, and Jacobian Point MultiplicationFor details, see the ESP32-C6 Technical Reference Manual > Chapter ECC Accelerator (ECC).4.1.4.3 HMAC AcceleratorThe HMAC Accelerator (HMAC) module is designed to compute Message Authentication Codes (MACs) usingthe SHA-256 Hash algorithm and keys as described in RFC 2104. It provides hardware support for HMACcomputations, significantly reducing software complexity and improving performance.Feature List• Standard HMAC-SHA-256 algorithm• HMAC-SHA-256 calculation based on key in eFuse– Whose result cannot be accessed by software in downstream mode for high security– Whose result can be accessed by software in upstream mode• Generates required keys for the Digital Signature Algorithm (DSA) peripheral in downstream mode• Re-enables soft-disabled JTAG in downstream modeFor details, see the ESP32-C6 Technical Reference Manual > Chapter HMAC Accelerator.4.1.4.4 RSA AcceleratorThe RSA accelerator provides hardware support for high-precision computation used in various RSA asymmetriccipher algorithms, significantly improving their run time and reducing their software complexity. Compared withRSA algorithms implemented solely in software, this hardware accelerator can speed up RSA algorithmssignificantly.Feature List• Large-number modular exponentiation with two optional acceleration options, operands width up to 3072bitsEspressif Systems 47Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 4 Functional Description• Large-number modular multiplication, operands width up to 3072 bits• Large-number multiplication, operands width up to 1536 bits• Operands of different widths• Interrupt on completion of computationFor details, see the ESP32-C6 Technical Reference Manual > Chapter RSA Accelerator.4.1.4.5 SHA AcceleratorThe SHA Accelerator (SHA) is a hardware device that significantly speeds up the SHA algorithm compared tosoftware-only implementations.Feature List• Support for multiple SHA algorithms: SHA-1, SHA-224, and SHA-256• Two working modes: Typical SHA based on CPU and DMA-SHA based on DMAFor more details, see the ESP32-C6 Technical Reference Manual > Chapter SHA Accelerator (SHA).4.1.4.6 Digital SignatureThe Digital Signature (DS) module in the ESP32-C6 chip generates message signatures based on RSA withhardware acceleration.Feature List• RSA digital signatures with key length up to 3072 bits• Encrypted private key data, only decryptable by DS module• SHA-256 digest to protect private key data against tampering by an attackerFor more details, see the ESP32-C6 Technical Reference Manual > Chapter Digital Signature (DS).4.1.4.7 External Memory Encryption and DecryptionThe External Memory Encryption and Decryption (XTS_AES) module in the ESP32-C6 chip provides security forusers’ application code and data stored in the external memory (flash).Feature List• General XTS-AES algorithm, compliant with IEEE Std 1619-2007• Software-based manual encryption• High-speed auto decryption without software’s participation• Encryption and decryption functions jointly enabled/disabled by registers configuration, eFuse parameters,and boot mode• Configurable Anti-DPAEspressif Systems 48Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 4 Functional DescriptionFor more details, see the ESP32-C6 Technical Reference Manual > Chapter External Memory Encryption andDecryption (XTS_AES).4.1.4.8 Random Number GeneratorThe Random Number Generator (RNG) in the ESP32-C6 is a true random number generator that generates32-bit random numbers for cryptographic operations from a physical process.Feature List• RNG entropy source– Thermal noise from high-speed ADC or SAR ADC– An asynchronous clock mismatchFor more details about the Random Number Generator, refer to the ESP32-C6 Technical Reference Manual >Chapter Random Number Generator (RNG).Espressif Systems 49Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 4 Functional Description4.2 PeripheralsThis section describes the chip’s peripheral capabilities, covering connectivity interfaces and on-chip sensors thatextend its functionality.4.2.1 Connectivity InterfaceThis subsection describes the connectivity interfaces on the chip that enable communication and interaction withexternal devices and networks.4.2.1.1 UART ControllerThe UART Controller in the ESP32-C6 chip facilitates the transmission and reception of asynchronous serial databetween the chip and external UART devices. It consists of two UARTs in the main system, and one low-powerLP UART.Feature List• Programmable baud rates up to 5 MBaud• RAM shared by TX FIFOs and RX FIFOs• Support for various lengths of data bits and stop bits• Parity bit support• Special character AT_CMD detection• RS485 protocol support (not supported by LP UART)• IrDA protocol support (not supported by LP UART)• High-speed data communication using GDMA (not supported by LP UART)• Receive timeout feature• UART as the wake-up source• Software and hardware flow controlFor details, see ESP32-C6 Technical Reference Manual > Chapter UART Controller (UART, LP_UART).Pin AssignmentFor details, see Section 2.3.5 Peripheral Pin Assignment.4.2.1.2 SPI ControllerESP32-C6 has the following SPI interfaces:• SPI0 used by ESP32-C6’s cache and GDMA to access in-package or off-package flash• SPI1 used by the CPU to access in-package or off-package flash• SPI2 is a general-purpose SPI controller with access to general-purpose DMA channelsSPI0 and SPI1 are reserved for system use, and only SPI2 is available for users.Espressif Systems 50Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 4 Functional DescriptionFeatures of SPI0 and SPI1• Supports Single SPI, Dual SPI, Quad SPI (QPI) modes• Data transmission is in bytesFeatures of SPI2• Supports operation as a master or slave• Support for GDMA• Supports Single SPI, Dual SPI, Quad SPI (QPI) modes• Configurable clock polarity (CPOL) and phase (CPHA)• Configurable clock frequency• Data transmission is in bytes• Configurable read and write data bit order: most-significant bit (MSB) first, or least-significant bit (LSB) first• As a master– Supports 2-line full-duplex communication with clock frequency up to 80 MHz– Supports 1-, 2-, 4-line half-duplex communication with clock frequency up to 80 MHz– Provides six FSPICS… pins for connection with six independent SPI slaves– Configurable CS setup time and hold time• As a slave– Supports 2-line full-duplex communication with clock frequency up to 40 MHz– Supports 1-, 2-, 4-line half-duplex communication with clock frequency up to 40 MHzFor details, see ESP32-C6 Technical Reference Manual > Chapter SPI Controller (SPI).Pin AssignmentFor details, see Section 2.3.5 Peripheral Pin Assignment.4.2.1.3 I2C ControllerThe I2C Controller supports communication between the master and slave devices using the I2C bus.Feature List• Two I2C controllers: one in the main system and one in the low-power system• Communication with multiple external devices• Master and slave modes for I2C, and master mode only for LP I2C• Standard mode (100 Kbit/s) and fast mode (400 Kbit/s)• SCL clock stretching in slave mode• Programmable digital noise filteringEspressif Systems 51Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 4 Functional Description• Support for 7-bit and 10-bit addressing, as well as dual address modeFor details, see ESP32-C6 Technical Reference Manual > Chapter I2C Controller (I2C).Pin AssignmentFor details, see Section 2.3.5 Peripheral Pin Assignment.4.2.1.4 I2S ControllerThe I2S Controller in the ESP32-C6 chip provides a flexible communication interface for streaming digital data inmultimedia applications, particularly digital audio applications.Feature List• Master mode and slave mode• Full-duplex and half-duplex communications• Separate TX and RX units that can work independently or simultaneously• A variety of audio standards supported:– TDM Philips standard– TDM MSB alignment standard– TDM PCM standard– PDM standard• PCM-to-PDM TX interface• Configurable high-precision BCK clock, with frequency up to 40 MHz– Sampling frequencies can be 8 kHz, 16 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 128 kHz,192 kHz, etc.• 8-/16-/24-/32-bit data communication• Direct Memory Access (DMA)• A-law and µ-law compression/decompression algorithms for improved signal-to-quantization noise ratio• Flexible data format controlFor details, see ESP32-C6 Technical Reference Manual > Chapter I2S Controller (I2S).Pin AssignmentFor details, see Section 2.3.5 Peripheral Pin Assignment.4.2.1.5 Pulse Count ControllerThe Pulse Count Controller (PCNT) is designed to count input pulses by tracking rising and falling edges of theinput pulse signal.Espressif Systems 52Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 4 Functional DescriptionFeature List• Four independent pulse counters with two channels each• Counter modes: increment, decrement, or disable• Glitch filtering for input pulse signals and control signals• Selection between counting on rising or falling edges of the input pulse signalFor details, see ESP32-C6 Technical Reference Manual > Chapter Pulse Count Controller.Pin AssignmentFor details, see Section 2.3.5 Peripheral Pin Assignment.4.2.1.6 USB Serial/JTAG ControllerThe USB Serial/JTAG controller in the ESP32-C6 chip provides an integrated solution for communicating to thechip over a standard USB CDC-ACM serial port as well as a convenient method for JTAG debugging. Iteliminates the need for external chips or JTAG adapters, saving space and reducing cost.Feature List• USB 2.0 full speed compliant, capable of up to 12 Mbit/s transfer speed (Note that this controller does notsupport the faster 480 Mbit/s high-speed transfer mode)• CDC-ACM virtual serial port and JTAG adapter functionality• CDC-ACM:– CDC-ACM adherent serial port emulation (plug-and-play on most modern OSes)– Host controllable chip reset and entry into download mode• JTAG adapter functionality:– Fast communication with CPU debugging core using a compact representation of JTAG instructions• Support for reprogramming of attached flash memory through the ROM startup code• Internal PHYFor details, see ESP32-C6 Technical Reference Manual > Chapter USB Serial/JTAG Controller(USB_SERIAL_JTAG).Pin AssignmentFor details, see Section 2.3.5 Peripheral Pin Assignment.4.2.1.7 Two-wire Automotive InterfaceThe Two-wire Automotive Interface (TWAI®) is a multi-master, multi-cast communication protocol designed forautomotive applications. The TWAI controller facilitates the communication based on this protocol.Espressif Systems 53Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 4 Functional DescriptionFeature List• Compatible with ISO 11898-1 protocol (CAN Specification 2.0)• Standard frame format (11-bit ID) and extended frame format (29-bit ID)• Bit rates from 1 Kbit/s to 1 Mbit/s• Multiple modes of operation: Normal, Listen Only, and Self-Test (no acknowledgment required)• Special transmissions: Single-shot and Self Reception• Acceptance filter (single and dual filter modes)• Error detection and handling: error counters, configurable error warning limit, error code capture, arbitrationlost capture, automatic transceiver standbyFor details, see ESP32-C6 Technical Reference Manual > Chapter Two-wire Automotive Interface.Pin AssignmentFor details, see Section 2.3.5 Peripheral Pin Assignment.4.2.1.8 SDIO Slave ControllerThe SDIO Slave Controller in the ESP32-C6 chip provides hardware support for the Secure Digital Input/Output(SDIO) device interface. It allows an SDIO host to access the ESP32-C6 via an SDIO bus protocol.Feature List• Compatible with SD Physical Layer Specification V2.00 and SDIO V2.00 specifications• Support for SPI, 1-bit SDIO, and 4-bit SDIO transfer modes• Clock range of 0 ~ 50 MHz• Configurable sample and drive clock edge• Integrated and SDIO-accessible registers for information interaction• Support for SDIO interrupt mechanism• Automatic padding data and discarding the padded data on the SDIO bus• Block size up to 512 bytes• Interrupt vector between the host and slave for bidirectional interrupt• Support DMA for data transfer• Support for wake-up from sleep when connection is retainedFor more details about the SDIO Slave Controller, refer to the ESP32-C6 Technical Reference Manual > ChapterSDIO Slave Controller (SDIO).Pin AssignmentFor details, see Section 2.3.5 Peripheral Pin Assignment.Espressif Systems 54Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 4 Functional Description4.2.1.9 LED PWM ControllerThe LED PWM Controller (LEDC) is designed to generate PWM signals for LED control.Feature List• Six independent PWM generators• Maximum PWM duty cycle resolution of 20 bits• Four independent timers with 20-bit counters, configurable fractional clock dividers and counter overflowvalues• Adjustable phase of PWM signal output• PWM duty cycle dithering• Automatic duty cycle fading– Linear duty cycle fading — only one duty cycle range– Gamma curve fading — up to 16 duty cycle ranges for each PWM generator, with independentlyconfigured fading direction (increase or decrease), fading amount, number of fades, and fadingfrequency• PWM signal output in low-power mode (Light-sleep mode)• Event generation and task response achieved by the Event Task Matrix (ETM)For details, see ESP32-C6 Technical Reference Manual > Chapter LED PWM Controller.Pin AssignmentFor details, see Section 2.3.5 Peripheral Pin Assignment.4.2.1.10 Motor Control PWMThe Motor Control Pulse Width Modulator (MCPWM) is designed for driving digital motors and smart light. TheMCPWM is divided into five main modules: PWM timers, PWM operators, Capture module, Fault Detectionmodule, and Event Task Matrix (ETM) module.Feature List• Three PWM timers for precise timing and frequency control– Every PWM timer has a dedicated 8-bit clock prescaler– The 16-bit counter in the PWM timer can work in count-up mode, count-down mode, orcount-up-down mode– Hardware or software synchronization to trigger a reload on the PWM timer or the prescaler’s restart,with selectable hardware synchronization source• Three PWM operators for generating waveform pairs– Six PWM outputs to operate in several topologies– Configurable dead time on rising and falling edges; each set up independentlyEspressif Systems 55Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 4 Functional Description– Modulating of PWM output by high-frequency carrier signals, useful when gate drivers are insulatedwith a transformer• Capture module for hardware-based signal processing– Speed measurement of rotating machinery– Measurement of elapsed time between position sensor pulses– Period and duty cycle measurement of pulse train signals– Decoding current or voltage amplitude derived from duty-cycle-encoded signals of current/voltagesensors– Three individual capture channels, each of which with a 32-bit time-stamp register– Selection of edge polarity and prescaling of input capture signals– The capture timer can sync with a PWM timer or external signals• Fault Detection module– Programmable fault handling in both cycle-by-cycle mode and one-shot mode– A fault condition can force the PWM output to either high or low logic levels• Event generation and task response achieved by the Event Task Matrix (ETM)For details, see ESP32-C6 Technical Reference Manual > Chapter Motor Control PWM (MCPWM).Pin AssignmentFor details, see Section 2.3.5 Peripheral Pin Assignment.4.2.1.11 Remote Control PeripheralThe Remote Control Peripheral (RMT) controls the transmission and reception of infrared remote controlsignals.Feature List• Four channels for sending and receiving infrared remote control signals• Independent transmission and reception capabilities for each channel• Support for Normal TX/RX mode, Wrap TX/RX mode, Continuous TX mode• Modulation on TX pulses and Demodulation on RX pulses• RX filtering for improved signal reception• Ability to transmit data simultaneously on multiple channels• Clock divider counter, state machine, and receiver for each RX channel• Default allocation of RAM blocks to channels based on channel number• RAM containing 16-bit entries with “level” and “period” fieldsFor more details, see ESP32-C6 Technical Reference Manual > ChapterRemote Control Peripheral (RMT).Espressif Systems 56Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 4 Functional DescriptionPin AssignmentFor details, see Section 2.3.5 Peripheral Pin Assignment.4.2.1.12 Parallel IO ControllerThe Parallel IO Controller (PARLIO) in the ESP32-C6 chip enables data transfer between external devices andinternal memory on a parallel bus through GDMA. It consists of a transmitter (TX unit) and a receiver (RX unit),making it a versatile interface for connecting various peripherals.Feature List• 1/2/4/8/16-bit configurable data bus width• Half-duplex communication with 16-bit data bus width and full-duplex communication with 8-bit data buswidth• Bit reordering in 1/2/4-bit data bus width mode• RX unit supports 15 receive modes categorized into three major categories: Level Enable mode, PulseEnable mode, and Software Enable mode• TX unit can generate a valid signal aligned with TXFor more details, see ESP32-C6 Technical Reference Manual > Chapter Parallel IO Controller.Pin AssignmentFor details, see Section 2.3.5 Peripheral Pin Assignment.4.2.2 Analog Signal ProcessingThis subsection describes components on the chip that sense and process real-world data.4.2.2.1 SAR ADCESP32-C6 integrates a Successive Approximation Analog-to-Digital Converter (SAR ADC) to convert analogsignals into digital representations.Feature List• 12-bit sampling resolution• Analog voltage sampling from up to seven pins• Attenuation of input signals for voltage conversion• Software-triggered one-time sampling• Timer-triggered multi-channel scanning• DMA continuous conversion for seamless data transfer• Two filters with configurable filter coefficient• Threshold monitoring which helps to trigger an interruptEspressif Systems 57Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 4 Functional Description• Support for Event Task MatrixFor more details, see ESP32-C6 Technical Reference Manual > Chapter On-Chip Sensors and Analog SignalProcessing.Pin AssignmentFor details, see Section 2.3.5 Peripheral Pin Assignment.4.2.2.2 Temperature SensorThe Temperature Sensor in the ESP32-C6 chip allows for real-time monitoring of temperature changes inside thechip.Feature List• Measurement range: –40°C ~ 125°C• Software triggering, wherein the data can be read continuously once triggered• Hardware automatic triggering and temperature monitoring• Configurable temperature offset based on the environment to improve the accuracy• Adjustable measurement range• Two automatic monitoring wake-up modes: absolute value mode and incremental value mode• Support for Event Task MatrixFor more details, see ESP32-C6 Technical Reference Manual > Chapter On-Chip Sensors and Analog SignalProcessing.Espressif Systems 58Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 4 Functional Description4.3 Wireless CommunicationThis section describes the chip’s wireless communication capabilities, spanning radio technology, Wi-Fi,Bluetooth, and 802.15.4.4.3.1 RadioThis subsection describes the fundamental radio technology embedded in the chip that facilitates wirelesscommunication and data exchange. The ESP32-C6 radio consists of the following blocks:• 2.4 GHz receiver• 2.4 GHz transmitter• Bias and regulators• Balun and transmit-receive switch• Clock generator4.3.1.1 2.4 GHz ReceiverThe 2.4 GHz receiver demodulates the 2.4 GHz RF signal to quadrature baseband signals and converts them tothe digital domain with two high-resolution, high-speed ADCs. To adapt to varying signal channel conditions,ESP32-C6 integrates RF filters, Automatic Gain Control (AGC), DC offset cancelation circuits, and basebandfilters.4.3.1.2 2.4 GHz TransmitterThe 2.4 GHz transmitter modulates the quadrature baseband signals to the 2.4 GHz RF signal, and drives theantenna with a high-powered CMOS power amplifier. The use of digital calibration further improves the linearity ofthe power amplifier.Additional calibrations are integrated to cancel any radio imperfections, such as:• Carrier leakage• I/Q amplitude/phase matching• Baseband nonlinearities• RF nonlinearities• Antenna matchingThese built-in calibration routines reduce the cost, time, and specialized equipment required for producttesting.4.3.1.3 Clock GeneratorThe clock generator produces quadrature clock signals of 2.4 GHz for both the receiver and the transmitter. Allcomponents of the clock generator are integrated into the chip, including inductors, varactors, filters, regulatorsand dividers.Espressif Systems 59Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 4 Functional DescriptionThe clock generator has built-in calibration and self-test circuits. Quadrature clock phases and phase noise areoptimized on chip with patented calibration algorithms which ensure the best performance of the receiver and thetransmitter.4.3.2 Wi-FiThis subsection describes the chip’s Wi-Fi capabilities, which facilitate wireless communication at a high datarate.4.3.2.1 Wi-Fi Radio and BasebandThe ESP32-C6 Wi-Fi radio and baseband support the following features:• compliant with IEEE 802.11b/g/n/ax• 1T1R in 2.4 GHz band• 802.11ax– 20 MHz-only non-AP mode– MCS0 ~MCS9– Uplink and downlink OFDMA– Downlink MU-MIMO (multi-user, multiple input, multiple output)– Longer OFDM symbol, with 0.8, 1.6, 3.2 µs guard interval– DCM (dual carrier modulation), up to 16-QAM– Single-user/multi-user beamformee– Channel quality indication (CQI)– RX STBC (single spatial stream)• 802.11b/g/n– MCS0 ~MCS7 that supports 20 MHz and 40 MHz bandwidth– MCS32– Data rate up to 150 Mbps– 0.4 µs guard interval• adjustable transmitting power• antenna diversityESP32-C6 supports antenna diversity with an external RF switch. This switch is controlled by one or moreGPIOs, and used to select the best antenna to minimize the effects of channel imperfections.4.3.2.2 Wi-Fi MACESP32-C6 implements the full IEEE 802.11 b/g/n/ax Wi-Fi MAC protocol. It supports the Basic Service Set (BSS)STA and SoftAP operations under the Distributed Control Function (DCF). Power management is handledautomatically with minimal host interaction to minimize the active duty period.Espressif Systems 60Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 4 Functional DescriptionThe ESP32-C6 Wi-Fi MAC applies the following low-level protocol functions automatically:• 4 × virtual Wi-Fi interfaces• Infrastructure BSS in Station mode, SoftAP mode, Station + SoftAP mode, and promiscuous mode• RTS protection, CTS protection, Immediate Block ACK• Fragmentation and defragmentation• TX/RX A-MPDU, TX/RX A-MSDU• Transmit opportunity (TXOP)• Wi-Fi multimedia (WMM)• GCMP, CCMP, TKIP, WAPI, WEP, BIP, WPA2-PSK/WPA2-Enterprise, and WPA3-PSK/WPA3-Enterprise• Automatic beacon monitoring (hardware TSF)• 802.11mc FTMNote:This feature is not supported in some chip revisions. See ESP32-C6 Series SoC Errata.• 802.11ax supports:– Target wake time (TWT) requester– Multiple BSSIDs– Triggered response scheduling– Uplink power headroom– Operating mode– Buffer status report– Multi-user Request-to-Send (MU-RTS), Multi-user Block ACK Request (MU-BAR), and Multi-STABlock ACK (M-BA) frame– Intra-PPDU power saving mechanism– Two network allocation vectors (NAV)– BSS coloring– Spatial reuse– Uplink power headroom– Operating mode control– Buffer status report– TXOP duration RTS threshold– UL-OFDMA random access (UORA)Espressif Systems 61Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 4 Functional Description4.3.2.3 Networking FeaturesEspressif provides libraries for TCP/IP networking, ESP-WIFI-MESH networking, and other networking protocolsover Wi-Fi. TLS 1.0, 1.1 and 1.2 is also supported.4.3.3 Bluetooth LEThis subsection describes the chip’s Bluetooth capabilities, which facilitate wireless communication forlow-power, short-range applications. ESP32-C6 includes a Bluetooth Low Energy subsystem that integrates ahardware link controller, an RF/modem block and a feature-rich software protocol stack. It supports the corefeatures of Bluetooth 5 and Bluetooth mesh.4.3.3.1 Bluetooth LE PHYBluetooth Low Energy PHY in ESP32-C6 supports:• 1 Mbps PHY• 2 Mbps PHY for higher data rates• Coded PHY for longer range (125 Kbps and 500 Kbps)• HW listen before talk (LBT)4.3.3.2 Bluetooth LE Link ControllerBluetooth Low Energy Link Controller in ESP32-C6 supports:• LE Advertising Extensions, to enhance broadcasting capacity and broadcast more intelligent data• Multiple advertising sets• Simultaneous advertising and scanning• Multiple connections in simultaneous central and peripheral roles• Adaptive Frequency Hopping (AFH) and channel assessment• LE Channel Selection Algorithm #2• LE Power Control• Connection parameter update• High Duty Cycle Non-Connectable Advertising• LE privacy 1.2• LE Data Packet Length Extension• Link Layer Extended Scanner Filter policies• Low duty cycle directed advertising• Link layer encryption• LE PingEspressif Systems 62Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 4 Functional Description4.3.4 802.15.4This subsection describes the chip’s compatibility with the 802.15.4 standard, which facilitates wirelesscommunication for low-power, short-range applications. ESP32-C6 includes an IEEE Standard 802.15.4subsystem that integrates PHY and MAC layer. It supports various software stacks including Thread, Zigbee,Matter, HomeKit, MQTT and so on.4.3.4.1 802.15.4 PHYESP32-C6 ’s 802.15.4 PHY supports:• O-QPSK PHY in 2.4 GHz• 250 Kbps data rate• RSSI and LQI supported4.3.4.2 802.15.4 MACESP32-C6 supports most key features defined in IEEE Standard 802.15.4-2015, including:• CSMA/CA• Active scan and energy detect• HW frame filter• HW auto acknowledge• HW auto frame pending• Coordinated sampled listening (CSL)Espressif Systems 63Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 5 Electrical Characteristics5 Electrical Characteristics5.1 Absolute Maximum RatingsStresses above those listed in Table 5-1 Absolute Maximum Ratings may cause permanent damage to the device.These are stress ratings only and normal operation of the device at these or any other conditions beyond thoseindicated in Section 5.2 Recommended Operating Conditions is not implied. Exposure toabsolute-maximum-rated conditions for extended periods may affect device reliability.Table 5-1. Absolute Maximum RatingsParameter Description Min Max UnitInput power pins1Allowed input voltage –0.3 3.6 VIoutput2Cumulative IO output current — 1000 mATST OREStorage temperature –40 150 °C1For more information on input power pins, see Section 2.5.1 Power Pins.2The product proved to be fully functional after all its IO pins were pulled high whilebeing connected to ground for 24 consecutive hours at ambient temperature of25 °C.5.2 Recommended Operating ConditionsTable 5-2. Recommended Operating ConditionsParameter1Description Min Typ Max UnitVDDA1, VDDA2, VDDA3P3 Recommended input voltage 3.0 3.3 3.6 VVDDPST1 Recommended input voltage 3.0 3.3 3.6 VVDD_SPI (as input) — 3.0 3.3 3.6 VVDDPST22, 3Recommended input voltage 3.0 3.3 3.6 VIV DDCumulative input current 0.5 — — ATAAmbient temperature –40 — 105 °C1See in conjunction with Section 2.5 Power Supply.2If VDDPST2 is used to power VDD_SPI (see Section 2.5.2 Power Scheme), the voltage dropon RSP Ishould be accounted for. See also Section 5.3 VDD_SPI Output Characteristics.3If writing to eFuses, the voltage on VDDPST2 should not exceed 3.3 V as the circuits respon-sible for burning eFuses are sensitive to higher voltages.Espressif Systems 64Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 5 Electrical Characteristics5.3 VDD_SPI Output CharacteristicsTable 5-3. VDD_SPI Internal and Output CharacteristicsParameter Description1Typ UnitRSP IVDD_SPI powered by VDDPST2 via RSP Ifor3.3 V flash23 Ω1See in conjunction with Section 2.5.2 Power Scheme.2VDD3P3_RTC must be more than VDD_flash_min + I_flash_max * RSP I;where• VDD_flash_min – minimum operating voltage of flash• I_flash_max – maximum operating current of flash5.4 DC Characteristics (3.3 V, 25 °C)Table 5-4. DC Characteristics (3.3 V, 25 °C)Parameter Description Min Typ Max UnitCINPin capacitance — 2 — pFVIHHigh-level input voltage0.75 × VDD1— VDD1+ 0.3 VVILLow-level input voltage –0.3 —0.25 × VDD1VIIHHigh-level input current — — 50 nAIILLow-level input current — — 50 nAVOH2High-level output voltage 0.8 × VDD1— — VVOL2Low-level output voltage — — 0.1 × VDD1VIOHHigh-level source current (VDD1= 3.3 V, VOH>= 2.64 V, PAD_DRIVER = 3)— 40 — mAIOLLow-level sink current (VDD1= 3.3 V, VOL=0.495 V, PAD_DRIVER = 3)— 28 — mARP UInternal weak pull-up resistor — 45 — kΩRP DInternal weak pull-down resistor — 45 — kΩVIH_nRSTChip reset release voltage (CHIP_PU voltage iswithin the specified range)0.75 × VDD1— VDD1+ 0.3 VVIL_nRSTChip reset voltage (CHIP_PU voltage is withinthe specified range)–0.3 —0.25 × VDD1V1VDD – voltage from a power pin of a respective power domain.2VOHand VOLare measured using high-impedance load.5.5 ADC CharacteristicsThe measurements in this section are taken with an external 100 nF capacitor connected to the ADC, using DCsignals as input, and at an ambient temperature of 25 °C with disabled Wi-Fi.Espressif Systems 65Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 5 Electrical CharacteristicsTable 5-5. ADC CharacteristicsSymbol Min Max UnitDNL (Differential nonlinearity)1–8 12 LSBINL (Integral nonlinearity) –10 10 LSBSampling rate — 100 kSPS21To get better DNL results, you can sample multiple times andapply a filter, or calculate the average value.2kSPS means kilo samples-per-second.The calibrated ADC results after hardware calibration and software calibration are shown in Table 5-6. For higheraccuracy, you may implement your own calibration methods.Table 5-6. ADC Calibration ResultsParameter Description Min Max UnitTotal errorATTEN0, effective measurement range of 0 ~ 1000 –12 12 mVATTEN1, effective measurement range of 0 ~ 1300 –12 12 mVATTEN2, effective measurement range of 0 ~ 1900 –23 23 mVATTEN3, effective measurement range of 0 ~ 3300 –40 40 mVNote:The above ADC measurement range and accuracy are applicable to chips manufactured on and after the Date Code212023 on shielding cases, or assembled on and after the D/C 1 and D/C 2 2321 on bar-code labels. For chips manu-factured or assembled earlier than these date codes, please ask our sales team to provide the actual range and accuracyaccording to batch.For details of Date Code and D/C, please refer to Espressif Chip Packaging Information.5.6 Current Consumption Characteristics5.6.1 Current Consumption in Active ModeThe current consumption measurements are taken with a 3.3 V supply at 25 °C ambient temperature.TX current consumption is rated at a 100% duty cycle.RX current consumption is rated when the peripherals are disabled and the CPU idle.Table 5-7. Current Consumption for Wi-Fi (2.4 GHz) in Active ModeWork Mode RF Condition Description Peak (mA)Active (RF working)TX802.11b, 1 Mbps, DSSS @ 21.0 dBm 354802.11g, 54 Mbps, OFDM @ 19.5 dBm 300802.11n, HT20, MCS7 @ 18.5 dBm 280802.11n, HT40, MCS7 @ 18.0 dBm 268802.11ax, MCS9, @ 16.5 dBm 252Cont’d on next pageEspressif Systems 66Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 5 Electrical CharacteristicsTable 5-7 – cont’d from previous pageWork Mode RF Condition Description Peak (mA)RX802.11b/g/n, HT20 78802.11n, HT40 82802.11ax, HE20 78Table 5-8. Current Consumption for Bluetooth LE in Active ModeWork Mode RF Condition Description Peak (mA)Active (RF working)TXBluetooth LE @ 20.0 dBm 315Bluetooth LE @ 9.0 dBm 190Bluetooth LE @ 0 dBm 130Bluetooth LE @ –15.0 dBm 94RX Bluetooth LE 71Table 5-9. Current Consumption for 802.15.4 in Active ModeWork Mode RF Condition Description Peak (mA)Active (RF working)TX802.15.4 @ 20.0 dBm 305802.15.4 @ 12.0 dBm 187802.15.4 @ 0 dBm 119802.15.4 @ –15.0 dBm 92RX 802.15.4 745.6.2 Current Consumption in Other ModesTable 5-10. Current Consumption in Modem-sleep ModeTyp (mA)ModeCPU Frequency(MHz) DescriptionAll PeripheralsClocks DisabledAll PeripheralsClocks Enabled1Modem-sleep2, 3160CPU is running 27 38CPU is idle 17 2880CPU is running 19 30CPU is idle 14 251In practice, the current consumption might be different depending on which peripherals are en-abled.2In Modem-sleep mode, Wi-Fi is clock gated.3In Modem-sleep mode, the consumption might be higher when accessing flash.Espressif Systems 67Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 5 Electrical CharacteristicsTable 5-11. Current Consumption in Low-Power ModesMode Description Typ (µA)Light-sleepCPU and wireless communication modules are powered down, pe-ripheral clocks are disabled, and all GPIOs are high-impedance180CPU, wireless communication modules and peripherals are pow-ered down, and all GPIOs are high-impedance35Deep-sleep RTC timer and LP memory are powered on 7Power off CHIP_PU is set to low level, the chip is powered off 15.7 Memory SpecificationsThe data below is sourced from the memory vendor datasheet. These values are guaranteed through designand/or characterization but are not fully tested in production. Devices are shipped with the memoryerased.Table 5-12. Flash SpecificationsParameter Description Min Typ Max UnitVCCPower supply voltage (1.8 V) 1.65 1.80 2.00 VPower supply voltage (3.3 V) 2.7 3.3 3.6 VFCMaximum clock frequency 80 — — MHz— Program/erase cycles 100,000 — — cyclesTRETData retention time 20 — — yearsTP PPage program time — 0.8 5 msTSESector erase time (4 KB) — 70 500 msTBE1Block erase time (32 KB) — 0.2 2 sTBE2Block erase time (64 KB) — 0.3 3 sTCEChip erase time (16 Mb) — 7 20 sChip erase time (32 Mb) — 20 60 sChip erase time (64 Mb) — 25 100 sChip erase time (128 Mb) — 60 200 sChip erase time (256 Mb) — 70 300 s5.8 ReliabilityTable 5-13. Reliability QualificationsTest Item Test Conditions Test StandardHTOL (High TemperatureOperating Life)125 °C, 1000 hours JESD22-A108ESD (Electro-StaticDischarge Sensitivity)HBM (Human Body Mode)1± 2000 V JS-001CDM (Charge Device Mode)2± 1000 V JS-002Latch upCurrent trigger ± 200 mAJESD78Voltage trigger 1.5 × VDDmaxCont’d on next pageEspressif Systems 68Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 5 Electrical CharacteristicsTable 5-13 – cont’d from previous pageTest Item Test Conditions Test StandardPreconditioningBake 24 hours @125 °CMoisture soak (level 3: 192 hours @30 °C, 60% RH)IR reflow solder: 260 + 0 °C, 20 seconds, three timesJ-STD-020, JESD47,JESD22-A113TCT (Temperature CyclingTest)–65 °C / 150 °C, 500 cycles JESD22-A104uHAST (HighlyAccelerated Stress Test,unbiased)130 °C, 85% RH, 96 hours JESD22-A118HTSL (High TemperatureStorage Life)150 °C, 1000 hours JESD22-A103LTSL (Low TemperatureStorage Life)–40 °C, 1000 hours JESD22-A1191JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.2JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.Espressif Systems 69Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 6 RF Characteristics6 RF CharacteristicsThis section contains tables with RF characteristics of the Espressif product.The RF data is measured at the antenna port, where RF cable is connected, including the front-end loss. Thefront-end circuit is a 0 Ω resistor.Devices should operate in the center frequency range allocated by regional regulatory authorities. The targetcenter frequency range and the target transmit power are configurable by software. See ESP RF Test Tool andTest Guide for instructions.Unless otherwise stated, the RF tests are conducted with a 3.3 V (±5%) supply at 25 ºC ambient temperature.6.1 Wi-Fi RadioTable 6-1. Wi-Fi RF CharacteristicsName DescriptionCenter frequency range of operating channel 2412 ~ 2484 MHzWi-Fi wireless standard IEEE 802.11b/g/n/ax6.1.1 Wi-Fi RF Transmitter (TX) CharacteristicsTable 6-2. TX Power with Spectral Mask and EVM Meeting 802.11 StandardsMin Typ MaxRate (dBm) (dBm) (dBm)802.11b, 1 Mbps, DSSS — 21.0 —802.11b, 11 Mbps, CCK — 21.0 —802.11g, 6 Mbps, OFDM — 20.5 —802.11g, 54 Mbps, OFDM — 19.5 —802.11n, HT20, MCS0 — 19.5 —802.11n, HT20, MCS7 — 18.5 —802.11n, HT40, MCS0 — 19.0 —802.11n, HT40, MCS7 — 18.0 —802.11ax, HE20, MCS0 — 19.5 —802.11ax, HE20, MCS9 — 16.5 —Table 6-3. TX EVM Test1Min Typ LimitRate (dB) (dB) (dB)802.11b, 1 Mbps, DSSS — –25.5 –10.0802.11b, 11 Mbps, CCK — –25.5 –10.0802.11g, 6 Mbps, OFDM — –26.5 –5.0Cont’d on next pageEspressif Systems 70Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 6 RF CharacteristicsTable 6-3 – cont’d from previous pageMin Typ LimitRate (dB) (dB) (dB)802.11g, 54 Mbps, OFDM — –29.0 –25.0802.11n, HT20, MCS0 — –29.0 –5.0802.11n, HT20, MCS7 — –30.0 –27.0802.11n, HT40, MCS0 — –28.5 –5.0802.11n, HT40, MCS7 — –29.5 –27.0802.11ax, HE20, MCS0 — –29.0–5.0802.11ax, HE20, MCS9 — –34.0 –32.01EVM is measured at the corresponding typical TX power providedin Table 6-2 TX Power with Spectral Mask and EVM Meeting 802.11Standards above.6.1.2 Wi-Fi RF Receiver (RX) CharacteristicsFor RX tests, the PER (packet error rate) limit is 8% for 802.11b, and 10% for 802.11g/n/ax.Table 6-4. RX SensitivityMin Typ MaxRate (dBm) (dBm) (dBm)802.11b, 1 Mbps, DSSS — –99.2 —802.11b, 2 Mbps, DSSS — –96.8 —802.11b, 5.5 Mbps, CCK — –93.8 —802.11b, 11 Mbps, CCK — –90.0 —802.11g, 6 Mbps, OFDM — –94.0 —802.11g, 9 Mbps, OFDM — –93.2—802.11g, 12 Mbps, OFDM — –92.6 —802.11g, 18 Mbps, OFDM — –90.0 —802.11g, 24 Mbps, OFDM — –86.8 —802.11g, 36 Mbps, OFDM — –83.2 —802.11g, 48 Mbps, OFDM — –79.0 —802.11g, 54 Mbps, OFDM — –77.6 —802.11n, HT20, MCS0 — –93.6 —802.11n, HT20, MCS1 — –92.4 —802.11n, HT20, MCS2 — –89.6 —802.11n, HT20, MCS3 — –86.2 —802.11n, HT20, MCS4 — –82.8 —802.11n, HT20, MCS5 — –78.8 —802.11n, HT20, MCS6 — –77.2 —802.11n, HT20, MCS7 — –75.6 —802.11n, HT40, MCS0 — –91.0 —802.11n, HT40, MCS1 — –90.0 —802.11n, HT40, MCS2 — –87.4 —Cont’d on next pageEspressif Systems 71Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 6 RF CharacteristicsTable 6-4 – cont’d from previous pageMin Typ MaxRate (dBm) (dBm) (dBm)802.11n, HT40, MCS3 — –83.8 —802.11n, HT40, MCS4 — –80.8 —802.11n, HT40, MCS5 — –76.6 —802.11n, HT40, MCS6 — –75.0 —802.11n, HT40, MCS7 — –73.4 —802.11ax, HE20, MCS0 — –93.8—802.11ax, HE20, MCS1 — –91.2 —802.11ax, HE20, MCS2 — –88.4 —802.11ax, HE20, MCS3 — –85.6 —802.11ax, HE20, MCS4 — –82.2 —802.11ax, HE20, MCS5 — –78.4 —802.11ax, HE20, MCS6 — –76.6 —802.11ax, HE20, MCS7 — –74.8 —802.11ax, HE20, MCS8 — –71.0 —802.11ax, HE20, MCS9 — –69.0 —Table 6-5. Maximum RX LevelMin Typ MaxRate (dBm) (dBm) (dBm)802.11b, 1 Mbps, DSSS — 5 —802.11b, 11 Mbps, CCK — 5 —802.11g, 6 Mbps, OFDM — 5 —802.11g, 54 Mbps, OFDM — 0 —802.11n, HT20, MCS0 — 5 —802.11n, HT20, MCS7 — 0 —802.11n, HT40, MCS0 — 5 —802.11n, HT40, MCS7 — 0 —802.11ax, HE20, MCS0 — 5 —802.11ax, HE20, MCS9 — 0 —Table 6-6. RX Adjacent Channel RejectionMin Typ MaxRate (dB) (dB) (dB)802.11b, 1 Mbps, DSSS — 38 —802.11b, 11 Mbps, CCK — 38 —802.11g, 6 Mbps, OFDM — 31 —802.11g, 54 Mbps, OFDM — 20 —802.11n, HT20, MCS0 — 31 —Cont’d on next pageEspressif Systems 72Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 6 RF CharacteristicsTable 6-6 – cont’d from previous pageMin Typ MaxRate (dB) (dB) (dB)802.11n, HT20, MCS7 — 16 —802.11n, HT40, MCS0 — 28 —802.11n, HT40, MCS7 — 10 —802.11ax, HE20, MCS0 — 25 —802.11ax, HE20, MCS9 — 2 —6.2 Bluetooth 5 (LE) RadioTable 6-7. Bluetooth LE RF CharacteristicsName DescriptionCenter frequency range of operating channel 2402 ~ 2480 MHzRF transmit power range –15.0 ~ 20.0 dBm6.2.1 Bluetooth LE RF Transmitter (TX) CharacteristicsTable 6-8. Bluetooth LE - Transmitter Characteristics - 1 MbpsParameter Description Min Typ Max UnitCarrier frequency offset and driftMax. |fn|n=0, 1, 2, 3, ...k— 1.3 — kHzMax. |f0 −fn|n=2, 3, 4, ...k— 1.5 — kHzMax. |fn −fn−5|n=6, 7, 8, ...k— 0.9 — kHz|f1 −f0| — 0.6 — kHzModulation characteristics∆ F 1avg— 249.9 — kHzMin. ∆ F 2max(for at least99.9% of all ∆ F 2max)— 212.1 — kHz∆ F 2avg/∆ F 1avg— 0.88 — —In-band emissions± 2 MHz offset — –29 — dBm± 3 MHz offset — –36 — dBm> ± 3 MHz offset — –39 — dBmTable 6-9. Bluetooth LE - Transmitter Characteristics - 2 MbpsParameter Description Min Typ Max UnitCarrier frequency offset and driftMax. |fn|n=0, 1, 2, 3, ...k— 2.2 — kHzMax. |f0 −fn|n=2, 3, 4, ...k— 1.1 — kHzMax. |fn −fn−5|n=6, 7, 8, ...k— 1.1 — kHz|f1 −f0| — 0.5 — kHzCont’d on next pageEspressif Systems 73Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 6 RF CharacteristicsTable 6-9 – cont’d from previous pageParameter Description Min Typ Max UnitModulation characteristics∆ F 1avg— 499.4 — kHzMin. ∆ F 2max(for at least99.9% of all ∆ F 2max)— 443.5 — kHz∆ F 2avg/∆ F 1avg— 0.95 — —In-band emissions± 4 MHz offset — –40 — dBm± 5 MHz offset — –41 — dBm> ± 5 MHz offset — –42 — dBmTable 6-10. Bluetooth LE - Transmitter Characteristics - 125 KbpsParameter Description Min Typ Max UnitCarrier frequency offset and driftMax. |fn|n=0, 1, 2, 3, ...k— 0.7 — kHzMax. |f0 −fn|n=1, 2, 3, ...k— 0.3 — kHz|f0 −f3| — 0.1 — kHzMax. |fn −fn−3|n=7, 8, 9, ...k— 0.4 — kHzModulation characteristics∆ F 1avg— 250.0 — kHzMin. ∆ F 1max(for at least99.9% of all ∆ F 1max)— 238.0 — kHzIn-band emissions± 2 MHz offset — –29 — dBm± 3 MHz offset — –36 — dBm> ± 3 MHz offset — –39 — dBmTable 6-11. Bluetooth LE - Transmitter Characteristics - 500 KbpsParameter Description Min Typ Max UnitCarrier frequency offset and driftMax. |fn|n=0, 1, 2, 3, ...k— 0.5 — kHzMax. |f0 −fn|n=1, 2, 3, ...k— 0.3 — kHz|f0 −f3| — 0.1 — kHzMax. |fn −fn−3|n=7, 8, 9, ...k— 0.4 — kHzModulation characteristics∆ F 2avg— 230.7 — kHzMin. ∆ F 2max(for at least99.9% of all ∆ F 2max)— 217.6 — kHzIn-band emissions± 2 MHz offset — –28 — dBm± 3 MHz offset — –36 — dBm> ± 3 MHz offset — –39 — dBmEspressif Systems 74Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 6 RF Characteristics6.2.2 Bluetooth LE RF Receiver (RX) CharacteristicsTable 6-12. Bluetooth LE - Receiver Characteristics - 1 MbpsParameter Description Min Typ Max UnitSensitivity @30.8% PER — — –98.5 — dBmMaximum received signal @30.8% PER — — 8 — dBmC/I and receiverselectivity performanceCo-channel F = F0 MHz — 7 — dBAdjacent channelF = F0 + 1 MHz — 4 — dBF = F0 – 1 MHz — 3 — dBF = F0 + 2 MHz — –21 — dBF = F0 – 2 MHz — –22 — dBF = F0 + 3 MHz — –28 — dBF = F0 – 3 MHz — –36 — dBF ≥ F0 + 4 MHz — –27 — dBF ≤ F0 – 4 MHz — –36 — dBImage frequency — — –26 — dBAdjacent channel toimage frequencyF = Fimage+ 1 MHz — –29 — dBF = Fimage– 1 MHz — –28 — dB30 MHz ~ 2000 MHz — –16 — dBmOut-of-band blocking performance2003 MHz ~ 2399 MHz — –24 — dBm2484 MHz ~ 2997 MHz — –16 — dBm3000 MHz ~ 12.75 GHz — –1 — dBmIntermodulation — — –27 — dBmTable 6-13. Bluetooth LE - Receiver Characteristics - 2 MbpsParameter Description Min Typ Max UnitSensitivity @30.8% PER — — –95.5 — dBmMaximum received signal @30.8% PER — — 8 — dBmC/I and receiverselectivity performanceCo-channel F = F0 MHz — 8 — dBAdjacent channelF = F0 + 2 MHz — 3 — dBF = F0 – 2 MHz — 2 — dBF = F0 + 4 MHz — –23 — dBF = F0 – 4 MHz — –25 — dBF = F0 + 6 MHz — –31 — dBF = F0 – 6 MHz — –35 — dBF ≥ F0 + 8 MHz — –36 — dBF ≤ F0 – 8 MHz — –36 — dBImage frequency — — –23 — dBAdjacent channel toimage frequencyF = Fimage+ 2 MHz — –30 — dBF = Fimage– 2 MHz — 3 — dB30 MHz ~ 2000 MHz — –18 — dBmOut-of-band blocking performance2003 MHz ~ 2399 MHz — –28 — dBm2484 MHz ~ 2997 MHz — –16 — dBmCont’d on next pageEspressif Systems 75Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 6 RF CharacteristicsTable 6-13 – cont’d from previous pageParameter Description Min Typ Max Unit3000 MHz ~ 12.75 GHz — –1 — dBmIntermodulation — — –29 — dBmTable 6-14. Bluetooth LE - Receiver Characteristics - 125 KbpsParameter Description Min Typ Max UnitSensitivity @30.8% PER — — –106.0 — dBmMaximum received signal @30.8% PER — — 8 — dBmC/I and receiverselectivity performanceCo-channel F = F0 MHz — 2 — dBAdjacent channelF = F0 + 1 MHz — –1 — dBF = F0 – 1 MHz — –3 — dBF = F0 + 2 MHz — –31 — dBF = F0 – 2 MHz — –27 — dBF = F0 + 3 MHz — –33 — dBF = F0 – 3 MHz — –42 — dBF ≥ F0 + 4 MHz — –31 — dBF ≤ F0 – 4 MHz — –48 — dBImage frequency — — –31 — dBAdjacent channel toimage frequencyF = Fimage+ 1 MHz — –36 — dBF = Fimage– 1 MHz — –33 — dBTable 6-15. Bluetooth LE - Receiver Characteristics - 500 KbpsParameter Description Min Typ Max UnitSensitivity @30.8% PER — — –102.0 — dBmMaximum received signal @30.8% PER — — 8 — dBmC/I and receiverselectivity performanceCo-channel F = F0 MHz — 4 — dBAdjacent channelF = F0 + 1 MHz — 1 — dBF = F0 – 1 MHz — –1 — dBF = F0 + 2 MHz — –23 — dBF = F0 – 2 MHz — –24 — dBF = F0 + 3 MHz — –33 — dBF = F0 – 3 MHz — –41 — dBF ≥ F0 + 4 MHz — –31 — dBF ≤ F0 – 4 MHz — –41 — dBImage frequency — — –30 — dBAdjacent channel toimage frequencyF = Fimage+ 1 MHz — –35 — dBF = Fimage– 1 MHz — –27 — dBEspressif Systems 76Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 6 RF Characteristics6.3 802.15.4 RadioTable 6-16. 802.15.4 RF CharacteristicsName DescriptionCenter frequency range of operating channel 2405 ~ 2480 MHz1Zigbee in the 2.4 GHz range supports 16 channels at 5 MHz spacing fromchannel 11 to channel 26.6.3.1 802.15.4 RF Transmitter (TX) CharacteristicsTable 6-17. 802.15.4 Transmitter Characteristics - 250 KbpsParameter Min Typ Max UnitRF transmit power range –15.0 — 20.0 dBmEVM — 13.0% — —6.3.2 802.15.4 RF Receiver (RX) CharacteristicsTable 6-18. 802.15.4 Receiver Characteristics - 250 KbpsParameter Description Min Typ Max UnitSensitivity @1% PER — — –104.0 — dBmMaximum received signal @1% PER — — 8 — dBmRelative jamming levelAdjacent channelF = F0 + 5 MHz — 27 — dBF = F0 – 5 MHz — 32 — dBAlternate channelF = F0 + 10 MHz — 47 — dBF = F0 – 10 MHz — 50 — dBEspressif Systems 77Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 7 Packaging7 Packaging• For information about tape, reel, and chip marking, please refer to ESP32-C6 Chip Packaging Information.• The pins of the chip are numbered in anti-clockwise order starting from Pin 1 in the top view. For pinnumbers and pin names, see also Figure 2-1 ESP32-C6 Pin Layout (QFN40, Top View) and Figure 2-2ESP32-C6 Pin Layout (QFN32, Top View).• The recommended land pattern source file (asc) is available for download. You can import the file withsoftware such as PADS and Altium Designer.40L SLP (5x5MM) TOP VIEw  A □□L   ° ,----------,-,fr-lr--r-+----,L j L  j BOTTOM VIEw ! Lc:=:==:JSIDE VIEw  t Figure 7-1. QFN40 (5×5 mm) PackageFigure 7-2. QFN32 (5×5 mm) PackageEspressif Systems 78Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 ESP32-C6 Consolidated Pin OverviewESP32-C6 Consolidated Pin OverviewTable 7-1. QFN40 Pin OverviewPin Pin Pin Pin Providing Pin Settings Analog Function LP IO MUX Function IO MUX FunctionNo. Name Type Power At Reset After Reset 0 1 0 1 0 Type 1 Type 2 Type1 ANT Analog2 VDDA3P3 Power3 VDDA3P3 Power4 CHIP_PU Analog5 VDDPST1 Power6 XTAL_32K_P IO VDDPST1 XTAL_32K_P ADC1_CH0 LP_GPIO0 LP_UART_DTRN GPIO0 I/O/T GPIO0 I/O/T7 XTAL_32K_N IO VDDPST1 XTAL_32K_N ADC1_CH1 LP_GPIO1 LP_UART_DSRN GPIO1 I/O/T GPIO1 I/O/T8 GPIO2 IO VDDPST1 IE IE ADC1_CH2 LP_GPIO2 LP_UART_RTSN GPIO2 I/O/T GPIO2 I/O/T FSPIQ I1/O/T9 GPIO3 IO VDDPST1 IE IE ADC1_CH3 LP_GPIO3 LP_UART_CTSN GPIO3 I/O/T GPIO3 I/O/T10 MTMS IO VDDPST1 IE IE ADC1_CH4 LP_GPIO4 LP_UART_RXD MTMS I1 GPIO4 I/O/T FSPIHD I1/O/T11 MTDI IO VDDPST1 IE IE ADC1_CH5 LP_GPIO5 LP_UART_TXD MTDI I1 GPIO5 I/O/T FSPIWP I1/O/T12 MTCK IO VDDPST1 IE, WPU ADC1_CH6 LP_GPIO6 LP_I2C_SDA MTCK I1 GPIO6 I/O/T FSPICLK I1/O/T13 MTDO IO VDDPST1 IE LP_GPIO7 LP_I2C_SCL MTDO O/T GPIO7 I/O/T FSPID I1/O/T14 GPIO8 IO VDDPST2 IE IE GPIO8 I/O/T GPIO8 I/O/T15 GPIO9 IO VDDPST2 IE, WPU IE, WPU GPIO9 I/O/T GPIO9 I/O/T16 GPIO10 IO VDDPST2 IE GPIO10 I/O/T GPIO10 I/O/T17 GPIO11 IO VDDPST2 IE GPIO11 I/O/T GPIO11 I/O/T18 GPIO12 IO VDDPST2 IE USB_D- GPIO12 I/O/T GPIO12 I/O/T19 GPIO13 IO VDDPST2 IE, WPU USB_D+ GPIO13 I/O/T GPIO13 I/O/T20 SPICS0 IO VDD_SPI WPU IE, WPU SPICS0 O/T GPIO24 I/O/T21 SPIQ IO VDD_SPI WPU IE, WPU SPIQ I1/O/T GPIO25 I/O/T22 SPIWP IO VDD_SPI WPU IE, WPU SPIWP I1/O/T GPIO26 I/O/T23 VDD_SPI Power/IO — VDD_SPI GPIO27 I/O/T GPIO27 I/O/T24 SPIHD IO VDD_SPI WPU IE, WPU SPIHD I1/O/T GPIO28 I/O/T25 SPICLK IO VDD_SPI WPU IE, WPU SPICLK O/T GPIO29 I/O/T26 SPID IO VDD_SPI WPU IE, WPU SPID I1/O/T GPIO30 I/O/T27 GPIO15 IO VDDPST2 IE IE GPIO15 I/O/T GPIO15 I/O/T28 VDDPST2 Power29 U0TXD IO VDDPST2 WPU U0TXD O GPIO16 I/O/T FSPICS0 I1/O/T30 U0RXD IO VDDPST2 IE, WPU U0RXD I1 GPIO17 I/O/T FSPICS1 O/T31 SDIO_CMD IO VDDPST2 WPU IE SDIO_CMD I1/O/T GPIO18 I/O/T FSPICS2 O/T32 SDIO_CLK IO VDDPST2 WPU IE SDIO_CLK I1 GPIO19 I/O/T FSPICS3 O/T33 SDIO_DATA0 IO VDDPST2 WPU IE SDIO_DATA0 I1/O/T GPIO20 I/O/T FSPICS4 O/T34 SDIO_DATA1 IO VDDPST2 WPU IE SDIO_DATA1 I1/O/T GPIO21 I/O/T FSPICS5 O/T35 SDIO_DATA2 IO VDDPST2 WPU IE SDIO_DATA2 I1/O/T GPIO22 I/O/T36 SDIO_DATA3 IO VDDPST2 WPU IE SDIO_DATA3 I1/O/T GPIO23 I/O/T37 VDDA1 Power38 XTAL_N Analog39 XTAL_P Analog40 VDDA2 Power41 GND Power*For details, see Section 2 Pins. Regarding highlighted cells, see Section 2.3.4 Restrictions for GPIOs and LP GPIOs.Espressif Systems 79Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 ESP32-C6 Consolidated Pin OverviewTable 7-2. QFN32 Pin OverviewPin Pin Pin Pin Providing Pin Settings Analog Function LP IO MUX Function IO MUX FunctionNo. Name Type Power At Reset After Reset 0 1 0 1 0 Type 1 Type 2 Type1 ANT Analog2 VDDA3P3 Power3 VDDA3P3 Power4 CHIP_PU Analog5 VDDPST1 Power6 XTAL_32K_P IO VDDPST1 XTAL_32K_P ADC1_CH0 LP_GPIO0 LP_UART_DTRN GPIO0 I/O/T GPIO0 I/O/T7 XTAL_32K_N IO VDDPST1 XTAL_32K_N ADC1_CH1 LP_GPIO1 LP_UART_DSRN GPIO1 I/O/T GPIO1 I/O/T8 GPIO2 IO VDDPST1 IE IE ADC1_CH2 LP_GPIO2 LP_UART_RTSN GPIO2 I/O/T GPIO2 I/O/T FSPIQ I1/O/T9 GPIO3 IO VDDPST1 IE IE ADC1_CH3 LP_GPIO3 LP_UART_CTSN GPIO3 I/O/T GPIO3 I/O/T10 MTMS IO VDDPST1 IE IE ADC1_CH4 LP_GPIO4 LP_UART_RXD MTMS I1 GPIO4 I/O/T FSPIHD I1/O/T11 MTDI IO VDDPST1 IE IE ADC1_CH5 LP_GPIO5 LP_UART_TXD MTDI I1 GPIO5 I/O/T FSPIWP I1/O/T12 MTCK IO VDDPST1 IE, WPU ADC1_CH6 LP_GPIO6 LP_I2C_SDA MTCK I1 GPIO6 I/O/T FSPICLK I1/O/T13 MTDO IO VDDPST1 IE LP_GPIO7 LP_I2C_SCL MTDO O/T GPIO7 I/O/T FSPID I1/O/T14 GPIO8 IO VDDPST2 IE IE GPIO8 I/O/T GPIO8 I/O/T15 GPIO9 IO VDDPST2 IE, WPU IE, WPU GPIO9 I/O/T GPIO9 I/O/T16 GPIO12 IO VDDPST2 IE USB_D- GPIO12 I/O/T GPIO12 I/O/T17 GPIO13 IO VDDPST2 IE, WPU USB_D+ GPIO13 I/O/T GPIO13 I/O/T18 GPIO14 IO VDDPST2 IE GPIO14 I/O/T GPIO14 I/O/T19 GPIO15 IO VDDPST2 IE IE GPIO15 I/O/T GPIO15 I/O/T20 VDDPST2 Power21 U0TXD IO VDDPST2 WPU U0TXD O GPIO16 I/O/T FSPICS0 I1/O/T22 U0RXD IO VDDPST2 IE, WPU U0RXD I1 GPIO17 I/O/T FSPICS1 O/T23 SDIO_CMD IO VDDPST2 WPU IE SDIO_CMD I1/O/T GPIO18 I/O/T FSPICS2 O/T24 SDIO_CLK IO VDDPST2 WPU IE SDIO_CLK I1 GPIO19 I/O/T FSPICS3 O/T25 SDIO_DATA0 IO VDDPST2 WPU IE SDIO_DATA0 I1/O/T GPIO20 I/O/T FSPICS4 O/T26 SDIO_DATA1 IO VDDPST2 WPU IE SDIO_DATA1 I1/O/T GPIO21 I/O/T FSPICS5 O/T27 SDIO_DATA2 IO VDDPST2 WPU IE SDIO_DATA2 I1/O/T GPIO22 I/O/T28 SDIO_DATA3 IO VDDPST2 WPU IE SDIO_DATA3 I1/O/T GPIO23 I/O/T29 VDDA1 Power30 XTAL_N Analog31 XTAL_P Analog32 VDDA2 Power33 GND Power*For details, see Section 2 Pins. Regarding highlighted cells, see Section 2.3.4 Restrictions for GPIOs and LP GPIOs.Espressif Systems 80Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 Datasheet VersioningDatasheet VersioningDatasheetVersionStatus Watermark Definitionv0.1 ~ v0.5(excluding v0.5)Draft ConfidentialThis datasheet is under development for products inthe design stage. Specifications may change withoutprior notice.v0.5 ~ v1.0(excluding v1.0)PreliminaryreleasePreliminaryThis datasheet is actively updated for products in theverification stage. Specifications may change beforemass production, and the changes will bedocumentation in the datasheet’s Revision History.v1.0 and higher Official release —This datasheet is publicly released for products inmass production. Specifications are finalized, andmajor changes will be communicated via ProductChange Notifications (PCN).Any version —NotRecommendedfor New Design(NRND)1This datasheet is updated less frequently forproducts not recommended for new designs.Any version —End of Life(EOL)2This datasheet is no longer mtained for products thathave reached end of life.1Watermark will be added to the datasheet title page only when all the product variants covered by this datasheetare not recommended for new designs.2Watermark will be added to the datasheet title page only when all the product variants covered by this datasheethave reached end of life.Espressif Systems 81Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 GlossaryGlossarymoduleA self-contained unit integrated within the chip to extend its capabilities, such as cryptographic modules,RF modules 2peripheralA hardware component or subsystem within the chip to interface with the outside world 2off-package flashFlash external to the chip’s package 4, 32, 40in-package flashFlash integrated directly into the chip’s package, and external to the chip die 32strapping pinA type of GPIO pin used to configure certain operational settings during the chip’s power-up, and can bereconfigured as normal GPIO after the chip’s reset 33eFuse parameterA parameter stored in an electrically programmable fuse (eFuse) memory within a chip. The parameter canbe set by programming EFUSE_PGM_DATAn_REG registers, and read by reading a register field namedafter the parameter 33SPI boot modeA boot mode in which users load and execute the existing code from SPI flash 34joint download boot modeA boot mode in which users can download code into flash via the UART or other interfaces (see Table 3-3Chip Boot Mode Control > Note), and load and execute the downloaded code from the flash or SRAM 34eFuseA one-time programmable (OTP) memory which stores system and user parameters, such as MACaddress, chip revision number, flash encryption key, etc. Value 0 indicates the default state, and value 1indicates the eFuse has been programmed 40Espressif Systems 82Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 Related Documentation and ResourcesRelated Documentation and ResourcesRelated Documentation• ESP32-C6 Technical Reference Manual – Detailed information on how to use the ESP32-C6 memory and peripherals.• ESP32-C6 Hardware Design Guidelines – Guidelines on how to integrate the ESP32-C6 into your hardware product.• ESP32-C6 Series SoC Errata – Descriptions of known errors in ESP32-C6 series of SoCs.• Certificateshttps://espressif.com/en/support/documents/certificates• ESP32-C6 Product/Process Change Notifications (PCN)https://espressif.com/en/support/documents/pcns?keys=ESP32-C6• Documentation Updates and Update Notification Subscriptionhttps://espressif.com/en/support/download/documentsDeveloper Zone• ESP-IDF Programming Guide for ESP32-C6 – Extensive documentation for the ESP-IDF development framework.• ESP-IDF and other development frameworks on GitHub.https://github.com/espressif• ESP32 BBS Forum – Engineer-to-Engineer (E2E) Community for Espressif products where you can post questions,share knowledge, explore ideas, and help solve problems with fellow engineers.https://esp32.com/• ESP-FAQ – A summary document of frequently asked questions released by Espressif.https://espressif.com/projects/esp-faq/en/latest/index.html• The ESP Journal – Best Practices, Articles, and Notes from Espressif folks.https://blog.espressif.com/• See the tabs SDKs and Demos, Apps, Tools, AT Firmware.https://espressif.com/en/support/download/sdks-demosProducts• ESP32-C6 Series SoCs – Browse through all ESP32-C6 SoCs.https://espressif.com/en/products/socs?id=ESP32-C6• ESP32-C6 Series Modules – Browse through all ESP32-C6-based modules.https://espressif.com/en/products/modules?id=ESP32-C6• ESP32-C6 Series DevKits – Browse through all ESP32-C6-based devkits.https://espressif.com/en/products/devkits?id=ESP32-C6• ESP Product Selector – Find an Espressif hardware product suitable for your needs by comparing or applying filters.https://products.espressif.com/#/product-selector?language=enContact Us• See the tabs Sales Questions, Technical Enquiries, Circuit Schematic & PCB Design Review, Get Samples(Online stores), Become Our Supplier, Comments & Suggestions.https://espressif.com/en/contact-us/sales-questionsEspressif Systems 83Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 Revision HistoryRevision HistoryDate Version Release notes2025-11-20 v1.4• Updated ”Ordering Code” to ”Part Number” in Table 1-1 ESP32-C6 SeriesComparison• Added Section 1.3 Chip Revision• Added a note about USB pin swapping to Table 2-10 QFN40 Peripheral PinAssignment and Table 2-11 QFN32 Peripheral Pin Assignment• Added Section 5.7 Memory Specifications• Deleted TSLP related information from QFN40 package diagram in Chapter7 Packaging• Added Appendix Datasheet Versioning• Other minor updates2025-03-21 v1.3• Updated CPU CoreMark®scode in Section Product Overview• Added Section 2.3.5 Peripheral Pin Assignment• According to AR2024-011, removed ”32 kHz internal slow RC oscillator”in Section 4.1.3.3 Clock2024-08-23 v1.2 Added the ESP32-C6FH8 variant2024-05-10 v1.1• Updated CPU CoreMark®scode in Section Product Overview• Added flash erase cycles, retention time, maximum clock frequency in Sec-tion 4.1.2.1 Internal Memory• Updated cumulative IO output current in Table 5-1 Absolute Maximum Rat-ings• Updated the value of RSP Iin Table 5-3 VDD_SPI Internal and Output Char-acteristics• Added links and descriptions of PCB land pattern in Section 7 Packaging• Added Section Glossary• Improved the formatting, structure, and wording in the following sections:– Section 2 Pins– Section 3 Boot Configurations (used to be named as “Strapping Pins”)– Section 4 Functional Description• Other minor updatesCont’d on next pageEspressif Systems 84Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 Revision HistoryCont’d from previous pageDate Version Release notes2023-07-25 v1.0• Added descriptions of USB_PU in Table 2-4 QFN40 IO MUX Pin Functionsand Table 2-5 QFN32 IO MUX Pin Functions, note 4• Updated Section 3.3 ROM Messages Printing Control• Added Section 5.5 ADC Characteristics• Updated the measurement conditions in Table 5-8 Current Consumption forBluetooth LE in Active Mode and Table 5-9 Current Consumption for 802.15.4in Active Mode from –24.0 dBm to –15.0 dBm, and the corresponding peakvalues• Added Section 5.8 Reliability• Updated the minimum value of RF transmit power range to –15.0 dBm inTable 6-7 Bluetooth LE RF Characteristics and Table 6-17 802.15.4 Trans-mitter Characteristics - 250 Kbps• Updated Related Documentation and Resources• Other minor changes2023-01-16 v0.5Preliminary releaseEspressif Systems 85Submit Documentation FeedbackESP32-C6 Series Datasheet v1.4 Disclaimer and Copyright NoticeInformation in this document, including URL references, is subject to change without notice.ALL THIRD PARTY’S INFORMATION IN THIS DOCUMENT IS PROVIDED AS IS WITH NO WARRANTIES TO ITS AUTHENTICITY ANDACCURACY.NO WARRANTY IS PROVIDED TO THIS DOCUMENT FOR ITS MERCHANTABILITY, NON-INFRINGEMENT, FITNESS FOR ANYPARTICULAR PURPOSE, NOR DOES ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE.All liability, including liability for infringement of any proprietary rights, relating to use of information in this document is disclaimed. No licensesexpress or implied, by estoppel or otherwise, to any intellectual property rights are granted herein.The Wi-Fi Alliance Member logo is a trademark of the Wi-Fi Alliance. The Bluetooth logo is a registered trademark of Bluetooth SIG.All trade names, trademarks and registered trademarks mentioned in this document are property of their respective owners, and are herebyacknowledged.Copyright © 2025 Espressif Systems (Shanghai) Co., Ltd. All rights reserved.www.espressif.com