Product OverviewFeaturesApplications1 ESP32-C61 Series Comparison1.1 Nomenclature1.2 Comparison2 Pins2.1 Pin Layout2.2 Pin Overview2.3 IO Pins2.3.1 IO MUX Functions2.3.2 LP IO MUX Functions2.3.3 Analog Functions2.3.4 Restrictions for GPIOs and LP GPIOs2.4 Analog Pins2.5 Power Supply2.5.1 Power Pins2.5.2 Power Scheme2.5.3 Chip Power-up and Reset2.6 Pin Mapping Between Chip and Flash/PSRAM3 Boot Configurations3.1 Chip Boot Mode Control3.2 SDIO Sampling and Driving Clock Edge Control3.3 ROM Messages Printing Control3.4 JTAG Signal Source Control4 Functional Description4.1 System4.1.1 Microprocessor and Master4.1.2 Memory Organization4.1.3 System Components4.1.4 Cryptography and Security Component4.2 Peripherals4.2.1 Connectivity Interface4.2.2 Analog Signal Processing4.3 Wireless Communication4.3.1 Radio4.3.2 Wi-Fi4.3.3 Bluetooth LE5 Electrical Characteristics5.1 Absolute Maximum Ratings5.2 Recommended Operating Conditions5.3 VDD_SPI Output Characteristics5.4 ADC Characteristics5.5 Current Consumption Characteristics5.5.1 Current Consumption in Active Mode5.5.2 Current Consumption in Other Modes5.6 Memory Specifications5.7 Reliability6 RF Characteristics6.1 Wi-Fi Radio (2.4 GHz)6.1.1 Wi-Fi RF Transmitter (TX) Characteristics6.1.2 Wi-Fi RF Receiver (RX) Characteristics6.2 Bluetooth 5 (LE) Radio6.2.1 Bluetooth LE RF Transmitter (TX) Characteristics6.2.2 Bluetooth LE RF Receiver (RX) Characteristics7 PackagingRelated Documentation and ResourcesAppendix A – ESP32-C61 Consolidated Pin OverviewRevision History ESP32-C61 SeriesDatasheet v1.032-bit RISC-V single-core microprocessor2.4 GHz Wi-Fi 6 (IEEE 802.11ax)Bluetooth®5 (LE)3.3 V flash or PSRAM in the chip’s package30 GPIOsQFN40 (5×5 mm) or LGA40 (5×5 mm) PackageIncluding:ESP32-C61HF4ESP32-C61HR2ESP32-C61HR8ESP32-C61NF8R8LAwww.espressif.com Product OverviewESP32-C61 is a low-power MCU-based system on a chip (SoC). ESP32-C61 integrates 2.4 GHz Wi-Fi 6 andBluetooth®Low Energy (Bluetooth LE). ESP32-C61 consists of a 32-bit RISC-V single-core microprocessor, aWi-Fi baseband, a Bluetooth LE baseband, RF module, and numerous peripherals.The functional block diagram of the SoC is shown below.CPU SystemWireless MAC and BasebandWi-Fi MAC Bluetooth LE Link ControllerBluetooth LE Baseband2.4 GHz Balun + Switch2.4 GHz Receiver2.4 GHz TransmitterRF SynthesizerRFSecurityRISC-V 32-bitMicroprocessorJTAGPeripherals Espressif’s ESP32-C61 Wi-Fi + Bluetooth® Low Energy SoCSRAMPMUPower ManagementSecure Boot⚙SHA⚙ROMTRNG⚙Modules having power in specific power modes:ActiveActive and Modem-sleepActive, Modem-sleep, Light-sleep; optional in Light-sleep⚙All modes⚙optional in Deep-sleepECC⚙APM⚙Digital Signature - ECDSA⚙CacheTemperature Sensor⚙General-Purpose SPI⚙General-Purpose Timers⚙Main System Watchdog Timers⚙RTC Watchdog TimereFuse ControllerSuper WatchdogLP IO⚙GPIOUARTI2CADCSystem TimerGDMALED PWM⚙⚙⚙⚙⚙⚙⚙I2S⚙USB Serial/JTAG⚙Brown-out Detector⚙Analog Voltage Comparator⚙ETM⚙Power Glitch DetectorWi-Fi BasebandSDIO 2.0 Slave⚙Flash/PSRAM Encryption(XTS-AES)⚙ESP32-C61 Functional Block DiagramFor more information on power consumption, see Section 4.1.3.7 Power Management Unit.Espressif Systems 2 ESP32-C61 Series Datasheet v1.0 FeaturesWi-Fi• 1T1R in 2.4 GHz single band• Operating frequency: 2412 ~ 2484 MHz• IEEE 802.11ax-compliant– 20 MHz-only non-AP mode– Uplink and downlink OFDMA to enhance connectivity and performance in congested environments forIoT applications– Downlink MU-MIMO (multi-user, multiple input, multiple output) to increase network capacity– Beamformee that improves signal quality– Spatial reuse to maximize parallel transmissions– Target wake time (TWT) that optimizes power saving mechanisms• Fully compatible with IEEE 802.11b/g/n protocol– 20 MHz and 40 MHz bandwidth– Data rate up to 150 Mbps– Wi-Fi Multimedia (WMM)– TX/RX A-MPDU, TX/RX A-MSDU– Immediate Block ACK– Fragmentation and defragmentation– Transmission opportunity (TXOP)– Automatic Beacon monitoring (hardware TSF)– Four virtual Wi-Fi interfaces– Simultaneous support for Infrastructure BSS in Station mode, SoftAP mode, Station + SoftAP mode,and promiscuous modeNote that when ESP32-C61 scans in Station mode, the SoftAP channel will change along with the Stationchannel– Antenna diversity– 802.11mc FTMBluetooth®• Bluetooth LE: Bluetooth Core 6.0 certified• Bluetooth mesh 1.1• High power mode (20 dBm)• Direction finding (AoA/AoD)Espressif Systems 3 ESP32-C61 Series Datasheet v1.0 • Periodic advertising with responses (PAwR)• LE connection subrating• LE power control• Speed: 125 Kbps, 500 Kbps, 1 Mbps, 2 Mbps• LE advertising extensions and multiple advertising sets• Allow devices to operate in Broadcaster, Observer, Central, and Peripheral roles concurrentlyCPU and Memory• 32-bit RISC-V single-core processor:– Clock speed: up to 160 MHz– CoreMark®score at 160 MHz: 553.78 CoreMark; 3.46 CoreMark/MHz (O3)– Five-stage pipeline• L1 cache (32 KB)• ROM: 256 KB• SRAM: 320 KB• Supported SPI protocols: SPI, Dual SPI, Quad SPI, and QPI interfaces that allow connection to flash,external RAM, and other SPI devices• Flash/external RAM controller with cache is supported• Flash in-Circuit Programming (ICP) is supportedAdvanced Peripheral Interfaces• 30 programmable GPIOs– Five strapping GPIOs• Digital interfaces:– Two SPI ports for communication with flash and PSRAM– General-purpose SPI port– Three UART– I2C– I2S– LED PWM controller, up to 6 channels– USB Serial/JTAG controller– SDIO 2.0 slave controller– General DMA controller, with 2 transmit channels and 2 receive channels– On-chip debug functionality via JTAGEspressif Systems 4 ESP32-C61 Series Datasheet v1.0 – Event task matrix (ETM)• Analog interfaces:– 12-bit SAR ADC, up to 4 channels– Temperature sensor– Brown-out detector– Analog voltage comparator• Timers:– Two 54-bit general-purpose timers– 52-bit system timer– Two main system watchdog timers– Three watchdog timersPower Management• Fine-resolution power control through a selection of clock frequency, duty cycle, Wi-Fi operating modes,and individual power control of internal components• Four power modes designed for typical scenarios: Active, Modem-sleep, Light-sleep, Deep-sleep• Power consumption in Deep-sleep mode is 10 µASecurity• Secure boot - permission control on accessing internal and external memory• Flash and PSRAM encryption - external memory encryption and decryption• 4096-bit OTP, up to 1792 bits for users• Cryptographic hardware acceleration:– Hash (FIPS PUB 180-4)– ECC (Curve P-192 and curve P-256 defined in FIPS 186-3 are supported)– Elliptic curve digital signature algorithm (ECDSA)• True random number generator (TRNG)• Power glitch detectorRF Module• Antenna switches, RF balun, power amplifier, low-noise receive amplifier• Up to +19.5 dBm of power for an 802.11ax transmission• Up to +21 dBm of power for an 802.11b transmission• Up to –106 dBm receiver sensitivity for Bluetooth LE (125 Kbps)Espressif Systems 5 ESP32-C61 Series Datasheet v1.0 ApplicationsWith low power consumption, ESP32-C61 is an ideal choice for IoT devices in the following areas:• Smart Home• Industrial Automation• Health Care• Consumer Electronics• Smart Agriculture• POS Machines• Service Robot• Audio Devices• Generic Low-power IoT Sensor Hubs• Generic Low-power IoT Data LoggersEspressif Systems 6 ESP32-C61 Series Datasheet v1.0 ContentsContentsProduct Overview 2Features 3Applications 61 ESP32-C61 Series Comparison 131.1 Nomenclature 131.2 Comparison 132 Pins 142.1 Pin Layout 142.2 Pin Overview 162.3 IO Pins 182.3.1 IO MUX Functions 182.3.2 LP IO MUX Functions 202.3.3 Analog Functions 212.3.4 Restrictions for GPIOs and LP GPIOs 222.4 Analog Pins 232.5 Power Supply 242.5.1 Power Pins 242.5.2 Power Scheme 242.5.3 Chip Power-up and Reset 252.6 Pin Mapping Between Chip and Flash/PSRAM 263 Boot Configurations 283.1 Chip Boot Mode Control 293.2 SDIO Sampling and Driving Clock Edge Control 303.3 ROM Messages Printing Control 303.4 JTAG Signal Source Control 314 Functional Description 324.1 System 324.1.1 Microprocessor and Master 324.1.1.1 High-Performance CPU 324.1.1.2 RISC-V Trace Encoder 334.1.1.3 GDMA Controller 334.1.2 Memory Organization 334.1.2.1 Internal Memory 344.1.2.2 External Memory 354.1.2.3 eFuse Controller 354.1.3 System Components 354.1.3.1 IO MUX and GPIO Matrix 364.1.3.2 Reset 364.1.3.3 Clock 36Espressif Systems 7 ESP32-C61 Series Datasheet v1.0 Contents4.1.3.4 Interrupt Matrix 374.1.3.5 Event Task Matrix 374.1.3.6 System Timer 384.1.3.7 Power Management Unit 384.1.3.8 Brownout Detector 404.1.3.9 RTC Timer 404.1.3.10 Timer Group 404.1.3.11 Watchdog Timers 414.1.3.12 Permission Control 414.1.3.13 System Registers 414.1.3.14 Debug Assistant 424.1.4 Cryptography and Security Component 424.1.4.1 ECC Accelerator 424.1.4.2 Elliptic Curve Digital Signature Algorithm (ECDSA) 424.1.4.3 SHA Accelerator 434.1.4.4 External Memory Encryption and Decryption 434.1.4.5 True Random Number Generator 444.1.4.6 Power Glitch Detector 444.2 Peripherals 454.2.1 Connectivity Interface 454.2.1.1 UART Controller 454.2.1.2 SPI Controller 454.2.1.3 I2C Controller 464.2.1.4 I2S Controller 474.2.1.5 USB Serial/JTAG Controller 474.2.1.6 LED PWM Controller 484.2.1.7 SDIO Slave Controller 484.2.2 Analog Signal Processing 494.2.2.1 SAR ADC 494.2.2.2 Temperature Sensor 504.2.2.3 Analog Voltage Comparator 504.3 Wireless Communication 514.3.1 Radio 514.3.1.1 2.4 GHz Receiver 514.3.1.2 2.4 GHz Transmitter 514.3.1.3 Clock Generator 514.3.2 Wi-Fi 514.3.2.1 Wi-Fi Radio and Baseband 524.3.2.2 Wi-Fi MAC 524.3.2.3 Networking Features 534.3.3 Bluetooth LE 534.3.3.1 Bluetooth LE PHY 534.3.3.2 Bluetooth LE Link Controller 545 Electrical Characteristics 555.1 Absolute Maximum Ratings 55Espressif Systems 8 ESP32-C61 Series Datasheet v1.0 Contents5.2 Recommended Operating Conditions 555.3 VDD_SPI Output Characteristics 565.4 ADC Characteristics 565.5 Current Consumption Characteristics 565.5.1 Current Consumption in Active Mode 565.5.2 Current Consumption in Other Modes 575.6 Memory Specifications 585.7 Reliability 586 RF Characteristics 606.1 Wi-Fi Radio (2.4 GHz) 606.1.1 Wi-Fi RF Transmitter (TX) Characteristics 606.1.2 Wi-Fi RF Receiver (RX) Characteristics 616.2 Bluetooth 5 (LE) Radio 636.2.1 Bluetooth LE RF Transmitter (TX) Characteristics 636.2.2 Bluetooth LE RF Receiver (RX) Characteristics 647 Packaging 67Related Documentation and Resources 69Appendix A – ESP32-C61 Consolidated Pin Overview 70Revision History 71Espressif Systems 9 ESP32-C61 Series Datasheet v1.0 List of TablesList of Tables1-1 ESP32-C61 Series Comparison 132-1 ESP32-C61 Pin Overview 162-2 Peripheral Signals Routed via IO MUX 182-3 IO MUX Pin Functions 182-4 LP IO MUX Functions 202-5 Analog Signals Routed to Analog Functions 212-6 Analog Functions 212-7 Analog Pins 232-8 Power Pins 242-9 Voltage Regulators 242-10 Description of Timing Parameters for Power-up and Reset 252-11 Pin Mapping Between Chip and Off-Package Flash for ESP32-C611262-12 Pin Mapping Between Chip and Off-Package PSRAM1273-1 Default Configuration of Strapping Pins 283-2 Description of Timing Parameters for the Strapping Pins 293-3 Chip Boot Mode Control 293-4 SDIO Input Sampling Edge/Output Driving Edge Control 303-5 UART0 ROM Message Printing Control 303-6 USB Serial/JTAG ROM Message Printing Control 313-7 JTAG Signal Source Control 315-1 Absolute Maximum Ratings 555-2 Recommended Operating Conditions 555-3 VDD_SPI Internal and Output Characteristics 565-4 ADC Characteristics 565-5 ADC Calibration Results 565-6 Current Consumption for Wi-Fi (2.4 GHz) in Active Mode 575-7 Current Consumption for Bluetooth LE in Active Mode 575-8 Current Consumption in Modem-sleep Mode 575-9 Current Consumption in Low-Power Modes 585-10 Flash Specifications 585-11 PSRAM Specifications 585-12 Reliability Qualifications 596-1 Wi-Fi RF Characteristics 606-2 TX Power with Spectral Mask and EVM Meeting 802.11 Standards 606-3 TX EVM Test1606-4 RX Sensitivity 616-5 Maximum RX Level 626-6 RX Adjacent Channel Rejection 626-7 Bluetooth LE RF Characteristics 636-8 Bluetooth LE - Transmitter Characteristics - 1 Mbps 636-9 Bluetooth LE - Transmitter Characteristics - 2 Mbps 636-10 Bluetooth LE - Transmitter Characteristics - 125 Kbps 646-11 Bluetooth LE - Transmitter Characteristics - 500 Kbps 64Espressif Systems 10 ESP32-C61 Series Datasheet v1.0 List of Tables6-12 Bluetooth LE - Receiver Characteristics - 1 Mbps 646-13 Bluetooth LE - Receiver Characteristics - 2 Mbps 656-14 Bluetooth LE - Receiver Characteristics - 125 Kbps 666-15 Bluetooth LE - Receiver Characteristics - 500 Kbps 667-1 Pin Overview 70Espressif Systems 11 ESP32-C61 Series Datasheet v1.0 List of FiguresList of Figures1-1 ESP32-C61 Series Nomenclature 132-1 ESP32-C61HR2 & ESP32-C61HR8 & ESP32-C61HF4 Pin Layout (Top View) 142-2 ESP32-C61NF8R8LA Pin Layout (Top View) 152-3 ESP32-C61 Power Scheme 252-4 Visualization of Timing Parameters for Power-up and Reset 253-1 Visualization of Timing Parameters for the Strapping Pins 294-1 Address Mapping Structure 344-2 Components and Power Domains 394-3 Components and Power Domains Table 397-1 QFN40 (5×5 mm) Package 677-2 LGA40 (5×5 mm) Package 68Espressif Systems 12 ESP32-C61 Series Datasheet v1.0 1 ESP32-C61 Series Comparison1 ESP32-C61 Series Comparison1.1 NomenclatureESP32-C61H/NChip seriesx: In-package flash or PSRAM sizeF/ RAmbient temperatureH: High temperatureN: Normal temperatureF: In-package flashR: In-package PSRAMx L APackage Type (optional)L：LGA Package Package Version Code (optional)Figure 1-1. ESP32-C61 Series Nomenclature1.2 ComparisonTable 1-1. ESP32-C61 Series ComparisonPart Number In-PackageFlashIn-PackagePSRAMAmbient Temp.1Off-PackageFlashOff-PackagePSRAMESP32-C61HF4 4 MB (Quad SPI)2— –40 ∼ 105°C— —ESP32-C61HR2 — 2 MB (Quad SPI) –40 ∼ 105°CSupported —ESP32-C61HR8 — 8 MB (Quad SPI) –40 ∼ 105°CSupported —ESP32-C61NF8R8LA38 MB (Quad SPI) 8 MB (Quad SPI) –40 ∼ 85 °C — —1Ambient temperature specifies the recommended temperature range of the environment immediately outside anEspressif chip.2For details about SPI modes, see Section 2.6 Pin Mapping Between Chip and Flash/PSRAM.3This variant uses an LGA package and is not yet in mass production.Espressif Systems 13 ESP32-C61 Series Datasheet v1.0 2 Pins2 Pins2.1 Pin Layout9XTAL_32K_N40VDDA28710GPIO2MTDIMTMSSPICS0/NC2728293025SPICLK/NCSPID/NCUSB_D-USB_D+GPIO2441 GNDESP32-C6111141312SDIO_CLKSDIO_CMDMTDOMTCK232421SPIQ/NCSPIWP/NCVDD_SPI/NC22VDDPST238XTAL_N37VDDA136GPIO735GPIO2934U0TXD33U0RXD32GPIO931GPIO83213954626151918171620ANT_2GCHIP_PUVDDA4VDDA3VDDPST1XTAL_32K_PSPIHD/NCSDIO_DATA3SDIO_DATA2SDIO_DATA1SDIO_DATA0SPICS1XTAL_PFigure 2-1. ESP32-C61HR2 & ESP32-C61HR8 & ESP32-C61HF4 Pin Layout (Top View)Notice: For ESP32-C61HF4, SPICS0, SPIQ, SPIWP, VDD_SPI, SPIHD, SPICLK, and SPID pins are not connected (NC).Espressif Systems 14 ESP32-C61 Series Datasheet v1.0 2 Pins9XTAL_32K_N40VDDA28710GPIO2MTDIMTMSNC2728293025NCNCUSB_D-USB_D+GPIO2441 GNDESP32-C6111141312SDIO_CLKSDIO_CMDMTDOMTCK232421NCNCNC22VDDPST238XTAL_N37VDDA136GPIO735GPIO2934U0TXD33U0RXD32GPIO931GPIO83213954626151918171620ANT_2GCHIP_PUVDDA4VDDA3VDDPST1XTAL_32K_PNCSDIO_DATA3SDIO_DATA2SDIO_DATA1SDIO_DATA0NCXTAL_PFigure 2-2. ESP32-C61NF8R8LA Pin Layout (Top View)Espressif Systems 15 ESP32-C61 Series Datasheet v1.0 2 Pins2.2 Pin OverviewThe ESP32-C61 chip integrates multiple peripherals that require communication with the outside world. To keepthe chip package size reasonably small, the number of available pins has to be limited. So the only way to routeall the incoming and outgoing signals is through pin multiplexing. Pin muxing is controlled via softwareprogrammable registers.All in all, the ESP32-C61 chip has the following types of pins:• IO pins with the following predefined sets of functions to choose from:– Each IO pin has predefined IO MUX functions – see Table 2-3 IO MUX Functions– Some IO pins have predefined LP IO MUX functions – see Table 2-4 LP IO MUX Functions– Some IO pins have predefined analog functions – see Table 2-6 Analog FunctionsPredefined functions means that each IO pin has a set of direct connections to certain signals from on-chipperipherals. During run-time, the user can configure which peripheral signal from a predefined set toconnect to a certain pin at a certain time via memory mapped registers.• Analog pins that have exclusively-dedicated analog functions – see Table 2-7 Analog Pins• Power pins that supply power to the chip components and non-power pins – see Table 2-8 Power PinsTable 2-1 Pin Overview gives an overview of all the pins. For more information, see the respective sections foreach pin type below, or Appendix A – ESP32-C61 Consolidated Pin Overview.Table 2-1. ESP32-C61 Pin OverviewPin Pin Pin Pin Providing Pin Settings3Pin Function Sets1No. Name Type Power2At Reset After Reset IO MUX LP IO MUX Analog1 ANT_2G Analog – – – – – –2 VDDA3 Power – – – – – –3 VDDA4 Power – – – – – –4 CHIP_PU I VDDPST1 – – – – –5 VDDPST1 Power – – – – – –6 XTAL_32K_P I/O/T VDDPST1 – – IO MUX LP IO MUX Analog7 XTAL_32K_N I/O/T VDDPST1 – – IO MUX LP IO MUX Analog8 GPIO2 I/O/T VDDPST1 – – IO MUX LP IO MUX –9 MTMS I/O/T VDDPST1 IE IE IO MUX LP IO MUX Analog10 MTDI I/O/T VDDPST1 IE IE IO MUX LP IO MUX Analog11 MTCK I/O/T VDDPST1 – IE IO MUX LP IO MUX Analog12 MTDO I/O/T VDDPST1 – IE IO MUX LP IO MUX –13 SDIO_CMD I/O/T VDDPST2 – IE IO MUX – –14 SDIO_CLK I/O/T VDDPST2 – IE IO MUX – –15 SDIO_DATA0 I/O/T VDDPST2 – IE IO MUX – –16 SDIO_DATA1 I/O/T VDDPST2 – IE IO MUX – –17 SDIO_DATA2 I/O/T VDDPST2 – IE IO MUX – –18 SDIO_DATA3 I/O/T VDDPST2 – IE IO MUX – –19 SPICS15I/O/T VDD_SPI/VDDPST2 – – IO MUX – –20 SPICS04,5I/O/T VDD_SPI/VDDPST2 – – IO MUX – –Cont’d on next pageEspressif Systems 16 ESP32-C61 Series Datasheet v1.0 2 PinsTable 2-1 – cont’d from previous pagePin Pin Pin Pin Providing Pin Settings3Pin Function Sets1No. Name Type Power2At Reset After Reset IO MUX LP IO MUX Analog21 VDDPST2 Power – – – – – –22 SPIQ4,5I/O/T VDD_SPI/VDDPST2 – – IO MUX – –23 SPIWP4,5I/O/T VDD_SPI/VDDPST2 – – IO MUX – –24 VDD_SPI5Power VDDPST2 – – IO MUX – Analog25 SPIHD4,5I/O/T VDD_SPI/VDDPST2 – – IO MUX – –26 SPICLK4,5O VDD_SPI/VDDPST2 – – IO MUX – –27 SPID4,5I/O/T VDD_SPI/VDDPST2 – – IO MUX – –28 USB_D- I/O/T VDDPST2 – IE IO MUX – Analog29 USB_D+ I/O/T VDDPST2 – IE,WPU IO MUX – Analog30 GPIO24 I/O/T VDDPST2 – – IO MUX – –31 GPIO8 I/O/T VDDPST2 IE IE IO MUX – Analog32 GPIO9 I/O/T VDDPST2 IE,WPU IE,WPU IO MUX – Analog33 U0RXD I/O/T VDDPST2 – IE,WPU IO MUX – –34 U0TXD I/O/T VDDPST2 – IE,WPU IO MUX – –35 GPIO29 I/O/T VDDPST2 – – IO MUX – –36 GPIO7 I/O/T VDDPST2 IE IE IO MUX – –37 VDDA1 Power – – – – – –38 XTAL_N Analog – – – – – –39 XTAL_P Analog – – – – – –40 VDDA2 Power – – – – – –1. Bold marks the pin function set in which a pin has its default function in the default boot mode. See Section 3.1 Chip Boot ModeControl.2. Except for GPIO12 and GPIO13 whose default drive strength is 40 mA, the default drive strength for all the other pins is 20 mA.3. Column Pin Settings shows predefined settings at reset and after reset with the following abbreviations:• IE – input enabled• WPU – internal weak pull-up resistor enabled• WPD – internal weak pull-down resistor enabled• USB_PU – USB pull-up resistor enabled– By default, the USB function is enabled for USB pins (i.e., GPIO12 and GPIO13), and the pin pull-up is decided by theUSB pull-up resistor. This resistor is controlled by USB_SERIAL_JTAG_DP/DM_PULLUP and the pull-up value is managedby USB_SERIAL_JTAG_PULLUP_VALUE.– When the USB function is disabled, USB pins are used as regular GPIOs and the pin’s internal weak pull-up and pull-downresistors are disabled by default (configurable by IO_MUX_FUN_WPU/WPD).4. For ESP32-C61HF4, the SPICS0, SPIQ, SPIWP, VDD_SPI, SPIHD, SPICLK, and SPID pins are not connected (NC).5. For ESP32-C61NF8R8LA, the SPICS1, SPICS0, SPIQ, SPIWP, VDD_SPI, SPIHD, SPICLK, and SPID pins are not connected (NC).Espressif Systems 17 ESP32-C61 Series Datasheet v1.0 2 Pins2.3 IO Pins2.3.1 IO MUX FunctionsThe IO MUX allows multiple input/output signals to be connected to a single input/output pin. Each IO pin ofESP32-C61 can be connected to one of the three signals (IO MUX functions, i.e., F0–F2), as listed in Table 2-3 IOMUX Functions.Among the three sets of signals:• Some are routed via the GPIO Matrix (GPIO0, GPIO1, etc.), which incorporates internal signal routingcircuitry for mapping signals programmatically. It gives the pin access to almost any peripheral signals.However, the flexibility of programmatic mapping comes at a cost as it might affect the latency of routedsignals.• Some are directly routed from certain peripherals (U0TXD, MTCK, etc.), including UART0, JTAG, SPI0/1,SPI2 and SDIO 2.0 Slave - see Table 2-2 IO MUX Functions.Table 2-2. Peripheral Signals Routed via IO MUXPin Function Signal DescriptionU0TXD Transmit dataUART0 interfaceU0RXD Receive dataMTCK Test clockJTAG interface for debuggingMTDO Test data outMTDI Test data inMTMS Test mode selectSPIQ Data out3.3 V SPI0/1 interface for connection to in-package oroff-package-flash/PSRAM via the SPI bus. It supports 1-, 2-, 4-line SPImodes. See also Section 2.6 Pin Mapping Between Chip andFlash/PSRAMSPID Data inSPIHD HoldSPIWP Write protectSPICLK ClockSPICS… Chip selectFSPIQ Data outSPI2 interface for fast SPI connection. It supports 1-, 2-, 4-line SPI modesFSPID Data inFSPIHD HoldFSPIWP Write protectFSPICLK ClockFSPICS0 Chip selectSDIO_CLK ClockThe Secure Digital Input Output (SDIO) interface forconnecting to an external SDIO hostSDIO_CMD CommandSDIO_DATA… DataTable 2-3 IO MUX Functions shows the IO MUX functions of IO pins.Table 2-3. IO MUX Pin FunctionsPin IO MUX / IO MUX Function1, 2No. GPIO Name2F0 Type F1 Type F2 Type6 XTAL_32K_P GPIO0 I/O/T GPIO0 I/O/TCont’d on next pageEspressif Systems 18 ESP32-C61 Series Datasheet v1.0 2 PinsTable 2-3 – cont’d from previous pagePin IO MUX / IO MUX Function1, 2No. GPIO Name2F0 Type F1 Type F2 Type7 XTAL_32K_N GPIO1 I/O/T GPIO1 I/O/T8 GPIO2 GPIO2 I/O/T GPIO2 I/O/T FSPIQ I1/O/T9 MTMS MTMS I1 GPIO3 I/O/T FSPIHD I1/O/T10 MTDI MTDI I1 GPIO4 I/O/T FSPIWP I1/O/T11 MTCK MTCK I1 GPIO5 I/O/T12 MTDO MTDO O/T GPIO6 I/O/T FSPICLK I1/O/T13 SDIO_CMD SDIO_CMD I1/O/T GPIO25 I/O/T14 SDIO_CLK SDIO_CLK I1 GPIO26 I/O/T15 SDIO_DATA0 SDIO_DATA0 I1/O/T GPIO27 I/O/T16 SDIO_DATA1 SDIO_DATA1 I1/O/T GPIO28 I/O/T17 SDIO_DATA2 SDIO_DATA2 I1/O/T GPIO22 I/O/T18 SDIO_DATA3 SDIO_DATA3 I1/O/T GPIO23 I/O/T19 SPICS1/NC SPICS1 O/T GPIO14 I/O/T20 SPICS0/NC SPICS0 O/T GPIO15 I/O/T22 SPIQ/NC SPIQ I1/O/T GPIO16 I/O/T23 SPIWP/NC SPIWP I1/O/T GPIO17 I/O/T24 VDD_SPI/NC GPIO18 I/O/T GPIO18 I/O/T25 SPIHD/NC SPIHD I1/O/T GPIO19 I/O/T26 SPICLK/NC SPICLK O/T GPIO20 I/O/T27 SPID/NC SPID I1/O/T GPIO21 I/O/T28 USB_D- GPIO12 I/O/T GPIO12 I/O/T29 USB_D+ GPIO13 I/O/T GPIO13 I/O/T30 GPIO24 GPIO24 I/O/T GPIO24 I/O/T31 GPIO8 GPIO8 I/O/T GPIO8 I/O/T FSPICS0 I1/O/T32 GPIO9 GPIO9 I/O/T GPIO9 I/O/T33 U0RXD U0RXD I1 GPIO10 I/O/T34 U0TXD U0TXD O GPIO11 I/O/T35 GPIO29 GPIO29 I/O/T GPIO29 I/O/T36 GPIO7 GPIO7 I/O/T GPIO7 I/O/T FSPID I1/O/T1Bold marks the default pin functions in the default boot mode. See Section 3.1 Chip BootMode Control.2Regarding highlighted cells, see Section 2.3.4 Restrictions for GPIOs and LP GPIOs.3Each IO MUX function (Fn, n = 0 ~ 2) is associated with a type. The description of type is asfollows:• I – input. O – output. T – high impedance.• I1 – input; if the pin is assigned a function other than Fn, the input signal of Fn is always1.• I0 – input; if the pin is assigned a function other than Fn, the input signal of Fn is always0.Espressif Systems 19 ESP32-C61 Series Datasheet v1.0 2 Pins2.3.2 LP IO MUX FunctionsThe LP IO MUX function is activated when the HP digital system is shut down, thereby saving power.Table 2-4. LP IO MUX FunctionsPin LP IO LP IO MUX FunctionNo. Name F06 LP_GPIO0 LP_GPIO07 LP_GPIO1 LP_GPIO18 LP_GPIO2 LP_GPIO29 LP_GPIO3 LP_GPIO310 LP_GPIO4 LP_GPIO411 LP_GPIO5 LP_GPIO512 LP_GPIO6 LP_GPIO6Espressif Systems 20 ESP32-C61 Series Datasheet v1.0 2 Pins2.3.3 Analog FunctionsSome IO pins also have analog functions, for analog peripherals (such as ADC) in any power mode. Internalanalog signals are routed to these analog functions, see Table 2-5 Analog Functions.Table 2-5. Analog Signals Routed to Analog FunctionsPin Function Signal DescriptionADC1_CHn ADC1 channel n signal ADC1 channel n interfaceXTAL_32K_N Negative clock signal The differential clock input of the chip, connecting to the 32kHz differential clock output of the external crystalXTAL_32K_P Positive clock signalUSB_D-USB data differential signal USB Serial/JTAG functionUSB_D+ZCDn Voltage from GPIO Pad Analog Pad voltage comparator interfaceTable 2-6 Analog Functions shows the analog functions of IO pins.Table 2-6. Analog FunctionsPin Analog Analog Function3No. IO Name1, 2F0 F16 XTAL_32K_P XTAL_32K_P –7 XTAL_32K_N XTAL_32K_N ADC1_CH09 MTMS – ADC1_CH110 MTDI – ADC1_CH211 MTCK – ADC1_CH328 USB_D- USB_D-1–29 USB_D+ USB_D+ –24 VDD_SPI VDD_SPI –31 GPIO82ZCD0 –32 GPIO9 ZCD1 –1Bold marks the default pin functions in the default bootmode. See Section 3.1 Chip Boot Mode Control.2Regarding highlighted cells, see Section 2.3.4 Restric-tions for GPIOs and LP GPIOs.Espressif Systems 21 ESP32-C61 Series Datasheet v1.0 2 Pins2.3.4 Restrictions for GPIOs and LP GPIOsAll IO pins of ESP32-C61 have GPIO and some have RTC_GPIO pin functions. However, the IO pins aremultiplexed and can be configured for different purposes based on the requirements. Some IOs have restrictionsfor usage. It is essential to consider the multiplexed nature and the limitations when using these IO pins.In tables of this chapter, some pin functions are highlighted . The non-highlighted GPIO or RTC_GPIO pins arerecommended for use first. If more pins are needed, the highlighted GPIOs or RTC_GPIOs should be chosencarefully to avoid conflicts with important pin functions.The highlighted IO pins have the following important pin functions:• GPIO – allocated for communication with in-package flash/PSRAM and NOT recommended for otheruses. For details, see Section 2.6 Pin Mapping Between Chip and Flash/PSRAM.• GPIO – have one of the following important functions:– Strapping pins – need to be at certain logic levels at startup. See Section 3 Boot Configurations.– USB_D+/- – by default, connected to the USB Serial/JTAG Controller. To function as GPIOs, thesepins need to be reconfigured.– JTAG interface – often used for debugging. See Table 2-2 IO MUX Functions. To free these pins up,the pin functions USB_D+/- of the USB Serial/JTAG Controller can be used instead. See also Section3.4 JTAG Signal Source Control.– UART interface – often used for debugging. See Table 2-2 IO MUX Functions.See also Appendix A – ESP32-C61 Consolidated Pin Overview.Espressif Systems 22 ESP32-C61 Series Datasheet v1.0 2 Pins2.4 Analog PinsTable 2-7. Analog PinsPin Pin Pin PinNo. Name Type Function1 ANT_2G I/O RF input/output4 CHIP_PU —High: on, enables the chip (powered up).Low: off, disables the chip (powered down).Note: Do not leave the CHIP_PU pin floating.38 XTAL_N — External clock input/output connected to chip’s crystal.P/N means differential clock positive/negative.39 XTAL_P —Espressif Systems 23 ESP32-C61 Series Datasheet v1.0 2 Pins2.5 Power Supply2.5.1 Power PinsThe chip is powered via the power pins described in Table 2-8 Power Pins.Table 2-8. Power PinsPin Pin Power Supply1,2No. Name Direction Power Domain / Other IO Pins32 VDDA3 Input Analog power domain3 VDDA4 Input Analog power domain5 VDDPST1 Input HP digital and part of LP digital power domains LP IO24 VDD_SPI Output A power supply from VDDPST2 used to power the flash21 VDDPST2 Input HP digital power domain HP IO37 VDDA1 Input Analog power domain40 VDDA2 Input Analog power domain41 GND — External ground connection1See in conjunction with Section 2.5.2 Power Scheme.2For recommended and maximum voltage and current, see Section 5.1 Absolute Maximum Ratings andSection 5.2 Recommended Operating Conditions.3LP IO pins are those powered by VDDPST1 and so on, as shown in Figure 2-3 ESP32-C61 Power Scheme.See also Table 2-1 Pin Overview > Column Pin Providing Power.2.5.2 Power SchemeThe power scheme is shown in Figure 2-3 ESP32-C61 Power Scheme.The components on the chip are powered via voltage regulators.Table 2-9. Voltage RegulatorsVoltage Regulator Output Power SupplyHP 1.1 V HP power domainLP 1.1 V LP power domainEspressif Systems 24 ESP32-C61 Series Datasheet v1.0 2 PinsLPVoltageRegulatorHPVoltageRegulatorLP SystemHPSystemVDDPST1 VDDPST2VDDA1VDDA2AnalogVDD_SPILP IOHP IORSPIC61/C31VDDA3VDDA4Figure 2-3. ESP32-C61 Power Scheme2.5.3 Chip Power-up and ResetOnce the power is supplied to the chip, its power rails need a short time to stabilize. After that, CHIP_PU – thepin used for power-up and reset – is pulled high to activate the chip. For information on CHIP_PU as well aspower-up and reset timing, see Figure 2-4 and Table 2-10.VIL_nRSTtST BLtRST2.8 VVDDA3,VDDA4,VDDPST1,VDDPST2,VDDA1,VDDA2CHIP_PUFigure 2-4. Visualization of Timing Parameters for Power-up and ResetTable 2-10. Description of Timing Parameters for Power-up and ResetParameter Description Min (µs)tST BLTime reserved for the power rails of VDDA3, VDDA4, VDDPST1,VDDPST2, VDDA1 and VDDA2 to stabilize before the CHIP_PU pinis pulled high to activate the chip50tRSTTime reserved for CHIP_PU to stay below VIL_nRSTto reset thechip50Espressif Systems 25 ESP32-C61 Series Datasheet v1.0 2 Pins2.6 Pin Mapping Between Chip and Flash/PSRAMTable 2-11 lists the pin mapping between the chip and flash/PSRAM for all SPI modes.For chip variants with in-package flash/PSRAM (see Table 1-1 Comparison), the pins allocated for communicationwith in-package flash/PSRAM can be identified depending on the SPI mode used. The recommended pins forconnecting to off-package flash/PSRAM can be found in table below.For variants with in-package flash/PSRAM, the in-package flash or PSRAM must be powered by VDD_SPI, andthe corresponding pin cannot be used as a digital function pin.For off-package flash or PSRAM, the power supply is optional. It can be provided either by VDD_SPI or by anexternal power source supplied by the user. In general, if VDD_SPI is used to power flash or PSRAM, then thepin cannot be used as a digital function pin.For more information on SPI controllers, see also Section 4.2.1.2 SPI Controller.Notice:It is not recommended to use the pins connected to flash/PSRAM for any other purposes.Table 2-11. Pin Mapping Between Chip and Off-Package Flash for ESP32-C611Pin No. Pin Name Single SPI Dual SPI Quad SPIFlash Flash Flash26 SPICLK CLK CLK CLK20 SPICS02CS# CS# CS#27 SPID MOSI SIO03SIO022 SPIQ MISO SIO1 SIO123 SPIWP WP# SIO225 SPIHD HOLD# SIO31An off-package flash can only be connected if the chip variantdoes not have in-package flash.2SPICS0 is used to access flash3SIO: Serial Data Input and OutputEspressif Systems 26 ESP32-C61 Series Datasheet v1.0 2 PinsTable 2-12. Pin Mapping Between Chip and Off-Package PSRAM1QFN48 Pin Name Single SPI Quad SPIPin No. PSRAM PSRAM26 SPICLK CLK CLK19 SPICS12CE# CE#27 SPID SI3SIO022 SPIQ SO4SIO123 SPIWP SIO225 SPIHD SIO31An off-package PSRAM can only be connectedif the chip variant does not have in-packagePSRAM. If PSRAM is not connected, these pinscannot be used as GPIO pins.2SPICS1 is used to access PSRAM3SI: Serial Data Input, equivalent to MOSI4SO: Serial Data Output, equivalent to MISOEspressif Systems 27 ESP32-C61 Series Datasheet v1.0 3 Boot Configurations3 Boot ConfigurationsThe chip allows for configuring the following boot parameters through strapping-pins and eFuse parameter atpower-up or a hardware reset, without microcontroller interaction.• Chip boot mode– Strapping pin: GPIO8 and GPIO9• SDIO sampling and driving clock edge– Strapping pin: MTDI and MTMS• ROM message printing– Strapping pin: GPIO8– eFuse parameter: EFUSE_UART_PRINT_CONTROL andEFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT• JTAG signal source– Strapping pin: GPIO7– eFuse parameter: EFUSE_DIS_PAD_JTAG, EFUSE_DIS_USB_JTAG, andEFUSE_JTAG_SEL_ENABLEThe default values of all the above eFuse parameters are 0, which means that they are not burnt. Given thateFuse is one-time programmable, once programmed to 1, it can never be reverted to 0.The default values of the strapping pins, namely the logic levels, are determined by pins’ internal weakpull-up/pull-down resistors at reset if the pins are not connected to any circuit, or connected to an externalhigh-impedance circuit.Table 3-1. Default Configuration of Strapping PinsStrapping Pin Default Configuration Bit ValueMTMS Floating –MTDI Floating –GPIO7 Floating –GPIO8 Floating –GPIO9 Pull-up 1To change the bit values, the strapping pins should be connected to external pull-down/pull-up resistances. If theESP32-C61 is used as a device by a host MCU, the strapping pin voltage levels can also be controlled by thehost MCU.All strapping pins have latches. At system reset, the latches sample the bit values of their respective strappingpins and store them until the chip is powered down or shut down. The states of latches cannot be changed inany other way. It makes the strapping pin values available during the entire chip operation, and the pins are freedup to be used as regular IO pins after reset.The timing of signals connected to the strapping pins should adhere to the setup time and hold time specificationsin Table 3-2 and Figure 3-1.Espressif Systems 28 ESP32-C61 Series Datasheet v1.0 3 Boot ConfigurationsTable 3-2. Description of Timing Parameters for the Strapping PinsParameter Description Min (ms)tSUSetup time is the time reserved for the power rails to stabilize beforethe CHIP_PU pin is pulled high to activate the chip.0tHHold time is the time reserved for the chip to read the strapping pinvalues after CHIP_PU is already high and before these pins startoperating as regular IO pins.3Strapping pinVIH_nRSTVIHtSUtHCHIP_PUFigure 3-1. Visualization of Timing Parameters for the Strapping Pins3.1 Chip Boot Mode ControlGPIO8 and GPIO9 control the boot mode after the reset is released. See Table 3-3 Chip Boot ModeControl.Table 3-3. Chip Boot Mode ControlBoot Mode GPIO8 GPIO9SPI Boot1Any value 1Joint Download Boot21 01Bold marks the default value and configura-tion.2Joint Download Boot mode supports the fol-lowing download methods:• USB-Serial-JTAG Download Boot• UART Download Boot• SDIO Slave 2.0 Download BootIn SPI Boot mode, the ROM bootloader loads and executes the program from SPI flash to boot thesystem.In Joint Download Boot mode, users can download binary files into flash using UART0, USB or SDIO Slaveinterfaces and execute it in SPI Boot mode.Espressif Systems 29 ESP32-C61 Series Datasheet v1.0 3 Boot ConfigurationsIn Joint Download Boot mode, it is also possible to download binary files into SRAM using UART0, USB or SDIOSlave interfaces and execute it from SRAM.3.2 SDIO Sampling and Driving Clock Edge ControlThe strapping pin MTMS and MTDI can be used to decide on which clock edge to sample signals and driveoutput lines. See Table 3-4 SDIO Input Sampling Edge/Output Driving Edge Control.Table 3-4. SDIO Input Sampling Edge/Output Driving Edge ControlEdge behavior MTMS MTDIFalling edge sampling, falling edge output 0 0Falling edge sampling, rising edge output 0 1Rising edge sampling, falling edge output 1 0Rising edge sampling, rising edge output 1 11MTMS and MTDI are floating by default, so above are notdefault configurations.3.3 ROM Messages Printing ControlDuring the boot process, the messages by the ROM code can be printed to:• (Default) UART0 and USB Serial/JTAG controller• USB Serial/JTAG controller• UART0LP_AON_STORE4_REG[0], EFUSE_UART_PRINT_CONTROL and GPIO8 control ROM messages printing toUART0 as shown in Table 3-5 UART0 ROM Message Printing Control.Table 3-5. UART0 ROM Message Printing ControlUART0 ROM Code Printing EFUSE_UART_PRINT_CONTROL GPIO8 Register1Always enabled20 Ignored0Enabled10Disabled 1Disabled20Enabled 1Always disabled 3 IgnoredDisabled Ignored Ignored 11Register: LP_AON_STORE4_REG[0]2Bold marks the default value and configuration.EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT and LP_AON_STORE4_REG[0] control the printing to USBSerial/JTAG controller as shown in Table 3-6 USB Serial/JTAG ROM Message Printing Control.Espressif Systems 30 ESP32-C61 Series Datasheet v1.0 3 Boot ConfigurationsTable 3-6. USB Serial/JTAG ROM Message Printing ControlUSB Serial/JTAG ROM Mes-sage Printing ControlLP_AON_STORE4_REG[0] EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINTEnabled 0 0Disabled0 11 Ignored1Bold marks the default value and configuration.3.4 JTAG Signal Source ControlThe strapping pin GPIO7 can be used to control the source of JTAG signals during the early boot process. Thispin does not have any internal pull resistors and the strapping value must be controlled by the external circuit thatcannot be in a high impedance state.As Table 3-7 shows, GPIO7 is used in combination with EFUSE_DIS_PAD_JTAG, EFUSE_DIS_USB_JTAG, andEFUSE_JTAG_SEL_ENABLE.Table 3-7. JTAG Signal Source ControleFuse11eFuse22eFuse33GPIO7 JTAG Signal Source0 00 x4USB Serial/JTAG Controller5110JTAG pins MTDI, MTCK, MTMS and MTDO0 x x x0 1 x x1 0 x x USB Serial/JTAG Controller1 1 x xJTAG is disabled1 x x x1eFuse 1: EFUSE_DIS_PAD_JTAG2eFuse 2: EFUSE_DIS_USB_JTAG3eFuse 3: EFUSE_JTAG_SEL_ENABLE4x: x indicates that the value has no effect on the result and can be ignored.5Bold marks the default value and configuration.Espressif Systems 31 ESP32-C61 Series Datasheet v1.0 4 Functional Description4 Functional Description4.1 SystemThis section describes the core of the chip’s operation, covering its microprocessor, memory organization,system components, and security features.4.1.1 Microprocessor and MasterThis subsection describes the core processing units within the chip and their capabilities.4.1.1.1 High-Performance CPUThe ESP-RISC-V CPU (HP CPU) is a high-performance 32-bit core based on the RISC-V instruction setarchitecture (ISA) comprising base integer (I), multiplication/division (M), atomic (A) and compressed (C) standardextensions.Feature List• Five-stage pipeline that supports an operating clock frequency up to 160 MHz• RV32IMAC ISA (instruction set architecture)• Zc extensions (Zcb, Zcmp, and Zcmt)• Two-cycle pipelined multiplier and radix-4 SRT divider• Compatible with RISC-V ISA Manual Volume I: Unprivileged ISA Version 2.2 and RISC-V ISA Manual,Volume II: Privileged Architecture, Version 1.10• Zero wait cycle access to on-chip SRAM and cache for program and data access over IRAM/DRAMinterface• Branch predictor BHT, BTB, and RAS• Compliant with RISC-V Core Local Interrupt (CLINT)• Compliant with RISC-V Core-Local Interrupt Controller (CLIC)• Two privilege modes: Machine (M) mode and User (U) mode• Debug module (DM) compliant with the specification RISC-V External Debug Support Version 0.13 withexternal debugger support over an industry-standard JTAG/USB port• Offline trace debug compliant with RISC-V Trace Specification v2.0, see Section 4.1.1.2 RISC-V TraceEncoder• Hardware trigger compliant with the specification RISC-V External Debug Support Version 0.13 with up tothree breakpoints/watchpoints• Physical memory protection (PMP) and attributes (PMA) for up to 16 configurable regionsEspressif Systems 32 ESP32-C61 Series Datasheet v1.0 4 Functional Description4.1.1.2 RISC-V Trace EncoderThe RISC-V Trace Encoder in the ESP32-C61 chip provides a way to capture detailed trace information from theHigh-Performance CPU’s execution, enabling deeper analysis and optimization of the system. It connects to theHP CPU’s instruction trace interface and compresses the information into smaller packets, which are then storedin internal SRAM.Feature List• Compatible with Efficient Trace for RISC-V Version 2.0• Synchronization packets sent every few clock cycles or packets• Zero bytes as anchor tags to identify boundaries between data packets• Configurable memory writing mode: loop mode or non-loop mode• Trace lost status to indicate packet loss• Automatic restart after packet loss• Support for delta address mode and full address mode• Support for filter unit4.1.1.3 GDMA ControllerThe GDMA Controller is a General Direct Memory Access (GDMA) controller that allows peripheral-to-memory,memory-to-peripheral, and memory-to-memory data transfer without the CPU’s intervention. The GDMA hasfour independent channels, two transmit channels and two receive channels. These channels are shared byperipherals with the GDMA feature, such as SPI2, I2S, SHA, and ADC.Feature List• Programmable length of data to be transferred in bytes• Linked list of descriptors for efficient data transfer management• INCR burst transfer when accessing internal RAM for improved performance• Access to internal RAM and off-package PSRAM• Software-configurable selection of peripheral requesting service• Fixed-priority and round-robin channel arbitration schemes for managing bandwidth• Support for Event Task Matrix4.1.2 Memory OrganizationThis subsection describes the memory arrangement to explain how data is stored, accessed, and managed forefficient operation.Figure 4-1 illustrates the address mapping structure of ESP32-C61.Espressif Systems 33 ESP32-C61 Series Datasheet v1.0 4 Functional DescriptionCPU0x3000_00000x3FFF_FFFF0x4000_00000x4003_FFFF0x4004_00000x407F_FFFF0x4080_00000x4084_FFFF0x4085_00000x41FF_FFFF0x4200_00000x43FF_FFFF0x4400_00000x5FFF_FFFF0x6000_00000x600B_FFFF0x600C_00000x600C_FFFFCache(32 KB)MMUExternalMemoryROM(256 KB)HP Memory(320 KB)GDMA0x600D_00000xFFFF_FFFFPeripheralsNot available for use0x0000_00000x1FFF_FFFF0x2000_00000x2FFF_FFFFCPU Sub-systemFigure 4-1. Address Mapping Structure4.1.2.1 Internal MemoryThe internal memory of ESP32-C61 refers to the memory integrated on the chip die or in the chip package,including ROM, SRAM, eFuse, flash, and PSRAM.Feature List• 256 KB of ROM for booting and core functions• 320 KB of SRAM for data and instructions• 4096-bit eFuse memory, with 1792 bits available for users• In-package flash– See flash size in Chapter 1 ESP32-C61 Series Comparison– More than 100,000 program/erase cyclesEspressif Systems 34 ESP32-C61 Series Datasheet v1.0 4 Functional Description– More than 20 years of data retention time– Clock frequency up to 120 MHz• In-package PSRAM– See PSRAM size in Chapter 1 ESP32-C61 Series Comparison– Clock frequency up to 120 MHz4.1.2.2 External MemorySome variants of ESP32-C61 allow connection to flash/PSRAM via the SPI, Dual SPI, Quad SPI, and QPIinterfaces. For more information, please refer to Table 1-1.CPU’s instruction memory space and read-only data memory space can map into the flash/PSRAM ofESP32-C61, and the size of the flash/PSRAM can be 32 MB at most respectively. ESP32-C61 supportshardware encryption/decryption based on XTS-AES to protect developers’ programs and data in theflash/PSRAM.Feature ListThrough the cache, ESP32-C61 can support at a time up to:• 32 MB of instruction memory space which can map into the flash/PSRAM as individual blocks of 64/32/16KB. 32-bit fetch is supported• 32 MB of data memory space which can map into the flash/PSRAM as individual blocks of 64/32/16 KB.8-bit, 16-bit, and 32-bit reads are supported by the flash. 8-bit, 16-bit, and 32-bit reads and writes aresupported by the PSRAMNote:After ESP32-C61 is initialized, software can customize the mapping of flash/PSRAM into the CPU address space.4.1.2.3 eFuse ControllerThe eFuse memory is a one-time programmable memory that stores parameters and user data, and the eFusecontroller of ESP32-C61 is used to program and read this eFuse memory.Feature List• Configure write protection for some blocks• Configure read protection for some blocks• Various hardware encoding schemes against data corruption4.1.3 System ComponentsThis subsection describes the essential components that contribute to the overall functionality and control of thesystem.Espressif Systems 35 ESP32-C61 Series Datasheet v1.0 4 Functional Description4.1.3.1 IO MUX and GPIO MatrixThe IO MUX and GPIO Matrix in the ESP32-C61 chip provide flexible routing of peripheral input and outputsignals to the GPIO pins. These peripherals enhance the functionality and performance of the chip by allowingthe configuration of I/O, support for multiplexing, and signal synchronization for peripheral inputs.Feature List• 30 GPIO pins for general-purpose I/O or connection to internal peripheral signals• GPIO matrix:– Routing 37 peripheral input and 57 output signals to any GPIO pin– Signal synchronization for peripheral inputs based on IO MUX operating clock– GPIO Filter hardware for input signal filtering• IO MUX for directly connecting certain digital signals (SPI, JTAG, UART, SDIO) to pins• Support for Event Task Matrix4.1.3.2 ResetThe ESP32-C61 chip provides four types of reset that occur at different levels, namely CPU Reset, Core Reset,System Reset, and Chip Reset. Except for Chip Reset, all reset types preserve the data stored in internalmemory.Feature List• Four types of reset:– CPU Reset – Resets the CPU core– Core Reset – Resets the whole digital system except for the LP system– System Reset – Resets the whole digital system, including the LP system– Chip Reset – Resets the whole chip• Reset trigger:– Directly by hardware– Via software by configuring the corresponding registers of the CPU• Support for retrieving reset cause4.1.3.3 ClockThe ESP32-C61 chip has clocks sourced from oscillators, RC circuits, and PLL circuits, which are thenprocessed by dividers or selectors. The clocks can be classified into high-speed clocks for devices working athigher frequencies and slow-speed clocks for low-power systems and some peripherals.Espressif Systems 36 ESP32-C61 Series Datasheet v1.0 4 Functional DescriptionFeature List• High-speed clocks for HP system– 40 MHz external crystal clockNote:* ESP32-C61 cannot operate without the external crystal clock.* ESP32-C61 can automatically filter out high-frequency glitches in the external main crystal clock.– 480 MHz internal PLL clock• Slow-speed clocks for LP system and some peripherals working in low-power mode– 32 kHz external crystal clock (must be an external differential clock input, generally provided by apassive crystal)– Internal fast RC oscillator with adjustable frequency (20 MHz by default)– Internal slow RC oscillator with adjustable frequency (150 kHz by default)– External slow clock input through XTAL_32K_P (32 kHz by default, can be provided by an activeoscillator or other sources)Note:– The 32 kHz external crystal clock and the external slow clock input through XTAL_32K_P cannot coexist; onlyone can be used at a time.4.1.3.4 Interrupt MatrixThe Interrupt Matrix in the ESP32-C61 chip routes interrupt requests generated by various peripherals to CPUinterrupts.Feature List• 53 peripheral interrupt sources accepted as input• 32 CPU peripheral interrupts generated to CPU as output• Current interrupt status query of peripheral interrupt sources• Multiple interrupt sources mapping to a single CPU interrupt (i.e., shared interrupts)4.1.3.5 Event Task MatrixESP32-C61 integrates an SoC ETM with multiple channels. Each input event on channels is mapped to anoutput task. Events are generated by peripherals, while tasks are received by peripherals.Feature List• Up to 50 mapping channels, each connected to an event and a task and controlled independentlyEspressif Systems 37 ESP32-C61 Series Datasheet v1.0 4 Functional Description• An event or a task can be mapped to any tasks or events in the matrix. That is to say, one event can bemapped to different tasks via multiple channels, or different events can be mapped to the same task viatheir individual channels• Peripherals supporting ETM include GPIO, LED PWM, general-purpose timers, RTC Timer, system timer,temperature sensor, ADC, I2S, GDMA, and PMU4.1.3.6 System TimerThe System Timer (SYSTIMER) in the ESP32-C61 chip is a 52-bit timer that can be used to generate tickinterrupts for the operating system or as a general timer to generate periodic or one-time interrupts.Feature List• Two 52-bit counters and three 52-bit comparators• 52-bit alarm values and 26-bit alarm periods• Two modes to generate alarms: target mode and period mode• Three comparators generating three independent interrupts based on configured alarm value or alarmperiod• Ability to load back sleep time recorded by RTC timer via software after Deep-sleep or Light-sleep• Counters can be stalled if the CPU is stalled or in OCD mode• Real-time alarm events4.1.3.7 Power Management UnitThe ESP32-C61 has an advanced Power Management Unit (PMU). It can be flexibly configured to power updifferent power domains of the chip to achieve the best balance between chip performance, power consumption,and wakeup latency.Configuring the PMU is a complex procedure. To simplify power management for typical scenarios, there are thefollowing predefined power modes that power up different combinations of power domains:• Active mode – The CPU, RF circuits, and all peripherals are on. The chip can process data, receive,transmit, and listen.• Modem-sleep mode – The CPU is on, but the clock frequency can be reduced. The wireless connectionscan be configured to remain active as RF circuits are periodically switched on when required.• Light-sleep mode – The CPU stops running, and can be optionally powered on. The chip can be wokenup via all wake up mechanisms: MAC, host, RTC timer, or external interrupts. Wireless connections canremain active. Some groups of digital peripherals can be optionally powered off.• Deep-sleep mode – Only LP system is powered onFigure 4-2 Components and Power Domains and the following Figure 4-3 Components and Power DomainsTable show the distribution of chip components between power domains and power subdomains .Espressif Systems 38 ESP32-C61 Series Datasheet v1.0 4 Functional DescriptionWireless Digital CircuitsWi-Fi MAC Wi-Fi BasebandBluetooth LE Link ControllerBluetooth LE BasebandHP Power DomainEspressif’s ESP32-C61 Wi-Fi + Bluetooth® Low Energy SoCROM2.4 GHz Receiver2.4 GHz TransmitterRF SynthesizerRF CircuitsPLLXTAL_CLKRC_FAST_CLKAnalog Power DomainLP IOPMULP Power DomaineFuse ControllerPower distributionPower domainPower subdomainSuper WatchdogCPURISC-V 32-bit MicroprocessorJTAGCachePower Glitch DetectorTRNGI2C I2SSystem TimerTemperature SensorMain System Watchdog TimersECDSAUART ETMGPIO ADCUSB Serial/JTAGXTS-AESSHA APM ECCSecure BootAnalog Voltage ComparatorGeneral-purpose SPIGeneral-purpose TimersLED PWM2.4 GHz Balun + SwitchExternal Main ClockFast RC OsciillatorPhase-Locked LoopGDMAWireless Power CircuitsModem PowerMemorySRAMMMUInterrupt MatrixBrown-out DetectorRTC Watchdog TimerFigure 4-2. Components and Power Domains LP Power DomainHP Power DomainAnalog Power DomainAlways-onLP PeriMemoryWireless Pwr CircuitsCPUWireless Digital CurcuitsOthersRC_FAST_CLKXTAL_CLKPLLRF CircuitsActiveONONONONONONONONONONONModem_sleepONONONONONONONONONOFFOFFLight-sleepONONONONOFFOFFOFFOFFOFFOFFOFFDeep-sleepONOFFOFFOFFOFFOFFOFFOFFOFFOFFOFFPower DomainPower mode1Figure 4-3. Components and Power Domains TableEspressif Systems 39 ESP32-C61 Series Datasheet v1.0 4 Functional Description4.1.3.8 Brownout DetectorESP32-C61 can periodically monitor the voltage of the power supply, and in the event of abnormal voltage, it iscapable of generating interrupts or initiating resets.Feature List• Configurable detection threshold• Configurable reset level• Glitch filtering4.1.3.9 RTC TimerESP32-C61 RTC Timer starts counting once the chip is powered on and keeps counting in any state.Feature List• 46-bit counter operating under the RTC clock• Real-time reading of the time-base counter’s value• Configurable target value for the counter to trigger an interrupt upon timeout4.1.3.10 Timer GroupThe Timer Group (TIMG) in the ESP32-C61 chip can be used to precisely time an interval, trigger an interruptafter a particular interval (periodically and aperiodically), or act as a hardware clock. ESP32-C61 has two timergroups, each consisting of one general-purpose timer and one Main System Watchdog Timer.Feature List• 16-bit prescaler• 54-bit auto-reload-capable up-down counter• Able to read real-time value of the time-base counter• Halt, resume, and disable the time-base counter• Programmable alarm generation• Timer value reload (auto-reload at an alarm or a software-controlled instant reload)• RTC slow clock frequency calculation• Level interrupt generation• Real-time alarm events• Support for several ETM tasks and eventsEspressif Systems 40 ESP32-C61 Series Datasheet v1.0 4 Functional Description4.1.3.11 Watchdog TimersThe Watchdog Timers (WDT) in ESP32-C61 are used to detect and recover from malfunctions. The chip containsthree digital watchdog timers: one in each of the two timer groups (MWDT) and one in the RTC Module (RWDT).Additionally, there is one analog watchdog timer called the Super watchdog (SWD) that helps prevent the systemfrom operating in a sub-optimal state.Feature List• Digital watchdog timers:– Four stages, each with a separately programmable timeout value and timeout action– Timeout actions: Interrupt, CPU reset, core reset, system reset (RWDT only)– Flash boot protection under SPI Boot mode at stage 0– Write protection that makes WDT register read only unless unlocked– 32-bit timeout counter• Analog watchdog timer:– Timeout period slightly less than one second– Timeout actions: Interrupt, system reset4.1.3.12 Permission ControlThe Permission Control module in ESP32-C61 is responsible for managing access permissions to memory andperipheral registers. It consists of two parts: PMP (Physical Memory Protection) and APM (Access PermissionManagement).Feature List• Access permission management for ROM, HP memory, HP peripheral, and LP peripheral address spaces• APM supports each master (such as DMA) to select one of the four security modes• Access permission configuration for up to 16 address ranges• Interrupt function and exception information record4.1.3.13 System RegistersThe System Registers in the ESP32-C61 chip are used to configure various auxiliary chip features.Feature List• Control External memory encryption and decryption• Control CPU core debugging• Control Bus timeout protectionEspressif Systems 41 ESP32-C61 Series Datasheet v1.0 4 Functional Description4.1.3.14 Debug AssistantThe Debug Assistant provides a set of functions to help locate bugs and issues during software debugging. Itoffers various monitoring capabilities and logging features to assist in identifying and resolving software errorsefficiently.Feature List• Read/write monitoring: Monitor whether the CPU bus reads from or writes to a specified memory addressspace• Stack pointer (SP) monitoring: Prevent stack overflow or erroneous push/pop operations violation willtrigger an interrupt.• Program counter (PC) logging: Record PC value. The developer can get the last PC value at the mostrecent CPU reset• Bus access logging: Record information about bus access when the CPU or DMA writes a specified value4.1.4 Cryptography and Security ComponentThis subsection describes the security features incorporated into the chip, which safeguard data andoperations.4.1.4.1 ECC AcceleratorThe ECC Accelerator accelerates calculations based on the Elliptic Curve Cryptography (ECC) algorithm andECC-derived algorithms like ECDSA, which offers the advantages of smaller public keys compared to RSAcryptography with equivalent security.Feature List• Supports two different elliptic curves (P-192 and P-256)• 11 working modes that supports Base Point Verification, Base Point Multiplication, Jacobian PointVerification, and Jacobian Point Multiplication• Secure operating mode for Base Point Multiplication in a fixed amount of time4.1.4.2 Elliptic Curve Digital Signature Algorithm (ECDSA)In cryptography, the Elliptic Curve Digital Signature Algorithm (ECDSA) offers a variant of the Digital SignatureAlgorithm (DSA) which uses elliptic-curve cryptography.ESP32-C61’s ECDSA accelerator provides a secure and efficient environment for computing ECDSA signatures.It offers fast computations while ensuring the confidentiality of the signing process to prevent information leakage.This makes it a valuable tool for applications that require high-speed cryptographic operations with strongsecurity guarantees. By using the ECDSA accelerator, users can be confident that their data is being protectedwithout sacrificing performance.Espressif Systems 42 ESP32-C61 Series Datasheet v1.0 4 Functional DescriptionFeature List• Digital signature generation and verification• Two elliptic curves, namely P-192 and P-256 defined in FIPS 186-3• Two hash algorithms for message hash in the ECDSA operation, namely SHA-224 and SHA-256 defined inFIPS PUB 180-4• High security features:– Dynamic access permission in different operation statuses to ensure information security, preventingkey leakage due to intermediate data leakage– Fixed-duration signing and verification processes to resist side-channel attacks4.1.4.3 SHA AcceleratorESP32-C61 integrates an SHA accelerator, which is a hardware device that speeds up the SHA algorithmsignificantly, compared to SHA algorithms implemented solely in software. The SHA accelerator has two workingmodes, Typical SHA and DMA-SHA.Feature List• Support for multiple SHA algorithms: SHA-1, SHA-224, and SHA-256• Two working modes: Typical SHA based on CPU and DMA-SHA based on DMA• Interleaved function in Typical SHA working mode• Interrupt function in DMA-SHA working mode4.1.4.4 External Memory Encryption and DecryptionThe ESP32-C61 integrates an External Memory Encryption and Decryption module that complies with theXTS-AES standard algorithm specified in IEEE Std 1619-2007, providing security for users’ application code anddata stored in the external memory (flash and PSRAM). Users can store proprietary firmware and sensitive data(e.g., credentials for gaining access to a private network) to the external flash, and securely run data-sensitiveapplications in PSRAM.Feature List• General XTS-AES algorithm, compliant with IEEE Std 1619-2007• Software-based manual encryption• High-speed auto decryption without software• Encryption and decryption functions jointly enabled/disabled by registers configuration, eFuse parameters,and boot mode• configurable counter measures against DPA attacks• Flash and PSRAM use their own separate keysEspressif Systems 43 ESP32-C61 Series Datasheet v1.0 4 Functional Description4.1.4.5 True Random Number GeneratorThe ESP32-C61 contains a true random number generator, which generates 32-bit random numbers that can beused for cryptographical operations, among other things.The true random number generator in ESP32-C61 generates true random numbers, which means randomnumbers generated from a physical process, rather than by means of an algorithm. No number generated withinthe specified range is more or less likely to appear than any other number.Feature List• RNG entropy source– Thermal noise from high-speed ADC or SAR ADC– An asynchronous clock mismatch4.1.4.6 Power Glitch DetectorESP32-C61 can monitor the voltage of the power supply in real time. When a voltage glitch occurs, the chip willreset immediately to prevent power glitch attacks.Feature List• Configurable threshold for power glitch (around 2.7 V by default)• Enabled upon power-upEspressif Systems 44 ESP32-C61 Series Datasheet v1.0 4 Functional Description4.2 PeripheralsThis section describes the chip’s peripheral capabilities, covering connectivity interfaces and on-chip sensors thatextend its functionality.4.2.1 Connectivity InterfaceThis subsection describes the connectivity interfaces on the chip that enable communication and interaction withexternal devices and networks.4.2.1.1 UART ControllerThe UART Controller in the ESP32-C61 chip facilitates the transmission and reception of asynchronous serialdata between the chip and external UART devices. It supports three UART interfaces.Feature List• Programmable baud rates up to 5 MBaud• RAM shared by TX FIFOs and RX FIFOs• Support for various lengths of data bits and stop bits• Parity bit support• Special character AT_CMD detection• RS485 protocol support• IrDA protocol support• High-speed data communication using GDMA• Receive timeout feature• UART as the wake-up source• Software and hardware flow controlPin AssignmentThe pins connected to transmit and receive signals (U0TXD and U0RXD) for UART0 are multiplexed with GPIO10~ GPIO11 via IO MUX. Other signals can be routed to any GPIOs via the GPIO matrix.4.2.1.2 SPI ControllerESP32-C61 has the following SPI interfaces:• SPI0 used by ESP32-C61’s cache and GDMA to access in-package or off-package flash/PSRAM• SPI1 used by the CPU to access in-package or off-package flash/PSRAM• SPI2 is a general-purpose SPI controller with access to general-purpose DMA channelsSPI0 and SPI1 are reserved for system use, and only SPI2 is available for users.Espressif Systems 45 ESP32-C61 Series Datasheet v1.0 4 Functional DescriptionFeatures of SPI0 and SPI1• Supports Single SPI, Dual SPI, Quad SPI, QPI modes• Data transmission is in bytesFeatures of SPI2• Supports operation as a master or slave• Support for DMA• Supports Single SPI, Dual SPI, Quad SPI, QPI modes• Configurable clock polarity (CPOL) and phase (CPHA)• Configurable clock frequency• Data transmission is in bytes• Configurable read and write data bit order: most-significant bit (MSB) first, or least-significant bit (LSB) first• As a master– Supports 2-line full-duplex communication with clock frequency up to 80 MHz– Supports 1-, 2-, 4-line half-duplex communication with clock frequency up to 80 MHz– Provides six FSPICS… pins for connection with six independent SPI slaves– Configurable CS setup time and hold time• As a slave– Supports 2-line full-duplex communication with clock frequency up to 60 MHz– Supports 1-, 2-, 4-line half-duplex communication with clock frequency up to 60 MHzPin AssignmentFor SPI0/1, the pins are multiplexed with GPIO14 ~ GPIO17 and GPIO19 ~ GPIO20 via the IO MUX.For SPI2, the pins for data and clock signals are multiplexed with GPIO2, GPIO7, and JTAG interface via the IOMUX. The pins for chip select signals for multiplexed with GPIO8 via the IO MUX.For more information about the pin assignment, see Section 2.3 IO Pins.4.2.1.3 I2C ControllerThe I2C Controller supports communication between the master and slave devices using the I2C bus.Feature List• Communication with multiple external devices• Master and slave modes for I2C• Standard mode (100 Kbit/s) and fast mode (400 Kbit/s)• SCL clock stretching in slave modeEspressif Systems 46 ESP32-C61 Series Datasheet v1.0 4 Functional Description• Programmable digital noise filtering• Support for 7-bit and 10-bit addressing, as well as dual address modePin AssignmentFor regular I2C, the pins used can be chosen from any GPIOs via the GPIO Matrix.For more information about the pin assignment, see Section 2.3 IO Pins.4.2.1.4 I2S ControllerThe I2S Controller in the ESP32-C61 chip provides a flexible communication interface for streaming digital data inmultimedia applications, particularly digital audio applications.Feature List• Master mode and slave mode• Full-duplex and half-duplex communications• Separate TX and RX units that can work independently or simultaneously• A variety of audio standards supported:– TDM Philips standard– TDM MSB alignment standard– TDM PCM standard– PDM standard• PCM-to-PDM TX interface• Configurable high-precision BCK clock, with frequency up to 40 MHz– Sampling frequencies can be 8 kHz, 16 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 128 kHz,192 kHz, etc.• 8-/16-/24-/32-bit data communication• Direct Memory Access (DMA)• A-law and µ-law compression/decompression algorithms for improved signal-to-quantization noise ratio• Flexible data format controlPin AssignmentThe pins for the I2S Controller can be chosen from any GPIOs via the GPIO Matrix.For more information about the pin assignment, see Section 2.3 IO Pins.4.2.1.5 USB Serial/JTAG ControllerThe USB Serial/JTAG controller in the ESP32-C61 chip provides an integrated solution for communicating to thechip over a standard USB CDC-ACM serial port as well as a convenient method for JTAG debugging. Iteliminates the need for external chips or JTAG adapters, saving space and reducing cost.Espressif Systems 47 ESP32-C61 Series Datasheet v1.0 4 Functional DescriptionFeature List• USB 2.0 full speed compliant, capable of up to 12 Mbit/s transfer speed (Note that this controller does notsupport the faster 480 Mbit/s high-speed transfer mode)• CDC-ACM virtual serial port and JTAG adapter functionality• CDC-ACM:– CDC-ACM adherent serial port emulation (plug-and-play on most modern OSes)– Host controllable chip reset and entry into download mode• JTAG adapter functionality:– Fast communication with CPU debugging core using a compact representation of JTAG instructions• Support for reprogramming of attached flash memory through the ROM startup code• Internal PHYPin AssignmentThe pins for the USB Serial/JTAG Controller are multiplexed with GPIO12 ~ GPIO13 via IO MUX.For more information about the pin assignment, see Section 2.3 IO Pins.4.2.1.6 LED PWM ControllerThe LED PWM controller can generate independent digital waveform on six channels. The LED PWM controllersupports:Feature List• Generating digital waveform with configurable periods and duty cycle. The resolution of duty cycle can beup to 20 bits• Multiple clock sources, including 80 MHz PLL clock, external main crystal clock, and internal fast RCoscillator• Operation when the CPU is in Light-sleep mode• Gradual increase or decrease of duty cycle, which is useful for the LED RGB color-gradient generator• Up to 16 duty cycle ranges for gamma curve generation, each can be independently configured in terms ofduty cycle direction (increase or decrease), step size, the number of steps, and step frequencyPin AssignmentThe pins for the LED PWM Controller can be chosen from any GPIOs via the GPIO Matrix.For more information about the pin assignment, see Section 2.3 IO Pins.4.2.1.7 SDIO Slave ControllerThe SDIO Slave controller in ESP32-C61 provides hardware support for the Secure Digital Input/Output (SDIO)device interface. It allows an SDIO host to access ESP32-C61 via an SDIO bus protocol.Espressif Systems 48 ESP32-C61 Series Datasheet v1.0 4 Functional DescriptionFeature List• compatible with SDIO Physical Layer Specification V2.00 and SDIO Specifications V2.00• support SPI, 1-bit SDIO, and 4-bit SDIO transfer modes• clock range of 0 ~ 50 MHz• configurable sample and drive clock edge• integrated and SDIO-accessible registers for information interaction• support SDIO interrupts• automatic padding data and discarding the padded data on the SDIO bus• block size up to 512 bytes• interrupt vector between the host and slave for bidirectional interrupt• support DMA for data transfer• support wake-up from sleep when connection is retainedPin AssignmentThe pins for the SDIO Slave controller are multiplexed with GPIO22 ~ GPIO23, and GPIO25 ~ GPIO28 via IOMUX.For more information about the pin assignment, see Section 2.3 IO Pins.4.2.2 Analog Signal ProcessingThis subsection describes components on the chip that sense and process real-world data.4.2.2.1 SAR ADCESP32-C61 integrates a Successive Approximation Analog-to-Digital Converter (SAR ADC) to convert analogsignals into digital representations.Feature List• 12-bit sampling resolution• Analog voltage sampling from up to four pins• Attenuation of input signals for voltage conversion• Software-triggered one-time sampling• Timer-triggered multi-channel scanning• DMA continuous conversion for seamless data transfer• Two filters with configurable filter coefficient• Threshold monitoring which helps to trigger an interrupt• Support for Event Task MatrixEspressif Systems 49 ESP32-C61 Series Datasheet v1.0 4 Functional DescriptionPin AssignmentThe SAR ADC pins are multiplexed with GPIO1 and GPIO3 ~ GPIO5. These GPIOs are also multiplexed withLP_GPIO1, LP_GPIO3 ~ LP_GPIO5, and with the JTAG interface.For more information about the pin assignment, see Section 2.3 IO Pins.4.2.2.2 Temperature SensorThe Temperature Sensor in the ESP32-C61 chip allows for real-time monitoring of temperature changes insidethe chip.Feature List• Measurement range: –40°C ~ 125°C• Software triggering, wherein the data can be read continuously once triggered• Hardware automatic triggering and temperature monitoring• Configurable temperature offset based on the environment to improve the accuracy• Adjustable measurement range• Two automatic monitoring wake-up modes: absolute value mode and incremental value mode• Support for Event Task Matrix4.2.2.3 Analog Voltage ComparatorESP32-C61 provides a group of analog voltage comparators which contain two special pads. This peripheralcan be used to compare the voltages of the two pads or compare the voltage of one pad with an internallyadjustable stable voltage.Feature List• Internal or external reference voltage• Supported internal reference voltage ranging from 0 to 0.7 × VDD_PST• Support for ETM• Interrupt triggered when the measured voltage reaches the reference voltagePin AssignmentThe analog voltage comparator has dedicated pads, GPIO8 and GPIO9. GPIO9 is the test pad, and GPIO8serves as the reference pad when using an external reference voltage.For more information about the pin assignment, see Section 2.3 IO Pins.Espressif Systems 50 ESP32-C61 Series Datasheet v1.0 4 Functional Description4.3 Wireless CommunicationThis section describes the chip’s wireless communication capabilities, spanning radio technology, Wi-Fi, andBluetooth.4.3.1 RadioThis subsection describes the fundamental radio technology embedded in the chip that facilitates wirelesscommunication and data exchange.4.3.1.1 2.4 GHz ReceiverThe 2.4 GHz receiver demodulates the 2.4 GHz RF signal to quadrature baseband signals and converts them tothe digital domain with two high-resolution, high-speed ADCs. To adapt to varying signal channel conditions,ESP32-C61 integrates RF filters, Automatic Gain Control (AGC), DC offset cancelation circuits, and basebandfilters.4.3.1.2 2.4 GHz TransmitterThe 2.4 GHz transmitter modulates the quadrature baseband signals to the 2.4 GHz RF signal, and drives theantenna with a high-powered CMOS power amplifier. The use of digital calibration further improves the linearity ofthe power amplifier.Additional calibrations are integrated to cancel any radio imperfections, such as:• Carrier leakage• I/Q amplitude/phase matching• Baseband nonlinearities• RF nonlinearities• Antenna matchingThese built-in calibration routines reduce the cost, time, and specialized equipment required for producttesting.4.3.1.3 Clock GeneratorThe clock generator produces quadrature clock signals of 2.4 GHz for both the receiver and the transmitter. Allcomponents of the clock generator are integrated into the chip, including inductors, varactors, filters, regulatorsand dividers.The clock generator has built-in calibration and self-test circuits. Quadrature clock phases and phase noise areoptimized on chip with patented calibration algorithms which ensure the best performance of the receiver and thetransmitter.4.3.2 Wi-FiThis subsection describes the chip’s Wi-Fi capabilities, which facilitate wireless communication at a high datarate.Espressif Systems 51 ESP32-C61 Series Datasheet v1.0 4 Functional Description4.3.2.1 Wi-Fi Radio and BasebandThe ESP32-C61 Wi-Fi radio and baseband support the following features:• 1T1R in 2.4 GHz band• 802.11ax– 20 MHz-only non-AP mode– MCS0 ~MCS9– Uplink and downlink OFDMA– Downlink MU-MIMO (multi-user, multiple input, multiple output)– Longer OFDM symbol, with 0.8, 1.6, 3.2 µs guard interval– DCM (dual carrier modulation), up to 16-QAM– Single-user/multi-user beamformee– Channel quality indication (CQI)– RX STBC (single spatial stream)• 802.11b/g/n– MCS0 ~MCS7 that supports 20 MHz and 40 MHz bandwidth– MCS32– Data rate up to 150 Mbps– 0.4 µs guard interval• Adjustable transmitting power• Antenna diversityESP32-C61 supports antenna diversity with an external RF switch. This switch is controlled by one or moreGPIOs, and used to select the best antenna to minimize the effects of channel imperfections.4.3.2.2 Wi-Fi MACESP32-C61 implements the full IEEE 802.11 b/g/n/ax Wi-Fi MAC protocol. ESP32-C61 supports the BasicService Set (BSS) STA and SoftAP operations under the Enhanced Distributed Channel Access (EDCA). Powermanagement is handled automatically with minimal host interaction to minimize the active duty period.The ESP32-C61 Wi-Fi MAC applies the following low-level protocol functions automatically:• Four virtual Wi-Fi interfaces• Infrastructure BSS in Station mode, SoftAP mode, Station + SoftAP mode, and promiscuous mode• RTS protection, CTS-to-Self protection, Immediate Block ACK• Fragmentation and defragmentation• TX/RX A-MPDU, TX/RX A-MSDU• Transmit opportunity (TXOP)Espressif Systems 52 ESP32-C61 Series Datasheet v1.0 4 Functional Description• Wi-Fi multimedia (WMM)• GCMP, CCMP, TKIP, WAPI, WEP, BIP, WPA2-PSK, and WPA3-PSK• Automatic beacon monitoring (hardware TSF)• 802.11mc FTM• 802.11ax supports:– Target wake time (TWT) requester– Multiple BSSIDs– Triggered response scheduling– Multi-user Request-to-Send (MU-RTS), Multi-user Block ACK Request (MU-BAR), and Multi-STABlock ACK (M-BA) frame– Intra-PPDU power saving mechanism– Two network allocation vectors (NAV)– BSS coloring– Spatial reuse– Uplink power headroom– Operating mode control– Buffer status report– TXOP duration RTS threshold– UL-OFDMA random access (UORA)4.3.2.3 Networking FeaturesEspressif provides libraries for TCP/IP networking, ESP-WIFI-MESH networking, and other networking protocolsover Wi-Fi. TLS 1.0, 1.1, and 1.2 is also supported.4.3.3 Bluetooth LEThis subsection describes the chip’s Bluetooth capabilities, which facilitate wireless communication forlow-power, short-range applications.4.3.3.1 Bluetooth LE PHYBluetooth Low Energy PHY in ESP32-C61 supports:• 1 Mbps PHY• 2 Mbps PHY for higher data rates• coded PHY for longer range (125 Kbps and 500 Kbps)• HW listen before talk (LBT)Espressif Systems 53 ESP32-C61 Series Datasheet v1.0 4 Functional Description4.3.3.2 Bluetooth LE Link ControllerBluetooth Low Energy Link Controller and Host in ESP32-C61 support:• direction finding (AoA/AoD)• periodic advertising with responses (PAwR)• LE connection subrating (LE enhanced connection update)• LE advertising extensions and multiple advertising sets• allow devices to operate in Broadcaster, Observer, Central, and Peripheral roles concurrently• adaptive frequency hopping and channel assessment• LE channel selection algorithm #2• LE power control• advertising coding selection• encrypted advertising data• LE GATT security levels characteristic• AdvDataInfo in periodic advertising• LE channel classification• enhanced attribute protocol• advertising channel index• GATT caching• periodic advertising sync transfer• high duty cycle non-connectable advertising• LE data packet length extension• LE secure connections• LE privacy 1.2• link layer extended scanner filter policies• low duty cycle directed advertising• link layer encryption• LE pingEspressif Systems 54 ESP32-C61 Series Datasheet v1.0 5 Electrical Characteristics5 Electrical Characteristics5.1 Absolute Maximum RatingsStresses above those listed in Table 5-1 Absolute Maximum Ratings may cause permanent damage to the device.These are stress ratings only and normal operation of the device at these or any other conditions beyond thoseindicated in Section 5.2 Recommended Operating Conditions is not implied. Exposure toabsolute-maximum-rated conditions for extended periods may affect device reliability.Table 5-1. Absolute Maximum RatingsParameter Description Min Max UnitInput power pins1Allowed input voltage –0.3 3.6 VIoutput2Cumulative IO output current — 1500 mATST OREStorage temperature –40 150 °C1For more information on input power pins, see Section 2.5.1 Power Pins.2The product proved to be fully functional after all its IO pins were pulled highwhile being connected to ground for 24 consecutive hours at ambient temper-ature of 25 °C.5.2 Recommended Operating ConditionsTable 5-2. Recommended Operating ConditionsParameter1Description Min Typ Max UnitVDDA1, VDDA2, VDDA3P3 Recommended input voltage 3.0 3.3 3.6 VVDDPST1 Recommended input voltage 3.0 3.3 3.6 VVDD_SPI (as input) — 1.8 3.3 3.6 VVDDPST22,3Recommended input voltage 3.0 3.3 3.6 VIV DDCumulative input current 0.5 — — A1See in conjunction with Section 2.5 Power Supply.2If VDDPST2 is used to power VDD_SPI (see Section 2.5.2 Power Scheme), the voltage dropon RSP Ishould be accounted for.3If writing to eFuses, the voltage on VDDPST2 should not exceed 3.3 V as the circuits respon-sible for burning eFuses are sensitive to higher voltages.Espressif Systems 55 ESP32-C61 Series Datasheet v1.0 5 Electrical Characteristics5.3 VDD_SPI Output CharacteristicsTable 5-3. VDD_SPI Internal and Output CharacteristicsParameter Description1Typ UnitRSP IVDD_SPI powered by VDD3P3_RTC via RSP Ifor 3.3 V flash/PSRAM23 Ω1See in conjunction with Section 2.5.2 Power Scheme.2VDD3P3_RTC must be more than VDD_flash_min + I_flash_max × RSP I;where• VDD_flash_min – minimum operating voltage of flash/PSRAM• I_flash_max – maximum operating current of flash/PSRAM5.4 ADC CharacteristicsThe measurements in this section are taken with an external 100 nF capacitor connected to the ADC, using DCsignals as input, and at an ambient temperature of 25 °C with disabled Wi-Fi.Table 5-4. ADC CharacteristicsSymbol Min Max UnitDNL (Differential nonlinearity)1–5 5 LSBINL (Integral nonlinearity) –5 5 LSBSampling rate — 2000 kSPS21To get better DNL results, you can sample multiple times and applya filter, or calculate the average value.2kSPS means kilo samples-per-second.The calibrated ADC results after hardware calibration and software calibration are shown in Table 5-5. For higheraccuracy, you may implement your own calibration methods.Table 5-5. ADC Calibration ResultsParameter Description Min Max UnitTotal errorATTEN0, effective measurement range of 0 ~ 1000 –10 10 mVATTEN1, effective measurement range of 0 ~ 1300 –10 10 mVATTEN2, effective measurement range of 0 ~ 1900 –12 12 mVATTEN3, effective measurement range of 0 ~ 3300 –15 15 mV5.5 Current Consumption Characteristics5.5.1 Current Consumption in Active ModeThe current consumption measurements are taken with a 3.3 V supply at 25 °C ambient temperature.TX current consumption is rated at a 100% duty cycle.RX current consumption is rated when the peripherals are disabled and the CPU idle.Espressif Systems 56 ESP32-C61 Series Datasheet v1.0 5 Electrical CharacteristicsTable 5-6. Current Consumption for Wi-Fi (2.4 GHz) in Active ModeWork Mode RF Condition Description Peak (mA)Active (RF working)TX802.11b, 1 Mbps, DSSS @21 dBm 360802.11g, 54 Mbps, OFDM @19 dBm 310802.11n, HT20, MCS7 @18 dBm 285802.11n, HT40, MCS7 @17.5 dBm 267802.11ax, MCS9 @15 dBm 240RX802.11b/g/n, HT20 88802.11n, HT40 90802.11ax, HE20 88Table 5-7. Current Consumption for Bluetooth LE in Active ModeWork Mode RF Condition Description Peak (mA)Active (RF working)TXBluetooth LE @ 18 dBm 283Bluetooth LE @ 9 dBm 160Bluetooth LE @ 0 dBm 128Bluetooth LE @ –15 dBm 96RX Bluetooth LE 815.5.2 Current Consumption in Other ModesTable 5-8. Current Consumption in Modem-sleep ModeTyp (mA)ModeCPU Frequency(MHz) DescriptionAll PeripheralsClocks DisabledAll PeripheralsClocks Enabled1Modem-sleep2,3160WAITI 11 18CPU while loop 16 23Run CoreMark 21 2880WAITI 10 16CPU while loop 12 19Run CoreMark 15 2140WAITI 6 11CPU while loop 7 12Run CoreMark 9 131In practice, the current consumption might be different depending on which peripherals areenabled.2In Modem-sleep mode, Wi-Fi is clock gated.3In Modem-sleep mode, the consumption might be higher when accessing flash.Espressif Systems 57 ESP32-C61 Series Datasheet v1.0 5 Electrical CharacteristicsTable 5-9. Current Consumption in Low-Power ModesMode Description Typ (mA)Light-sleepCPU and wireless communication modules are powered down, pe-ripheral clocks are disabled, and all GPIOs are high-impedance0.2CPU, wireless communication modules and peripherals are pow-ered down, and all GPIOs are high-impedance0.05Deep-sleep LP timer and LP memory are powered on 0.01Power off CHIP_PU is set to low level, the chip is powered off 0.0015.6 Memory SpecificationsThe data below is sourced from the memory vendor datasheet. These values are guaranteed through designand/or characterization but are not fully tested in production. Devices are shipped with the memoryerased.Table 5-10. Flash SpecificationsParameter Description Min Typ Max UnitVCCPower supply voltage (1.8 V) 1.65 1.80 2.00 VPower supply voltage (3.3 V) 2.7 3.3 3.6 VFCMaximum clock frequency 80 — — MHz— Program/erase cycles 100,000 — — cyclesTRETData retention time 20 — — yearsTP PPage program time — 0.8 5 msTSESector erase time (4 KB) — 70 500 msTBE1Block erase time (32 KB) — 0.2 2 sTBE2Block erase time (64 KB) — 0.3 3 sTCEChip erase time (16 Mb) — 7 20 sChip erase time (32 Mb) — 20 60 sChip erase time (64 Mb) — 25 100 sChip erase time (128 Mb) — 60 200 sChip erase time (256 Mb) — 70 300 sTable 5-11. PSRAM SpecificationsParameter Description Min Typ Max UnitVCCPower supply voltage (1.8 V) 1.62 1.80 1.98 VPower supply voltage (3.3 V) 2.7 3.3 3.6 VFCMaximum clock frequency 80 — — MHz5.7 ReliabilityEspressif Systems 58 ESP32-C61 Series Datasheet v1.0 5 Electrical CharacteristicsTable 5-12. Reliability QualificationsTest Item Test Conditions Test StandardHTOL (High TemperatureOperating Life)125 °C, 1000 hours JESD22-A108ESD (Electro-StaticDischarge Sensitivity)HBM (Human Body Mode)1± 2000 V JS-001CDM (Charge Device Mode)2± 1000 V JS-002Latch upCurrent trigger ± 200 mAJESD78Voltage trigger 1.5 × VDDmaxPreconditioningBake 24 hours @125 °CMoisture soak (level 3: 192 hours @30 °C, 60% RH)IR reflow solder: 260 + 0 °C, 20 seconds, three timesJ-STD-020, JESD47,JESD22-A113TCT (Temperature CyclingTest)–65 °C / 150 °C, 500 cycles JESD22-A104uHAST (HighlyAccelerated Stress Test,unbiased)130 °C, 85% RH, 96 hours JESD22-A118HTSL (High TemperatureStorage Life)150 °C, 1000 hours JESD22-A103LTSL (Low TemperatureStorage Life)–40 °C, 1000 hours JESD22-A1191JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.2JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.Espressif Systems 59 ESP32-C61 Series Datasheet v1.0 6 RF Characteristics6 RF CharacteristicsThis section contains tables with RF characteristics of the Espressif product.The RF data is measured at the antenna port, where RF cable is connected, including the front-end loss. Thefront-end circuit is a 0 Ω resistor.Devices should operate in the center frequency range allocated by regional regulatory authorities. The targetcenter frequency range and the target transmit power are configurable by software. See ESP RF Test Tool andTest Guide for instructions.Unless otherwise stated, the RF tests are conducted with a 3.3 V (±5%) supply at 25 ºC ambient temperature.6.1 Wi-Fi Radio (2.4 GHz)Table 6-1. Wi-Fi RF CharacteristicsName DescriptionCenter frequency range of operating channel 2412 ~ 2484 MHzWi-Fi wireless standard IEEE 802.11b/g/n/ax6.1.1 Wi-Fi RF Transmitter (TX) CharacteristicsTable 6-2. TX Power with Spectral Mask and EVM Meeting 802.11 StandardsMin Typ MaxRate (dBm) (dBm) (dBm)802.11b, 1 Mbps, DSSS — 21.0 —802.11b, 11 Mbps, CCK — 21.0 —802.11g, 6 Mbps, OFDM — 20.0 —802.11g, 54 Mbps, OFDM — 19.0 —802.11n, HT20, MCS0 — 19.0 —802.11n, HT20, MCS7 — 18.0 —802.11n, HT40, MCS0 — 18.5 —802.11n, HT40, MCS7 — 17.5 —802.11ax, HE20, MCS0 — 19.0 —802.11ax, HE20, MCS9 — 15.0 —Table 6-3. TX EVM Test1Min Typ LimitRate (dB) (dB) (dB)802.11b, 1 Mbps, DSSS — –24.8 –10.0802.11b, 11 Mbps, CCK — –24.8 –10.0802.11g, 6 Mbps, OFDM — –26.0 –5.0Cont’d on next pageEspressif Systems 60 ESP32-C61 Series Datasheet v1.0 6 RF CharacteristicsTable 6-3 – cont’d from previous pageMin Typ LimitRate (dB) (dB) (dB)802.11g, 54 Mbps, OFDM — –29.0 –25.0802.11n, HT20, MCS0 — –24.5 –5.0802.11n, HT20, MCS7 — –31.5 –27.0802.11n, HT40, MCS0 — –26.8 –5.0802.11n, HT40, MCS7 — –30.5 –27.0802.11ax, HE20, MCS0 — –26.0–5.0802.11ax, HE20, MCS9 — –34.0 –32.01EVM is measured at the corresponding typical TX power provided inTable 6-2 Wi-Fi RF Transmitter (TX) Characteristics above.6.1.2 Wi-Fi RF Receiver (RX) CharacteristicsFor RX tests, the PER (packet error rate) limit is 8% for 802.11b, and 10% for 802.11g/n/ax.Table 6-4. RX SensitivityMin Typ MaxRate (dBm) (dBm) (dBm)802.11b, 1 Mbps, DSSS — –99.5 —802.11b, 2 Mbps, DSSS — –96.5 —802.11b, 5.5 Mbps, CCK — –94.0 —802.11b, 11 Mbps, CCK — –90.0 —802.11g, 6 Mbps, OFDM — –94.0 —802.11g, 9 Mbps, OFDM — –93.0—802.11g, 12 Mbps, OFDM — –92.0 —802.11g, 18 Mbps, OFDM — –90.0 —802.11g, 24 Mbps, OFDM — –87.0 —802.11g, 36 Mbps, OFDM — –83.5 —802.11g, 48 Mbps, OFDM — –79.0 —802.11g, 54 Mbps, OFDM — –77.5 —802.11n, HT20, MCS0 — –94.0 —802.11n, HT20, MCS1 — –92.5 —802.11n, HT20, MCS2 — –89.5 —802.11n, HT20, MCS3 — –86.5 —802.11n, HT20, MCS4 — –83.0 —802.11n, HT20, MCS5 — –79.0 —802.11n, HT20, MCS6 — –77.0 —802.11n, HT20, MCS7 — –75.5 —802.11n, HT40, MCS0 — –91.0 —802.11n, HT40, MCS1 — –90.0 —802.11n, HT40, MCS2 — –87.0 —Cont’d on next pageEspressif Systems 61 ESP32-C61 Series Datasheet v1.0 6 RF CharacteristicsTable 6-4 – cont’d from previous pageMin Typ MaxRate (dBm) (dBm) (dBm)802.11n, HT40, MCS3 — –83.5 —802.11n, HT40, MCS4 — –80.5 —802.11n, HT40, MCS5 — –76.0 —802.11n, HT40, MCS6 — –74.5 —802.11n, HT40, MCS7 — –73.5 —802.11ax, HE20, MCS0 — –94.0—802.11ax, HE20, MCS1 — –91.0 —802.11ax, HE20, MCS2 — –88.0 —802.11ax, HE20, MCS3 — –85.5 —802.11ax, HE20, MCS4 — –82.0 —802.11ax, HE20, MCS5 — –78.0 —802.11ax, HE20, MCS6 — –76.5 —802.11ax, HE20, MCS7 — –74.5 —802.11ax, HE20, MCS8 — –71.0 —802.11ax, HE20, MCS9 — –68.0 —Table 6-5. Maximum RX LevelMin Typ MaxRate (dBm) (dBm) (dBm)802.11b, 1 Mbps, DSSS — 5 —802.11b, 11 Mbps, CCK — 5 —802.11g, 6 Mbps, OFDM — 5 —802.11g, 54 Mbps, OFDM — 0 —802.11n, HT20, MCS0 — 5 —802.11n, HT20, MCS7 — 0 —802.11n, HT40, MCS0 — 5 —802.11n, HT40, MCS7 — 0 —802.11ax, HE20, MCS0 — 5 —802.11ax, HE20, MCS9 — 0 —Table 6-6. RX Adjacent Channel RejectionMin Typ MaxRate (dB) (dB) (dB)802.11b, 1 Mbps, DSSS — 38 —802.11b, 11 Mbps, CCK — 38 —802.11g, 6 Mbps, OFDM — 33 —802.11g, 54 Mbps, OFDM — 16 —802.11n, HT20, MCS0 — 32 —Cont’d on next pageEspressif Systems 62 ESP32-C61 Series Datasheet v1.0 6 RF CharacteristicsTable 6-6 – cont’d from previous pageMin Typ MaxRate (dB) (dB) (dB)802.11n, HT20, MCS7 — 17 —802.11n, HT40, MCS0 — 24 —802.11n, HT40, MCS7 — 13 —802.11ax, HE20, MCS0 — 37 —802.11ax, HE20, MCS9 — 13 —6.2 Bluetooth 5 (LE) RadioTable 6-7. Bluetooth LE RF CharacteristicsName DescriptionCenter frequency range of operating channel 2402 ~ 2480 MHzRF transmit power range –15 ~ 20 dBm6.2.1 Bluetooth LE RF Transmitter (TX) CharacteristicsTable 6-8. Bluetooth LE - Transmitter Characteristics - 1 MbpsParameter Description Min Typ Max UnitCarrier frequency offset and driftMax. |fn|n=0, 1, 2, 3, ...k— 10.85 — kHzMax. |f0 −fn|n=2, 3, 4, ...k— 3.5 — kHzMax. |fn −fn−5|n=6, 7, 8, ...k— 2.4 — kHz|f1 −f0| — 2.7 — kHzModulation characteristics∆ F 1avg— 250.0 — kHzMin. ∆ F 2max(for at least99.9% of all ∆ F 2max)— 243.0 — kHz∆ F 2avg/∆ F 1avg— 0.88 — —In-band emissions± 2 MHz offset — –27 — dBm± 3 MHz offset — –36 — dBm> ± 3 MHz offset — –42 — dBmTable 6-9. Bluetooth LE - Transmitter Characteristics - 2 MbpsParameter Description Min Typ Max UnitCarrier frequency offset and driftMax. |fn|n=0, 1, 2, 3, ...k— 9.4 — kHzMax. |f0 −fn|n=2, 3, 4, ...k— 3.7 — kHzMax. |fn −fn−5|n=6, 7, 8, ...k— 1.1 — kHz|f1 −f0| — 3.3 — kHzModulation characteristics∆ F 1avg— 499.4 — kHzCont’d on next pageEspressif Systems 63 ESP32-C61 Series Datasheet v1.0 6 RF CharacteristicsTable 6-9 – cont’d from previous pageParameter Description Min Typ Max UnitMin. ∆ F 2max(for at least99.9% of all ∆ F 2max)— 532.0 — kHz∆ F 2avg/∆ F 1avg— 0.95 — —In-band emissions± 4 MHz offset — –41 — dBm± 5 MHz offset — –44 — dBm> ± 5 MHz offset — –45 — dBmTable 6-10. Bluetooth LE - Transmitter Characteristics - 125 KbpsParameter Description Min Typ Max UnitCarrier frequency offset and driftMax. |fn|n=0, 1, 2, 3, ...k— 10.1 — kHzMax. |f0 −fn|n=1, 2, 3, ...k— 2.1 — kHz|f0 −f3| — 1.2 — kHzMax. |fn −fn−3|n=7, 8, 9, ...k— 0.7 — kHzModulation characteristics∆ F 1avg— 253.1 — kHzMin. ∆ F 1max(for at least99.9% of all ∆ F 1max)— 270.5 — kHzIn-band emissions± 2 MHz offset — –27 — dBm± 3 MHz offset — –38 — dBm> ± 3 MHz offset — –43 — dBmTable 6-11. Bluetooth LE - Transmitter Characteristics - 500 KbpsParameter Description Min Typ Max UnitCarrier frequency offset and driftMax. |fn|n=0, 1, 2, 3, ...k— 10.2 — kHzMax. |f0 −fn|n=1, 2, 3, ...k— 1.2 — kHz|f0 −f3| — 0.6 — kHzMax. |fn −fn−3|n=7, 8, 9, ...k— 1.8 — kHzModulation characteristics∆ F 2avg— 223.4 — kHzMin. ∆ F 2max(for at least99.9% of all ∆ F 2max)— 243.5 — kHzIn-band emissions± 2 MHz offset — –27 — dBm± 3 MHz offset — –37 — dBm> ± 3 MHz offset — 43 — dBm6.2.2 Bluetooth LE RF Receiver (RX) CharacteristicsTable 6-12. Bluetooth LE - Receiver Characteristics - 1 MbpsParameter Description Min Typ Max UnitSensitivity @30.8% PER — — –98.0 — dBmMaximum received signal @30.8% PER — — 8 — dBmCont’d on next pageEspressif Systems 64 ESP32-C61 Series Datasheet v1.0 6 RF CharacteristicsTable 6-12 – cont’d from previous pageParameter Description Min Typ Max UnitC/I and receiverselectivity performanceCo-channel F = F0 MHz — 7 — dBAdjacent channelF = F0 + 1 MHz — –2 — dBF = F0 – 1 MHz — –3 — dBF = F0 + 2 MHz — –34 — dBF = F0 – 2 MHz — –27 — dBF = F0 + 3 MHz — –33 — dBF = F0 – 3 MHz — –40 — dBF ≥ F0 + 4 MHz — –27 — dBF ≤ F0 – 4 MHz — –53 — dBImage frequency — — –35 — dBAdjacent channel toimage frequencyF = Fimage+ 1 MHz — –34 — dBF = Fimage– 1 MHz — –33 — dB30 MHz ~ 2000 MHz — –20 — dBmOut-of-band blocking performance2003 MHz ~ 2399 MHz — –25 — dBm2484 MHz ~ 2997 MHz — –25 — dBm3000 MHz ~ 12.75 GHz — –10 — dBmIntermodulation — — –32 — dBmTable 6-13. Bluetooth LE - Receiver Characteristics - 2 MbpsParameter Description Min Typ Max UnitSensitivity @30.8% PER — — –94.0 — dBmMaximum received signal @30.8% PER — — 8 — dBmC/I and receiverselectivity performanceCo-channel F = F0 MHz — 9 — dBAdjacent channelF = F0 + 2 MHz — –7 — dBF = F0 – 2 MHz — –6 — dBF = F0 + 4 MHz — –21 — dBF = F0 – 4 MHz — –27 — dBF = F0 + 6 MHz — –38 — dBF = F0 – 6 MHz — –41 — dBF ≥ F0 + 8 MHz — –46 — dBF ≤ F0 – 8 MHz — –46 — dBImage frequency — — –21 — dBAdjacent channel toimage frequencyF = Fimage+ 2 MHz — –38 — dBF = Fimage– 2 MHz — –7 — dB30 MHz ~ 2000 MHz — –25 — dBmOut-of-band blocking performance2003 MHz ~ 2399 MHz — –25 — dBm2484 MHz ~ 2997 MHz — –25 — dBm3000 MHz ~ 12.75 GHz — –10 — dBmIntermodulation — — –31 — dBmEspressif Systems 65 ESP32-C61 Series Datasheet v1.0 6 RF CharacteristicsTable 6-14. Bluetooth LE - Receiver Characteristics - 125 KbpsParameter Description Min Typ Max UnitSensitivity @30.8% PER — — –106.0 — dBmMaximum received signal @30.8% PER — — 8 — dBmC/I and receiverselectivity performanceCo-channel F = F0 MHz — 4 — dBAdjacent channelF = F0 + 1 MHz — –2 — dBF = F0 – 1 MHz — –3 — dBF = F0 + 2 MHz — –33 — dBF = F0 – 2 MHz — –36 — dBF = F0 + 3 MHz — –35 — dBF = F0 – 3 MHz — –50 — dBF ≥ F0 + 4 MHz — –31 — dBF ≤ F0 – 4 MHz — –50 — dBImage frequency — — –31 — dBAdjacent channel toimage frequencyF = Fimage+ 1 MHz — –36 — dBF = Fimage– 1 MHz — –35 — dBTable 6-15. Bluetooth LE - Receiver Characteristics - 500 KbpsParameter Description Min Typ Max UnitSensitivity @30.8% PER — — –102.0 — dBmMaximum received signal @30.8% PER — — 8 — dBmC/I and receiverselectivity performanceCo-channel F = F0 MHz — 4 — dBAdjacent channelF = F0 + 1 MHz — –4 — dBF = F0 – 1 MHz — –3 — dBF = F0 + 2 MHz — –32 — dBF = F0 – 2 MHz — –36 — dBF = F0 + 3 MHz — –35 — dBF = F0 – 3 MHz — –50 — dBF ≥ F0 + 4 MHz — –29 — dBF ≤ F0 – 4 MHz — –50 — dBImage frequency — — –29 — dBAdjacent channel toimage frequencyF = Fimage+ 1 MHz — –36 — dBF = Fimage– 1 MHz — –35 — dBEspressif Systems 66 ESP32-C61 Series Datasheet v1.0 7 Packaging7 Packaging• For information about tape, reel, and chip marking, please refer to ESP32-C61 Chip Packaging Information.• The pins of the chip are numbered in anti-clockwise order starting from Pin 1 in the top view. For pinnumbers and pin names, see also Figure 2-1 ESP32-C61HR2 & ESP32-C61HR8 & ESP32-C61HF4 PinLayout (Top View) and 2-2 ESP32-C61NF8R8LA Pin Layout (Top View).• The recommended land pattern source file (asc) is available for download. You can import the file withsoftware such as PADS and Altium Designer.40L SLP (5x5MM) TOP VIEw  A □□L   ° ,----------,-,fr-lr--r-+----,L j L  j BOTTOM VIEw ! Lc:=:==:JSIDE VIEw  t Figure 7-1. QFN40 (5×5 mm) PackageEspressif Systems 67 ESP32-C61 Series Datasheet v1.0 7 PackagingD2Xaaa CAEBaaa C2XPIN #1CORNERTop ViewAccc CCCCAVITYSEATING PLANESide ViewBottom View11011202130314041e4×L140×L40×bbbb C A Bddd CD1E1eee C A Beee C A BPIN #1HH1DRAWING NO. REV.DIMENSION AND TOLERANCES SCALEPACKAGE OUTLINE DRAWING[产品外形图]PAGEASME Y14.5MTITLE:DESIGNPROJECTIONA3SIZEMMSIGNATURE AREAAPPROVECHECKDESIGN APPROVEPROCESSSTAND.UNIT甬矽电子 FOREHOPE ELECTRONICFOREHOPE CONFIDENTIAL-BThis document and its information herein are the property of Forehope and all unauthorized use and reproduction are prohibited.14:1symbolDimension in mm Dimension in inchMIN NOM MAX MIN NOM MAXA 0.700 0.800 0.900 0.028 0.031 0.035c 0.190 0.220 0.250 0.007 0.009 0.010D 4.900 5.000 5.100 0.193 0.197 0.201E 4.900 5.000 5.100 0.193 0.197 0.201D1 3.200 3.300 3.400 0.126 0.130 0.134E1 3.200 3.300 3.400 0.126 0.130 0.134H --- 0.309 --- --- 0.012 ---H1 --- 0.309 --- --- 0.012 ---L 0.350 0.400 0.450 0.014 0.016 0.018L1 0.000 0.075 0.150 0.000 0.003 0.006e --- 0.400 --- --- 0.016 ---b0.150 0.200 0.250 0.006 0.008 0.010aaa 0.100 0.004bbb0.150 0.006ccc 0.100 0.004ddd0.080 0.003eee 0.150 0.006 TECHNOLOGY SPECIFICATION[技术要求]1.BAN TO USE THE LEVEL 1 ENVIRONMENT-RELATED SUBSTANCES；[禁止使用一级环境管理物质；]1 OF 1PO-ALGA550X99AKE Chen 2025.11.28YL Zhou 2025.11.28LGA-5X5-41(P0.4 T0.9)Unit: mmFigure 7-2. LGA40 (5×5 mm) PackageEspressif Systems 68 ESP32-C61 Series Datasheet v1.0 Related Documentation and ResourcesRelated Documentation and ResourcesRelated Documentation• ESP32-C61 Technical Reference Manual – Detailed information on how to use the ESP32-C61 memory and pe-ripherals.• ESP32-C61 Hardware Design Guidelines – Guidelines on how to integrate the ESP32-C61 into your hardwareproduct.• Certificateshttps://espressif.com/en/support/documents/certificates• ESP32-C61 Product/Process Change Notifications (PCN)https://espressif.com/en/support/documents/pcns?keys=ESP32-C61• ESP32-C61 Advisories – Information on security, bugs, compatibility, component reliability.https://espressif.com/en/support/documents/advisories?keys=ESP32-C61• Documentation Updates and Update Notification Subscriptionhttps://espressif.com/en/support/download/documentsDeveloper Zone• ESP-IDF Programming Guide for ESP32-C61 – Extensive documentation for the ESP-IDF development framework.• ESP-IDF and other development frameworks on GitHub.https://github.com/espressif• ESP32 BBS Forum – Engineer-to-Engineer (E2E) Community for Espressif products where you can post questions,share knowledge, explore ideas, and help solve problems with fellow engineers.https://esp32.com/• ESP-FAQ – A summary document of frequently asked questions released by Espressif.https://espressif.com/projects/esp-faq/en/latest/index.html• The ESP Journal – Best Practices, Articles, and Notes from Espressif folks.https://blog.espressif.com/• See the tabs SDKs and Demos, Apps, Tools, AT Firmware.https://espressif.com/en/support/download/sdks-demosProducts• ESP32-C61 Series SoCs – Browse through all ESP32-C61 SoCs.https://espressif.com/en/products/socs?id=ESP32-C61• ESP32-C61 Series Modules – Browse through all ESP32-C61-based modules.https://espressif.com/en/products/modules?id=ESP32-C61• ESP32-C61 Series DevKits – Browse through all ESP32-C61-based devkits.https://espressif.com/en/products/devkits?id=ESP32-C61• ESP Product Selector – Find an Espressif hardware product suitable for your needs by comparing or applying filters.https://products.espressif.com/#/product-selector?language=enContact Us• See the tabs Sales Questions, Technical Enquiries, Circuit Schematic & PCB Design Review, Get Samples(Online stores), Become Our Supplier, Comments & Suggestions.https://espressif.com/en/contact-us/sales-questionsEspressif Systems 69 ESP32-C61 Series Datasheet v1.0 Appendix A – ESP32-C61 Consolidated Pin OverviewAppendix A – ESP32-C61 Consolidated Pin OverviewTable 7-1. Pin OverviewPin Pin Pin Pin Providing Pin Settings IO MUX Function LP IO MUX Function Analog FunctionNo. Name Type Power At Reset After Reset F0 Type F1 Type F2 Type F0 F0 F11 ANT_2G Analog - – – – – – – – – – – –2 VDDA3 Power – – – – – – – – – – – –3 VDDA4 Power – – – – – – – – – – – –4 CHIP_PU I VDDPST1 – – – – – – – – – – –5 VDDPST1 Power – – – – – – – – – – – –6 XTAL_32K_P I/O/T VDDPST1 – – GPIO0 I/O/T GPIO0 I/O/T – – LP_GPIO0 XTAL_32K_P –7 XTAL_32K_N I/O/T VDDPST1 – – GPIO1 I/O/T GPIO1 I/O/T – – LP_GPIO1 XTAL_32K_N ADC1_CH08 GPIO2 I/O/T VDDPST1 – – GPIO2 I/O/T GPIO2 I/O/T FSPIQ I1/O/T LP_GPIO2 – –9 MTMS I/O/T VDDPST1 IE IE MTMS I1 GPIO3 I/O/T FSPIHD I1/O/T LP_GPIO3 – ADC1_CH110 MTDI I/O/T VDDPST1 IE IE MTDI I1 GPIO4 I/O/T FSPIWP I1/O/T LP_GPIO4 – ADC1_CH211 MTCK I/O/T VDDPST1 – IE* MTCK I1 GPIO5 I/O/T – – LP_GPIO5 – ADC1_CH312 MTDO I/O/T VDDPST1 – IE MTDO O/T GPIO6 I/O/T FSPICLK I1/O/T LP_GPIO6 – –13 SDIO_CMD I/O/T VDDPST2 – IE SDIO_CMD I1/O/T GPIO25 I/O/T – – – – –14 SDIO_CLK I/O/T VDDPST2 – IE SDIO_CLK I1 GPIO26 I/O/T – – – – –15 SDIO_DATA0 I/O/T VDDPST2 – IE SDIO_DATA0 I1/O/T GPIO27 I/O/T – – – – –16 SDIO_DATA1 I/O/T VDDPST2 – IE SDIO_DATA1 I1/O/T GPIO28 I/O/T – – – – –17 SDIO_DATA2 I/O/T VDDPST2 – IE SDIO_DATA2 I1/O/T GPIO22 I/O/T – – – – –18 SDIO_DATA3 I/O/T VDDPST2 – IE SDIO_DATA3 I1/O/T GPIO23 I/O/T – – – – –19 SPICS1/NC I/O/T VDD_SPI/VDDPST2 – – SPICS1 O/T GPIO14 I/O/T – – – – –20 SPICS0/NC I/O/T VDD_SPI/VDDPST2 – – SPICS0 O/T GPIO15 I/O/T – – – – –21 VDDPST2 Power – – – – – – – – – – – –22 SPIQ/NC I/O/T VDD_SPI/VDDPST2 – – SPIQ I1/O/T GPIO16 I/O/T – – – – –23 SPIWP/NC I/O/T VDD_SPI/VDDPST2 – – SPIWP I1/O/T GPIO17 I/O/T – – – – –24 VDD_SPI/NC Power VDDPST2 – – GPIO18 I/O/T GPIO18 I/O/T – – – VDD_SPI –25 SPIHD/NC I/O/T VDD_SPI/VDDPST2 – – SPIHD I1/O/T GPIO19 I/O/T – – – – –26 SPICLK/NC O VDD_SPI/VDDPST2 – – SPICLK O/T GPIO20 I/O/T – – – – –27 SPID/NC I/O/T VDD_SPI/VDDPST2 – – SPID I1/O/T GPIO21 I/O/T – – – – –28 USB_D- I/O/T VDDPST2 – IE GPIO12 I/O/T GPIO12 I/O/T – – – USB_D- –29 USB_D+ I/O/T VDDPST2 – IE,WPU* GPIO13 I/O/T GPIO13 I/O/T – – – USB_D+ –30 GPIO24 I/O/T VDDPST2 – – GPIO24 I/O/T GPIO24 I/O/T – – – – –31 GPIO8 I/O/T VDDPST2 IE IE GPIO8 I/O/T GPIO8 I/O/T FSPICS0 I1/O/T – ZCD0 –32 GPIO9 I/O/T VDDPST2 IE,WPU IE,WPU GPIO9 I/O/T GPIO9 I/O/T – – – ZCD1 –33 U0RXD I/O/T VDDPST2 – IE,WPU U0RXD I1 GPIO10 I/O/T – – – – –34 U0TXD I/O/T VDDPST2 – IE,WPU U0TXD O GPIO11 I/O/T – – – – –35 GPIO29 I/O/T VDDPST2 – – GPIO29 I/O/T GPIO29 I/O/T – – – – –36 GPIO7 I/O/T VDDPST2 IE IE GPIO7 I/O/T GPIO7 I/O/T FSPID I1/O/T – – –37 VDDA1 Power – – – – – – – – – – – –38 XTAL_N Analog - – – – – – – – – – – –39 XTAL_P Analog - – – – – – – – – – – –40 VDDA2 Power – – – – – – – – – – – –*For details, see Section 2 Pins. Regarding highlighted cells, see Section 2.3.4 Restrictions for GPIOs and LP GPIOs.Espressif Systems 70 ESP32-C61 Series Datasheet v1.0 Revision HistoryRevision HistoryDate Version Release notes2026-01-20 v1.0• Updated the ”Ordering Code” to ”Part Number” in Table 1-1 Comparison• Updated the pin VDD_SPI to NC for ESP32-C61HF42025-11-18 v0.6• Added the new variant ESP32-C61NF8R8LA, and updated section 2.1 PinLayout• Updated figure 3-1 Visualization of Timing Parameters for the Strapping Pins• Updated figure 7 Packaging by removing the TSLP2025-08-05 v0.5 Preliminary release2025-04-22 v0.3• Updated Chapter 2 Pins• Added Section 4.2.1.7 SDIO Slave Controller• Updated Section 4.1.3.1 IO MUX and GPIO Matrix• Updated Section 4.1.3.4 Interrupt Matrix2024-08-26 v0.2• Updated the package from QFN32 to QFN40• Added chip series ESP32-C61HF4R2, and removed ESP32-C61NR4 andESP32-C31 chip series• Updated section 1 ESP32-C61 Series Comparison, section 2 Pins, section 3Boot Configurations and Appendix ESP32-C61 Consolidated Pin Overview• Updated CoreMark score• Updated section Applications2024-01-23 v0.1 DraftEspressif Systems 71 ESP32-C61 Series Datasheet v1.0 Disclaimer and Copyright NoticeInformation in this document, including URL references, is subject to change without notice.ALL THIRD PARTY’S INFORMATION IN THIS DOCUMENT IS PROVIDED AS IS WITH NO WARRANTIES TO ITS AUTHENTICITY ANDACCURACY.NO WARRANTY IS PROVIDED TO THIS DOCUMENT FOR ITS MERCHANTABILITY, NON-INFRINGEMENT, FITNESS FOR ANYPARTICULAR PURPOSE, NOR DOES ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE.All liability, including liability for infringement of any proprietary rights, relating to use of information in this document is disclaimed. No licensesexpress or implied, by estoppel or otherwise, to any intellectual property rights are granted herein.The Wi-Fi Alliance Member logo is a trademark of the Wi-Fi Alliance. The Bluetooth logo is a registered trademark of Bluetooth SIG.All trade names, trademarks and registered trademarks mentioned in this document are property of their respective owners, and are herebyacknowledged.Copyright © 2026 Espressif Systems (Shanghai) Co., Ltd. All rights reserved.www.espressif.com