I Microprocessor and Master 1 RISC-V Trace Encoder (TRACE) 1.1 Terminology 1.2 Introduction 1.3 Features 1.4 Architectural Overview 1.5 Functional Description 1.5.1 Synchronization 1.5.2 Address Mode 1.5.3 Optional Sideband Signals 1.5.4 Filtering 1.5.5 Anchor Tag 1.5.6 Memory Writing Mode 1.5.7 Automatic Restart 1.6 Encoder Output Packets 1.6.1 Header 1.6.2 Index 1.6.3 Payload 1.6.3.1 Format 3 Packets 1.6.3.2 Format 2 Packets 1.6.3.3 Format 1 Packets 1.7 Interrupt 1.8 Programming Procedures 1.8.1 Encoder Option Configuration 1.8.2 Filter Configuration 1.8.3 Enable Encoder 1.8.4 Disable Encoder 1.8.5 Notify 1.8.6 Decode Data Packets 1.8.7 AHB Configuration 1.8.8 Software Retention 1.9 Register Summary 1.10 Registers 2 Low-Power CPU 2.1 Features 2.2 Configuration and Status Registers (CSRs) 2.2.1 Register Summary 2.2.2 Registers 2.3 Interrupts and Exceptions 2.3.1 Interrupts 2.3.2 Interrupt Handling 2.3.3 Exceptions 2.4 Debugging 2.4.1 Features 2.4.2 Functional Description 2.4.3 Register Summary 2.4.4 Registers 2.5 Hardware Trigger 2.5.1 Features 2.5.2 Functional Description 2.5.3 Trigger Execution Flow 2.5.4 Register Summary 2.5.5 Registers 2.6 Performance Counter 2.7 System Access 2.7.1 Memory Access 2.7.2 Peripheral Access 2.8 Event Task Matrix Feature 2.9 Sleep and Wake-Up Process 2.9.1 Features 2.9.2 Process 2.9.3 Wake-Up Sources 2.10 Register Summary 2.11 Registers 3 GDMA Controller (GDMA) 3.1 Overview 3.2 Features 3.3 Architecture 3.4 Functional Description 3.4.1 Linked List 3.4.2 Peripheral-to-Memory and Memory-to-Peripheral Data Transfer 3.4.3 Memory-to-Memory Data Transfer 3.4.4 Enabling GDMA 3.4.5 Linked List Reading Process 3.4.6 EOF 3.4.7 Accessing Memory 3.4.8 Arbitration 3.5 Event Task Matrix Feature 3.6 Interrupts 3.7 Programming Procedures 3.7.1 Programming Procedures for GDMA's Transmit Channel 3.7.2 Programming Procedures for GDMA's Receive Channel 3.7.3 Programming Procedures for Memory-to-Memory Transfer 3.7.4 Programming Procedures for Channel Priority and Weight 3.8 Register Summary 3.9 Registers II Memory Organization 4 System and Memory 4.1 Overview 4.2 Features 4.3 Functional Description 4.3.1 Address Mapping 4.3.2 Internal Memory 4.3.2.1 ROM 4.3.2.2 HP SRAM 4.3.2.3 LP SRAM 4.3.3 External Memory 4.3.3.1 External Memory Address Mapping 4.3.3.2 Cache 4.3.3.3 Cache Operations 4.3.4 GDMA Address Space 4.3.5 Modules/Peripherals Address Mapping 5 eFuse Controller (eFuse) 5.1 Overview 5.2 Features 5.3 Functional Description 5.3.1 Structure 5.3.1.1 EFUSE_WR_DIS 5.3.1.2 EFUSE_RD_DIS 5.3.1.3 Data Storage 5.3.2 Programming of Parameters 5.3.3 Reading of Parameters 5.3.4 eFuse VDDQ Timing 5.3.5 Parameters Used by Hardware Modules 5.4 Interrupts 5.5 Register Summary 5.6 Registers III System Component 6 GPIO Matrix and IO MUX 6.1 Overview 6.2 Features 6.2.1 HP GPIO Matrix and HP IO MUX 6.2.2 LP GPIO Matrix and LP IO MUX 6.3 Architectural Overview 6.4 Peripheral Input via GPIO Matrix 6.4.1 Overview 6.4.2 Signal Synchronization 6.4.3 GPIO Filter 6.4.4 Glitch Filter 6.4.5 Simple GPIO Input 6.4.6 GPIO Wakeup 6.4.6.1 HP GPIO Wakeup 6.4.6.2 LP GPIO Wakeup 6.4.7 Programming Procedure 6.4.7.1 HP GPIO Matrix 6.4.7.2 LP GPIO Matrix 6.5 Peripheral Output via GPIO Matrix 6.5.1 Overview 6.5.2 Simple GPIO Output 6.5.3 Sigma Delta Modulated Output (SDM) 6.5.3.1 Functional Description 6.5.3.2 SDM Configuration 6.5.4 Programming Procedure 6.5.4.1 HP GPIO Matrix 6.5.4.2 LP GPIO Matrix 6.6 Direct Input and Output via IO MUX 6.6.1 Overview 6.6.2 Functional Description 6.6.2.1 HP IO MUX 6.6.2.2 LP IO MUX 6.7 Analog Functions 6.7.1 Overview 6.7.2 Analog Functions 6.8 Pin Functions in Light-sleep 6.9 Pin Hold Feature 6.10 Hysteresis Characteristics 6.11 Power Supplies and Management of GPIO Pins 6.11.1 Power Supplies of GPIO Pins 6.11.2 Power Supply Management 6.12 HP Peripheral Signal List 6.13 HP IO MUX Function List 6.14 LP IO MUX Function List 6.15 GPIO Pin Analog Function List 6.16 Event Task Matrix Function 6.17 Interrupts 6.18 Register Summary 6.18.1 HP GPIO Matrix Register Summary 6.18.2 HP IO MUX Register Summary 6.18.3 GPIO EXT Register Summary 6.18.4 LP GPIO Matrix Register Summary 6.18.5 LP IO MUX Register Summary 6.19 Registers 6.19.1 HP GPIO Matrix Registers 6.19.2 HP IO MUX Registers 6.19.3 GPIO EXT Registers 6.19.4 LP GPIO Matrix Registers 6.19.5 LP IO MUX Registers 7 Reset and Clock 7.1 Reset 7.1.1 Overview 7.1.2 Architectural Overview 7.1.3 Features 7.1.4 Functional Description 7.1.5 Peripheral Reset 7.2 Clock 7.2.1 Overview 7.2.2 Architectural Overview 7.2.3 Features 7.2.4 Functional Description 7.2.4.1 HP System Clock 7.2.4.2 LP System Clock 7.2.4.3 Peripheral Clocks 7.2.4.4 PMU Control of High-Performance System Clock Gating 7.3 Programming Procedures 7.3.1 HP System Clock Configuration 7.3.2 LP System Clock Configuration 7.3.3 Peripheral Clock Reset and Configuration 7.4 Register Summary 7.4.1 PCR Register Summary 7.4.2 LP System Clock Register Summary 7.5 Registers 7.5.1 PCR Registers 7.5.2 LP System Clock Registers 8 Chip Boot Control 8.1 Overview 8.2 Functional Description 8.2.1 Default Configuration 8.2.2 Chip Boot Mode Control 8.2.3 SDIO Sampling and Driving Clock Edge Control 8.2.4 ROM Messages Printing Control 8.2.5 JTAG Signal Source Control 8.2.6 Crystal Frequency Selection 9 Interrupt Matrix 9.1 Overview 9.2 Terminology 9.2.1 Interrupt 9.2.2 Interrupt Signal/Interrupt Source 9.2.3 Interrupt Flow in ESP32-C5 9.3 Features 9.4 Architecture 9.5 Functional Description 9.5.1 Peripheral Interrupt Sources 9.5.2 HP CPU Interrupts 9.5.3 Assign Peripheral Interrupt Source to HP CPU Peripheral Interrupt 9.5.3.1 Assign One Peripheral Interrupt Source to HP CPU Peripheral Interrupt 9.5.3.2 Assign Multiple Peripheral Interrupt Sources to HP CPU Peripheral Interrupt 9.5.3.3 Unassign SOURCE 9.5.4 Delegated Interrupts 9.5.5 Query Current Interrupt Status of SOURCE 9.6 Register Summary 9.6.1 Interrupt Matrix Register Summary 9.6.2 Software Interrupt Register Summary 9.7 Registers 9.7.1 Interrupt Matrix Registers 9.7.2 Software Interrupt Registers 10 Event Task Matrix (ETM) 10.1 Overview 10.2 Features 10.3 Functional Description 10.3.1 Architecture 10.3.2 Events 10.3.3 Tasks 10.3.4 Event and Task Status 10.3.5 Timing Considerations 10.3.6 Channel Control 10.4 Register Summary 10.5 Registers 11 System Timer 11.1 Overview 11.2 Features 11.3 System Timer Structure 11.4 Clock Source Selection 11.5 Functional Description 11.5.1 Counter 11.5.2 Comparator and Alarm 11.5.3 Event Task Matrix 11.5.4 Synchronization Operation 11.6 Interrupts 11.7 Programming Procedure 11.7.1 Read Current Count Value 11.7.2 Configure a One-Time Alarm in Target Mode 11.7.3 Configure Periodic Alarms in Period Mode 11.7.4 Update After Light-sleep 11.8 Register Summary 11.9 Registers 12 Timer Group (TIMG) 12.1 Overview 12.2 Feature List 12.3 Architectural Overview 12.4 Functional Description 12.4.1 16-bit Prescaler and Clock Selection 12.4.2 54-bit Time-base Counter 12.4.3 Alarm Generation 12.4.4 Timer Reload 12.4.5 Frequency Calculation of Slow Clock for Timer Group 0 12.5 Event Task Matrix Feature 12.6 Interrupts 12.7 Programming Procedures 12.7.1 Timer as a Simple Clock 12.7.2 Timer as One-shot Alarm 12.7.3 Timer as Periodic Alarm by APB 12.7.4 Timer as Periodic Alarm by ETM 12.7.5 Frequency Calculation of Slow Clock 12.8 Register Summary 12.9 Registers 13 Watchdog Timers (WDT) 13.1 Overview 13.2 Digital Watchdog Timers 13.2.1 Features 13.2.2 Functional Description 13.2.2.1 Clock Source and 32-Bit Counter 13.2.2.2 Stages and Timeout Actions 13.2.2.3 Write Protection 13.2.2.4 Flash Boot Protection 13.3 Super Watchdog 13.3.1 Features 13.3.2 Super Watchdog Controller 13.3.2.1 Structure 13.3.2.2 Workflow 13.4 Interrupts 13.5 Register Summary 13.6 Registers 14 RTC Timer 14.1 Introduction 14.2 Feature List 14.3 Functional Description 14.4 Event Task Matrix Feature 14.5 Interrupts 14.6 Register Summary 14.7 Registers 15 Permission Control (PMS) 15.1 Overview 15.2 Introduction to APM 15.3 Features 15.4 TEE and REE Terminology 15.5 Functional Description 15.5.1 TEE Controller Functional Description 15.5.2 APM Controller Functional Description 15.5.2.1 Architecture 15.5.2.2 SYS_APM Controller 15.5.2.2.1 Address Ranges 15.5.2.2.2 Access Permissions of Address Ranges 15.5.2.3 PERI_APM Controller 15.6 Illegal Access and Interrupts 15.6.1 SYS_APM Controller 15.6.2 PERI_APM Controller 15.7 Programming Procedure 15.8 Register Summary 15.8.1 HP_APM_REG 15.8.2 LP_APM_REG 15.8.3 LP_APM0_REG 15.8.4 CPU_APM_REG 15.8.5 TEE_REG 15.8.6 LP_TEE_REG 15.9 Registers 15.9.1 HP_APM_REG 15.9.2 LP_APM_REG 15.9.3 LP_APM0_REG 15.9.4 CPU_APM_REG 15.9.5 TEE_REG 15.9.6 LP_TEE_REG 16 System Registers 16.1 Overview 16.2 Features 16.3 Function Description 16.3.1 External Memory Encryption/Decryption Configuration 16.3.2 Anti-DPA Attack Security Control 16.3.3 HP CPU/LP CPU Debug Control 16.3.4 Bus Timeout Protection 16.3.4.1 CPU Peripheral Timeout Protection Register 16.3.4.2 HP Peripheral Timeout Protection Register 16.3.4.3 LP Peripheral Timeout Protection Register 16.4 Register Summary 16.5 Registers 17 Debug Assistant 17.1 Overview 17.2 Features 17.3 Functional Description 17.3.1 Region Read/Write Monitoring 17.3.2 SP Monitoring 17.3.3 PC Logging 17.3.4 CPU/DMA Bus Access Logging 17.4 Interrupts 17.5 Programming Procedures 17.5.1 Region Monitoring and SP Monitoring Configuration 17.5.2 PC Logging Configuration 17.5.3 CPU/DMA Bus Access Logging Configuration 17.5.3.1 Bus Access Logging 1 Configuration 17.5.3.2 Bus Access Logging 2 Configuration 17.6 Register Summary 17.6.1 Bus Logging Configuration Register Summary 17.6.2 Summary of Other Registers 17.7 Registers 17.7.1 Bus Logging Configuration Registers 17.7.2 Other Registers 18 Power Supply Detector 18.1 Overview 18.2 Features 18.3 Functional Description 18.3.1 Architecture 18.3.2 Brown-out Detector 18.3.3 Voltage Glitch Detectors 18.4 Interrupts 18.5 Register Summary 18.6 Registers IV Cryptography/Security Component 19 AES Accelerator (AES) 19.1 Introduction 19.2 Features 19.3 Clock and Reset 19.4 AES Working Modes 19.5 Typical AES Working Mode 19.5.1 Key, Plaintext, and Ciphertext 19.5.2 Endianness 19.5.3 Operation Process 19.6 DMA-AES Working Mode 19.6.1 Key, Plaintext, and Ciphertext 19.6.2 Endianness 19.6.3 Standard Incrementing Function 19.6.4 Block Number 19.6.5 Initialization Vector 19.6.6 Block Operation Process 19.7 Anti-Attack Pseudo-Round Function 19.8 Memory Summary 19.9 Register Summary 19.10 Registers 20 ECC Accelerator (ECC) 20.1 Overview 20.2 Feature List 20.3 ECC Basics 20.3.1 Elliptic Curve and Points on the Curves 20.3.2 Affine Coordinates and Jacobian Coordinates 20.3.3 Memory Blocks 20.3.4 Data and Data Block 20.3.5 Writing Data 20.3.6 Reading Data 20.3.7 Standard Calculation and Jacobian Calculation 20.4 Function Description 20.4.1 Curve Mode 20.4.2 Working Modes 20.4.2.1 Affine Point Multiplication (Affine Point Multi) 20.4.2.2 Affine Point Verification (Affine Point Verif) 20.4.2.3 Affine Point Verification + Affine Point Multiplication (Affine Point Verif + Multi) 20.4.2.4 Jacobian Point Multiplication (Jacobian Point Multi) 20.4.2.5 Point Addition (Point Add) 20.4.2.6 Jacobian Point Verification (Jacobian Point Verif) 20.4.2.7 Affine Point Verification + Jacobian Point Multiplication (Affine Point Verif + Jacobian Point Multi) 20.4.2.8 Mod Addition (Mod Add) 20.4.2.9 Mod Subtraction (Mod Sub) 20.4.2.10 Mod Multiplication (Mod Multi) 20.4.2.11 Mod Division (Mod Div) 20.4.3 Enhancing Anti-Attack Performance 20.4.4 Clock 20.4.5 Reset 20.5 Interrupts 20.6 Programming Procedures 20.7 Register Summary 20.8 Registers 21 HMAC Accelerator (HMAC) 21.1 Overview 21.2 Feature List 21.3 Functional Description 21.3.1 Upstream Mode 21.3.2 Downstream Mode - JTAG Enable Feature 21.3.3 Downstream Mode - Digital Signature Algorithm and Key Derivation Feature 21.4 HMAC eFuse Configuration 21.5 HMAC Process (Detailed) 21.5.1 Enable HMAC module 21.5.2 Configure HMAC keys and key purposes 21.5.3 Downstream mode process 21.5.4 Upstream mode process 21.6 HMAC Algorithm Details 21.6.1 Padding Bits 21.6.2 HMAC Algorithm Structure 21.6.3 Register Summary 21.6.4 Registers 22 RSA Accelerator (RSA) 22.1 Introduction 22.2 Features 22.3 Functional Description 22.3.1 Large-Number Modular Exponentiation 22.3.2 Large-Number Modular Multiplication 22.3.3 Large-Number Multiplication 22.3.4 Options for Additional Acceleration 22.4 Interrupts 22.5 Memory Summary 22.6 Register Summary 22.7 Registers 23 SHA Accelerator (SHA) 23.1 Introduction 23.2 Features 23.3 Working Modes 23.4 Function Description 23.4.1 Preprocessing 23.4.1.1 Padding the Message 23.4.1.2 Parsing the Message 23.4.1.3 Setting the Initial Hash Value 23.4.2 Hash Operation 23.4.2.1 Typical SHA Mode Process 23.4.2.2 DMA-SHA Mode Process 23.4.3 Message Digest 23.4.4 Interrupt 23.5 Register Summary 23.6 Registers 24 Digital Signature Algorithm (DSA) 24.1 Overview 24.2 Features 24.3 Functional Description 24.3.1 Overview 24.3.2 Private Key Operands 24.3.3 Software Prerequisites 24.3.4 DSA Operation at the Hardware Level 24.3.5 DSA Operation at the Software Level 24.4 Memory Summary 24.5 Register Summary 24.6 Registers 25 Elliptic Curve Digital Signature Algorithm (ECDSA) 25.1 Introduction 25.2 Features 25.3 ECDSA Basics 25.3.1 Domain Parameters 25.3.2 Key Generation 25.3.3 Signature Generation 25.3.4 Signature Verification 25.4 Functional Description 25.4.1 ECDSA Working Modes 25.4.2 Data and Data Block 25.4.2.1 Writing Data 25.4.2.2 Reading Data 25.4.2.3 Padding the Message 25.4.2.4 Parsing the Message 25.4.3 Security Features 25.4.3.1 High Anti-Attack Performance 25.4.3.2 Dynamic Access Permission 25.4.3.3 Hardware Occupation 25.5 Programming Procedures 25.5.1 ECDSA Process 25.5.1.1 IDLE Stage 25.5.1.2 PREP Stage 25.5.1.3 LOAD Stage 25.5.1.4 PROC Stage 25.5.1.5 GAIN Stage 25.5.1.6 POST Stage 25.5.1.7 ECDSA SHA Interface 25.5.2 Clock 25.5.3 Reset 25.6 Interrupts 25.7 Memory Blocks 25.8 Register Summary 25.9 Registers 26 External Memory Encryption and Decryption (XTS_AES) 26.1 Overview 26.2 Features 26.3 Module Structure 26.4 Functional Description 26.4.1 XTS Algorithm 26.4.2 Key 26.4.3 Target Memory Space 26.4.4 Data Writing 26.4.5 Manual Encryption Block 26.4.6 Auto Encryption Block 26.4.7 Auto Decryption Block 26.5 Software Process 26.6 Anti-DPA 26.6.1 Clock Anti-DPA Function 26.6.2 Pseudo-round Anti-DPA Function 26.7 Register Summary 26.8 Registers 27 Random Number Generator (RNG) 27.1 Introduction 27.2 Features 27.3 Functional Description 27.4 Programming Procedure 27.5 Register Summary 27.6 Registers V Connectivity Interface 28 UART Controller (UART) 28.1 Overview 28.2 Features 28.3 UART Structure 28.4 Functional Description 28.4.1 Clock and Reset 28.4.2 UART FIFO 28.4.3 Baud Rate Generation and Detection 28.4.3.1 Baud Rate Generation 28.4.3.2 Baud Rate Detection 28.4.4 UART Data Frame 28.4.5 AT_CMD Character Structure 28.4.6 RS485 28.4.6.1 Driver Control 28.4.6.2 Turnaround Delay 28.4.6.3 Bus Snooping 28.4.7 IrDA 28.4.8 Wakeup 28.4.9 Flow Control 28.4.9.1 Hardware Flow Control 28.4.9.2 Software Flow Control 28.4.10 GDMA Mode 28.5 Interrupts 28.6 Programming Procedures 28.6.1 Register Type 28.6.2 Detailed Steps 28.6.2.1 Initializing UARTn 28.6.2.2 Configuring UARTn Communication 28.6.2.3 Enabling UARTn 28.7 Register Summary 28.7.1 UART Register Summary 28.7.2 LP UART Register Summary 28.7.3 UHCI Register Summary 28.8 Registers 28.8.1 UART Registers 28.8.2 LP UART Registers 28.8.3 UHCI Registers 29 SPI Controller (SPI) 29.1 Overview 29.2 Glossary 29.3 Features 29.4 Architectural Overview 29.5 Functional Description 29.5.1 Data Modes 29.5.2 FSPI Bus Signals 29.5.3 Bit Read/Write Order Control 29.5.4 Unaligned Byte Transfer 29.5.5 Transfer Types 29.5.6 CPU-Controlled Data Transfer 29.5.6.1 CPU-Controlled Master Transfer 29.5.6.2 CPU-Controlled Slave Transfer 29.5.7 DMA-Controlled Data Transfer 29.5.7.1 DMA Configuration 29.5.7.2 GDMA TX/RX Buffer Length Control 29.5.8 Data Flow Control 29.5.8.1 GP-SPI2 Functional Blocks 29.5.8.2 Data Flow Control When GP-SPI2 Works as Master 29.5.8.3 Data Flow Control When GP-SPI2 Works as Slave 29.5.9 GP-SPI2 Works as Master 29.5.9.1 State Machine 29.5.9.2 Register Configuration for State and Bit Mode Control 29.5.9.3 Full-Duplex Communication (1-bit Mode Only) 29.5.9.4 Half-Duplex Communication (1/2/4-bit Mode) 29.5.9.5 DMA-Controlled Configurable Segmented Transfer 29.5.10 GP-SPI2 Works as Slave 29.5.10.1 Configurable Communication Formats 29.5.10.2 CMD Values Supported in Half-Duplex Communication 29.5.10.3 Slave Single Transfer and Slave Segmented Transfer 29.5.10.4 Configuration of Slave Single Transfer 29.5.10.5 Configuration of Slave Segmented Transfer in Half-Duplex 29.5.10.6 Configuration of Slave Segmented Transfer in Full-Duplex 29.6 CS Setup Time and Hold Time Control 29.7 GP-SPI2 Clock Control 29.7.1 Clock Phase and Polarity 29.7.2 Clock Control When GP-SPI2 Works as Master 29.7.3 Clock Control When GP-SPI2 Works as Slave 29.8 GP-SPI2 Timing Compensation 29.9 Interrupt 29.9.1 Interrupt Description 29.9.2 Interrupts Used in Master and in Slave 29.10 Register Summary 29.11 Register 30 I2C Controller (I2C) 30.1 Overview 30.2 Feature List 30.3 Architecture Overview 30.4 Functional Description 30.4.1 Clock Configuration 30.4.2 SCL and SDA Noise Filtering 30.4.3 SCL Clock Stretching 30.4.4 Generating SCL Pulses in Idle State 30.4.5 Synchronization 30.4.6 Open-Drain Output 30.4.7 Timing Parameters Configuration 30.4.8 Timeout Control 30.4.9 Command Configuration 30.4.10 TX/RX RAM Data Storage 30.4.11 Data Conversion 30.4.12 Addressing Mode 30.4.13 R/W Bit Check in 10-bit Addressing Mode 30.4.14 Start the I2C Controller 30.5 Functional Differences Between LP_I2C and I2C 30.6 Interrupts 30.7 Programming Procedures 30.7.1 I2C master Writes to I2C slave with a 7-bit Address in One Command Sequence 30.7.1.1 Introduction 30.7.1.2 Configuration Example 30.7.2 I2C master Writes to I2C slave with a 10-bit Address in One Command Sequence 30.7.2.1 Introduction 30.7.2.2 Configuration Example 30.7.3 I2C master Writes to I2C slave with Two 7-bit Addresses in One Command Sequence 30.7.3.1 Introduction 30.7.3.2 Configuration Example 30.7.4 I2C master Writes to I2C slave with a 7-bit Address in Multiple Command Sequences 30.7.4.1 Introduction 30.7.4.2 Configuration Example 30.7.5 I2C master Reads I2C slave with a 7-bit Address in One Command Sequence 30.7.5.1 Introduction 30.7.5.2 Configuration Example 30.7.6 I2C master Reads I2C slave with a 10-bit Address in One Command Sequence 30.7.6.1 Introduction 30.7.6.2 Configuration Example 30.7.7 I2C master Reads I2C slave with Two 7-bit Addresses in One Command Sequence 30.7.7.1 Introduction 30.7.7.2 Configuration Example 30.7.8 I2C master Reads I2C slave with a 7-bit Address in Multiple Command Sequences 30.7.8.1 Introduction 30.7.8.2 Configuration Example 30.8 Register Summary 30.8.1 I2C Register Summary 30.8.2 LP_I2C Register Summary 30.9 Registers 30.9.1 I2C Registers 30.9.2 LP_I2C Registers 31 I2S Controller (I2S) 31.1 Overview 31.2 Terminology 31.3 Features 31.4 System Architecture 31.5 Supported Audio Standards 31.5.1 TDM Philips Standard 31.5.2 TDM MSB Alignment Standard 31.5.3 TDM PCM Standard 31.5.4 PDM Standard 31.6 I2S TX/RX Clock 31.7 I2S Reset 31.8 I2S Master/Slave Mode 31.8.1 Master/Slave TX Mode 31.8.2 Master/Slave RX Mode 31.9 Transmitting Data 31.9.1 Data Format Control 31.9.1.1 Bit Width Control of Channel Valid Data 31.9.1.2 Endian Control of Channel Valid Data 31.9.1.3 A-law/-law Compression and Decompression 31.9.1.4 Bit Width Control of Channel TX Data 31.9.1.5 Bit Order Control of Channel Data 31.9.2 Channel Mode Control 31.9.2.1 TDM TX Mode 31.9.2.2 PDM TX Mode 31.9.3 Synchronous Counter 31.10 Receiving Data 31.10.1 Channel Mode Control 31.10.1.1 TDM RX Mode 31.10.1.2 PDM RX Mode 31.10.2 Data Format Control 31.10.2.1 Bit Order Control of Channel Data 31.10.2.2 Bit Width Control of Channel Storage (Valid) Data 31.10.2.3 Bit Width Control of Channel RX Data 31.10.2.4 Endian Control of Channel Storage Data 31.10.2.5 A-law/-law Compression and Decompression 31.11 Event Task Matrix Feature 31.12 I2S Interrupts 31.13 Software Configuration Process 31.13.1 Configure I2S as TX Mode 31.13.2 Configure I2S as RX Mode 31.14 Register Summary 31.15 Registers 32 Pulse Count Controller (PCNT) 32.1 Features 32.2 Functional Description 32.3 Applications 32.3.1 Channel 0 Incrementing Independently 32.3.2 Channel 0 Decrementing Independently 32.3.3 Channel 0 and Channel 1 Incrementing Together 32.4 Register Summary 32.5 Registers 33 USB Serial/JTAG Controller 33.1 Overview 33.2 Feature List 33.3 Functional Description 33.3.1 CDC-ACM USB Interface Functional Description 33.3.2 CDC-ACM Firmware Interface Functional Description 33.3.3 USB-to-JTAG Interface: JTAG Command Processor 33.3.4 USB-to-JTAG Interface: CMD_REP Usage Example 33.3.5 USB-to-JTAG Interface: Response Capture Unit 33.3.6 USB-to-JTAG Interface: Control Transfer Requests 33.4 Interrupts 33.5 Programming Procedures 33.6 Register Summary 33.7 Registers 34 SDIO Slave Controller (SDIO) 34.1 Overview 34.2 Features 34.3 Architecture Overview 34.4 Standards Compliance 34.5 Functional Description 34.5.1 Physical Bus 34.5.2 Supported Commands 34.5.3 I/O Function 0 Address Space 34.5.4 I/O Function 1/2 Address Space Map 34.5.4.1 Accessing SLC HOST Register Space 34.5.4.2 Transferring Incremental-Address Packets 34.5.4.3 Transferring Fixed-Address Packets 34.5.5 DMA 34.5.5.1 Linked List 34.5.5.2 Write-Back of Linked List 34.5.5.3 Data Padding and Discarding 34.5.6 SDIO Bus Timing 34.6 Interrupt 34.6.1 Host Interrupt 34.6.2 Slave Interrupt 34.7 Packet Sending and Receiving Procedure 34.7.1 Sending Packets to SDIO Host 34.7.2 Receiving Packets from SDIO Host 34.8 Register Summary 34.8.1 HINF Register Summary 34.8.2 SLC Register Summary 34.8.3 SLC Host Register Summary 34.9 Registers 34.9.1 HINF Registers 34.9.2 SLC Registers 34.9.3 SLC Host Registers 35 LED PWM Controller (LEDC) 35.1 Overview 35.2 Feature List 35.3 Architectural Overview 35.4 Functional Description 35.4.1 Timers 35.4.1.1 Clock Source 35.4.1.2 Clock Divider Configuration 35.4.1.3 20-Bit Counter 35.4.2 PWM Generators 35.4.3 Duty Cycle Fading 35.4.3.1 Linear Duty Cycle Fading 35.4.3.2 Gamma Curve Fading 35.4.3.3 Suspend and Resume Duty Cycle Fading 35.5 Event Task Matrix Feature 35.6 Interrupts 35.7 Programming Procedures 35.8 Memory Blocks 35.9 Register Summary 35.10 Registers 36 Motor Control PWM (MCPWM) 36.1 Overview 36.2 Features 36.3 Modules 36.3.1 Overview 36.3.1.1 Timer Module 36.3.1.2 Operator Module 36.3.1.3 Capture Module 36.3.1.4 ETM Module 36.3.2 PWM Timer Module 36.3.2.1 Configurations of the PWM Timer Module 36.3.2.2 PWM Timer's Working Modes and Timing Event Generation 36.3.2.3 Shadow Register of PWM Timer 36.3.2.4 PWM Timer Synchronization and Phase Locking 36.3.3 PWM Operator Module 36.3.3.1 PWM Generator Module 36.3.3.2 Dead Time Generator Module 36.3.3.3 PWM Carrier Module 36.3.3.4 Fault Detection Module 36.3.4 Capture Module 36.3.4.1 Introduction 36.3.4.2 Capture Timer 36.3.4.3 Capture Channel 36.3.5 ETM Module 36.3.5.1 Overview 36.3.5.2 MCPWM-Related ETM Events 36.3.5.3 MCPWM-Related ETM Tasks 36.4 Interrupts 36.5 Register Summary 36.6 Registers 37 Remote Control Peripheral (RMT) 37.1 Overview 37.2 Features 37.3 Functional Description 37.3.1 RMT Architecture 37.3.2 RAM 37.3.2.1 Structure of RAM 37.3.2.2 Use of RAM 37.3.2.3 RAM Access 37.3.3 Clock 37.3.4 Transmitter 37.3.4.1 Normal TX Mode 37.3.4.2 Wrap TX Mode 37.3.4.3 TX Modulation 37.3.4.4 Continuous TX Mode 37.3.4.5 Simultaneous TX Mode 37.3.5 Receiver 37.3.5.1 Normal RX Mode 37.3.5.2 Wrap RX Mode 37.3.5.3 RX Filtering 37.3.5.4 RX Demodulation 37.4 Configuration Update 37.5 Interrupts 37.6 Register Summary 37.7 Registers 38 Parallel IO Controller (PARLIO) 38.1 Introduction 38.2 Glossary 38.3 Features 38.4 Architectural Overview 38.5 Functional Description 38.5.1 Clock Generator 38.5.2 Clock and Reset Restriction 38.5.3 Master-Slave Mode 38.5.4 Receive Modes of the RX Unit 38.5.4.1 Level Enable Mode 38.5.4.2 Pulse Enable Mode 38.5.4.3 Software Enable Mode 38.5.5 RX Unit GDMA SUC EOF Generation 38.5.6 RX Unit Timeout 38.5.7 Unlimited Length Data Transmission of TX Unit 38.5.8 TX Chip Select Function 38.5.9 Output Clock Gating of TX Unit 38.5.10 Bus Idle Value of TX Unit 38.5.11 Data Transfer in a Single Frame 38.5.12 Bit Reversal in One Byte 38.6 Interrupts 38.7 Programming Procedures 38.7.1 Data Receiving Operation Process 38.7.2 Data Transmitting Operation Process 38.8 Application Examples 38.8.1 Co-working with SPI 38.8.2 Co-working with I2S 38.9 Register Summary 38.10 Registers 39 BitScrambler 39.1 Introduction 39.2 Feature List 39.3 Application Examples 39.4 Architectural Overview 39.4.1 Data Path 39.4.2 Control Path 39.5 Functional Description 39.5.1 Instructions 39.5.2 Configuration Registers 39.6 Programming Procedures 39.7 Register Summary 39.8 Registers VI Analog Signal Processing 40 Temperature Sensor 40.1 Overview 40.2 Features 40.3 Architecture 40.4 Functional Description 40.4.1 Temperature Sensor Power Up 40.4.2 Temperature Sensor Clock 40.4.3 Automatic Temperature Monitoring Modes 40.4.4 Temperature Measurement Range and Offset 40.4.5 Data Conversion 40.5 Programming Procedure 40.6 Interrupts 40.7 Event Task Matrix Feature 40.8 Register Summary 40.9 Registers 41 ADC Controller 41.1 Overview 41.2 Terminology 41.3 Feature List 41.4 Architectural Overview 41.5 Functional Description 41.5.1 ADC Power Up 41.5.2 ADC Channels 41.5.3 ADC Clock 41.5.4 One-Shot Sampling Mode 41.5.5 Multi-Channel Sampling Mode 41.5.6 ADC Conversion and Attenuation 41.5.7 DIG ADC FSM 41.5.8 Pattern Table 41.5.9 ADC Filters 41.5.10 Threshold Monitors 41.5.11 GDMA Support 41.6 Event Task Matrix Feature 41.7 Interrupts 41.8 Programming Procedure 41.8.1 Configuring One-shot Sampling Mode 41.8.2 Configuring Multi-Channel Sampling Mode 41.9 Register Summary 41.10 Registers 42 Analog Voltage Comparator 42.1 Introduction 42.2 Feature List 42.3 Architectural Overview 42.4 Functional Description 42.5 Event Task Matrix Feature 42.6 Interrupts 42.7 Programming Procedures VII Appendix Related Documentation and Resources Glossary Abbreviations for Peripherals Abbreviations Related to Registers Access Types for Registers Programming Reserved Register Field Introduction Programming Reserved Register Field Interrupt Configuration Registers Revision History PRELIMINARY ESP32-C5 Technical Reference Manual Pre-release v0.2 www.espressif.com About This Document The ESP32-C5 Technical Reference Manual is targeted at developers working on low level software projects that use the ESP32-C5 SoC. It describes the hardware modules listed below for the ESP32-C5 SoC and other products in ESP32-C5 series. The modules detailed in this document provide an overview, list of features, hardware architecture details, any necessary programming procedures, as well as register descriptions. Navigation in This Document Here are some tips on navigation through this extensive document: • Release Status at a Glance on the very next page is a minimal list of all chapters from where you can directly jump to a specific chapter. • Use the Bookmarks on the side bar to jump to any specific chapters or sections from anywhere in the document. Note this PDF document is configured to automatically display Bookmarks when open, which is necessary for an extensive document like this one. However, some PDF viewers or browsers ignore this setting, so if you don’t see the Bookmarks by default, try one or more of the following methods: – Install a PDF Reader Extension for your browser; – Download this document, and view it with your local PDF viewer; – Set your PDF viewer to always automatically display the Bookmarks on the left side bar when open. • Use the native Navigation function of your PDF viewer to navigate through the documents. Most PDF viewers support to go Up, Down, Previous, Next, Back, Forward and Page with buttons, menu, or hot keys. • You can also use the built-in GoBack button on the upper right corner on each and every page to go back to the previous place before you click a link within the document. Note this feature may only work with some Acrobat-specific PDF viewers (for example, Acrobat Reader and Adobe DC) and browsers with built-in Acrobat-specific PDF viewers or extensions (for example, Firefox). Release Status at a Glance Release Status at a Glance Note that this manual in still work in progress. See our release progress below: No. Chapter Progress Part I. Microprocessor and Master 1 High-Performance CPU [to be added later] 36% 2 RISC-V Trace Encoder (TRACE) Published 3 Low-Power CPU Published 4 GDMA Controller (GDMA) Published Part II. Memory Organization 5 System and Memory Published 6 eFuse Controller (eFuse) Published Part III. System Component 7 GPIO Matrix and IO MUX Published 8 Reset and Clock Published 9 Chip Boot Control Published 10 Interrupt Matrix Published 11 Event Task Matrix (ETM) Published 12 Low-power Management [to be added later] 64% 13 System Timer Published 14 Timer Group (TIMG) Published 15 Watchdog Timers (WDT) Published 16 RTC Timer Published 17 Permission Control (PMS) Published 18 System Registers Published 19 Debug Assistant Published 20 Power Supply Detector Published Part IV. Cryptography/Security Component 21 AES Accelerator (AES) Published 22 ECC Accelerator (ECC) Published 23 HMAC Accelerator (HMAC) Published 24 RSA Accelerator (RSA) Published 25 SHA Accelerator (SHA) Published 26 Digital Signature Algorithm (DSA) Published 27 Elliptic Curve Digital Signature Algorithm (ECDSA) Published 28 External Memory Encryption and Decryption (XTS_AES) Published 29 Random Number Generator (RNG) Published Part V. Connectivity Interface 30 UART Controller (UART) Published 31 SPI Controller (SPI) Published 32 I2C Controller (I2C) Published 33 I2S Controller (I2S) Published 34 Pulse Count Controller (PCNT) Published 35 USB Serial/JTAG Controller Published Espressif Systems 3 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Release Status at a Glance No. Chapter Progress 36 Controller Area Network Flexible Data-Rate [to be added later] 67% 37 SDIO Slave Controller (SDIO) Published 38 LED PWM Controller (LEDC) Published 39 Motor Control PWM (MCPWM) Published 40 Remote Control Peripheral (RMT) Published 41 Parallel IO Controller (PARLIO) Published 42 BitScrambler Published Part VI. Analog Signal Processing 43 Temperature Sensor Published 44 ADC Controller Published 45 Analog Voltage Comparator Published Note: Check the link or the QR code to make sure that you use the latest version of this document: https://www.espressif.com/documentation/esp32-c5_technical_reference_manual_en.pdf Espressif Systems 4 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Contents Contents I Microprocessor and Master 38 1 RISC-V Trace Encoder (TRACE) 39 1.1 Terminology 39 1.2 Introduction 40 1.3 Features 41 1.4 Architectural Overview 42 1.5 Functional Description 42 1.5.1 Synchronization 42 1.5.2 Address Mode 43 1.5.3 Optional Sideband Signals 43 1.5.4 Filtering 44 1.5.5 Anchor Tag 44 1.5.6 Memory Writing Mode 45 1.5.7 Automatic Restart 45 1.6 Encoder Output Packets 45 1.6.1 Header 45 1.6.2 Index 46 1.6.3 Payload 46 1.6.3.1 Format 3 Packets 46 1.6.3.2 Format 2 Packets 48 1.6.3.3 Format 1 Packets 49 1.7 Interrupt 50 1.8 Programming Procedures 51 1.8.1 Encoder Option Configuration 51 1.8.2 Filter Configuration 52 1.8.3 Enable Encoder 53 1.8.4 Disable Encoder 54 1.8.5 Notify 54 1.8.6 Decode Data Packets 55 1.8.7 AHB Configuration 55 1.8.8 Software Retention 56 1.9 Register Summary 57 1.10 Registers 58 2 Low-Power CPU 69 2.1 Features 69 2.2 Configuration and Status Registers (CSRs) 70 2.2.1 Register Summary 70 2.2.2 Registers 71 2.3 Interrupts and Exceptions 78 2.3.1 Interrupts 79 Espressif Systems 5 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Contents 2.3.2 Interrupt Handling 79 2.3.3 Exceptions 79 2.4 Debugging 80 2.4.1 Features 80 2.4.2 Functional Description 80 2.4.3 Register Summary 80 2.4.4 Registers 81 2.5 Hardware Trigger 83 2.5.1 Features 83 2.5.2 Functional Description 83 2.5.3 Trigger Execution Flow 84 2.5.4 Register Summary 84 2.5.5 Registers 84 2.6 Performance Counter 87 2.7 System Access 88 2.7.1 Memory Access 88 2.7.2 Peripheral Access 88 2.8 Event Task Matrix Feature 88 2.9 Sleep and Wake-Up Process 89 2.9.1 Features 89 2.9.2 Process 89 2.9.3 Wake-Up Sources 91 2.10 Register Summary 91 2.11 Registers 91 3 GDMA Controller (GDMA) 93 3.1 Overview 93 3.2 Features 93 3.3 Architecture 94 3.4 Functional Description 95 3.4.1 Linked List 95 3.4.2 Peripheral-to-Memory and Memory-to-Peripheral Data Transfer 96 3.4.3 Memory-to-Memory Data Transfer 97 3.4.4 Enabling GDMA 97 3.4.5 Linked List Reading Process 98 3.4.6 EOF 98 3.4.7 Accessing Memory 99 3.4.8 Arbitration 99 3.5 Event Task Matrix Feature 100 3.6 Interrupts 101 3.7 Programming Procedures 102 3.7.1 Programming Procedures for GDMA’s Transmit Channel 102 3.7.2 Programming Procedures for GDMA’s Receive Channel 102 3.7.3 Programming Procedures for Memory-to-Memory Transfer 103 3.7.4 Programming Procedures for Channel Priority and Weight 103 3.8 Register Summary 104 Espressif Systems 6 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Contents 3.9 Registers 111 II Memory Organization 139 4 System and Memory 140 4.1 Overview 140 4.2 Features 140 4.3 Functional Description 141 4.3.1 Address Mapping 141 4.3.2 Internal Memory 143 4.3.2.1 ROM 143 4.3.2.2 HP SRAM 144 4.3.2.3 LP SRAM 144 4.3.3 External Memory 145 4.3.3.1 External Memory Address Mapping 145 4.3.3.2 Cache 145 4.3.3.3 Cache Operations 145 4.3.4 GDMA Address Space 147 4.3.5 Modules/Peripherals Address Mapping 148 5 eFuse Controller (eFuse) 151 5.1 Overview 151 5.2 Features 151 5.3 Functional Description 151 5.3.1 Structure 151 5.3.1.1 EFUSE_WR_DIS 160 5.3.1.2 EFUSE_RD_DIS 160 5.3.1.3 Data Storage 160 5.3.2 Programming of Parameters 162 5.3.3 Reading of Parameters 163 5.3.4 eFuse VDDQ Timing 165 5.3.5 Parameters Used by Hardware Modules 165 5.4 Interrupts 165 5.5 Register Summary 167 5.6 Registers 171 III System Component 204 6 GPIO Matrix and IO MUX 205 6.1 Overview 205 6.2 Features 205 6.2.1 HP GPIO Matrix and HP IO MUX 205 6.2.2 LP GPIO Matrix and LP IO MUX 206 6.3 Architectural Overview 206 6.4 Peripheral Input via GPIO Matrix 208 6.4.1 Overview 208 Espressif Systems 7 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Contents 6.4.2 Signal Synchronization 209 6.4.3 GPIO Filter 209 6.4.4 Glitch Filter 210 6.4.5 Simple GPIO Input 210 6.4.6 GPIO Wakeup 210 6.4.6.1 HP GPIO Wakeup 210 6.4.6.2 LP GPIO Wakeup 211 6.4.7 Programming Procedure 211 6.4.7.1 HP GPIO Matrix 211 6.4.7.2 LP GPIO Matrix 213 6.5 Peripheral Output via GPIO Matrix 213 6.5.1 Overview 213 6.5.2 Simple GPIO Output 213 6.5.3 Sigma Delta Modulated Output (SDM) 214 6.5.3.1 Functional Description 214 6.5.3.2 SDM Configuration 215 6.5.4 Programming Procedure 215 6.5.4.1 HP GPIO Matrix 215 6.5.4.2 LP GPIO Matrix 216 6.6 Direct Input and Output via IO MUX 216 6.6.1 Overview 216 6.6.2 Functional Description 216 6.6.2.1 HP IO MUX 216 6.6.2.2 LP IO MUX 216 6.7 Analog Functions 217 6.7.1 Overview 217 6.7.2 Analog Functions 217 6.8 Pin Functions in Light-sleep 217 6.9 Pin Hold Feature 218 6.10 Hysteresis Characteristics 219 6.11 Power Supplies and Management of GPIO Pins 220 6.11.1 Power Supplies of GPIO Pins 220 6.11.2 Power Supply Management 220 6.12 HP Peripheral Signal List 220 6.13 HP IO MUX Function List 225 6.14 LP IO MUX Function List 227 6.15 GPIO Pin Analog Function List 228 6.16 Event Task Matrix Function 228 6.17 Interrupts 230 6.18 Register Summary 230 6.18.1 HP GPIO Matrix Register Summary 230 6.18.2 HP IO MUX Register Summary 234 6.18.3 GPIO EXT Register Summary 235 6.18.4 LP GPIO Matrix Register Summary 236 6.18.5 LP IO MUX Register Summary 237 6.19 Registers 237 Espressif Systems 8 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Contents 6.19.1 HP GPIO Matrix Registers 237 6.19.2 HP IO MUX Registers 253 6.19.3 GPIO EXT Registers 256 6.19.4 LP GPIO Matrix Registers 272 6.19.5 LP IO MUX Registers 281 7 Reset and Clock 285 7.1 Reset 285 7.1.1 Overview 285 7.1.2 Architectural Overview 285 7.1.3 Features 285 7.1.4 Functional Description 286 7.1.5 Peripheral Reset 287 7.2 Clock 287 7.2.1 Overview 287 7.2.2 Architectural Overview 288 7.2.3 Features 288 7.2.4 Functional Description 289 7.2.4.1 HP System Clock 289 7.2.4.2 LP System Clock 290 7.2.4.3 Peripheral Clocks 291 7.2.4.4 PMU Control of High-Performance System Clock Gating 294 7.3 Programming Procedures 296 7.3.1 HP System Clock Configuration 296 7.3.2 LP System Clock Configuration 297 7.3.3 Peripheral Clock Reset and Configuration 297 7.4 Register Summary 299 7.4.1 PCR Register Summary 299 7.4.2 LP System Clock Register Summary 301 7.5 Registers 303 7.5.1 PCR Registers 303 7.5.2 LP System Clock Registers 356 8 Chip Boot Control 368 8.1 Overview 368 8.2 Functional Description 368 8.2.1 Default Configuration 369 8.2.2 Chip Boot Mode Control 369 8.2.3 SDIO Sampling and Driving Clock Edge Control 371 8.2.4 ROM Messages Printing Control 371 8.2.5 JTAG Signal Source Control 372 8.2.6 Crystal Frequency Selection 373 9 Interrupt Matrix 374 9.1 Overview 374 9.2 Terminology 374 Espressif Systems 9 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Contents 9.2.1 Interrupt 374 9.2.2 Interrupt Signal/Interrupt Source 374 9.2.3 Interrupt Flow in ESP32-C5 375 9.3 Features 375 9.4 Architecture 375 9.5 Functional Description 376 9.5.1 Peripheral Interrupt Sources 376 9.5.2 HP CPU Interrupts 380 9.5.3 Assign Peripheral Interrupt Source to HP CPU Peripheral Interrupt 380 9.5.3.1 Assign One Peripheral Interrupt Source to HP CPU Peripheral Interrupt 380 9.5.3.2 Assign Multiple Peripheral Interrupt Sources to HP CPU Peripheral Interrupt 380 9.5.3.3 Unassign SOURCE 380 9.5.4 Delegated Interrupts 381 9.5.5 Query Current Interrupt Status of SOURCE 381 9.6 Register Summary 382 9.6.1 Interrupt Matrix Register Summary 382 9.6.2 Software Interrupt Register Summary 385 9.7 Registers 386 9.7.1 Interrupt Matrix Registers 386 9.7.2 Software Interrupt Registers 392 10 Event Task Matrix (ETM) 394 10.1 Overview 394 10.2 Features 394 10.3 Functional Description 394 10.3.1 Architecture 394 10.3.2 Events 395 10.3.3 Tasks 398 10.3.4 Event and Task Status 402 10.3.5 Timing Considerations 402 10.3.6 Channel Control 403 10.4 Register Summary 405 10.5 Registers 409 11 System Timer 504 11.1 Overview 504 11.2 Features 504 11.3 System Timer Structure 505 11.4 Clock Source Selection 505 11.5 Functional Description 506 11.5.1 Counter 506 11.5.2 Comparator and Alarm 507 11.5.3 Event Task Matrix 508 11.5.4 Synchronization Operation 508 11.6 Interrupts 509 11.7 Programming Procedure 509 Espressif Systems 10 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Contents 11.7.1 Read Current Count Value 509 11.7.2 Configure a One-Time Alarm in Target Mode 510 11.7.3 Configure Periodic Alarms in Period Mode 510 11.7.4 Update After Light-sleep 510 11.8 Register Summary 512 11.9 Registers 514 12 Timer Group (TIMG) 530 12.1 Overview 530 12.2 Feature List 530 12.3 Architectural Overview 531 12.4 Functional Description 531 12.4.1 16-bit Prescaler and Clock Selection 531 12.4.2 54-bit Time-base Counter 532 12.4.3 Alarm Generation 532 12.4.4 Timer Reload 533 12.4.5 Frequency Calculation of Slow Clock for Timer Group 0 534 12.5 Event Task Matrix Feature 534 12.6 Interrupts 535 12.7 Programming Procedures 536 12.7.1 Timer as a Simple Clock 536 12.7.2 Timer as One-shot Alarm 536 12.7.3 Timer as Periodic Alarm by APB 536 12.7.4 Timer as Periodic Alarm by ETM 537 12.7.5 Frequency Calculation of Slow Clock 538 12.8 Register Summary 539 12.9 Registers 540 13 Watchdog Timers (WDT) 553 13.1 Overview 553 13.2 Digital Watchdog Timers 554 13.2.1 Features 554 13.2.2 Functional Description 555 13.2.2.1 Clock Source and 32-Bit Counter 555 13.2.2.2 Stages and Timeout Actions 556 13.2.2.3 Write Protection 556 13.2.2.4 Flash Boot Protection 557 13.3 Super Watchdog 557 13.3.1 Features 557 13.3.2 Super Watchdog Controller 557 13.3.2.1 Structure 558 13.3.2.2 Workflow 558 13.4 Interrupts 558 13.5 Register Summary 559 13.6 Registers 559 Espressif Systems 11 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Contents 14 RTC Timer 567 14.1 Introduction 567 14.2 Feature List 567 14.3 Functional Description 567 14.4 Event Task Matrix Feature 569 14.5 Interrupts 569 14.6 Register Summary 571 14.7 Registers 572 15 Permission Control (PMS) 581 15.1 Overview 581 15.2 Introduction to APM 582 15.3 Features 583 15.4 TEE and REE Terminology 584 15.5 Functional Description 584 15.5.1 TEE Controller Functional Description 584 15.5.2 APM Controller Functional Description 585 15.5.2.1 Architecture 585 15.5.2.2 SYS_APM Controller 587 15.5.2.2.1Address Ranges 587 15.5.2.2.2Access Permissions of Address Ranges 588 15.5.2.3 PERI_APM Controller 589 15.6 Illegal Access and Interrupts 590 15.6.1 SYS_APM Controller 590 15.6.2 PERI_APM Controller 591 15.7 Programming Procedure 591 15.8 Register Summary 592 15.8.1 HP_APM_REG 592 15.8.2 LP_APM_REG 595 15.8.3 LP_APM0_REG 596 15.8.4 CPU_APM_REG 598 15.8.5 TEE_REG 599 15.8.6 LP_TEE_REG 601 15.9 Registers 603 15.9.1 HP_APM_REG 603 15.9.2 LP_APM_REG 616 15.9.3 LP_APM0_REG 622 15.9.4 CPU_APM_REG 626 15.9.5 TEE_REG 635 15.9.6 LP_TEE_REG 637 16 System Registers 641 16.1 Overview 641 16.2 Features 641 16.3 Function Description 641 16.3.1 External Memory Encryption/Decryption Configuration 641 Espressif Systems 12 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Contents 16.3.2 Anti-DPA Attack Security Control 641 16.3.3 HP CPU/LP CPU Debug Control 642 16.3.4 Bus Timeout Protection 642 16.3.4.1 CPU Peripheral Timeout Protection Register 642 16.3.4.2 HP Peripheral Timeout Protection Register 643 16.3.4.3 LP Peripheral Timeout Protection Register 643 16.4 Register Summary 644 16.5 Registers 645 17 Debug Assistant 654 17.1 Overview 654 17.2 Features 654 17.3 Functional Description 654 17.3.1 Region Read/Write Monitoring 654 17.3.2 SP Monitoring 655 17.3.3 PC Logging 655 17.3.4 CPU/DMA Bus Access Logging 655 17.4 Interrupts 655 17.5 Programming Procedures 656 17.5.1 Region Monitoring and SP Monitoring Configuration 656 17.5.2 PC Logging Configuration 657 17.5.3 CPU/DMA Bus Access Logging Configuration 658 17.5.3.1 Bus Access Logging 1 Configuration 658 17.5.3.2 Bus Access Logging 2 Configuration 662 17.6 Register Summary 665 17.6.1 Bus Logging Configuration Register Summary 665 17.6.2 Summary of Other Registers 666 17.7 Registers 668 17.7.1 Bus Logging Configuration Registers 668 17.7.2 Other Registers 677 18 Power Supply Detector 692 18.1 Overview 692 18.2 Features 692 18.3 Functional Description 692 18.3.1 Architecture 692 18.3.2 Brown-out Detector 693 18.3.3 Voltage Glitch Detectors 694 18.4 Interrupts 695 18.5 Register Summary 697 18.6 Registers 698 IV Cryptography/Security Component 705 19 AES Accelerator (AES) 706 19.1 Introduction 706 Espressif Systems 13 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Contents 19.2 Features 706 19.3 Clock and Reset 706 19.4 AES Working Modes 707 19.5 Typical AES Working Mode 708 19.5.1 Key, Plaintext, and Ciphertext 708 19.5.2 Endianness 709 19.5.3 Operation Process 711 19.6 DMA-AES Working Mode 712 19.6.1 Key, Plaintext, and Ciphertext 712 19.6.2 Endianness 713 19.6.3 Standard Incrementing Function 714 19.6.4 Block Number 714 19.6.5 Initialization Vector 714 19.6.6 Block Operation Process 714 19.7 Anti-Attack Pseudo-Round Function 715 19.8 Memory Summary 716 19.9 Register Summary 717 19.10 Registers 718 20 ECC Accelerator (ECC) 724 20.1 Overview 724 20.2 Feature List 724 20.3 ECC Basics 724 20.3.1 Elliptic Curve and Points on the Curves 724 20.3.2 Affine Coordinates and Jacobian Coordinates 724 20.3.3 Memory Blocks 725 20.3.4 Data and Data Block 725 20.3.5 Writing Data 726 20.3.6 Reading Data 726 20.3.7 Standard Calculation and Jacobian Calculation 726 20.4 Function Description 726 20.4.1 Curve Mode 726 20.4.2 Working Modes 727 20.4.2.1 Affine Point Multiplication (Affine Point Multi) 727 20.4.2.2 Affine Point Verification (Affine Point Verif) 728 20.4.2.3 Affine Point Verification + Affine Point Multiplication (Affine Point Verif + Multi) 728 20.4.2.4 Jacobian Point Multiplication (Jacobian Point Multi) 728 20.4.2.5 Point Addition (Point Add) 729 20.4.2.6 Jacobian Point Verification (Jacobian Point Verif) 729 20.4.2.7 Affine Point Verification + Jacobian Point Multiplication (Affine Point Verif + Jacobian Point Multi) 729 20.4.2.8 Mod Addition (Mod Add) 730 20.4.2.9 Mod Subtraction (Mod Sub) 730 20.4.2.10 Mod Multiplication (Mod Multi) 730 20.4.2.11 Mod Division (Mod Div) 731 20.4.3 Enhancing Anti-Attack Performance 731 Espressif Systems 14 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Contents 20.4.4 Clock 731 20.4.5 Reset 732 20.5 Interrupts 733 20.6 Programming Procedures 733 20.7 Register Summary 734 20.8 Registers 735 21 HMAC Accelerator (HMAC) 740 21.1 Overview 740 21.2 Feature List 740 21.3 Functional Description 740 21.3.1 Upstream Mode 741 21.3.2 Downstream Mode - JTAG Enable Feature 741 21.3.3 Downstream Mode - Digital Signature Algorithm and Key Derivation Feature 742 21.4 HMAC eFuse Configuration 742 21.5 HMAC Process (Detailed) 743 21.5.1 Enable HMAC module 743 21.5.2 Configure HMAC keys and key purposes 743 21.5.3 Downstream mode process 744 21.5.4 Upstream mode process 744 21.6 HMAC Algorithm Details 745 21.6.1 Padding Bits 745 21.6.2 HMAC Algorithm Structure 746 21.6.3 Register Summary 747 21.6.4 Registers 748 22 RSA Accelerator (RSA) 754 22.1 Introduction 754 22.2 Features 754 22.3 Functional Description 754 22.3.1 Large-Number Modular Exponentiation 755 22.3.2 Large-Number Modular Multiplication 756 22.3.3 Large-Number Multiplication 757 22.3.4 Options for Additional Acceleration 757 22.4 Interrupts 759 22.5 Memory Summary 760 22.6 Register Summary 760 22.7 Registers 761 23 SHA Accelerator (SHA) 766 23.1 Introduction 766 23.2 Features 766 23.3 Working Modes 766 23.4 Function Description 767 23.4.1 Preprocessing 767 23.4.1.1 Padding the Message 767 Espressif Systems 15 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Contents 23.4.1.2 Parsing the Message 767 23.4.1.3 Setting the Initial Hash Value 768 23.4.2 Hash Operation 768 23.4.2.1 Typical SHA Mode Process 768 23.4.2.2 DMA-SHA Mode Process 769 23.4.3 Message Digest 770 23.4.4 Interrupt 771 23.5 Register Summary 772 23.6 Registers 773 24 Digital Signature Algorithm (DSA) 777 24.1 Overview 777 24.2 Features 777 24.3 Functional Description 777 24.3.1 Overview 777 24.3.2 Private Key Operands 778 24.3.3 Software Prerequisites 778 24.3.4 DSA Operation at the Hardware Level 780 24.3.5 DSA Operation at the Software Level 780 24.4 Memory Summary 783 24.5 Register Summary 784 24.6 Registers 785 25 Elliptic Curve Digital Signature Algorithm (ECDSA) 788 25.1 Introduction 788 25.2 Features 788 25.3 ECDSA Basics 788 25.3.1 Domain Parameters 788 25.3.2 Key Generation 789 25.3.3 Signature Generation 789 25.3.4 Signature Verification 790 25.4 Functional Description 790 25.4.1 ECDSA Working Modes 790 25.4.2 Data and Data Block 792 25.4.2.1 Writing Data 792 25.4.2.2 Reading Data 792 25.4.2.3 Padding the Message 792 25.4.2.4 Parsing the Message 793 25.4.3 Security Features 793 25.4.3.1 High Anti-Attack Performance 793 25.4.3.2 Dynamic Access Permission 793 25.4.3.3 Hardware Occupation 794 25.5 Programming Procedures 794 25.5.1 ECDSA Process 794 25.5.1.1 IDLE Stage 795 25.5.1.2 PREP Stage 796 Espressif Systems 16 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Contents 25.5.1.3 LOAD Stage 796 25.5.1.4 PROC Stage 796 25.5.1.5 GAIN Stage 796 25.5.1.6 POST Stage 797 25.5.1.7 ECDSA SHA Interface 797 25.5.2 Clock 798 25.5.3 Reset 799 25.6 Interrupts 799 25.7 Memory Blocks 801 25.8 Register Summary 802 25.9 Registers 803 26 External Memory Encryption and Decryption (XTS_AES)810 26.1 Overview 810 26.2 Features 810 26.3 Module Structure 810 26.4 Functional Description 811 26.4.1 XTS Algorithm 812 26.4.2 Key 812 26.4.3 Target Memory Space 812 26.4.4 Data Writing 813 26.4.5 Manual Encryption Block 814 26.4.6 Auto Encryption Block 814 26.4.7 Auto Decryption Block 815 26.5 Software Process 815 26.6 Anti-DPA 816 26.6.1 Clock Anti-DPA Function 816 26.6.2 Pseudo-round Anti-DPA Function 817 26.7 Register Summary 819 26.8 Registers 820 27 Random Number Generator (RNG) 826 27.1 Introduction 826 27.2 Features 826 27.3 Functional Description 826 27.4 Programming Procedure 827 27.5 Register Summary 829 27.6 Registers 830 V Connectivity Interface 831 28 UART Controller (UART) 832 28.1 Overview 832 28.2 Features 832 28.3 UART Structure 833 28.4 Functional Description 834 Espressif Systems 17 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Contents 28.4.1 Clock and Reset 834 28.4.2 UART FIFO 835 28.4.3 Baud Rate Generation and Detection 835 28.4.3.1 Baud Rate Generation 835 28.4.3.2 Baud Rate Detection 836 28.4.4 UART Data Frame 837 28.4.5 AT_CMD Character Structure 838 28.4.6 RS485 838 28.4.6.1 Driver Control 838 28.4.6.2 Turnaround Delay 839 28.4.6.3 Bus Snooping 839 28.4.7 IrDA 839 28.4.8 Wakeup 840 28.4.9 Flow Control 841 28.4.9.1 Hardware Flow Control 841 28.4.9.2 Software Flow Control 843 28.4.10 GDMA Mode 843 28.5 Interrupts 844 28.6 Programming Procedures 846 28.6.1 Register Type 846 28.6.2 Detailed Steps 847 28.6.2.1 Initializing UARTn 847 28.6.2.2 Configuring UARTn Communication 847 28.6.2.3 Enabling UARTn 848 28.7 Register Summary 849 28.7.1 UART Register Summary 849 28.7.2 LP UART Register Summary 850 28.7.3 UHCI Register Summary 851 28.8 Registers 853 28.8.1 UART Registers 853 28.8.2 LP UART Registers 876 28.8.3 UHCI Registers 896 29 SPI Controller (SPI) 918 29.1 Overview 918 29.2 Glossary 918 29.3 Features 919 29.4 Architectural Overview 920 29.5 Functional Description 920 29.5.1 Data Modes 921 29.5.2 FSPI Bus Signals 921 29.5.3 Bit Read/Write Order Control 923 29.5.4 Unaligned Byte Transfer 925 29.5.5 Transfer Types 925 29.5.6 CPU-Controlled Data Transfer 925 29.5.6.1 CPU-Controlled Master Transfer 926 Espressif Systems 18 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Contents 29.5.6.2 CPU-Controlled Slave Transfer 928 29.5.7 DMA-Controlled Data Transfer 928 29.5.7.1 DMA Configuration 929 29.5.7.2 GDMA TX/RX Buffer Length Control 930 29.5.8 Data Flow Control 930 29.5.8.1 GP-SPI2 Functional Blocks 931 29.5.8.2 Data Flow Control When GP-SPI2 Works as Master 932 29.5.8.3 Data Flow Control When GP-SPI2 Works as Slave 932 29.5.9 GP-SPI2 Works as Master 933 29.5.9.1 State Machine 933 29.5.9.2 Register Configuration for State and Bit Mode Control 936 29.5.9.3 Full-Duplex Communication (1-bit Mode Only) 940 29.5.9.4 Half-Duplex Communication (1/2/4-bit Mode) 941 29.5.9.5 DMA-Controlled Configurable Segmented Transfer 943 29.5.10 GP-SPI2 Works as Slave 946 29.5.10.1 Configurable Communication Formats 947 29.5.10.2 CMD Values Supported in Half-Duplex Communication 948 29.5.10.3 Slave Single Transfer and Slave Segmented Transfer 950 29.5.10.4 Configuration of Slave Single Transfer 951 29.5.10.5 Configuration of Slave Segmented Transfer in Half-Duplex 951 29.5.10.6 Configuration of Slave Segmented Transfer in Full-Duplex 952 29.6 CS Setup Time and Hold Time Control 952 29.7 GP-SPI2 Clock Control 953 29.7.1 Clock Phase and Polarity 954 29.7.2 Clock Control When GP-SPI2 Works as Master 956 29.7.3 Clock Control When GP-SPI2 Works as Slave 956 29.8 GP-SPI2 Timing Compensation 956 29.9 Interrupt 959 29.9.1 Interrupt Description 959 29.9.2 Interrupts Used in Master and in Slave 960 29.10 Register Summary 961 29.11 Register 963 30 I2C Controller (I2C) 1003 30.1 Overview 1003 30.2 Feature List 1003 30.3 Architecture Overview 1004 30.4 Functional Description 1006 30.4.1 Clock Configuration 1006 30.4.2 SCL and SDA Noise Filtering 1007 30.4.3 SCL Clock Stretching 1007 30.4.4 Generating SCL Pulses in Idle State 1008 30.4.5 Synchronization 1008 30.4.6 Open-Drain Output 1009 30.4.7 Timing Parameters Configuration 1010 30.4.8 Timeout Control 1012 Espressif Systems 19 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Contents 30.4.9 Command Configuration 1012 30.4.10 TX/RX RAM Data Storage 1013 30.4.11 Data Conversion 1014 30.4.12 Addressing Mode 1014 30.4.13 R/W Bit Check in 10-bit Addressing Mode 1015 30.4.14 Start the I2C Controller 1015 30.5 Functional Differences Between LP_I2C and I2C 1015 30.6 Interrupts 1016 30.7 Programming Procedures 1017 30.7.1 I2C master Writes to I2C slave with a 7-bit Address in One Command Sequence 1017 30.7.1.1 Introduction 1017 30.7.1.2 Configuration Example 1018 30.7.2 I2C master Writes to I2C slave with a 10-bit Address in One Command Sequence 1019 30.7.2.1 Introduction 1019 30.7.2.2 Configuration Example 1019 30.7.3 I2C master Writes to I2C slave with Two 7-bit Addresses in One Command Sequence 1020 30.7.3.1 Introduction 1021 30.7.3.2 Configuration Example 1021 30.7.4 I2C master Writes to I2C slave with a 7-bit Address in Multiple Command Sequences 1022 30.7.4.1 Introduction 1023 30.7.4.2 Configuration Example 1024 30.7.5 I2C master Reads I2C slave with a 7-bit Address in One Command Sequence 1025 30.7.5.1 Introduction 1025 30.7.5.2 Configuration Example 1026 30.7.6 I2C master Reads I2C slave with a 10-bit Address in One Command Sequence 1027 30.7.6.1 Introduction 1027 30.7.6.2 Configuration Example 1027 30.7.7 I2C master Reads I2C slave with Two 7-bit Addresses in One Command Sequence 1029 30.7.7.1 Introduction 1029 30.7.7.2 Configuration Example 1030 30.7.8 I2C master Reads I2C slave with a 7-bit Address in Multiple Command Sequences 1031 30.7.8.1 Introduction 1032 30.7.8.2 Configuration Example 1033 30.8 Register Summary 1035 30.8.1 I2C Register Summary 1035 30.8.2 LP_I2C Register Summary 1036 30.9 Registers 1038 30.9.1 I2C Registers 1038 30.9.2 LP_I2C Registers 1061 31 I2S Controller (I2S) 1084 31.1 Overview 1084 31.2 Terminology 1084 31.3 Features 1085 31.4 System Architecture 1086 31.5 Supported Audio Standards 1088 Espressif Systems 20 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Contents 31.5.1 TDM Philips Standard 1089 31.5.2 TDM MSB Alignment Standard 1089 31.5.3 TDM PCM Standard 1090 31.5.4 PDM Standard 1090 31.6 I2S TX/RX Clock 1090 31.7 I2S Reset 1092 31.8 I2S Master/Slave Mode 1093 31.8.1 Master/Slave TX Mode 1093 31.8.2 Master/Slave RX Mode 1093 31.9 Transmitting Data 1094 31.9.1 Data Format Control 1094 31.9.1.1 Bit Width Control of Channel Valid Data 1094 31.9.1.2 Endian Control of Channel Valid Data 1095 31.9.1.3 A-law/µ-law Compression and Decompression 1095 31.9.1.4 Bit Width Control of Channel TX Data 1096 31.9.1.5 Bit Order Control of Channel Data 1096 31.9.2 Channel Mode Control 1097 31.9.2.1 TDM TX Mode 1097 31.9.2.2 PDM TX Mode 1098 31.9.3 Synchronous Counter 1101 31.10 Receiving Data 1101 31.10.1 Channel Mode Control 1101 31.10.1.1 TDM RX Mode 1102 31.10.1.2 PDM RX Mode 1102 31.10.2 Data Format Control 1102 31.10.2.1 Bit Order Control of Channel Data 1102 31.10.2.2 Bit Width Control of Channel Storage (Valid) Data 1103 31.10.2.3 Bit Width Control of Channel RX Data 1103 31.10.2.4 Endian Control of Channel Storage Data 1103 31.10.2.5 A-law/µ-law Compression and Decompression 1103 31.11 Event Task Matrix Feature 1104 31.12 I2S Interrupts 1105 31.13 Software Configuration Process 1105 31.13.1 Configure I2S as TX Mode 1105 31.13.2 Configure I2S as RX Mode 1106 31.14 Register Summary 1107 31.15 Registers 1108 32 Pulse Count Controller (PCNT) 1127 32.1 Features 1128 32.2 Functional Description 1129 32.3 Applications 1132 32.3.1 Channel 0 Incrementing Independently 1132 32.3.2 Channel 0 Decrementing Independently 1133 32.3.3 Channel 0 and Channel 1 Incrementing Together 1133 32.4 Register Summary 1135 Espressif Systems 21 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Contents 32.5 Registers 1136 33 USB Serial/JTAG Controller 1144 33.1 Overview 1144 33.2 Feature List 1144 33.3 Functional Description 1146 33.3.1 CDC-ACM USB Interface Functional Description 1146 33.3.2 CDC-ACM Firmware Interface Functional Description 1147 33.3.3 USB-to-JTAG Interface: JTAG Command Processor 1148 33.3.4 USB-to-JTAG Interface: CMD_REP Usage Example 1149 33.3.5 USB-to-JTAG Interface: Response Capture Unit 1150 33.3.6 USB-to-JTAG Interface: Control Transfer Requests 1150 33.4 Interrupts 1151 33.5 Programming Procedures 1152 33.6 Register Summary 1154 33.7 Registers 1156 34 SDIO Slave Controller (SDIO) 1182 34.1 Overview 1182 34.2 Features 1182 34.3 Architecture Overview 1183 34.4 Standards Compliance 1183 34.5 Functional Description 1183 34.5.1 Physical Bus 1183 34.5.2 Supported Commands 1184 34.5.3 I/O Function 0 Address Space 1184 34.5.4 I/O Function 1/2 Address Space Map 1187 34.5.4.1 Accessing SLC HOST Register Space 1187 34.5.4.2 Transferring Incremental-Address Packets 1187 34.5.4.3 Transferring Fixed-Address Packets 1188 34.5.5 DMA 1188 34.5.5.1 Linked List 1189 34.5.5.2 Write-Back of Linked List 1190 34.5.5.3 Data Padding and Discarding 1191 34.5.6 SDIO Bus Timing 1192 34.6 Interrupt 1193 34.6.1 Host Interrupt 1193 34.6.2 Slave Interrupt 1193 34.7 Packet Sending and Receiving Procedure 1194 34.7.1 Sending Packets to SDIO Host 1194 34.7.2 Receiving Packets from SDIO Host 1196 34.8 Register Summary 1199 34.8.1 HINF Register Summary 1199 34.8.2 SLC Register Summary 1199 34.8.3 SLC Host Register Summary 1200 34.9 Registers 1202 Espressif Systems 22 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Contents 34.9.1 HINF Registers 1202 34.9.2 SLC Registers 1207 34.9.3 SLC Host Registers 1229 35 LED PWM Controller (LEDC) 1241 35.1 Overview 1241 35.2 Feature List 1241 35.3 Architectural Overview 1241 35.4 Functional Description 1242 35.4.1 Timers 1242 35.4.1.1 Clock Source 1243 35.4.1.2 Clock Divider Configuration 1243 35.4.1.3 20-Bit Counter 1244 35.4.2 PWM Generators 1245 35.4.3 Duty Cycle Fading 1246 35.4.3.1 Linear Duty Cycle Fading 1247 35.4.3.2 Gamma Curve Fading 1247 35.4.3.3 Suspend and Resume Duty Cycle Fading 1248 35.5 Event Task Matrix Feature 1249 35.6 Interrupts 1250 35.7 Programming Procedures 1250 35.8 Memory Blocks 1252 35.9 Register Summary 1253 35.10 Registers 1255 36 Motor Control PWM (MCPWM) 1267 36.1 Overview 1267 36.2 Features 1267 36.3 Modules 1270 36.3.1 Overview 1270 36.3.1.1 Timer Module 1270 36.3.1.2 Operator Module 1270 36.3.1.3 Capture Module 1271 36.3.1.4 ETM Module 1271 36.3.2 PWM Timer Module 1272 36.3.2.1 Configurations of the PWM Timer Module 1272 36.3.2.2 PWM Timer’s Working Modes and Timing Event Generation 1272 36.3.2.3 Shadow Register of PWM Timer 1278 36.3.2.4 PWM Timer Synchronization and Phase Locking 1278 36.3.3 PWM Operator Module 1278 36.3.3.1 PWM Generator Module 1279 36.3.3.2 Dead Time Generator Module 1292 36.3.3.3 PWM Carrier Module 1297 36.3.3.4 Fault Detection Module 1299 36.3.4 Capture Module 1300 36.3.4.1 Introduction 1300 Espressif Systems 23 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Contents 36.3.4.2 Capture Timer 1301 36.3.4.3 Capture Channel 1301 36.3.5 ETM Module 1301 36.3.5.1 Overview 1301 36.3.5.2 MCPWM-Related ETM Events 1301 36.3.5.3 MCPWM-Related ETM Tasks 1302 36.4 Interrupts 1303 36.5 Register Summary 1304 36.6 Registers 1307 37 Remote Control Peripheral (RMT) 1354 37.1 Overview 1354 37.2 Features 1354 37.3 Functional Description 1355 37.3.1 RMT Architecture 1355 37.3.2 RAM 1356 37.3.2.1 Structure of RAM 1356 37.3.2.2 Use of RAM 1356 37.3.2.3 RAM Access 1357 37.3.3 Clock 1357 37.3.4 Transmitter 1358 37.3.4.1 Normal TX Mode 1358 37.3.4.2 Wrap TX Mode 1358 37.3.4.3 TX Modulation 1358 37.3.4.4 Continuous TX Mode 1359 37.3.4.5 Simultaneous TX Mode 1359 37.3.5 Receiver 1359 37.3.5.1 Normal RX Mode 1359 37.3.5.2 Wrap RX Mode 1360 37.3.5.3 RX Filtering 1360 37.3.5.4 RX Demodulation 1360 37.4 Configuration Update 1361 37.5 Interrupts 1361 37.6 Register Summary 1363 37.7 Registers 1365 38 Parallel IO Controller (PARLIO) 1380 38.1 Introduction 1380 38.2 Glossary 1380 38.3 Features 1380 38.4 Architectural Overview 1382 38.5 Functional Description 1382 38.5.1 Clock Generator 1382 38.5.2 Clock and Reset Restriction 1383 38.5.3 Master-Slave Mode 1384 38.5.4 Receive Modes of the RX Unit 1385 Espressif Systems 24 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Contents 38.5.4.1 Level Enable Mode 1386 38.5.4.2 Pulse Enable Mode 1386 38.5.4.3 Software Enable Mode 1387 38.5.5 RX Unit GDMA SUC EOF Generation 1387 38.5.6 RX Unit Timeout 1388 38.5.7 Unlimited Length Data Transmission of TX Unit 1388 38.5.8 TX Chip Select Function 1388 38.5.9 Output Clock Gating of TX Unit 1388 38.5.10 Bus Idle Value of TX Unit 1389 38.5.11 Data Transfer in a Single Frame 1389 38.5.12 Bit Reversal in One Byte 1389 38.6 Interrupts 1390 38.7 Programming Procedures 1390 38.7.1 Data Receiving Operation Process 1390 38.7.2 Data Transmitting Operation Process 1391 38.8 Application Examples 1391 38.8.1 Co-working with SPI 1392 38.8.2 Co-working with I2S 1393 38.9 Register Summary 1395 38.10 Registers 1396 39 BitScrambler 1407 39.1 Introduction 1407 39.2 Feature List 1408 39.3 Application Examples 1408 39.4 Architectural Overview 1409 39.4.1 Data Path 1409 39.4.2 Control Path 1411 39.5 Functional Description 1411 39.5.1 Instructions 1411 39.5.2 Configuration Registers 1418 39.6 Programming Procedures 1420 39.7 Register Summary 1422 39.8 Registers 1423 VI Analog Signal Processing 1435 40 Temperature Sensor 1436 40.1 Overview 1436 40.2 Features 1436 40.3 Architecture 1436 40.4 Functional Description 1437 40.4.1 Temperature Sensor Power Up 1437 40.4.2 Temperature Sensor Clock 1437 40.4.3 Automatic Temperature Monitoring Modes 1437 40.4.4 Temperature Measurement Range and Offset 1438 Espressif Systems 25 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Contents 40.4.5 Data Conversion 1438 40.5 Programming Procedure 1438 40.6 Interrupts 1439 40.7 Event Task Matrix Feature 1439 40.8 Register Summary 1441 40.9 Registers 1442 41 ADC Controller 1446 41.1 Overview 1446 41.2 Terminology 1446 41.3 Feature List 1446 41.4 Architectural Overview 1447 41.5 Functional Description 1448 41.5.1 ADC Power Up 1448 41.5.2 ADC Channels 1448 41.5.3 ADC Clock 1448 41.5.4 One-Shot Sampling Mode 1449 41.5.5 Multi-Channel Sampling Mode 1449 41.5.6 ADC Conversion and Attenuation 1449 41.5.7 DIG ADC FSM 1450 41.5.8 Pattern Table 1451 41.5.9 ADC Filters 1452 41.5.10 Threshold Monitors 1453 41.5.11 GDMA Support 1453 41.6 Event Task Matrix Feature 1454 41.7 Interrupts 1454 41.8 Programming Procedure 1455 41.8.1 Configuring One-shot Sampling Mode 1455 41.8.2 Configuring Multi-Channel Sampling Mode 1455 41.9 Register Summary 1456 41.10 Registers 1457 42 Analog Voltage Comparator 1470 42.1 Introduction 1470 42.2 Feature List 1470 42.3 Architectural Overview 1470 42.4 Functional Description 1471 42.5 Event Task Matrix Feature 1472 42.6 Interrupts 1472 42.7 Programming Procedures 1473 VII Appendix 1474 Related Documentation and Resources 1475 Glossary 1476 Espressif Systems 26 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Contents Abbreviations for Peripherals 1476 Abbreviations Related to Registers 1476 Access Types for Registers 1478 Programming Reserved Register Field 1480 Introduction 1480 Programming Reserved Register Field 1480 Interrupt Configuration Registers 1481 Revision History 1482 Espressif Systems 27 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY List of Tables List of Tables 1.3-1 Trace Encoder Parameters 41 1.5-1 Optional sideband signals 43 1.6-1 Header Format 46 1.6-2 Index Format 46 1.6-3 Packet format 3 subformat 0 46 1.6-4 Packet format 3 subformat 1 47 1.6-5 Packet format 3 subformat 3 47 1.6-6 Packet format 2 48 1.6-7 Packet format 1 with address 49 1.6-8 Packet format 1 without address 50 1.7-1 TRACE’s Internal Interrupt Sources 50 1.8-1 Debug module trigger support (the action field of the mcontrol register) 52 1.8-2 Trace Status 54 2.3-1 LP CPU Exception Causes 79 2.6-1 Performance Counter 87 2.9-1 Wake Sources 91 3.4-1 GDMA Selecting Peripherals via Register Configuration 96 4.3-1 Memory Address Mapping 142 4.3-2 Module/Peripheral Address Mapping 148 5.3-1 Parameters in eFuse BLOCK0 153 5.3-2 Secure Key Purpose Values 158 5.3-3 Parameters in BLOCK1 to BLOCK10 159 5.3-4 Registers Information 164 5.3-5 Default Configuration of VDDQ Timing Parameters 165 5.4-1 eFuse’s Internal Interrupt Sources 166 6.4-1 HP GPIO Wakeup Signal Trigger and Clear Conditions 210 6.4-2 LP GPIO Wakeup Signal Trigger and Clear Conditions 211 6.8-1 Bit Used to Control IO MUX Functions in Light-sleep Mode 217 6.12-1 Peripheral Signals via HP GPIO Matrix 221 6.13-1 HP IO MUX Pin Functions 225 6.14-1 LP IO MUX Pin Functions 227 6.15-1 GPIO Pin Analog Functions 228 6.17-1 HP IO MUX and HP GPIO Matrix’s Internal Interrupt Sources 230 6.17-2 LP IO MUX and LP GPIO Matrix’s Internal Interrupt Sources 230 7.1-1 Reset Source 286 7.2-1 Crystal Frequency 289 7.2-2 CPU_CLK Clock Source 289 7.2-3 Frequency of CPU_CLK, AHB_CLK and HP_ROOT_CLK 290 7.2-4 Derived HP Clock Source 292 Espressif Systems 28 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY List of Tables 7.2-5 HP Clocks Used by Each Peripheral 292 7.2-6 Derived LP Clock Source 293 7.2-7 LP Clocks Used by Each Peripheral 293 7.2-8 Mapping between controlling the clock gating of read/write registers and related PMU registers 295 7.2-9 Mapping between controlling the functional clock gating of high-performance system peripher- als and related PMU registers 296 8.2-1 Default Configuration of Strapping Pins 369 8.2-2 Boot Mode Control 369 8.2-3 SDIO Input Sampling Edge/Output Driving Edge Control 371 8.2-4 UART0 ROM Message Printing Control 372 8.2-5 USB Serial/JTAG ROM Message Printing Control 372 8.2-6 JTAG Signal Source Control 373 8.2-7 Crystal Frequency Selection 373 9.5-1 CPU Peripheral Interrupt Source Mapping/Status Registers and Peripheral Interrupt Sources 377 10.3-1 Selectable Events for ETM Channeln 395 10.3-2 Mappable Tasks for ETM Channeln 399 11.5-1 UNITn Configuration Bits 506 11.5-2 Trigger Point 508 11.5-3 Synchronization Operation for Configuration Registers 508 11.6-1 System Timer’s Internal Interrupt Sources 509 12.4-1 Alarm Generation When Up-Down Counter Increments 533 12.4-2 Alarm Generation When Up-Down Counter Decrements 533 12.6-1 TIMGn’s Internal Interrupt Sources 535 13.2-1 Timeout Actions 556 14.3-1 Configure RTC Timer to Log the Occurrence Time of Specific Events 568 14.3-2 Target Time Configuration 568 14.5-1 RTC Timer’s Internal Interrupt Sources 569 15.1-1 Management Areas by PMP and AMP 581 15.4-2 Comparison Between TEE and REE 584 15.5-1 Master Access Source from HP System 585 15.5-2 APM Controllers Configuration Registers 587 16.3-1 Security Level 642 17.5-1 HP CPU Packet Format 659 17.5-2 LP CPU Packet Format 659 17.5-3 DMA Packet Format 659 17.5-4 LOST Packet Format 660 17.5-5 DMA Access Source 661 17.5-6 DMA_0 Packet Format 663 17.5-7 DMA LOST Packet Format 663 Espressif Systems 29 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY List of Tables 18.3-1 Configuration for Detecting Power Pins 695 18.4-1 Power Supply Detector’s Internal Interrupt Source 695 19.4-1 AES Accelerator Working Mode 707 19.4-2 Key Length and Encryption/Decryption 707 19.5-1 Working Status under Typical AES Working Mode 708 19.5-2 Text Endianness Type for Typical AES 709 19.5-3 Key Endianness Type for AES-128 Encryption and Decryption 710 19.5-4 Key Endianness Type for AES-256 Encryption and Decryption 710 19.6-1 Block Cipher Mode 712 19.6-2 Working Status under DMA-AES Working mode 712 19.6-3 TEXT-PADDING 713 19.6-4 Text Endianness for DMA-AES 713 20.3-1 ECC Accelerator Memory Blocks 725 20.4-1 ECC Accelerator Curve Mode Selection 727 20.4-2 Working Modes of ECC Accelerator 727 21.4-1 HMAC Purposes and Configuration Value 743 22.3-1 Acceleration Performance 759 22.4-1 RSA’s Internal Interrupt Source 759 23.3-1 SHA Accelerator Working Mode 767 23.3-2 SHA Hash Algorithm Selection 767 23.4-1 The Storage and Length of Message Digest from Different Algorithms 771 23.4-2 SHA’s Internal Interrupt Sources 771 25.4-1 ECDSA Working Mode 791 25.4-2 ECDSA Elliptic Curves Selection 791 25.4-3 ECDSA SHA Algorithm 791 25.4-4 ECDSA Working Status 791 25.7-1 ECDSA Memory Blocks 801 26.4-1 Key Generated Based on Key A 812 26.4-2 Mapping Between Offsets and Registers 813 26.6-1 Configuration of XTS_AES Pseudo-round Anti-DPA 818 28.2-1 UART and LP UART Feautre Comparison 832 28.4-1 UART_CHAR_WAKEUP Mode Configuration 841 29.5-1 Data Modes Supported by GP-SPI2 921 29.5-2 Functional Description of FSPI Bus Signals 921 29.5-3 FSPI Bus Signals Used in Various SPI Modes 922 29.5-4 Bit Order Control in GP-SPI2 924 29.5-5 Supported Transfer Types as Master or Slave 925 29.5-6 Interrupt Trigger Condition on GP-SPI2 Data Transfer as Slave 929 29.5-7 Registers Used for State Control in 1/2/4-bit Modes 937 29.5-8 Sending Sequence of Command Value 939 Espressif Systems 30 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY List of Tables 29.5-9 Sending Sequence of Address Value 939 29.5-10 BM Table for CONF State 945 29.5-11 An Example of CONF bufferi in Segment i 945 29.5-12 BM Bit Value and Register to Be Updated in This Example 946 29.5-13 CMD Values Supported in SPI Mode 949 29.5-13 CMD Values Supported in SPI Mode 950 29.5-14 CMD Values Supported in QPI Mode 950 29.7-1 Clock Phase and Polarity Configuration as Master 956 29.7-2 Clock Phase and Polarity Configuration as Slave 956 29.9-1 Internal Interrupt Sources of GP-SPI2 959 29.9-2 GP-SPI2 Master Mode Interrupts 960 29.9-3 GP-SPI2 Slave Mode Interrupts 961 30.3-1 I2C Timing Parameters (Cited from Table 5 in The I2C-bus specification Version 2.1) 1006 30.4-1 I2C Synchronous Registers 1009 31.4-1 I2S Signal Description 1088 31.9-1 Bit Width of Channel Valid Data 1095 31.9-2 Endian of Channel Valid Data 1095 31.9-3 Data-Fetching Control in PDM Mode 1098 31.9-4 I2S Channel Control for Raw PDM Data 1099 31.9-5 I2S PCM-to-PDM Data Output 1099 31.10-1 Channel Storage Data Width 1103 31.10-2 Channel Storage Data Endian 1103 32.2-1 Counter Mode. Positive Edge of Input Pulse Signal. Control Signal in Low State 1130 32.2-2 Counter Mode. Positive Edge of Input Pulse Signal. Control Signal in High State 1130 32.2-3 Counter Mode. Negative Edge of Input Pulse Signal. Control Signal in Low State 1130 32.2-4 Counter Mode. Negative Edge of Input Pulse Signal. Control Signal in High State 1131 33.3-1 Standard CDC-ACM Control Requests 1146 33.3-2 CDC-ACM Settings with RTS and DTR 1147 33.3-3 Commands of a Nibble 1149 33.3-4 USB-to-JTAG Control Requests 1150 33.3-5 JTAG Capability Descriptors 1151 33.5-1 Reset SoC into Download Mode 1153 33.5-2 Reset SoC into Booting from flash 1153 34.5-1 SDIO Slave CCCR Configuration 1185 34.5-2 SDIO Slave FBR Configuration 1186 35.4-1 Commonly-used Frequencies and Resolutions 1245 35.8-1 LEDC Memory Blocks 1252 36.3-1 Functions of Each Submodule in the Operator Module 1271 36.3-2 Timing Events Used in PWM Generator 1280 36.3-3 Timing Events Priority When PWM Timer Increments 1281 36.3-4 Timing Events Priority when PWM Timer Decrements 1281 Espressif Systems 31 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY List of Tables 36.3-5 Dead Time Generator Switches Control Fields 1293 36.3-6 Typical Dead Time Generator Operating Modes 1294 36.3-7 MCPWM-Related ETM Events 1301 36.3-8 ETM Related Tasks 1302 37.4-1 Configuration Update 1361 38.5-1 Operations to Reset AHB Clock Domain with Clock Restrictions 1383 38.5-2 Requirements for TX Unit Operating as Slave with Clock Restrictions 1385 38.5-3 Requirements for RX Unit Operating as Slave with Clock Restrictions 1385 38.6-1 PARLIO’s Internal Interrupt Sources 1390 39.5-1 Instruction Structure 1412 39.5-2 Effective CTL_MUX_SEL_n values when CTL_MUX_REL is 1 1413 39.5-3 CTL_MUX_SEL Values 1413 39.5-4 Instruction Opcode 1414 39.5-5 LOOP Opcode 1415 39.5-6 ADD Opcode 1416 39.5-7 IF Opcode 1416 39.5-8 IFN Opcode 1416 39.5-9 LDCTD Opcode 1417 39.5-10 LDCTI Opcode 1417 39.5-11 ADDCTI Opcode 1418 39.5-12 Settings for EOF modes 1419 40.4-1 Temperature Measurement Range and Offset 1438 41.5-1 SAR ADC Channels 1448 42.4-1 Mapping Between PAD and GPIO 1471 42.6-1 Analog Voltage Comparator’s Internal Interrupt Sources 1472 42.7-4 Configuration of ENA/RAW/ST Registers 1481 Espressif Systems 32 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY List of Figures List of Figures 1.0-1 Trace Encoder Overview 39 1.2-1 Trace Flow Overview 40 1.6-1 Trace packet Format 45 2.0-1 LP CPU Overview 69 2.9-1 Wake-Up and Sleep Flow of LP CPU 89 3.1-1 Modules that Share GDMA Channels 93 3.3-1 GDMA controller Architecture 94 3.4-1 Structure of a Linked List 95 3.4-2 Relationship among Linked Lists 98 4.3-1 System Structure and Address Mapping 142 4.3-2 ROM-Cache Structure 144 4.3-3 Cache Structure 145 4.3-4 Modules/peripherals that can work with GDMA 147 5.3-1 Data Flow in eFuse 152 5.3-2 Shift Register Circuit (first 32 output) 161 5.3-3 Shift Register Circuit (last 12 output) 161 6.3-1 Architecture of HP GPIO Matrix, HP IO MUX, LP GPIO Matrix, and LP IO MUX 207 6.3-2 Internal Structure of a Pad 208 6.4-1 GPIO Input Synchronized on Rising Edge or on Falling Edge of HP IO MUX Operating Clock 209 6.4-2 GPIO Filter Timing of GPIO Input Signals 210 6.4-3 Glitch Filter Timing Example 212 6.10-1 Example of Level Flip on the Chip Pad — Hysteresis Function Not Enabled 219 6.10-2 Example of Level Flip on the Chip Pad — Hysteresis Function Enabled 219 7.1-1 Reset Types 285 7.2-1 System Clock 288 7.3-1 Clock Configuration Example 297 8.2-1 Chip Boot Flow 370 9.2-1 Interrupt Flow in ESP32-C5 375 9.4-1 Interrupt Matrix Structure 375 10.3-1 ETM Channeln Architecture 395 10.3-2 Event Task Matrix Clock Architecture 402 11.3-1 System Timer Structure 505 11.5-1 System Timer Alarm Generation 506 12.1-1 Timer Group Overview 530 12.3-1 Timer Group Architecture 531 13.1-1 Watchdog Timers Overview 553 Espressif Systems 33 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY List of Figures 13.2-1 Digital Watchdog Timers in ESP32-C5 555 13.3-1 Super Watchdog Controller Structure 558 15.1-1 PMP-APM Management Relation 582 15.5-1 APM Controller Architecture 586 18.3-1 Architecture of Power Supply Detector 693 18.3-2 Brown-out Reset Workflow 694 18.3-3 Structure of Voltage Glitch Detectors 695 20.4-1 clk_ecc Diagram 732 20.4-2 clk_apb_ecc Diagram 732 21.6-1 HMAC SHA-256 Padding Diagram 746 21.6-2 HMAC Structure Schematic Diagram 746 24.3-1 Software Preparations and Hardware Working Process 779 25.5-1 ECDSA Process 795 25.5-2 clk_ecdsa Diagram 798 25.5-3 clk_apb_ecdsa Diagram 798 26.3-1 Architecture of the External Memory Encryption and Decryption 811 27.3-1 Noise Source 827 28.3-1 UART Structure 833 28.4-1 UART Controllers Division 836 28.4-2 The Timing Diagram of Weak UART Signals Along Negative Edges 836 28.4-3 Structure of UART Data Frame 837 28.4-4 AT_CMD Character Structure 838 28.4-5 Driver Control Diagram in RS485 Mode 839 28.4-6 The Timing Diagram of Encoding and Decoding in SIR mode 840 28.4-7 IrDA Encoding and Decoding Diagram 840 28.4-8 Hardware Flow Control Diagram 842 28.4-9 Connection between Hardware Flow Control Signals 842 28.4-10 Data Transfer in GDMA Mode 844 28.6-1 UART Programming Procedures 847 29.4-1 SPI Module Overview 920 29.5-1 Data Buffer Used in CPU-Controlled Transfer 926 29.5-2 GP-SPI2 Functional Blocks 931 29.5-3 Data Flow Control When GP-SPI2 Works as Master 932 29.5-4 Data Flow Control When GP-SPI2 Works as Slave 932 29.5-5 GP-SPI2 State Machine 935 29.5-6 Full-Duplex Communication Between GP-SPI2 Master and a Slave 940 29.5-7 Connection of GP-SPI2 to Flash and External RAM in 4-bit Mode 942 29.5-8 SPI Quad I/O Read Command Sequence Sent by GP-SPI2 to Flash 943 29.5-9 Configurable Segmented Transfer 943 Espressif Systems 34 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY List of Figures 29.6-1 Recommended CS Timing and Settings When Accessing External RAM 953 29.6-2 Recommended CS Timing and Settings When Accessing Flash 953 29.7-1 SPI Clock Mode 0 or 2 955 29.7-2 SPI Clock Mode 1 or 3 955 29.8-1 Timing Compensation Control Diagram in GP-SPI as Master 957 29.8-2 Timing Compensation Example in GP-SPI2 958 30.3-1 I2C Master Architecture 1004 30.3-2 I2C Slave Architecture 1004 30.3-3 I2C Protocol Timing (Cited from Fig.31 in The I2C-bus specification Version 2.1) 1005 30.4-1 I2C Timing Diagram 1010 30.4-2 Structure of I2C Command Registers 1012 30.7-1 I2C master Writing to I2C slave with a 7-bit Address 1017 30.7-2 I2C master Writing to a Slave with a 10-bit Address 1019 30.7-3 I2C master Writing to I2C slave with Two 7-bit Addresses 1021 30.7-4 I2C master Writing to I2C slave with a 7-bit Address in Multiple Sequences 1023 30.7-5 I2C master Reading I2C slave with a 7-bit Address 1025 30.7-6 I2C master Reading I2C slave with a 10-bit Address 1027 30.7-7 I2C master Reading N Bytes of Data from addrM of I2C slave with a 7-bit Address 1029 30.7-8 I2C master Reading I2C slave with a 7-bit Address in Segments 1032 31.4-1 ESP32-C5 I2S System Diagram 1087 31.5-1 TDM Philips Standard Timing Diagram 1089 31.5-2 TDM MSB Alignment Standard Timing Diagram 1089 31.5-3 TDM PCM Standard Timing Diagram 1090 31.5-4 PDM Standard Timing Diagram 1090 31.6-1 I2S Clock Generator 1091 31.9-1 TX Data Format Control 1097 31.9-2 TDM Channel Control 1098 31.9-3 PDM Channel Control Example 1100 32.0-1 PCNT Block Diagram 1127 32.2-1 PCNT Unit Architecture 1129 32.3-1 Channel 0 Up Counting Diagram 1132 32.3-2 Channel 0 Down Counting Diagram 1133 32.3-3 Two Channels Up Counting Diagram 1133 33.2-1 USB Serial/JTAG High Level Diagram 1145 33.2-2 USB Serial/JTAG Block Diagram 1146 34.3-1 SDIO Slave Block Diagram 1183 34.5-1 CMD52 Content 1184 34.5-2 CMD53 Content 1184 34.5-3 Function 0 Address Space 1185 34.5-4 Function 1/2 Address Space Map 1187 34.5-5 DMA Linked List Descriptor Structure of the SDIO Slave 1189 34.5-6 DMA Linked List of the SDIO Slave 1190 34.5-7 Data Flow of Sending Incremental-address Packets From Host to Slave 1191 Espressif Systems 35 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY List of Figures 34.5-8 Sampling Timing Diagram 1192 34.5-9 Output Timing Diagram 1192 34.7-1 Procedure of Slave Sending Packets to Host 1195 34.7-2 Procedure of Slave Receiving Packets from Host 1197 34.7-3 Loading Receiving Buffer 1198 35.3-1 LED PWM Architecture 1242 35.3-2 Timer and PWM Generator Block Diagram 1242 35.4-1 Frequency Division When LEDC_CLK_DIV is a Non-Integer Value 1244 35.4-2 Relationship Between Counter And Resolution 1244 35.4-3 LED PWM Output Signal Diagram 1246 35.4-4 Output Signal of Linear Duty Cycle Fading 1247 35.4-5 Output Signal of Gamma Curve Fading 1248 36.2-1 MCPWM Module Overview 1268 36.3-1 Timer Module 1270 36.3-2 Operator Module 1270 36.3-3 Capture Module 1271 36.3-4 ETM Module 1271 36.3-5 Count-Up Mode Waveform 1273 36.3-6 Count-Down Mode Waveforms 1273 36.3-7 Count-Up-Down Mode Waveforms, Count-Down at Synchronization Event 1273 36.3-8 Count-Up-Down Mode Waveforms, Count-Up at Synchronization Event 1274 36.3-9 UTEP and UTEZ Generation in Count-Up Mode 1275 36.3-10 DTEP and DTEZ Generation in Count-Down Mode 1276 36.3-11 DTEP and UTEZ Generation in Count-Up-Down Mode 1276 36.3-12 Block Diagram of A PWM Operator 1279 36.3-13 Symmetrical Waveform in Count-Up-Down Mode 1283 36.3-14 Count-Up, Single Edge Asymmetric Waveform, with Independent Modulation on PWMxA and PWMxB — Active High 1284 36.3-15 Count-Up, Pulse Placement Asymmetric Waveform with Independent Modulation on PWMxA 1285 36.3-16 Count-Up-Down, Dual Edge Symmetric Waveform, with Independent Modulation on PWMxA and PWMxB — Active High 1286 36.3-17 Count-Up-Down, Dual Edge Symmetric Waveform, with Independent Modulation on PWMxA and PWMxB — Complementary 1287 36.3-18 Count-Up-Down, Fault or Synchronization Events, with Same Modulation on PWMxA and PWMxB1288 36.3-19 Example of an NCI Software-Force Event on PWMxA 1290 36.3-20 Example of a CNTU Software-Force Event on PWMxB 1291 36.3-21 Options for Setting up the Dead Time Generator Module 1293 36.3-22 Active High Complementary (AHC) Dead Time Waveforms 1294 36.3-23 Active Low Complementary (ALC) Dead Time Waveforms 1295 36.3-24 Active High (AH) Dead Time Waveforms 1295 36.3-25 Active Low (AL) Dead Time Waveforms 1296 36.3-26 Example of Waveforms Showing PWM Carrier Action 1297 36.3-27 Example of the First Pulse and the Subsequent Sustaining Pulses of the PWM Carrier Submodule1298 36.3-28 Possible Duty Cycle Settings for Sustaining Pulses in the PWM Carrier Submodule 1299 Espressif Systems 36 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY List of Figures 37.3-1 RMT Architecture 1355 37.3-2 Format of Pulse Code in RAM 1356 38.4-1 PARLIO Architecture 1382 38.5-1 PARLIO Clock Generation 1383 38.5-2 Positive Waveform 1385 38.5-3 Negative Waveform 1385 38.5-4 Sub-Modes of Level Enable Mode for RX Unit 1386 38.5-5 Sub-Modes of Pulse Enable Mode for RX Unit 1387 38.5-6 Sub-Mode of Software Enable Mode for RX Unit 1387 39.1-1 BitScrambler System Context Diagram 1408 39.4-1 BitScrambler Data Path Diagram 1409 39.4-2 BitScrambler Control Path Diagram 1411 40.3-1 Temperature Sensor Architecture 1437 41.4-1 SAR ADC Architecture 1447 41.5-1 SAR ADC Clock Structure 1448 41.5-2 DIG ADC FSM Block Diagram 1450 41.5-3 APB_SARADC_SAR_PATT_TAB1_REG Contains Patterns 0 - 3 1451 41.5-4 APB_SARADC_SAR_PATT_TAB2_REG Contains Patterns 4 - 7 1451 41.5-5 Pattern Structure 1451 41.5-6 cmd0 configuration 1452 41.5-7 cmd1 Configuration 1452 41.5-8 DMA Data Format 1453 42.3-1 Analog Voltage Comparator Architecture 1470 Espressif Systems 37 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Part I Microprocessor and Master This part covers the essential processing elements of the system, diving into the microprocessor architecture with both high-performance and low-power CPUs. Details include trace encoding for debugging purposes and controllers for Direct Memory Access (DMA). Espressif Systems 38 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 1 RISC-V Trace Encoder (TRACE) Chapter 1 RISC-V Trace Encoder (TRACE) The high-performance CPU (HP CPU) of ESP32-C5 supports the instruction trace interface through the trace encoder. The trace encoder connects to HP CPU’s instruction trace interface, compresses the information into smaller packets, and then stores the packets into internal SRAM. HP CPU Encoder FIFO Config Transmission Control Instruction Trace Interface APB Trace Encoder AHB Figure 1.0-1. Trace Encoder Overview 1.1 Terminology To better illustrate the functions of the RISC-V Trace Encoder, the following terms are used in this chapter. hart RISC-V hardware thread branch an instruction which conditionally changes the execution flow uninferable discontinuity (updiscon) a program counter change that can not be inferred from the pro- gram binary alone delta a change in the program counter that is other than the difference between two instructions placed consecutively in memory trap the transfer of control to a trap handler caused by either an excep- tion or an interrupt qualification an instruction that meets the filtering criteria passes the qualification, and will be traced te_inst the name of the packet type emitted by the encoder retire the final stage of executing an instruction, when the machine state is updated EPC exception program counter Espressif Systems 39 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 1 RISC-V Trace Encoder (TRACE) 1.2 Introduction In complex systems, understanding program execution flow is not straightforward. This may be due to a number of factors, for example, interactions with other cores, peripherals, real-time events, poor implementations, or some combination of all of the above. It is hard to use a debugger to monitor the program execution flow of a running system in real time, as this is intrusive and might affect the running state. However, it is important to provide the visibility of program execution. That is where instruction trace comes in, which provides a trace of the program execution. It works by tracking execution from a known start address and sending messages about the address deltas taken by the program. These deltas are typically introduced by jump, call, return, and branch type instructions, although interrupts and exceptions are also types of deltas. Trace Encoder System Memory ESP Chip JTAG/ USB-JTAG adapter Trace Decoder Debug Translator Debug Host HP CPU Core DM DMI JTAG DTM Instruction Trace Interface BUS Figure 1.2-1. Trace Flow Overview Figure 1.2-1 shows the instruction delta trace flow. • The HP CPU core provides an instruction trace interface that outputs the instruction information executed by the HP CPU. Such information includes instruction address, instruction type, etc. For more details about ESP32-C5 HP CPU’s instruction trace interface, please refer to Chapter 1 High-Performance CPU [to be added later]. • The trace encoder collects the relevant instruction trace information from HP CPU’s instruction trace interface, compresses the information into lower bandwidth packets, and then stores the packets in system memory. • The debugger (debug host) can dump the trace packets from the system memory via JTAG or USB Serial/JTAG, and use a decoder to decompress and reconstruct the program execution flow. The trace decoder, usually software on an external PC, takes in the trace packets and reconstructs the program instruction flow with the program binary that runs on the originating hart. This decoding step can be done offline or in real time while the hart is executing. Espressif Systems 40 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 1 RISC-V Trace Encoder (TRACE) 1.3 Features • Compatible with Efficient Trace for RISC-V Version 2.0. See Table 1.3-1 for the implemented parameters • Support for delta address mode and full address mode • Support for a filter unit • Support for notifying an instruction address via debug trigger or filter unit • Support for the following sideband signals to control trace data flow: – Support for debugging trigger to start or stop encoder – When the hart is halted, the encoder can report the last packet and then stop – When the hart is reset, the encoder can report the last packet and then stop – Support for stalling the hart when trace FIFO is almost full • Arbitrary address range of the trace memory size • Configurable synchronization modes: – Synchronization counter counts by packet – Synchronization counter counts by cycle – Synchronization counter can be disabled • Trace lost status to indicate packet loss • Automatic restart after packet loss • Memory writing in the loop or non-loop mode • Support two interrupts: – Triggered when the packet size exceeds the configured memory space – Triggered when a packet is lost • FIFO (128 × 8 bits) to buffer packets • AHB burst transmission with configurable burst length Table 1.3-1. Trace Encoder Parameters Parameter Name Value Description arch_p 0 Initial version bpred_size_p 0 Branch prediction mode is not supported cache_size_p 0 Jump target cache mode is not supported call_counter_size_p 0 Implicit return mode is not supported ctype_width_p 0 Width of the ctype bus context_width_p 0 Width of context bus ecause_width_p 6 Width of exception cause ecause_choice_p 0 Multiple choice is not supported f0s_width_p 0 Format 0 packets are not supported filter_context_p 0 Filtering on context is not supported Espressif Systems 41 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 1 RISC-V Trace Encoder (TRACE) Parameter Name Value Description filter_excint_p 1 Filtering on exception cause or interrupt is supported filter_privilege_p 1 Filtering on privilege is supported filter_tval_p 1 Filtering on trap value is supported iaddress_lsb_p 1 Compressed instructions are supported iaddress_width_p 32 The instruction bus is 32-bit iretire_width_p 1 Width of the iretire bus ilastsize_width_p 0 Width of the ilastsize itype_width_p 3 Width of the itype bus nocontext_p 1 Exclude context from te_inst packets notime_p 1 Exclude time from te_inst packets privilege_width_p 1 Only machine and user mode are supported retires_p 1 Maximum number of instructions that can be retired per block return_stack_size_p 0 Implicit return mode is not supported sijump_p 0 Sequentially inferable jump mode is not supported taken_branches_p 1 Only one instruction retired per cycle impdef_width_p 0 Not implemented For detailed descriptions of the above parameters, please refer to the Efficient Trace for RISC-V Version 2.0 > Chapter Parameters and Discovery. 1.4 Architectural Overview This chapter mainly introduces the implementation details of ESP32-C5’s trace encoder. As shown in Figure 1.0-1, the trace encoder contains an encoder, a FIFO, a register configuration module, and a transmission control module. The encoder receives the HP CPU’s instruction information via the instruction trace interface, compresses it into different packets, and writes it to the internal FIFO. The transmission control module writes the data in the FIFO to the internal SRAM through the AHB bus. The FIFO is 128 deep and 8-bit wide. When the memory bandwidth is insufficient, the FIFO may overflow, resulting in packet loss. When a packet is lost, the encoder will send a packet to indicate this event. Thereafter, the encoder will stop working till FIFO gets empty. An interrupt will also be generated to indicate this event if it has been enabled. 1.5 Functional Description 1.5.1 Synchronization In order to make the trace robust there must be regular synchronization points within the trace. Synchronization is accomplished by sending a full valued instruction address. When the synchronization counter value reaches the value of the TRACE_RESYNC_PROLONGED field of the TRACE_RESYNC_PROLONGED_REG register, the encoder will send a synchronization packet (format 3 subformat 0, see Section 1.6.3.1). Espressif Systems 42 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 1 RISC-V Trace Encoder (TRACE) The synchronization counter is configured via TRACE_RESYNC_MODE: • 0: Disable the synchronization counter • 1: Invalid. No effect • 2: Synchronization counter counts by packet • 3: Synchronization counter counts by cycle You can adjust the trace bandwidth by increasing the value of TRACE_RESYNC_PROLONGED to reduce the frequency of sending synchronization packets, thereby reducing the bandwidth occupied by packets. 1.5.2 Address Mode ESP32-C5 supports two address modes: delta address mode and full address mode. • Delta address mode (default): In delta address mode, addresses are encoded as the difference between the actual address of the current instruction and the actual address of the instruction reported in the previous packet that contained an address. This differential encoding requires fewer bits than the full address, and thus results in more efficient trace compression. • Full address mode: In full address mode, all addresses in the trace are encoded as absolute addresses instead of in differential form. This kind of encoding is always less efficient, but it can be a useful debugging aid for software decoder developers. This mode is enabled by setting TRACE_FULL_ADDRESS. 1.5.3 Optional Sideband Signals The Efficient Trace for RISC-V Version 2.0 > Chapter Optional Sideband Signals has provided some optional sideband signals for encoder control. ESP32-C5 has implemented the following functions: Table 1.5-1. Optional sideband signals Signal Function trigger[2:0] • A pulse on bit 0 will cause the encoder to start tracing, and continue until further notice, subject to other filtering criteria also being met. • A pulse on bit 1 will cause the encoder to stop tracing until further notice. • A pulse on bit 2 will cause the encoder to report a specific address. This function is enabled by setting TRACE_DM_TRIGGER_ENA. The trigger signal is asserted upon a trigger match. For example, if the action field of mcontrol is 2, while the trigger matched it will assert trigger bit0; if the action is 3, while the trigger matched it will assert trigger bit1. For details, please refer to Table 1.8-1. halted Hart is halted. Upon assertion, the encoder will output a packet to report the address of the last instruction retired before halting, followed by a support packet to indicate that tracing has stopped. Upon deassertion, the encoder will start tracing again, commencing with a synchronization packet. This function is enabled by setting TRACE_HALT_ENA. reset Hart is in reset. Behavior is as described above for halted. Espressif Systems 43 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 1 RISC-V Trace Encoder (TRACE) Signal Function stall Stall request to hart. Some applications may require lossless trace, which can be achieved by using this signal to stall the hart if the trace encoder is unable to output a trace packet (internal FIFO almost full). This function is enabled by setting TRACE_STALL_ENA. 1.5.4 Filtering Filtering provides a mechanism to control the criteria for the encoder to produce a trace. For example, it may be desirable to trace: • When the instruction address is within a particular range • Starting from one instruction address and continue until a second instruction address • For one or more specified privilege levels • Exception and/or interrupt handlers for specified exception causes The filtering unit has a filter and a comparator unit. Each comparator unit is actually a pair of comparators (Primary and Secondary, or P, S) allowing a bounded range to be matched with a signal unit if required, and offers: • Input selected from instruction address (iaddress) and trap value (tval) • A range of arithmetic options (<, >, =, ! =, etc.) independently selectable for each comparator • Secondary match value may be used as a mask for the primary comparator • The two comparators can be combined in several ways: P , P &&S, !(P &&S), latch (set on P clear on S) • Each comparator can also be used to explicitly report a particular instruction address Each filter can specify filtering against instruction from the hart, and offers: • 1 run-time selectable comparator units to match • Selection for specific privilege level (priv) and exception cause (ecause) as inputs • Select matching for interrupt 1.5.5 Anchor Tag Since the length of data packets is variable, in order to identify boundaries between data packets when packed packets are written to memory, the ESP32-C5 encoder inserts zero bytes between data packets: • The maximum packet length is 13 bytes, so a sequence of at least 14 zero bytes cannot occur within a normal packet. Therefore, the first non-zero byte seen after a sequence of at least 14 zero bytes must be the first byte of a packet. • Every time when 128 packets are transmitted, the encoder writes 14 zero bytes to the memory partition boundary as anchor tags. Espressif Systems 44 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 1 RISC-V Trace Encoder (TRACE) 1.5.6 Memory Writing Mode When writing the trace memory, the size of the trace packets might exceed the capacity of the memory. In this case, you can choose whether to wrap around the trace memory or not by configuring the memory writing mode: • Loop mode: When the size of the trace packets exceeds the capacity of the trace memory (namely when TRACE_MEM_CURRENT_ADDR_REG reaches the value of TRACE_MEM_END_ADDR_REG), the trace memory is wrapped around, so that the encoder loops back to the memory’s starting address TRACE_MEM_START_ADDR_REG, and old data in the memory will be overwritten by new data. • Non-loop mode: When the size of the trace packets exceeds the capacity of the trace memory, the trace memory is not wrapped around. The encoder stops at TRACE_MEM_END_ADDR_REG, and old data will be retained. 1.5.7 Automatic Restart When packets are lost due to FIFO overflow, the encoder will stop working and need to be resumed by software manually or restarted by hardware automatically. If the TRACE_RESTART_ENA bit of TRACE_TRIGGER_REG is set, once the FIFO is empty, the encoder can automatically be restarted. If the automatic restart feature is enabled, the encoder will be restarted in any case. Therefore, to disable the encoder, the automatic restart feature must be disabled first by clearing the TRACE_RESTART_ENA bit of the TRACE_TRIGGER_REG register. 1.6 Encoder Output Packets This section mainly introduces ESP32-C5 trace encoder output packet format. Header (1 byte) Index (2 bytes) Payload (1~10 bytes) Figure 1.6-1. Trace packet Format A packet includes header, index, and payload. Header, index and payload are transmitted sequentially in bit stream form, from the fields listed at the top of tables below to the fields listed at the bottom. If a field consists of multiple bits, then the least significant bit is transmitted first. 1.6.1 Header Header is 1-byte long. The format of header is shown in Table 1.6-1. Espressif Systems 45 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 1 RISC-V Trace Encoder (TRACE) Table 1.6-1. Header Format Field Bit Width Description Value length 5 Length of whole packet 4 13 flow 2 Reserved 0 timestamp 1 Reserved 0 1.6.2 Index Index has 2 bytes. The format of index is shown in Table 1.6-2. Table 1.6-2. Index Format Field Bit Width Description Value index 16 The index of each packet 065536 1.6.3 Payload The length of payload ranges from 1 byte to 10 bytes. 1.6.3.1 Format 3 Packets Format 3 packets are used for synchronization, and report supporting information. There are 4 subformats defined in the specification. ESP32-C5 only supports 3 of them. Format 3 Subformat 0 - Synchronization This packet contains all the information the decoder needs to fully identify an instruction. It is sent for the first traced instruction (unless that instruction also happens to be the first one in an exception handler), and when synchronization has been scheduled by the expiry of the synchronization timer. The payload length is 5 bytes. Table 1.6-3. Packet format 3 subformat 0 Field name Bit Width Description format 2 11 (sync): Synchronization subformat 2 00 (start): Start of tracing, or resync branch 1 Set to 0 if the address points to a branch instruction, and the branch was taken. Set to 1 if the instruction is not a branch or if the branch is not taken. privilege 1 The privilege level of the reported instruction address 31 Full instruction address. The address must be left shifted 1 bit in order to recreate the original byte address. sign_extend 3 Reserved Format 3 Subformat 1 - Exception This packet also contains all the information the decoder needs to fully identify an instruction. It is sent following an exception or interrupt, and includes the cause, the ’trap value’ (for exceptions), and the address of the trap Espressif Systems 46 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 1 RISC-V Trace Encoder (TRACE) handler or of the exception itself. The length is variable: if the interrupt field is 1, the tvalepc field is omitted and the length is 6 bytes, otherwise the length is 10 bytes. Table 1.6-4. Packet format 3 subformat 1 Field name Bit Width Description format 2 11 (sync): Synchronization subformat 2 01 (exception): Exception cause and trap handler address branch 1 Set to 0 if the address points to a branch instruction, and the branch was taken. Set to 1 if the instruction is not a branch or if the branch is not taken. privilege 1 The privilege level of the reported instruction ecause 6 Exception cause interrupt 1 Interrupt theaddr 1 When set to 1, the address field points to the trap handler address. When set to 0, the address field points to the EPC (exception program counter) for an exception at the target for an updiscon, and is undefined for other exceptions and interrupts. address 31 Full instruction address. The value of this field must be left shifted 1 bit in order to recreate the original byte address. tvalepc 32 Value from appropriate utval/stval/mtval CSR (control/status register). Omitted if the interrupt is 1 sign_extend 3 Reserved Format 3 Subformat 3 - Support This packet provides supporting information to aid the decoder. It is issued when the trace is ended, filter match is failed, or a packet is lost. The length is 2 bytes. Table 1.6-5. Packet format 3 subformat 3 Field name Bit Width Description format 2 11 (sync): Synchronization subformat 2 11 (support): Supporting information for the decoder enable 1 Indicates if the encoder is enabled encoder_mode 1 Always 0. Only supported by branch trace qual_status 2 Indicates qualification status: • 00 (no_change): No change to filter qualification • 01 (ended_rep): Qualification ended, preceding instruction sent explicitly to indicate last qualification instruction • 10 (trace lost): One or more packets lost • 11 (ended_upd): Qualification ended, preceding te_inst would have been sent anyway due to an updiscon, even if wasn’t the last qualified instruction Espressif Systems 47 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 1 RISC-V Trace Encoder (TRACE) Field name Bit Width Description ioptions 6 Indicates optional modes: • sequentially inferred jumps (Bits 5): When set to 1, the targets of sequentially inferable jumps will not be reported. (This feature is not implemented, so bit 5 should always be 0) • branch prediction (Bit 4): When set to 1, the branch prediction is enabled. (This feature is not implemented, so bit 4 should always be 0) • jump target cache (Bit 3): When set to 1, the jump target cache is enabled. (This feature is not implemented, so bit 3 should always be 0) • full address (Bit 2): – 0: delta address mode – 1: full address mode • implicit exception (Bit 1): Exclude address from format 3 subformat 1 packet if trap vector can be determined from ecause. (This feature is not implemented, so bit 1 should always be 0) • implicit return (Bit 0): When set to 1, function return addresses will not be reported. (This feature is not implemented, bit 0 should always be 0) sign_extend 2 Reserved 1.6.3.2 Format 2 Packets This packet contains only an instruction address, and is used when the address of an instruction must be reported (for example if the instruction is the target for an updiscon, or is the last instruction before exception), and there is no reported branch information. The length is variable if delta address mode is enabled, ranging from 5 bytes to 8 bytes. The address field can be 8/16/24/32 bits, inferred from the packet length. For example, if the header length is n bytes, the address bits are n − 4 bytes. A sign bit is required to extend the address field to 32 bits. Table 1.6-6. Packet format 2 Field name Bit Width Description format 2 10 (addr-only): No branch information notify 1 If the value of this bit is different from the MSB of address, it indicates that this packet is reporting an instruction that is not the target of an uninferable discontinuity because a notification was requested via trigger[2] or a filter matched. updiscon 1 If the value of this bit is different from notify, it indicates that this packet is reporting the instruction following an uninferable discontinuity and is also the instruction before an exception, privilege change or resync. zero_extend 4 Reserved Espressif Systems 48 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 1 RISC-V Trace Encoder (TRACE) Field name Bit Width Description address Variable Delta instruction address. These bits can be 8/16/24/32. 1.6.3.3 Format 1 Packets This packet includes branch information, and is used when either the branch information must be reported (for example because the branch map is full), or when the address of instruction must be reported, and there has been at least one branch since the previous packet. The packet length is variable if delta address mode is enabled, ranging from 5 bytes to 12 bytes. The address field can be 8/16/24/32 bits, inferred from the packet length. For example: • The header length is n bytes • The value of the format field is 1 • The value of the branch field is: – 0: the packet is format 1 without address – 1: branch_map is 1 bit wide, zero_ext is 6 bits wide, and address is n − 5 bits wide – 2 3: branch_map is 3 bits wide, zero_ext is 4 bits wide, and address is n − 5 bits wide – 4 7: branch_map is 7 bits wide, zero_ext is 0 bits wide, and address is n − 5 bits wide – 8 15: branch_map is 15 bits wide, zero_ext is 0 bits wide, and address is n − 6 bits wide – 16 31: branch_map is 31 bits wide, zero_ext is 0 bits wide, and address is n − 8 bits wide Format 1 - address, branch_map The length is variable. Table 1.6-7. Packet format 1 with address Field name Bit Width Description format 2 01: Includes branch information branches 5 Number of valid bits branch_map. The number of bits of branch_map is determined as follows: • 0: (cannot occur for this format) • 1: 1 bit • 2 3: 3 bits • 4 7: 7 bits • 8 15: 15 bits • 16 31: 31 bits For example if branches = 12, branch_map is 15-bit long, and the 12 LSBs are valid. branch_map Variable An array of bits indicating whether branches are taken or not. Bit 0 represents the oldest branch instruction executed. For each bit: • 0: branch taken • 1: branch not taken The field Bits is variable and determined by the branches field. Espressif Systems 49 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 1 RISC-V Trace Encoder (TRACE) Field name Bit Width Description notify 1 If the value of this bit is different from the MSB of address, it indicates that this packet is reporting an instruction that is not the target of an uninferable discontinuity because a notification was requested via trigger[2] or a filter matched. updiscon 1 If the value of this bit is different from notify, it indicates that this packet is reporting the instruction following an uninferable discontinuity and is also the instruction before an exception, privilege change or resync. zero_ext Variable The length of this field is determined by branches as follows: • 1: 6 bits • 2 3: 4 bits • 4 31: 0 bits address Variable Delta instruction address. These bits can be 8/16/24/32 Format 1 - no address, branch_map The length is 5 bytes. Table 1.6-8. Packet format 1 without address Field name Bit Width Description format 2 01: includes branch information branches 5 Number of valid bits in branch_map. The length of branch_map is 31 bits. Only 0 valid. branch_map 31 An array of bits indicating whether branches are taken or not. Bit 0 represents the oldest branch instruction executed. For each bit: • 0: branch taken • 1: branch not taken sign_extend 2 Reserved 1.7 Interrupt ESP32-C5’s TRACE (i.e., the trace encoder of HP CPU) can generate the TRACE_INTR interrupt signal that will be sent to the Interrupt Matrix. There are several internal interrupt sources from TRACE that can generate the TRACE_INTR interrupt signal. The interrupt sources from TRACE are listed in Table 1.7-1 with their trigger conditions and the resulted interrupt signal in Table 1.7-1. Table 1.7-1. TRACE’s Internal Interrupt Sources Internal Interrupt Source Trigger Condition Interrupt Signal Espressif Systems 50 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 1 RISC-V Trace Encoder (TRACE) TRACE_MEM_FULL_INTR Triggered when the packet size exceeds the capacity of the trace memory, namely when TRACE_MEM_CURRENT_ADDR_REG reaches the value of TRACE_MEM_END_ADDR_REG. If necessary, this interrupt can be enabled to notify the HP CPU for processing, such as applying for a new memory space again TRACE_INTR TRACE_FIFO_OVERFLOW_INTR Triggered when the internal FIFO overflows and one or more packets have been lost. TRACE_INTR Note: For definitions of interrupt, interrupt signal, interrupt source, and their correlations, please refer to Chapter 9 Interrupt Matrix > Section 9.2 Terminology. Each interrupt source can be configured by a common set of registers that are described in Section Interrupt Configuration Registers. The specific registers can be found in Section 1.9 Register Summary. 1.8 Programming Procedures 1.8.1 Encoder Option Configuration By default, trace packets are sent to memory with deltas address until the trace FIFO overflows or the trace memory becomes full. There are some optional configuration options that can change the trace behavior. • Full address mode – The encoder uses delta address mode by default. Users can set TRACE_FULL_ADDRESS to enable full address mode for debugging. • Restart after packet loss – Once the trace packet is lost due to FIFO overflow, the encoder will automatically stop if TRACE_RESTART_ENA is set. When the FIFO is empty, the encoder will restart to report packets. • Stall CPU while FIFO is almost full – If TRACE_STALL_ENA is set, when the FIFO is almost full, a stall request will be aserted to the CPU, and the CPU will be stalled until the request is deasserted. • Stop tracing when the CPU is halted If TRACE_HALT_ENA is set, when the CPU is halted, the encoder will output a packet to report the address of the last instruction before halting, followed by a support packet to indicate that tracing has stopped. Upon the deassertion of the halted signal, the encoder will start tracing again, commencing with a synchronization packet. • Stop tracing when the CPU is in reset Espressif Systems 51 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 1 RISC-V Trace Encoder (TRACE) The encoder will be reset separately, if TRACE_RESET_ENA is set. When the CPU is in reset, the encoder will output a packet to report the address of the last instruction before reset, followed by a support packet to indicate that tracing has stopped. Once the CPU exits from reset, the encoder will start tracing again, commencing with a synchronization packet. • Using trigger outputs from the Debug Module The debug module of the HP CPU has a trigger unit. This defines a match control register (mcontrol) containing a 4-bit action field, and reserves codes 2 4 of this field for trace use. ESP32-C5 has implemented this feature. The values of the action field are listed in Table 1.8-1. Table 1.8-1. Debug module trigger support (the action field of the mcontrol register) Value Description 2 Trace-on: start trace 3 Trace-off: end trace 4 Trace-notify: notify the encoder to report an address For details about the debug module trigger unit, please refer to Chapter 1 High-Performance CPU [to be added later]. 1.8.2 Filter Configuration The filter unit described in Section 1.5.4 can be configured as follows: 1. Select one of the following match modes: • Set TRACE_MATCH_PRIVILEGE to enable privilege match mode: – Configure TRACE_MATCH_CHOICE_PRIVILEGE to specify the privilege level. • Set TRACE_MATCH_ECAUSE to enable ecause match mode: – Configure TRACE_MATCH_CHOICE_ECAUSE to specify the ecause value • Set TRACE_MATCH_INTERRUPT to enable interrupt match mode: – Configure TRACE_MATCH_VALUE_INTERRUPT to specify interrupt level • Set TRACE_MATCH_COMP to enable comparator match mode: – Configure the primary comparator: * Configure TRACE_P_INPUT to choose the input * Configure TRACE_P_FUNCTION to select the comparator function * Configure TRACE_FILTER_P_COMPARATOR_MATCH_REG to define match value – Configure the secondary comparator if needed: * Configure TRACE_S_INPUT to choose the input * Configure TRACE_S_FUNCTION to select the comparator function * Configure TRACE_FILTER_S_COMPARATOR_MATCH_REG to define match value – Choose which comparator to match via TRACE_MATCH_MODE: Espressif Systems 52 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 1 RISC-V Trace Encoder (TRACE) * 0: only the primary comparator matches, and the secondary comparator has no effect * 1: both the primary comparator and the secondary comparator match (P &&S) * 2: neither the primary comparator nor secondary comparator match !(P &&S) * 3: start filtering when primary matches up until secondary matches If TRACE_P_NOTIFY or TRACE_S_NOTIFY is set, the comparator will report the matched address as a notification, the instructions will not be filtered. For example: – If the TRACE_MATCH_MODE is 0, and TRACE_P_NOTIFY is set, then all instructions will be traced, and the matched primary comparator will be notified. For details about notify, please refer to Section 1.8.5. – If the TRACE_MATCH_MODE is 0, and TRACE_S_NOTIFY is set, the instruction will be filtered by the primary comparator, and the instruction that matches the secondary comparator will be notified. 2. Set TRACE_FILTER_EN to enable filter unit. 1.8.3 Enable Encoder • Configure the address space for the trace memory via TRACE_MEM_START_ADDR_REG and TRACE_MEM_END_ADDR_REG. The encoder can access 0x40800000 0x4085FFFF • Update the value of TRACE_MEM_CURRENT_ADDR_REG to the value of TRACE_MEM_START_ADDR_REG by setting TRACE_MEM_CURRENT_ADDR_UPDATE • (Optional) Configure the memory writing mode via the TRACE_MEM_LOOP bit of TRACE_TRIGGER_REG – 0: Non-loop mode – 1: Loop mode (default) • Configure the synchronization mode via the TRACE_RESYNC_MODE bit of TRACE_RESYNC_PROLONGED_REG – 0: Disable the synchronization counter – 1: Invalid. No effect – 2: Synchronization counter counts by packet – 3: Synchronization counter counts by cycle • (Optional) Configures the threshold for the synchronization counter (default value is 128) via TRACE_RESYNC_PROLONGED_REG • (Optional) Enable Interrupt – Set the corresponding bit of TRACE_INTR_ENA_REG to enable the corresponding interrupt – Set the corresponding bit of TRACE_INTR_CLR_REG to clear the corresponding interrupt – Read TRACE_INTR_RAW_REG to know which interrupt occurs • (Optional) Enable automatic restart by setting the TRACE_RESTART_ENA bit of TRACE_TRIGGER_REG. This function is enabled by default Espressif Systems 53 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 1 RISC-V Trace Encoder (TRACE) • There are 2 ways to enable the trace encoder: – Setting the TRACE_TRIGGER_ON bit of TRACE_TRIGGER_REG – Through the Debug module by configuring Trace-on trigger action to start the encoder. When the trigger is matched and the action is 2, it will start the encoder. For trigger configurations, please refer to the RISC-V Debug Specification. Once the encoder is enabled, it will keep tracing the HP CPU’s instruction trace interface and writing packets to the trace memory. 1.8.4 Disable Encoder There are two ways to stop producing trace packets: 1. Set TRACE_TRIGGER_OFF of TRACE_TRIGGER_REG to end the encoder 2. Through the Debug module by configuring Trace-off trigger action to stop the encoder. When the trigger is matched and the action is 3, it will disable the encoder. For trigger configurations, please refer to the RISC-V Debug Specification. Due to the internal FIFO, the packets are not written to the memory immediately after the end of the trace. It is recommended to query the TRACE_FIFO_STATUS_REG to confirm that the data is all written to memory. Table 1.8-2. Trace Status Field Description TRACE_FIFO_EMPTY If 1 indicates that the FIFO is empty, all data have been written to memory TRACE_WORK_STATUS Encoder’s work status: • 0: idle state, the encoder is not started • 1: the encoder is normally working that output packets • 2: the encoder is not outputting packets, the CPU is halted or in reset • 3: the encoder is not outputting packets, it occurs while a packet is lost, and is waiting for FIFO empty to restart. 1.8.5 Notify Users may want to report a special address, even if it is not the target of an uninferable discontinuity. There are two ways to notify and report a special address: 1. The debug trigger unit matched, and the action is 4 2. The filter comparator matched When a notification is requested, the encoder will report a format 2 or format 1 with an address packet, determined by the branch_map. If branch_map is 0, report format 2, otherwise report format 1. The notify field shows whether the packet is reporting a notification address. If it is the target of an uninferable discontinuity, even if it is a notification, the notify field will not be asserted, otherwise the decoder cannot reconstruct the instruction stream correctly. Espressif Systems 54 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 1 RISC-V Trace Encoder (TRACE) 1.8.6 Decode Data Packets • Find the first address to decode – Read the TRACE_MEM_FULL_INTR_RAW bit of the TRACE_INTR_RAW_REG register to know if the trace memory is full * if read 0, read the trace packets from TRACE_MEM_START_ADDR_REG * if read 1, and the loop mode is enabled, then the old trace packets are overwritten. In this case, read the TRACE_MEM_CURRENT_ADDR_REG to know the last writing address, and use this address as the first address to decode • Use the decoder to decode data packets – The decoder reads all data packets starting from the first address, and reconstructs the data stream with the binary file – As mentioned in 1.6, the encoder writes 14 zero bytes to the memory partition boundary every time when 128 packets are transmitted. Given this fact, the first non-zero byte after 14 zero bytes should be the header of a new packet 1.8.7 AHB Configuration ESP32-C5 encoder supports the AHB bus. There are some optional configurations to control the transmission bandwidth of the encoder. If there are many DMA masters, users can increase the bandwidth of Trace by setting AHB burst TRACE_AHB_CONFIG_REG. • The TRACE_HBURST supports the following configurations: – 0x0: SINGLE – 0x1: INCR (length not defined) – 0x2: INCR4 – 0x4: INCR8 – Others: reserved Burst transfer means that once arbitration is successful, multiple words can be transferred continuously. For SINGLE, the length is 1; for INCR, the length is undefined; for INCR4, the length is 4; for INCR8, the length is 8. The longer the burst length, the better the bandwidth. • When configured as INCR transfer, since INCR is a burst of indeterminate length, in order to avoid Trace occupying the bus for a long time, it will end the INCR transfer after the transfer length up to TRACE_MAX_INCR, and restart bus arbitration. This is the configuration used to adjust the bandwidth. When the bandwidth is sufficient, it’s not required to do the configuration, and users can use the default configuration. Espressif Systems 55 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 1 RISC-V Trace Encoder (TRACE) 1.8.8 Software Retention The TRACE_WORK_STATUS represents the state of the encoder. When the encoder is not in the IDLE state, it must backup and restore the configuration when the chip enters sleep. Espressif Systems 56 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 1 RISC-V Trace Encoder (TRACE) 1.9 Register Summary The addresses in this section are relative to RISC-V Trace Encoder base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Memory configuration registers TRACE_MEM_START_ADDR_REG Memory start address 0x0000 R/W TRACE_MEM_END_ADDR_REG Memory end address 0x0004 R/W TRACE_MEM_CURRENT_ADDR_REG Memory current address 0x0008 RO TRACE_MEM_ADDR_UPDATE_REG Memory address update 0x000C WT Trace FIFO status register TRACE_FIFO_STATUS_REG FIFO status register 0x0010 RO Interrupt registers TRACE_INTR_ENA_REG Interrupt enable register 0x0014 R/W TRACE_INTR_RAW_REG Interrupt raw status register 0x0018 RO TRACE_INTR_CLR_REG Interrupt clear register 0x001C WT Trace configuration registers TRACE_TRIGGER_REG Trace trigger register 0x0020 varies TRACE_CONFIG_REG Trace configuration register 0x0024 R/W TRACE_FILTER_CONTROL_REG Filter control register 0x0028 R/W TRACE_FILTER_MATCH_CONTROL_REG Filter match control register 0x002C R/W TRACE_FILTER_COMPARATOR_CONTROL_REG Filter comparator match control register 0x0030 R/W TRACE_FILTER_P_COMPARATOR_MATCH_REG Primary comparator match value regis- ter 0x0034 R/W TRACE_FILTER_S_COMPARATOR_MATCH_REG Secondary comparator match value reg- ister 0x0038 R/W TRACE_RESYNC_PROLONGED_REG Resynchronization configuration register 0x003C R/W TRACE_AHB_CONFIG_REG AHB configuration register 0x0040 R/W Clock gate control and configuration register TRACE_CLOCK_GATE_REG Clock gating control register 0x0044 R/W Version register TRACE_DATE_REG Version control register 0x03FC R/W Espressif Systems 57 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 1 RISC-V Trace Encoder (TRACE) 1.10 Registers The addresses in this section are relative to RISC-V Trace Encoder base address provided in Table 4.3-2 in Chapter 4 System and Memory. For how to program reserved fields, please refer to Section Programming Reserved Register Field. Register 1.1. TRACE_MEM_START_ADDR_REG (0x0000) TRACE_MEM_START_ADDR 0x000000 31 0 Reset TRACE_MEM_START_ADDR Configures the start address of the trace memory. (R/W) Register 1.2. TRACE_MEM_END_ADDR_REG (0x0004) TRACE_MEM_END_ADDR 0xffffffff 31 0 Reset TRACE_MEM_END_ADDR Configures the end address of the trace memory. (R/W) Register 1.3. TRACE_MEM_CURRENT_ADDR_REG (0x0008) TRACE_MEM_CURRENT_ADDR 0x000000 31 0 Reset TRACE_MEM_CURRENT_ADDR Represents the current memory address for writing. (RO) Espressif Systems 58 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 1 RISC-V Trace Encoder (TRACE) Register 1.4. TRACE_MEM_ADDR_UPDATE_REG (0x000C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 TRACE_MEM_CURRENT_ADDR_UPDATE 0 0 Reset TRACE_MEM_CURRENT_ADDR_UPDATE Configures whether to update the value of TRACE_MEM_CURRENT_ADDR to TRACE_MEM_START_ADDR. 0: Not update 1: Update (WT) Register 1.5. TRACE_FIFO_STATUS_REG (0x0010) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 TRACE_WORK_STATUS 0 2 1 TRACE_FIFO_EMPTY 1 0 Reset TRACE_FIFO_EMPTY Represents whether the FIFO is empty. 1: Empty 0: Not empty (RO) TRACE_WORK_STATUS Represents the state of the encoder: 0: Idle state 1: Working state 2: Wait state because the hart is halted or in reset 3: Lost state (RO) Espressif Systems 59 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 1 RISC-V Trace Encoder (TRACE) Register 1.6. TRACE_INTR_ENA_REG (0x0014) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 2 TRACE_MEM_FULL_INTR_ENA 0 1 TRACE_FIFO_OVERFLOW_INTR_ENA 0 0 Reset TRACE_FIFO_OVERFLOW_INTR_ENA Write 1 to enable TRACE_FIFO_OVERFLOW_INTR. (R/W) TRACE_MEM_FULL_INTR_ENA Write 1 to enable TRACE_MEM_FULL_INTR. (R/W) Register 1.7. TRACE_INTR_RAW_REG (0x0018) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 2 TRACE_MEM_FULL_INTR_RAW 0 1 TRACE_FIFO_OVERFLOW_INTR_RAW 0 0 Reset TRACE_FIFO_OVERFLOW_INTR_RAW The raw interrupt status of TRACE_FIFO_OVERFLOW_INTR. (RO) TRACE_MEM_FULL_INTR_RAW The raw interrupt status of TRACE_MEM_FULL_INTR. (RO) Register 1.8. TRACE_INTR_CLR_REG (0x001C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 2 TRACE_MEM_FULL_INTR_CLR 0 1 TRACE_FIFO_OVERFLOW_INTR_CLR 0 0 Reset TRACE_FIFO_OVERFLOW_INTR_CLR Write 1 to clear TRACE_FIFO_OVERFLOW_INTR. (WT) TRACE_MEM_FULL_INTR_CLR Write 1 to clear TRACE_MEM_FULL_INTR. (WT) Espressif Systems 60 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 1 RISC-V Trace Encoder (TRACE) Register 1.9. TRACE_TRIGGER_REG (0x0020) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 4 TRACE_RESTART_ENA 1 3 TRACE_MEM_LOOP 1 2 TRACE_TRIGGER_OFF 0 1 TRACE_TRIGGER_ON 0 0 Reset TRACE_TRIGGER_ON Configures whether to enable the encoder. 0: Invalid 1: Enable (WT) TRACE_TRIGGER_OFF Configures whether to disable the encoder. 0: Invalid 1: Disable (WT) TRACE_MEM_LOOP Configures the memory writing mode. 0: Non-loop mode 1: Loop mode (R/W) TRACE_RESTART_ENA Configures whether to enable automatic restart. 0: Disable 1: Enable (R/W) Espressif Systems 61 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 1 RISC-V Trace Encoder (TRACE) Register 1.10. TRACE_CONFIG_REG (0x0024) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 7 TRACE_FULL_ADDRESS 0 4 TRACE_STALL_ENA 0 3 TRACE_HALT_ENA 0 2 TRACE_RESET_ENA 0 1 TRACE_DM_TRIGGER_ENA 0 0 Reset TRACE_DM_TRIGGER_ENA Configure whether to enable the trigger signal. 0: Disable 1: Enable (R/W) TRACE_RESET_ENA Configures whether to enable the reset signal. 0: Disable 1: Enable (R/W) TRACE_HALT_ENA Configures whether to enable the halted signal. 0: Disable 1: Enable (R/W) TRACE_STALL_ENA Configures whether to enable the stall signal. 0: Disable 1: Enable (R/W) TRACE_FULL_ADDRESS Configure the address mode. 0: Delta address mode 1: Full address mode Espressif Systems 62 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 1 RISC-V Trace Encoder (TRACE) Register 1.11. TRACE_FILTER_CONTROL_REG (0x0028) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 5 TRACE_MATCH_INTERRUPT 0 4 TRACE_MATCH_ECAUSE 0 3 TRACE_MATCH_PRIVILEGE 0 2 TRACE_MATCH_COMP 0 1 TRACE_FILTER_EN 0 0 Reset TRACE_FILTER_EN Configure whether to enable filtering. 0: Disable 1: Enable (R/W) TRACE_MATCH_COMP Configures whether to enable the comparator match mode. 0: Disable 1: Enable (R/W) TRACE_MATCH_PRIVILEGE Configures whether to enable the privilege match mode. 0: Disable 1: Enable (R/W) TRACE_MATCH_ECAUSE Configures whether to enable the ecause match mode. 0: Disable 1: Enable (R/W) TRACE_MATCH_INTERRUPT Configures whether to enable the interrupt match mode. 0: Disable 1: Enable (R/W) Espressif Systems 63 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 1 RISC-V Trace Encoder (TRACE) Register 1.12. TRACE_FILTER_MATCH_CONTROL_REG (0x002C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 TRACE_MATCH_CHOICE_ECAUSE 0 7 2 TRACE_MATCH_VALUE_INTERRUPT 0 1 TRACE_MATCH_CHOICE_PRIVILEGE 0 0 Reset TRACE_MATCH_CHOICE_PRIVILEGE Configures the privilege level for matching. 0: User mode 1: Machine mode (R/W) TRACE_MATCH_VALUE_INTERRUPT Configures the interrupt level for matching. Valid only when TRACE_MATCH_INTERRUPT is set. 0: itype=1 1: itype=2 (R/W) TRACE_MATCH_CHOICE_ECAUSE Configures the ecause code for matching. (R/W) Espressif Systems 64 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 1 RISC-V Trace Encoder (TRACE) Register 1.13. TRACE_FILTER_COMPARATOR_CONTROL_REG (0x0030) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 18 TRACE_MATCH_MODE 0 17 16 (reserved) 0 0 15 14 TRACE_S_NOTIFY 0 13 TRACE_S_FUNCTION 0 12 10 (reserved) 0 9 TRACE_S_INPUT 0 8 (reserved) 0 0 7 6 TRACE_P_NOTIFY 0 5 TRACE_P_FUNCTION 0 4 2 (reserved) 0 1 TRACE_P_INPUT 0 0 Reset TRACE_P_INPUT Configures the input of the primary comparator for matching. 0: iaddr 1: tval (R/W) TRACE_P_FUNCTION Configures the function for the primary comparator. 0: Equal 1: Not equal 2: Less than 3: Less than or equal 4: Greater than 5: Greater than or equal Others: Always match (R/W) TRACE_P_NOTIFY Configures whether to explicitly report an instruction address matched against the primary comparator. 0: Not report 1: Report (R/W) TRACE_S_INPUT Configures the input of the secondary comparator for matching. 0: iaddr 1: tval (R/W) TRACE_S_FUNCTION Configures the function of for secondary comparator. 0: Equal 1: Not equal 2: Less than 3: Less than or equal 4: Greater than 5: Greater than or equal 6: The second comparator value is the masked value of the primary comparator Others: Always match (R/W) Continued on the next page... Espressif Systems 65 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 1 RISC-V Trace Encoder (TRACE) Register 1.13. TRACE_FILTER_COMPARATOR_CONTROL_REG (0x0030) Continued from the previous page... TRACE_S_NOTIFY Configures whether to explicitly report an instruction address matched against the secondary comparator. 0: Not report 1: Report (R/W) TRACE_MATCH_MODE Configures the comparator match condition. 0: Only the primary comparator matches 1: Both primary and secondary comparators match (P&&S) 2: Neither primary nor secondary comparator match (!P&&S) 3: Start filtering when the primary comparator matches and stop filtering when the secondary comparator matches (R/W) Register 1.14. TRACE_FILTER_P_COMPARATOR_MATCH_REG (0x0034) TRACE_P_MATCH 0 31 0 Reset TRACE_P_MATCH Configures the match value for the primary comparator. (R/W) Register 1.15. TRACE_FILTER_S_COMPARATOR_MATCH_REG (0x0038) TRACE_S_MATCH 0 31 0 Reset TRACE_S_MATCH Configures the match value for the secondary comparator. (R/W) Espressif Systems 66 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 1 RISC-V Trace Encoder (TRACE) Register 1.16. TRACE_RESYNC_PROLONGED_REG (0x003C) (reserved) 0 0 0 0 0 0 31 26 TRACE_RESYNC_MODE 0 25 24 TRACE_RESYNC_PROLONGED 128 23 0 Reset TRACE_RESYNC_PROLONGED Configures the threshold for the synchronization counter. (R/W) TRACE_RESYNC_MODE Configures the synchronization mode. 0: Disable the synchronization counter 1: Invalid 2: Synchronization counter counts by packet 3: Synchronization counter counts by cycle (R/W) Register 1.17. TRACE_AHB_CONFIG_REG (0x0040) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 6 TRACE_MAX_INCR 0x0 5 3 TRACE_HBURST 0x0 2 0 Reset TRACE_HBURST Configures the AHB burst mode. 0: SINGLE 1: INCR (length not defined) 2: INCR4 4: INCR8 Others: Invalid (R/W) TRACE_MAX_INCR Configures the maximum burst length for INCR mode. (R/W) Espressif Systems 67 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 1 RISC-V Trace Encoder (TRACE) Register 1.18. TRACE_CLOCK_GATE_REG (0x0044) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 TRACE_CLK_EN 1 0 Reset TRACE_CLK_EN Configures register clock gating. 0: Support clock only when the application writes registers to save power 1: Always force the clock on for registers This bit doesn’t affect register access (R/W) Register 1.19. TRACE_DATE_REG (0x03FC) (reserved) 0 0 0 0 31 28 TRACE_DATE 0x2211300 27 0 Reset TRACE_DATE Version control register. (R/W) Espressif Systems 68 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 2 Low-Power CPU Chapter 2 Low-Power CPU The ESP32-C5 Low-Power CPU (LP CPU) is a 32-bit processor based upon RISC-V ISA comprising integer (I), multiplication/division (M), atomic (A), and compressed (C) standard extensions. It features ultra-low power consumption and has a 2-stage, in-order, and scalar pipeline. The LP CPU core complex has an interrupt controller (INTC), a debug module (DM), and system bus (SYS BUS) interfaces for memory and peripheral access. The LP CPU is in sleep mode by default (see Section 2.9). It can stay powered on when the chip enters Deep-sleep mode (see Chapter 2 Low-power Management [to be added later] for details) and can access most peripherals and memories (see Chapter 4 System and Memory for details). It has two application scenarios: • Power insensitive scenario: When the High-Performance CPU (HP CPU) is active, the LP CPU can assist the HP CPU with some speed- and efficiency-insensitive controls and computations. • Power sensitive scenario: When the HP CPU is in the power-down state to save power, the LP CPU can be woken up to handle some external wake-up events. Figure 2.0-1 shows the resources accessible to the HP CPU and the LP CPU. HP CPU HP Peripherals SYS Memory LP Peripherals LP RAM LP CPU HP Power Domain LP Power Domain Figure 2.0-1. LP CPU Overview In the figure above, the HP Power Domain and LP Power Domain can be powered on and off independently. When one domain is powered down, the CPU of the other domain cannot access the resources of that domain. In other words, only when the domain is powered on can its resources be accessed. For more information about power, please refer to the chapter 2 Low-power Management [to be added later]. 2.1 Features The LP CPU has the following features: • Operating clock frequency up to 20 MHz • One vector interrupt input Espressif Systems 69 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 2 Low-Power CPU • Debug module compliant with RISC-V External Debug Support Version 0.13 with external debugger support over an industry-standard JTAG/USB port • Hardware trigger compliant with RISC-V External Debug Support Version 0.13 with up to 2 breakpoints/watchpoints • 32-bit AHB system bus for peripheral and memory access • Core performance metric events • Able to wake up the HP CPU and send an interrupt to it • Access to HP memory and LP memory • Access to the entire peripheral address space 2.2 Configuration and Status Registers (CSRs) 2.2.1 Register Summary Below is a list of CSRs available to the CPU. Except for the custom performance counter CSRs, all the implemented CSRs follow the standard mapping of bit fields as described in the RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Version 1.10. It must be noted that even among the standard CSRs, not all bit fields have been implemented, limited by the subset of features implemented in the CPU. Refer to the next section for a detailed description of the subset of fields implemented under each of these CSRs. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Machine Information CSR mhartid Machine Hart ID 0xF14 RO Machine Trap Setup CSRs mstatus Machine Mode Status 0x300 R/W misa 1 Machine ISA 0x301 R/W mie Machine Interrupt Enable 0x304 R/W mtvec 2 Machine Trap Vector 0x305 R/W Machine Trap Handling CSRs mscratch Machine Scratch 0x340 R/W mepc Machine Trap Program Counter 0x341 R/W mcause 3 Machine Trap Cause 0x342 R/W mtval Machine Trap Value 0x343 R/W mip Machine Interrupt Pending 0x344 R/W Trigger Module CSRs (shared with Debug Mode) tselect Trigger Select Register 0x7A0 R/W tdata1 Trigger Abstract Data 1 0x7A1 R/W tdata2 Trigger Abstract Data 2 0x7A2 R/W 1 Although misa is specified as having both read and write access (R/W), its fields are hardwired and thus write has no effect. This is what would be termed WARL (Write Any Read Legal) in RISC-V terminology. 2 mtvec only provides configuration for trap handling in vectored mode with the base address aligned to 256 bytes. 3 External interrupt IDs reflected in mcause include even those IDs which have been reserved by RISC-V standard for core internal sources. Espressif Systems 70 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 2 Low-Power CPU Name Description Address Access Debug Mode CSRs dcsr Debug Control and Status 0x7B0 R/W dpc Debug PC 0x7B1 R/W dscratch0 Debug Scratch Register 0 0x7B2 R/W dscratch1 Debug Scratch Register 1 0x7B3 R/W Machine Counter/Timer CSRs mcycle Machine Clock Cycle Counter 0xB00 R/W minstret Machine Retired Instruction Counter 0xB02 R/W mhpmcountern(n:3-12) Machine Performance Monitor Counter 0xB00+n R/W mcycleh The higher 32 bits of mcycle 0xB80 R/W minstreth The higher 32 bits of minstret 0xB82 R/W mhpmcounternh(n:3-12) The higher 32 bits of mhpmcountern(n:3-12) 0xB80+n R/W Machine Counter Setup CSR mcountinhibit Machine Counter Control 0x320 R/W Note that if write, set, or clear operation is attempted on any of the read-only (RO) CSRs indicated in the above table, the CPU will generate an illegal instruction exception. 2.2.2 Registers For how to program reserved fields, please refer to Section Programming Reserved Register Field. Register 2.1. mhartid (0xF14) MHARTID 0x00000000 31 0 Reset MHARTID Represents Hart ID. The LP CPU hart ID is 0. (RO) Espressif Systems 71 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 2 Low-Power CPU Register 2.2. mstatus (0x300) (reserved) 0x000 31 22 reserved 0 21 (reserved) 0x00 20 13 MPP 0x0 12 11 (reserved) 0x0 10 8 MPIE 0 7 (reserved) 0x0 6 4 MIE 0 3 (reserved) 0x0 2 0 Reset MIE Write 1 to enable the global machine mode interrupt. (R/W) MPIE Write 1 to enable the machine previous interrupt (before trap). (R/W) MPP Configures machine previous privilege mode (before trap). 0x3: Machine mode Other values: Invalid Note: Only the lower bit is writable. Any write to the higher bit is ignored as it is directly tied to the lower bit. (R/W) Espressif Systems 72 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 2 Low-Power CPU Register 2.3. misa (0x301) MXL 0x1 31 30 (reserved) 0x0 29 26 Z 0 25 Y 0 24 X 0 23 W 0 22 V 0 21 U 0 20 T 0 19 S 0 18 R 0 17 Q 0 16 P 0 15 O 0 14 N 0 13 M 1 12 L 0 11 K 0 10 J 0 9 I 1 8 H 0 7 G 0 6 F 0 5 E 0 4 D 0 3 C 1 2 B 0 1 A 1 0 Reset MXL Machine XLEN = 1 (32-bit). (RO) Z Reserved = 0. (RO) Y Reserved = 0. (RO) X Non-standard extensions present = 0. (RO) W Reserved = 0. (RO) V Reserved = 0. (RO) U User mode implemented = 0. (RO) T Reserved = 0. (RO) S Supervisor mode implemented = 0. (RO) R Reserved = 0. (RO) Q Quad-precision floating-point extension = 0. (RO) P Reserved = 0. (RO) O Reserved = 0. (RO) N User-level interrupts supported = 0. (RO) M Integer Multiply/Divide extension = 1. (RO) L Reserved = 0. (RO) K Reserved = 0. (RO) J Reserved = 0. (RO) I RV32I base ISA = 1. (RO) H Hypervisor extension = 0. (RO) G Additional standard extensions present = 0. (RO) F Single-precision floating-point extension = 0. (RO) E RV32E base ISA = 0. (RO) D Double-precision floating-point extension = 0. (RO) C Compressed Extension = 1. (RO) B Reserved = 0. (RO) A Atomic Standard Extension = 1. (RO) Espressif Systems 73 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 2 Low-Power CPU Register 2.4. mie (0x304) (reserved) 0x0 31 IE 0x0 30 (reserved) 0x0 29 0 Reset IE Write 1 to enable the interrupt. (R/W) Register 2.5. mtvec (0x305) BASE 0x000000 31 8 (reserved) 0x00 7 2 MODE 0x1 1 0 Reset MODE Represents whether machine mode interrupts are vectored. Only vectored mode 0x1 is avail- able. (RO) BASE Configures the higher 24 bits of trap vector base address aligned to 256 bytes. (R/W) Register 2.6. mscratch (0x340) MSCRATCH 0x00000000 31 0 Reset MSCRATCH Contains machine scratch information for custom use. (R/W) Register 2.7. mepc (0x341) MEPC 0x00000000 31 0 Reset MEPC Configures the machine trap/exception program counter. This is automatically updated with address of the instruction which was about to be executed while CPU encountered the most recent trap. (R/W) Espressif Systems 74 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 2 Low-Power CPU Register 2.8. mcause (0x342) Interrupt Flag 0 31 (reserved) 0x0000000 30 5 Exception Code 0x00 4 0 Reset Exception Code This field is automatically updated with unique ID of the most recent exception or interrupt due to which CPU entered trap. Possible exception IDs are: 0x2: Illegal instruction 0x3: Hardware breakpoint/watchpoint or EBREAK 0x6: Misaligned atomic instructions Note: Exception ID 0x0 (instruction access misaligned) is not present because CPU always masks the lowest bit of the address during instruction fetch. (R/W) Interrupt Flag This flag is automatically updated when CPU enters trap. If this is found to be set, it indicates that the latest trap occurred due to an interrupt. For exceptions it remains unset. (R/W) Register 2.9. mtval (0x343) MTVAL 0x00000000 31 0 Reset MTVAL Configures machine trap value. This is automatically updated with an exception dependent data which may be useful for handling that exception. Data is to be interpreted depending upon exception IDs: 0x1: Faulting address of instruction 0x2: Faulting instruction opcode 0x5: Faulting data address of load operation 0x7: Faulting data address of store operation Note: The value of this register is not valid for other exception IDs and interrupts. (R/W) Espressif Systems 75 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 2 Low-Power CPU Register 2.10. mip (0x344) (reserved) 0x0 31 IP 0x0 30 (reserved) 0x0 29 0 Reset IP Configures the pending status of the interrupt. 0: Not pending 1: Pending (R/W) Register 2.11. mcycle (0xB00) mcycle 0x0 31 0 Reset MCYCLE Configures the lower 32 bits of the clock cycle counter. (R/W) Register 2.12. minstret (0xB02) minstret 0x0 31 0 Reset MINSTRET Configures the lower 32 bits of the instruction counter. (R/W) Register 2.13. mhpmcountern(n: 3-12) (0xB00+n) mhpmcountern 0x0 31 0 Reset MHPMCOUNTERn Configures the lower 32 bits of the performance counter n. (R/W) Espressif Systems 76 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 2 Low-Power CPU Register 2.14. mcycleh (0xB80) mcycleh 0x0 31 0 Reset MCYCLEH Configures the higher 32 bits of the clock cycle counter. (R/W) Register 2.15. minstreth (0xB82) minstreth 0x0 31 0 Reset MINSTRETH Configures the higher 32 bits of the instruction counter. (R/W) Register 2.16. mhpmcountern(n: 3-12)h (0xB80+n) mhpmcounternh 0x0 31 0 Reset MHPMCOUNTERnh Configures the higher 32 bits of the performance counter n. (R/W) Espressif Systems 77 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 2 Low-Power CPU Register 2.17. mcouninhibit (0x320) HPM 0x0 31 3 IR 0x0 2 (reserved) 0x0 1 CY 0x0 0 Reset CY Configure whether the clock cycle counter increments. 0: The counter does not count 1: The counter increments (R/W) IR Configure whether the instruction counter increments. 0: The counter does not count 1: The counter increments (R/W) HPM Configures whether the performance counter n(n:3-12) increments. 0: The counter does not count 1: The counter increments (R/W) 2.3 Interrupts and Exceptions The LP CPU handles interrupts and exceptions according to RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Version 1.10. After entering an interrupt/exception handler, the CPU: • Saves the current program counter (PC) value to the mepc CSR • Copies the state of MIE of mstatus to MPIE of mstatus • Saves the current privileged mode to MPP of mstatus • Clears MIE of mstatus • Toggles the privileged mode to machine mode (M mode) • Jumps to the handler address – For exceptions, the handler address is the base address of the vector table in the mtvec CSR. – For interrupts, the handler address is mtvec + 4 ∗ 30. • After the mret instruction is executed, the core jumps to the PC saved in the mepc CSR and restores the value of MPIE of mstatus to MIE of mstatus and the privileged mode to that configured by MPP. When the core starts up, the base address of the vector table is initialized to the boot address 0x50000000. After startup, the base address can be changed by writing to the mtvec CSR. For more information about CSRs, see Section 2.2.1. The core fetches instructions from address 0x50000080 after reset. Espressif Systems 78 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 2 Low-Power CPU 2.3.1 Interrupts The ESP32-C5 LP CPU supports only one interrupt entry, to which all interrupt events jump. The LP CPU supports the following peripheral interrupt sources: • Power Management Unit (PMU) • Low-Power Timer (RTC_TIMER) • Low-Power UART (LP_UART) • Low-Power I2C (LP_I2C) • Low-Power IO MUX (LP IO MUX) For more information on those peripheral interrupts, please refer to the corresponding chapter. 2.3.2 Interrupt Handling By default, interrupts are disabled globally because the MIE bit in mstatus has a reset value of 0. Software must set this bit to enable global interrupts. 1. Enable interrupts • To enable interrupts globally, set the MIE bit of mstatus. • To enable Interrupt 30, set the 30th bit of mie CSR. 2. After interrupts are enabled, the LP CPU can respond to interrupts. It also needs to configure interrupts of the peripherals so that they can send an interrupt signal to the LP CPU. 3. After the interrupt is triggered, the LP CPU jumps to mtvec + 4 ∗ 30. 4. After enterring the interrupt handler, users need to read LPPERI_INTERRUPT_SOURCE_REG to get the peripheral that triggered the interrupt and process the interrupt. Note that if the interrupts are triggered by multiple peripherals, the CPU will process them one by one in sequence until none is left. If not all interrupts are processed, the CPU will enter the interrupt handler again. 5. To clear interrupts, just clear the interrupt signal of the peripheral. 2.3.3 Exceptions The LP CPU supports the RISC-V standard exceptions and can trigger the following exceptions: Table 2.3-1. LP CPU Exception Causes Exception ID Description 2 Illegal instructions 3 Breakpoints (EBREAK) 6 Misaligned atomic instructions Espressif Systems 79 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 2 Low-Power CPU 2.4 Debugging This section describes how to debug and test the LP CPU. Debug support is provided through standard JTAG pins and complies with RISC-V External Debug Support Version 0.13. For ESP32-C5 system debugging overview, please refer to Chapter 1 High-Performance CPU [to be added later] > Figure 3. The user interacts with the Debug Host (e.g., laptop), which is running a debugger (e.g., gdb). The debugger communicates with a Debug Translator (e.g., OpenOCD, which may include a hardware driver) to communicate with Debug Transport Hardware (e.g., ESP-Prog adapter). The Debug Transport Hardware connects the Debug Host to the CPU’s Debug Transport Module (DTM) through a standard JTAG interface. The DTM provides access to the debug module (DM) using the Debug Module Interface (DMI). ESP32-C5 features two DTMs interconnected in a daisy-chain configuration. Specifically, TAP0 connects to the HP CPU, and TAP1 is dedicated to the LP CPU. The HP DM can debug the HP CPU and the LP DM the LP CPU. The LP CPU implements four registers for core debugging: dcsr, dpc, dscratch0, and dscratch1. All of those registers can only be accessed from debug mode. If software attempts to access them when the LP CPU is not in debug mode, an illegal instruction exception will be triggered. 2.4.1 Features The Low-Power CPU has the following debugging features: • Provides necessary information about the implementation to the debugger. • Allows the CPU core to be halted and resumed. • CPU core registers (including CSRs) can be read/written by the debugger. • CPU core can be reset through the debugger. • CPU can be halted on software breakpoint (planted breakpoint instruction). • Hardware single-stepping. • Two hardware triggers (which can be used as breakpoints/watchpoints). See Section 2.5 for details. 2.4.2 Functional Description The debugging mechanism adheres to the specification RISC-V External Debug Support Version 0.13. For a detailed description of the debugging features, refer to the specification. According to the specification, a hart can be in the following states: nonexistent, unavail, running, and halted. By default, the LP CPU is in the unavail state. To connect the LP CPU for debugging, users need to clear the state by configuring the LPPERI_CPU_REG register. 2.4.3 Register Summary The following table lists the debug CSRs supported for the LP CPU. The abbreviations given in Column Access are explained in Section Access Types for Registers. Espressif Systems 80 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 2 Low-Power CPU Name Description Address Access dcsr Debug Control and Status 0x7B0 R/W dpc Debug PC 0x7B1 R/W dscratch0 Debug Scratch Register 0 0x7B2 R/W dscratch1 Debug Scratch Register 1 0x7B3 R/W All debug module registers are implemented in accordance with the specification RISC-V External Debug Support Version 0.13. For more information, refer to the specification. 2.4.4 Registers The following is a detailed description of the debug CSR supported by the LP CPU. For how to program reserved fields, please refer to Section Programming Reserved Register Field. Espressif Systems 81 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 2 Low-Power CPU Register 2.18. dcsr (0x7B0) xdebugver 0 1 0 0 31 28 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 27 16 ebreakm 0 15 (reserved) 0 0 14 13 ebreaku 0 12 (reserved) 0 0 0 11 9 cause 0 0 0 8 6 (reserved) 0 0 0 5 3 step 0 2 prv 1 1 1 0 Reset xdebugver Represents the debug version. 4: External debug support exists (RO) ebreakm Configures execution of the EBREAK instruction in machine mode. 0: Trigger an exception with mcause = 3 1: Enter debug mode (R/W) ebreaku Configures execution of the EBREAK instruction in user mode. 0: Trigger an exception with mcause = 3 as described in privileged mode 1: Enter debug mode (R/W) cause Represents the reason why debug mode was entered. When there are multiple reasons to enter debug mode in a single cycle, the cause with the highest priority number is the one written. 1: An EBREAK instruction was executed. (priority 3) 2: The Trigger Module caused a halt. (priority 4) 3: haltreq was set. (priority 2) 4: The CPU core single stepped because step was set. (priority 1) Other values: Reserved for future use (RO) step When set and not in Debug Mode, the core will only execute a single instruction and then enter Debug Mode. If the instruction does not complete due to an exception, the core will immediately enter Debug Mode before executing the trap handler, with appropriate exception registers set. Setting this bit does not mask interrupts. This is a deviation from the RISC-V External Debug Support Specification Version 0.13. (R/W) prv Contains the privilege level the core is operating in when debug mode is entered. A debugger can change this value to change the core’s privilege level when exiting debug mode. Only 0x3 (machine mode) and 0x0 (user mode) are supported. (RO) Espressif Systems 82 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 2 Low-Power CPU Register 2.19. dpc (0x7B1) dpc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 0 Reset dpc Upon entry to debug mode, dpc is written with the address of the next instruction that will be executed. When resuming, the CPU core’s PC is updated to the address stored in dpc. In debug mode, dpc can be modified. This field can be accessed in debug mode. (R/W) Register 2.20. dscratch0 (0x7B2) dscratch0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 0 Reset dscratch0 Used by the debug module internally. (R/W) Register 2.21. dscratch1 (0x7B3) dscratch1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 0 Reset dscratch1 Used by the debug module internally.(R/W) 2.5 Hardware Trigger 2.5.1 Features Hardware Trigger module provides breakpoint and watchpoint capability for debugging. It has the following features: • Two independent trigger units • Configurable unit to match the address of the program counter • Able to halt execution and transfer control to the debugger 2.5.2 Functional Description The hardware trigger module provides three CSRs. See Section 2.5.4 for details. Among these, tdata1 and tdata2 are abstract CSRs, which means they are shadow registers for accessing internal registers in the trigger units, one at a time. Espressif Systems 83 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 2 Low-Power CPU To select a specific trigger unit, the corresponding number (0-1) needs to be written to the tselect CSR. When a valid value is written, the abstract CSRs, tdata1 and tdata2, automatically match the internal registers of the trigger unit. Each trigger unit has two internal registers, namely mcontrol and maddress, which are mapped to tdata1 and tdata2, respectively. Writing a value more than 1 to tselect will set tselect to 1. Since software or debugger may need to know the type of the selected trigger to correctly interpret tdata1 and tdata2, the 4-bit field (31-28) of tdata1 encodes the type of the selected trigger. This type field is read-only and always provides a value of 0x2 for every trigger, which stands for support for address and data matching. Hence, it is inferred that tdata1 and tdata2 are to be interpreted as fields of mcontrol and maddress, respectively. The specification RISC-V External Debug Support Version 0.13 provides information on other possible values, but the trigger module only supports the 0x2 type. Once a trigger unit has been chosen by writing its index to tselect, it will become possible to configure it by setting the appropriate bits in mcontrol CSR (tdata1) and writing the target address to maddress CSR (tdata2). 2.5.3 Trigger Execution Flow When a hart is halted and enters debug mode due to the firing of a trigger (action = 1): • dpc is set to the current PC in the decoding phase • The cause field in dcsr is set to 2, which means halt due to trigger 2.5.4 Register Summary Below is a list of Trigger Module CSRs supported by the CPU. These are only accessible from machine mode. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access tselect Trigger Select Register 0x7A0 R/W tdata1 Trigger Abstract Data 1 0x7A1 R/W mcontrol tdata1 Shadow Register 0x7A1 R/W tdata2 Trigger Abstract Data 2 0x7A2 R/W 2.5.5 Registers For how to program reserved fields, please refer to Section Programming Reserved Register Field. Register 2.22. tselect (0x7A0) tselect 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 0 Reset tselect Configures the index of the selected trigger unit. (R/W) Espressif Systems 84 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 2 Low-Power CPU Register 2.23. tdata1 (0x7A1) type 0 0 1 0 31 28 dmode 1 27 data 0 x 1 0 4 0 26 0 Reset type Represents the trigger type. This field is reserved since only match type (0x2) triggers are sup- ported. (RO) dmode This is set to 1 if a trigger is being used by the debugger. This field is reserved since it is only supported in debug mode. (RO) data Configures the abstract tdata1 content. This will always be interpreted as fields of mcontrol since only match type (0x2) triggers are supported. (R/W) Register 2.24. tdata2 (0x7A2) tdata2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 0 Reset tdata2 Configures the abstract tdata2 content. This will always be interpreted as maddress since only match type (0x2) triggers are supported. (R/W) Espressif Systems 85 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 2 Low-Power CPU Register 2.25. mcontrol (0x7A1) (reserved) 0x2 31 28 dmode 0 27 maskmax 0x0 26 21 hit 0 20 select 0 19 timing 0 18 sizelo 0 17 16 action 0001 15 12 chain 0 11 match 0 10 7 m 0 6 (reserved) 0 5 s 0 4 u 0 3 execute 0 2 store 0 1 load 0 0 Reset dmode Same as dmode in tdata1. (RO) maskmax Represents the maximum NAPOT range. 0: A byte. Only exact match is supported. Other values: Not supported. (RO) hit Not implemented in hardware. This field remains 0. (RO) select Configures to select between an address match or a data match. 0: Perform a match on the virtual address 1: Perform a match on the data value loaded or stored, or the instruction executed Note: Only address match is implemented. This field remains 0. (RO) timing Configures when the trigger will take action. 0: Take action before the instruction is executed 1: Take action after the instruction is executed Note: The field remains 0. (RO) sizelo Only match of any size is supported. This field remains 0. (RO) action Configure action of the selected trigger after it is triggered. 0x0: Cause a breakpoint exception 0x1: Enter debug mode (Valid only when dmode = 1) Note: Only entering debug mode is supported. This field remains 1. (RO) CHAIN Not implemented in hardware. This field remains 0. (RO) match Configures the trigger to perform the matching operation of the lower data/instruction address. 0x0: Exact match. Namely, the address corresponding to a certain byte during the access must exactly match the value of maddress. 0x1: NAPOT match. Namely, at least one byte during the access is in the NAPOT region specified in maddress. Note: Only exact byte match is supported. This field remains 0. (R/W) m Set this field to make the selected trigger operate in machine mode. (RO) s Set this field to make the selected trigger operate in supervisor mode. Operation in supervisor mode is not supported. This field is always 0. (RO) Continued on the next page... Espressif Systems 86 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 2 Low-Power CPU Register 2.25. mcontrol (0x7A1) Continued from the previous page... u Set this field to make the selected trigger operate in user mode. Operation in user mode is not supported. This field is always 0. (RO) execute Configures whether to enable the selected trigger to match the virtual address of instructions. 0: Not enable 1: Enable (R/W) store Set this field to make the selected trigger match the virtual address of the memory write opera- tion. Not supported by hardware. This field is always 0. (RO) load Set this field to make the selected trigger match the virtual address of a memory read operation. Not supported by hardware. This field is always 0. (RO) Register 2.26. maddress (0x7A2) maddress 0x00000000 31 0 Reset maddress Configures the address used by the selected trigger when performing match operation. (R/W) 2.6 Performance Counter The LP CPU implements a clock cycle counter mcycle(h), an instruction counter minstret(h), and 10 event counters mhpmcountern(n:3-12). The clock cycle counter and instruction counter are always available and each is 64-bit wide. Other performance counters are 40-bit wide each. By default, all counters are enabled after reset. A counter can be enabled or disabled individually via the corresponding bit in the mcountinhibit CSR. As shown in Table 2.6-1, each counter is dedicated to counting a particular event. Table 2.6-1. Performance Counter Counter Counted Event mcycle Clock cycles minstret The number of instructions mhpmcounter3 Wait cycles for memory access mhpmcounter4 Wait cycles for fetching instructions Espressif Systems 87 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 2 Low-Power CPU Counter Counted Event mhpmcounter5 The number of memory read operations. An unaligned read is counted as two. mhpmcounter6 The number of memory write operations. An unaligned write is counted as two. mhpmcounter7 The number of unconditional jump instructions (jal, jr, jalr) mhpmcounter8 The number of branch instructions mhpmcounter9 The number of taken branch instructions mhpmcounter10 The number of compressed instructions mhpmcounter11 Wait cycles for multiplication instructions mhpmcounter12 Wait cycles for division instructions 2.7 System Access 2.7.1 Memory Access The ESP32-C5 LP CPU can access LP SRAM and HP SRAM. For more information, please refer to Section 4 System and Memory. • LP SRAM: 16 KB starting from 0x5000_0000 to 0x5000_3FFF, where you can fetch instructions, read data, write data, etc. • HP SRAM: 384 KB starting from 0x4080_0000 to 0x4085_FFFF, where you can fetch instructions, read data, write data, etc. Note: The LP CPU has a high latency to access the HP SRAM, but can access the LP SRAM with no latency. The LP CPU supports the atomic instruction set. Both the LP CPU and the HP CPU can access memory through atomic instructions, thus achieving atomicity of memory access. For details on the atomic instruction set, please refer to RISC-V Instruction Set Manual Volume I: Unprivileged ISA, Version 2.2. Note that only HP SRAM supports atomic access from HP CPU and LP CPU. 2.7.2 Peripheral Access Table 4.3-2 in Chapter 4 System and Memory lists the peripherals accessible by the LP CPU and their base addresses. 2.8 Event Task Matrix Feature The LP CPU on ESP32-C5 supports the Event Task Matrix (ETM) function, which allows LP CPU’s ETM tasks to be triggered by any peripherals’ ETM events, or LP CPU’s ETM events to trigger any peripherals’ ETM tasks. This section introduces the ETM tasks and events related to the LP CPU. For more information, please refer to Chapter 10 Event Task Matrix (ETM). LP CPU can receive the following ETM task: • ULP_TASK_WAKEUP_CPU: Wakes up the LP CPU. Espressif Systems 88 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 2 Low-Power CPU LP CPU can generate the following ETM events: • ULP_EVT_ERR_INTR: Indicates that an LP CPU exception occurs. • ULP_EVT_START_INTR: Indicates that the LP CPU clock is turned on. 2.9 Sleep and Wake-Up Process 2.9.1 Features • Able to sleep, wake up, and operate independently in the low-power system when the HP CPU is working or sleeping • Able to actively configure registers to enter the sleep status based on software operating status • Wake-up events: – The HP CPU setting the register PMU_HP_TRIGGER_LP – The interrupt state of the LP IO – ETM events – The RTC timer timeout – The LP UART receiving a certain number of RX pulses when LPPERI_LP_UART_WAKEUP_EN is enabled 2.9.2 Process The LP CPU is in sleep by default and its wake-up module follows the process below to wake it up for work and make it sleep. To configure wake-up sources, please refer to Table 2.9-1. Wake up and send power-up request to PMU Clear stall Enable intr Clk on Halt Run (work) Start sleep flow Sets stall Disable intr Halt Clk off LP bus idle Reset enable (Optional) Wait for PMU to send completion signal Update LP state to IDLE Run (slp pre) Software Hardware Wake-up flow Sleep flowWorkSleep Sleep Reset release stall Stall Interrupt disable unstall enable Reset enable disable stall unstall disable enable enable disable PMU_LP_CPU_SLP_STALL_EN == 1 PMU_LP_CPU_SLP_STALL_EN == 0 PMU_LP_CPU_SLP_BYPASS_INTR_EN == 1 PMU_LP_CPU_SLP_BYPASS_INTR_EN == 0 PMU_LP_CPU_SLP_RESET_EN == 1 PMU_LP_CPU_SLP_RESET_EN == 0 PMU_LP_CPU_SLP_STALL_WAIT Figure 2.9-1. Wake-Up and Sleep Flow of LP CPU Espressif Systems 89 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 2 Low-Power CPU The first startup of the LP CPU after power-up depends on the wake-up enable and wake-up source configuration by the HP CPU. • Initialization of the LP CPU – Initialize the LP memory. – Start the LP CPU. Since the startup of the LP CPU depends on the wake-up process, it is recommended to use the PMU_HP_TRIGGER_LP register to start the initialization of the LP CPU in the following way: * Set PMU_LP_CPU_WAKEUP_EN to 0x1 * Set PMU_HP_TRIGGER_LP to 0x1 * The LP CPU will go through the wake-up process to start running • Wake-up process: – The wake-up module receives a wake-up signal and sends a power-up request to the PMU. – If the current power consumption state (clock, power supply, etc.) meets the requirements of the LP CPU, the PMU will immediately reply with the completion signal. Otherwise, it will adjust the power consumption state before replying with the completion signal. – The wake-up module disables the STALL state of the LP CPU and enables interrupt receiving. – The wake-up module starts the clock, releases reset (ignore this step if reset is not enabled for sleep), and starts working. • Sleep process: – The LP CPU configures the register PMU_LP_CPU_SLEEP_REQ to enable the wake-up module to start the sleep process. – If PMU_LP_CPU_SLP_STALL_EN is 1, the wake-up module enables the STALL state of the LP CPU. If it is 0, the module does not enable that state. – The wake-up module waits for PMU_LP_CPU_SLP_STALL_WAIT LP CPU clock cycles, and then turns off the LP CPU clock. If PMU_LP_CPU_SLP_RESET_EN is 1, the module enables reset of the LP CPU. Espressif Systems 90 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 2 Low-Power CPU 2.9.3 Wake-Up Sources Table 2.9-1. Wake Sources Register Value 1 Wake-Up Source Description 0x1 Register PMU_HP_TRIGGER_LP The HP CPU sets the regis- ter PMU_HP_TRIGGER_LP to wake up the LP CPU, and sets PMU_HP_SW_TRIGGER_INT_CLR to clear this wake-up source. 0x2 LP UART The LP UART receives a certain number of RX pulses. LPPERI_LP_UART_WAKEUP_EN needs to be enabled. For more information, please refer to Chapter 28 UART Controller (UART). 0x4 LP IO This wake-up source uses the LP IO interrupt status register signal. For more information, please refer to Chapter 6 GPIO Matrix and IO MUX. 0x8 ETM Wake-up sources received from ETM can wake up the LP CPU. For more information, please refer to Chapter 10 Event Task Matrix (ETM). 0x10 RTC timer RTC timer target 1 timeout interrupt control. For more information, please refer to Chapter 2 Low-power Management [to be added later]. 1 Value of the PMU_LP_CPU_WAKEUP_EN register 2.10 Register Summary The addresses in this section are relative to Low-Power Peripheral base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access LPPERI_CPU_REG LP CPU Control Register 0x000C R/W LPPERI_INTERRUPT_SOURCE_REG LP CPU Interrupt Status Register 0x0020 RO 2.11 Registers For how to program reserved fields, please refer to Section Programming Reserved Register Field. The addresses in this section are relative to Low-Power Peripheral base address provided in Table 4.3-2 in Chapter 4 System and Memory. Espressif Systems 91 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 2 Low-Power CPU Register 2.27. LPPERI_CPU_REG (0x000C) LPPERI_LPCORE_DBGM_UNAVALIABLE 1 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 0 Reset LPPERI_LPCORE_DBGM_UNAVALIABLE Configures the LP CPU state. 0: LP CPU can connect to JTAG 1: LP CPU is unavailable and cannot connect to JTAG (R/W) Register 2.28. LPPERI_INTERRUPT_SOURCE_REG (0x0020) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 6 LPPERI_LP_INTERRUPT_SOURCE 0x0 5 0 Reset LPPERI_LP_INTERRUPT_SOURCE Represents the LP interrupt source. Bit 5: PMU_LP_INT Bit 4: Reserved Bit 3: RTC_TIMER_LP_INT Bit 2: LP_UART_INT Bit 1: LP_I2C_INT Bit 0: LP_IO_INT (RO) Espressif Systems 92 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) Chapter 3 GDMA Controller (GDMA) 3.1 Overview General Direct Memory Access (GDMA) is a feature that allows peripheral-to-memory, memory-to-peripheral, and memory-to-memory data transfer at high speed. The CPU is not involved in the GDMA transfer and therefore is more efficient with less workload. GDMA has six independent channels: three transmit channels and three receive channels. The GDMA channels are shared and can be assigned to PARLIO, ADC, UHCI, AES, SHA, I2S or general-purpose SPI (GP-SPI) to access internal or external memory. GDMA uses configurable priority and weight arbitration schemes to manage peripherals’ needs for bandwidth. Figure 3.1-1. Modules that Share GDMA Channels 3.2 Features GDMA has the following features: • AHB bus architecture • Programmable length of data to be transferred in bytes • Access via any address and size • Alignment: Espressif Systems 93 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) – Descriptor address: 1-word aligned – Data address and length: no requirements • Linked list of descriptors • INCR burst transfer when accessing memory • Three transmit channels and three receive channels • Software-configurable selection of peripheral requesting its service • Configurable channel priority and weight arbitration • Support for memory transfer 3.3 Architecture In ESP32-C5, all modules that need high-speed data transfer support GDMA. The GDMA controller and CPU data bus have access to the same address space in memory. Figure 3.3-1 shows the basic architecture of the GDMA controller. GDMA Controller Rx Channel 0 Arbiter Peri 0 Tx Channel 0 Rx Channel 1 Tx Channel 1 Rx Channel 2 Tx Channel 2 Peri Select Internal/ External RAM Peri 1 Peri 2 Peri n Figure 3.3-1. GDMA controller Architecture GDMA has six independent channels: three transmit channels and three receive channels. Every channel can be connected to different peripherals. In other words, channels are general-purpose, and shared by peripherals. GDMA reads data from or writes data to memory via AHB_BUS. Before this, GDMA uses configurable arbitration schemes for channels requesting read or write access. For the available address range of internal and external memory, please see Chapter 4 System and Memory. Software can use the GDMA through linked lists, which are stored in the internal memory. These linked lists consist of outlinkn and inlinkn, where n indicates the channel number (ranging from 0 to 2). The GDMA reads an Espressif Systems 94 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) outlinkn (i.e., a linked list of transmit descriptors) from memory and transmits data in the corresponding memory according to the outlinkn, or reads an inlinkn (i.e., a linked list of receive descriptors) and stores received data into specific address space in the memory according to the inlinkn. 3.4 Functional Description 3.4.1 Linked List Figure 3.4-1. Structure of a Linked List Figure 3.4-1 shows the structure of a linked list. An outlink and an inlink have the same structure. A linked list is formed by one or more descriptors, and each descriptor consists of three words. Linked lists should be stored in the memory for the GDMA to be able to use them. The meanings of a descriptor’s fields are as follows: • owner (DW0) [31]: Specifies who is allowed to access the buffer that this descriptor points to. 0: CPU can access the buffer. 1: The GDMA controller can access the buffer. When the GDMA controller stops using the buffer, this bit in a receive descriptor is automatically cleared by hardware, while this bit in a transmit descriptor can only be automatically cleared by hardware if AHB_DMA_OUT_AUTO_WRBACK_CHn is set to 1. Software can disable automatic clearing by hardware by setting the AHB_DMA_OUT_LOOP_TEST_CHn or AHB_DMA_IN_LOOP_TEST_CHn bit. When software loads a linked list, this bit should be set to 1. Note: AHB_DMA_OUT is the prefix of transmit channel registers, and AHB_DMA_IN is the prefix of receive channel registers. • suc_eof (DW0) [30]: Specifies whether the AHB_DMA_IN_SUC_EOF_CHn_INT or AHB_DMA_OUT_EOF_CHn_INT interrupt will be triggered when the data corresponding to this descriptor has been received or transmitted. 0: No interrupt will be triggered after the current descriptor’s successful transfer; 1: An interrupt will be triggered after the current descriptor’s successful transfer. For receive descriptors, software needs to clear this bit to 0, and hardware will set it to 1 after receiving data containing the EOF flag. Espressif Systems 95 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) For transmit descriptors, software needs to set this bit to 1 as needed. If software configures this bit to 1 in a descriptor, the GDMA will include the EOF flag in the data sent to the corresponding peripheral, indicating to the peripheral that this data segment marks the end of one transfer phase. • reserved (DW0) [29]: Reserved. The value of this bit does not matter. • err_eof (DW0) [28]: Specifies whether the received data has errors. 0: The received data does not have errors. 1: The received data has errors. This bit is used only when UHCI or PARLIO uses the GDMA to receive data. When an error is detected in the received data segment corresponding to a descriptor, this bit in the receive descriptor is set to 1 by hardware. • reserved (DW0) [27:24]: Reserved. • length (DW0) [23:12]: Specifies the number of valid bytes in the buffer that this descriptor points to. This field in a transmit descriptor is written by software and indicates how many bytes can be read from the buffer; this field in a receive descriptor is written by hardware automatically and indicates how many valid bytes have been stored in the buffer. • size (DW0) [11:0]: Specifies the size of the buffer that this descriptor points to. • buffer address pointer (DW1): Address of the buffer. • next descriptor address (DW2): Address of the next descriptor. If the current descriptor is the last one, this value is 0. This field can only point to the memory space. Note: Please note that addresses of GDMA descriptors should be 4-byte aligned. If the length of data received is smaller than the size of the buffer, the GDMA controller will not use the available space of the buffer in the next transaction. If the length of data received is larger than the size of the buffer, the GDMA controller will use new descriptors to complete the data transfer after the current transactions. 3.4.2 Peripheral-to-Memory and Memory-to-Peripheral Data Transfer The GDMA controller can transfer data from memory to peripheral (transmit) and from peripheral to memory (receive). A transmit channel transfers data in the specified memory location to a peripheral’s transmitter via an outlinkn, whereas a receive channel transfers data received by a peripheral to the specified memory location via an inlinkn. Every transmit and receive channel can be connected to any peripheral with the GDMA feature. Table 3.4-1 illustrates how to select the peripheral to be connected via registers. “Dummy-n” corresponds to register values for memory-to-memory data transfer. When a channel is connected to a peripheral, the rest of the channels cannot be connected to that peripheral. Table 3.4-1. GDMA Selecting Peripherals via Register Configuration AHB_DMA_PERI_IN_SEL_CHn AHB_DMA_PERI_OUT_SEL_CHn Peripheral Espressif Systems 96 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) 0 Dummy-0 1 GP-SPI 2 UHCI 3 I2S 4 5 Dummy-4 5 6 AES 7 SHA 8 ADC 9 PARLIO 10 15 Dummy-10 15 16 63 Invalid 3.4.3 Memory-to-Memory Data Transfer The GDMA controller also allows memory-to-memory data transfer. Such data transfer can be enabled by setting AHB_DMA_MEM_TRANS_EN_CHn, which connects the output of transmit channel n to the input of receive channel n. Note that a transmit channel is only connected to the receive channel with the same number (n), and AHB_DMA_PERI_IN_SEL_CHn and AHB_DMA_PERI_OUT_SEL_CHn should be configured to the same value corresponding to “Dummy”. 3.4.4 Enabling GDMA The software uses the GDMA controller through linked lists. When the GDMA controller receives data, software loads an inlink, configures the AHB_DMA_INLINK_ADDR_CHn field with the address of the first receive descriptor, and sets the AHB_DMA_INLINK_START_CHn bit to enable GDMA. When the GDMA controller transmits data, software loads an outlink, prepares data to be transmitted, configures the AHB_DMA_OUTLINK_ADDR_CHn field with the address of the first transmit descriptor, and sets the AHB_DMA_OUTLINK_START_CHn bit to enable GDMA. The AHB_DMA_INLINK_START_CHn bit and AHB_DMA_OUTLINK_START_CHn bit are cleared automatically by hardware. In some cases, you may want to append more descriptors to a DMA transfer that is already started. Naively, it would seem to be possible to do this by clearing the EOF bit of the final descriptor in the existing list and setting its next descriptor address pointer field (DW2) to the first descriptor of the to-be-added list. However, this strategy fails if the existing DMA transfer is almost or entirely finished. Instead, the GDMA controller has specialized logic to make sure a DMA transfer can be continued or restarted: if the transfer is ongoing, the controller will make sure to take the appended descriptors into account; if the transfer has already finished, the controller will restart with the new descriptors. This is implemented by the Restart function. When using the Restart function, software needs to rewrite the address of the first descriptor in the new list to DW2 of the last descriptor in the loaded list, and set AHB_DMA_INLINK_RESTART_CHn bit or AHB_DMA_OUTLINK_RESTART_CHn bit (these two bits are cleared automatically by hardware). As shown in Figure 3.4-2, by doing so hardware can obtain the address of the first descriptor in the new list when reading the last descriptor in the loaded list, and then read the new list. Espressif Systems 97 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) Figure 3.4-2. Relationship among Linked Lists 3.4.5 Linked List Reading Process Once configured and enabled by software, the GDMA controller starts to read the linked list from memory. The GDMA performs checks on descriptors in the linked list. Only if descriptors pass the checks, the corresponding GDMA channel will start data transfer. If the descriptors fail any of the checks, hardware will trigger descriptor error interrupt (either AHB_DMA_IN_DSCR_ERR_CHn_INT or AHB_DMA_OUT_DSCR_ERR_CHn_INT), and the channel will halt. The checks performed on descriptors are: • Owner bit check when AHB_DMA_IN_CHECK_OWNER_CHn or AHB_DMA_OUT_CHECK_OWNER_CHn is set to 1. If the owner bit is 0, the buffer is accessed by the CPU. In this case, the owner bit fails the check. The owner bit will not be checked if AHB_DMA_IN_CHECK_OWNER_CHn or AHB_DMA_OUT_CHECK_OWNER_CHn is 0. • Descriptor address check, which checks if the descriptor address is located in configured memory space for GDMA. If a GDMA descriptor points to AHB_DMA_ACCESS_INTR_MEM_START_ADDR AHB_DMA_ACCESS_INTR_MEM_END_ADDR, it passes the check. For details, please refer to Section 3.4.7. After the software detects a descriptor error interrupt, it must load new descriptors, and enable GDMA by setting AHB_DMA_OUTLINK_START_CHn or AHB_DMA_INLINK_START_CHn bit. 3.4.6 EOF Note: In this chapter, EOF of transmit descriptors refers to suc_eof (i.e., bit 30 of DW0), while EOF of receive descriptors refers to both suc_eof and err_eof (i.e., bit 28 of DW0). The GDMA controller uses EOF (end of frame) flags to indicate the end of data segment transfer corresponding to a specific descriptor. For data transmission, the GDMA generates two types of EOF interrupts: • AHB_DMA_OUT_EOF_CHn_INT, generated when the suc_eof bit of any descriptor in the linked list is set, and the data corresponding to this descriptor has been transmitted. This interrupt is enabled by setting the AHB_DMA_OUT_EOF_CHn_INT_ENA bit. Espressif Systems 98 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) • AHB_DMA_OUT_TOTAL_EOF_CHn_INT, generated when the suc_eof bit of the last descriptor in the linked list is set, and the data corresponding to the last descriptor has been transmitted. This interrupt is enabled by setting the AHB_DMA_OUT_TOTAL_EOF_CHn_INT_ENA bit. For data reception, the GDMA also generates two types of EOF interrupts: • AHB_DMA_IN_SUC_EOF_CHn_INT, generated when a data segment with an EOF flag has been received. This interrupt is enabled by setting the AHB_DMA_IN_SUC_EOF_CHn_INT_ENA bit. • (UHCI and PARLIO only) AHB_DMA_IN_ERR_CHn_EOF_INT, generated when a data segment corresponding to a descriptor has been received with errors. This interrupt is enabled by setting the AHB_DMA_IN_ERR_EOF_CHn_INT_ENA bit, and is valid only when the channel is connected to UHCI or PARLIO. When detecting an AHB_DMA_OUT_TOTAL_EOF_CHn_INT or AHB_DMA_IN_SUC_EOF_CHn_INT interrupt, software can read the value of the AHB_DMA_OUT_EOF_DES_ADDR_CHn or AHB_DMA_IN_SUC_EOF_DES_ADDR_CHn field, which stores the address of the finished descriptor. Therefore, the software can tell which descriptors have been used and reclaim them as needed. For RX, the address of the descriptor can also be stored to the AHB_DMA_IN_ERR_EOF_DES_ADDR_CHn field when an AHB_DMA_IN_ERR_EOF_CHn_INT interrupt is triggered. 3.4.7 Accessing Memory Any transmit and receive channels of GDMA can access the memory address space configured by AHB_DMA_ACCESS_INTR_MEM_START_ADDR and AHB_DMA_ACCESS_INTR_MEM_END_ADDR. To improve data transfer efficiency, GDMA can send data in burst mode. Burst mode is disabled by default, and the burst length can be configured to SINGLE, INCR4, or INCR8 respectively by setting AHB_DMA_IN_DATA_BURST_MODE_SEL_CHn and AHB_DMA_OUT_DATA_BURST_MODE_SEL_CHn to 0, 1, or 2. When GDMA accesses the configured memory space, there are no requirements for descriptor field alignment. 3.4.8 Arbitration To ensure timely response to peripherals running at a high speed with low latency (such as general-purpose SPI), the GDMA controller implements two arbitration schemes, based on channel priority and channel weight respectively. • Priority arbitration: Each channel can be assigned a priority from 0 5 (in total 6 levels). The larger the number, the higher the priority. When several channels perform data transfers at the same time, the GDMA would respond to the transfer requests according to priority levels, and the channel with higher priority would get a response more timely. • Weight arbitration: – Each channel is assigned a weight (i.e., the number of tokens) from 0 15. The GDMA divides the AHB bus clock period into multiple time slots, and in each time slot, the number of transfers performed by a channel is determined by the number of its tokens. Every time a channel performs a data transfer, one of its tokens is spent. If all of its tokens have been spent in a time slot, then this channel’s transfer Espressif Systems 99 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) request will no longer be responded to until the time slot expires, or until tokens of all channels have been spent and the new time slot starts. – If the number of tokens assigned to a channel is not zero, the GDMA waits for this channel’s tokens to be spent even if it does not have data transfer requests, and will not exit from this time slot ahead of expiration. This leads to a waste of bandwidth. Therefore, the GDMA provides weight arbitration optimization. When this feature is enabled, a channel without data transfer requests will not be involved in the arbitration and its tokens will be ignored. When all channels no longer have transfer requests, the GDMA arbiter exits from the current time slot before expiration. This way, the arbitration response is accelerated and the transfer efficiency is improved. Note: • If channels have the same weight but different priorities, on condition that the number of bytes to be transferred is the same and not large, channels with higher priorities would finish data transfers first. • If channels have different priorities and weights, on condition that the number of bytes to be transferred is the same, channels with higher weights would be allocated more bandwidth and finish data transfers first. 3.5 Event Task Matrix Feature The GDMA controller on ESP32-C5 supports the Event Task Matrix (ETM) function, which allows GDMA’s ETM tasks to be triggered by any peripherals’ ETM events, or GDMA’s ETM events to trigger any peripherals’ ETM tasks. This section introduces the ETM tasks and events related to GDMA. For more information, please refer to Chapter 10 Event Task Matrix (ETM). GDMA can receive the following ETM tasks: • GDMA_TASK_IN_START_CHn: Enables the corresponding RX channel n for data transfer. • GDMA_TASK_OUT_START_CHn: Enables the corresponding TX channel n for data transfer. Note: Above ETM tasks can achieve the same functions as CPU configuring AHB_DMA_INLINK_START_CHn and AHB_DMA_OUTLINK_START_CHn. When AHB_DMA_IN_ETM_EN_CHn or AHB_DMA_OUT_ETM_EN_CHn is 1, only ETM tasks can be used to configure the transfer direction and enable the corresponding GDMA channel. When AHB_DMA_IN_ETM_EN_CHn or AHB_DMA_OUT_ETM_EN_CHn is 0, only CPU can be used to enable the corresponding GDMA channel. GDMA can generate the following ETM events: • GDMA_EVT_IN_DONE_CHn: Indicates that the data has been received according to the receive descriptor via channel n. • GDMA_EVT_IN_SUC_EOF_CHn: Indicates that the data corresponding to a receive descriptor has been received via channel n and the EOF bit of this descriptor is 1. • GDMA_EVT_IN_FIFO_EMPTY_CHn: Indicates that the RX FIFO has become empty. • GDMA_EVT_IN_FIFO_FULL_CHn: Indicates that the RX FIFO has become full. Espressif Systems 100 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) • GDMA_EVT_OUT_DONE_CHn: Indicates that the data has been transmitted according to the transmit descriptor via channel n. • GDMA_EVT_OUT_EOF_CHn: Indicates that the data corresponding to a transmit descriptor has been transmitted or received via channel n and the EOF bit of this descriptor is 1. • GDMA_EVT_OUT_TOTAL_EOF_CHn: Indicates that the data corresponding to the last transmit descriptors has been sent via transmit channel n and the EOF bit of this descriptor is 1. • GDMA_EVT_OUT_FIFO_EMPTY_CHn: Indicates that the TX FIFO has become empty. • GDMA_EVT_OUT_FIFO_FULL_CHn: Indicates that the TX FIFO has become full. In practical applications, GDMA’s ETM events can trigger its own ETM tasks. For example, the GDMA_EVT_OUT_TOTAL_EOF_CH0 event can trigger the GDMA_TASK_IN_START_CH1 task, and in this way trigger a new round of GDMA operations. 3.6 Interrupts ESP32-C5’s GDMA module can generate the following interrupt signals that will be sent to the Interrupt Matrix. • GDMA_IN_CH0_INTR • GDMA_IN_CH1_INTR • GDMA_IN_CH2_INTR • GDMA_OUT_CH0_INTR • GDMA_OUT_CH1_INTR • GDMA_OUT_CH2_INTR There are several internal interrupt sources from GDMA that can generate the above interrupt signals. The GDMA_IN_CHn_INTR (n is 0 2) signals are generated by the following interrupt sources: • AHB_DMA_IN_DONE_CHn_INT: Triggered when all data corresponding to a receive descriptor has been received via receive channel n. • AHB_DMA_IN_SUC_EOF_CHn_INT: Triggered when the suc_eof bit in a receive descriptor is 1 and the data corresponding to this receive descriptor has been received via receive channel n. • AHB_DMA_IN_ERR_EOF_CHn_INT: Triggered when an error is detected in the data segment corresponding to a descriptor received via receive channel n. This interrupt is used only for UHCI (UART0 or UART1) or PARLIO. • AHB_DMA_IN_DSCR_EMPTY_CHn_INT: Triggered when the size of the buffer pointed by receive descriptors is smaller than the length of data to be received via receive channel n. • AHB_DMA_IN_DSCR_ERR_CHn_INT: Triggered when a receive descriptor on receive channel n fails any of the two descriptor checks. • AHB_DMA_INFIFO_OVF_CHn_INT: Triggered when the RX FIFO of GDMA overflows. • AHB_DMA_INFIFO_UDF_CHn_INT: Triggered when the RX FIFO of GDMA underflows. Espressif Systems 101 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) The GDMA_OUT_CHn_INTR (n is 0 2) signals are generated by the following interrupt sources: • AHB_DMA_OUT_DONE_CHn_INT: Triggered when all data corresponding to a transmit descriptor has been sent via transmit channel n. • AHB_DMA_OUT_EOF_CHn_INT: Triggered when the suc_eof bit in a transmit descriptor is 1 and data corresponding to this descriptor has been sent via transmit channel n. If AHB_DMA_OUT_EOF_MODE_CHn is 0, this interrupt will be triggered when the last byte of data corresponding to this descriptor enters GDMA’s transmit channel; if AHB_DMA_OUT_EOF_MODE_CHn is 1, this interrupt is triggered when the last byte of data is taken from GDMA’s transmit channel. • AHB_DMA_OUT_DSCR_ERR_CHn_INT: Triggered when a transmit descriptor on transmit channel n fails any of the two descriptor checks. • AHB_DMA_OUT_TOTAL_EOF_CHn_INT: Triggered when all data corresponding to a linked list (including multiple descriptors) has been sent via transmit channel n. • AHB_DMA_OUTFIFO_OVF_CHn_INT: Triggered when the TX FIFO of GDMA overflows. • AHB_DMA_OUTFIFO_UDF_CHn_INT: Triggered when the TX FIFO of GDMA underflows. 3.7 Programming Procedures The clock gating for GDMA can be configured via PCR_GDMA_CLK_EN, and is enabled by default. GDMA can be reset by configuring PCR_GDMA_RST_EN. 3.7.1 Programming Procedures for GDMA’s Transmit Channel To transmit data, GDMA’s transmit channel should be configured by software as follows: 1. Set AHB_DMA_OUT_RST_CHn first to 1 and then to 0, to reset the state machine of GDMA’s transmit channel and FIFO pointer. 2. Load an outlink, and configure AHB_DMA_OUTLINK_ADDR_CHn with address of the first transmit descriptor. 3. Configure AHB_DMA_PERI_OUT_SEL_CHn with the value corresponding to the peripheral to be connected, as shown in Table 3.4-1. 4. Set AHB_DMA_OUTLINK_START_CHn to enable GDMA’s transmit channel for data transfer. 5. Configure and enable the corresponding peripheral. See details in the individual chapter for the corresponding peripheral. 6. Wait for the AHB_DMA_OUT_TOTAL_EOF_CHn_INT interrupt, which indicates the completion of data transfer. 3.7.2 Programming Procedures for GDMA’s Receive Channel To receive data, GDMA’s receive channel should be configured by software as follows: 1. Set AHB_DMA_IN_RST_CHn first to 1 and then to 0, to reset the state machine of GDMA’s receive channel and FIFO pointer. Espressif Systems 102 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) 2. Load an inlink, and configure AHB_DMA_INLINK_ADDR_CHn with address of the first receive descriptor. 3. Configure AHB_DMA_PERI_IN_SEL_CHn with the value corresponding to the peripheral to be connected, as shown in Table 3.4-1. 4. Set AHB_DMA_INLINK_START_CHn to enable GDMA’s receive channel for data transfer. 5. Configure and enable the corresponding peripheral. See details in the individual chapter for the corresponding peripheral. 3.7.3 Programming Procedures for Memory-to-Memory Transfer To transfer data from one memory location to another, GDMA should be configured by software as follows: 1. Set AHB_DMA_OUT_RST_CHn first to 1 and then to 0, to reset the state machine of GDMA’s transmit channel and FIFO pointer. 2. Set AHB_DMA_IN_RST_CHn first to 1 and then to 0, to reset the state machine of GDMA’s receive channel and FIFO pointer. 3. Load an outlink, and configure AHB_DMA_OUTLINK_ADDR_CHn with address of the first transmit descriptor. 4. Load an inlink, and configure AHB_DMA_INLINK_ADDR_CHn with address of the first receive descriptor. 5. Set AHB_DMA_MEM_TRANS_EN_CHn to enable memory-to-memory transfer. 6. Set AHB_DMA_OUTLINK_START_CHn to enable GDMA’s transmit channel for data transfer. 7. Set AHB_DMA_INLINK_START_CHn to enable GDMA’s receive channel for data transfer. 8. If the suc_eof bit is set in a transmit descriptor, an AHB_DMA_IN_SUC_EOF_CHn_INT interrupt will be triggered when the data segment corresponding to this descriptor has been transmitted. 3.7.4 Programming Procedures for Channel Priority and Weight The priority arbitration can be configured as follows: 1. Configure the channel priority for TX and RX respectively via AHB_DMA_TX_PRI_CHn and AHB_DMA_RX_PRI_CHn. The weight arbitration can be configured as follows: 1. Configure the time slot via AHB_DMA_ARB_TIMEOUT. 2. Configure the number of tokens for TX and RX respectively via AHB_DMA_TX_CH_ARB_WEIGH_CHn and AHB_DMA_RX_CH_ARB_WEIGH_CHn. 3. Enable weight arbitration optimization for TX and RX respectively by clearing AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CHn and AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CHn. 4. Enable the arbitration by setting AHB_DMA_WEIGHT_EN. Espressif Systems 103 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) 3.8 Register Summary The addresses in this section are relative to GDMA base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Interrupt Registers AHB_DMA_IN_INT_RAW_CH0_REG RX channel 0 raw interrupt status register 0x0000 R/WTC/SS AHB_DMA_IN_INT_ST_CH0_REG RX channel 0 masked interrupt status register 0x0004 RO AHB_DMA_IN_INT_ENA_CH0_REG RX channel 0 interrupt enable register 0x0008 R/W AHB_DMA_IN_INT_CLR_CH0_REG RX channel 0 interrupt clear register 0x000C WT AHB_DMA_IN_INT_RAW_CH1_REG RX channel 1 raw interrupt status register 0x0010 R/WTC/SS AHB_DMA_IN_INT_ST_CH1_REG RX channel 1 masked interrupt status register 0x0014 RO AHB_DMA_IN_INT_ENA_CH1_REG RX channel 1 interrupt enable register 0x0018 R/W AHB_DMA_IN_INT_CLR_CH1_REG RX channel 1 interrupt clear register 0x001C WT AHB_DMA_IN_INT_RAW_CH2_REG RX channel 2 raw interrupt status register 0x0020 R/WTC/SS AHB_DMA_IN_INT_ST_CH2_REG RX channel 2 masked interrupt status register 0x0024 RO AHB_DMA_IN_INT_ENA_CH2_REG RX channel 2 interrupt enable register 0x0028 R/W AHB_DMA_IN_INT_CLR_CH2_REG RX channel 2 interrupt clear register 0x002C WT AHB_DMA_OUT_INT_RAW_CH0_REG TX channel 0 raw interrupt status register 0x0030 R/WTC/SS AHB_DMA_OUT_INT_ST_CH0_REG TX channel 0 masked interrupt status register 0x0034 RO AHB_DMA_OUT_INT_ENA_CH0_REG TX channel 0 interrupt enable register 0x0038 R/W AHB_DMA_OUT_INT_CLR_CH0_REG TX channel 0 interrupt clear register 0x003C WT AHB_DMA_OUT_INT_RAW_CH1_REG TX channel 1 raw interrupt status register 0x0040 R/WTC/SS AHB_DMA_OUT_INT_ST_CH1_REG TX channel 1 masked interrupt status register 0x0044 RO AHB_DMA_OUT_INT_ENA_CH1_REG TX channel 1 interrupt enable register 0x0048 R/W AHB_DMA_OUT_INT_CLR_CH1_REG TX channel 1 interrupt clear register 0x004C WT AHB_DMA_OUT_INT_RAW_CH2_REG TX channel 2 raw interrupt status register 0x0050 R/WTC/SS AHB_DMA_OUT_INT_ST_CH2_REG TX channel 2 masked interrupt status register 0x0054 RO AHB_DMA_OUT_INT_ENA_CH2_REG TX channel 2 interrupt enable register 0x0058 R/W Espressif Systems 104 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) Name Description Address Access AHB_DMA_OUT_INT_CLR_CH2_REG TX channel 2 interrupt clear register 0x005C WT Debug Registers AHB_DMA_AHB_TEST_REG Reserved 0x0060 R/W Configuration Registers AHB_DMA_MISC_CONF_REG Miscellaneous register 0x0064 R/W AHB_DMA_IN_CONF0_CH0_REG Configuration register 0 of RX channel 0 0x0070 R/W AHB_DMA_IN_CONF1_CH0_REG Configuration register 1 of RX channel 0 0x0074 R/W AHB_DMA_IN_POP_CH0_REG Pop control register of RX channel 0 0x007C varies AHB_DMA_IN_LINK_CH0_REG Linked list descriptor configuration and control register of RX channel 0 0x0080 varies AHB_DMA_OUT_CONF0_CH0_REG Configuration register 0 of TX channel 0 0x00D0 R/W AHB_DMA_OUT_CONF1_CH0_REG Configuration register 1 of TX channel 0 0x00D4 R/W AHB_DMA_OUT_PUSH_CH0_REG Push control register of TX channel 0 0x00DC varies AHB_DMA_OUT_LINK_CH0_REG Linked list descriptor configuration and control register of TX channel 0 0x00E0 varies AHB_DMA_IN_CONF0_CH1_REG Configuration register 0 of RX channel 1 0x0130 R/W AHB_DMA_IN_CONF1_CH1_REG Configuration register 1 of RX channel 1 0x0134 R/W AHB_DMA_IN_POP_CH1_REG Pop control register of RX channel 1 0x013C varies AHB_DMA_IN_LINK_CH1_REG Linked list descriptor configuration and control register of RX channel 1 0x0140 varies AHB_DMA_OUT_CONF0_CH1_REG Configuration register 0 of TX channel 1 0x0190 R/W AHB_DMA_OUT_CONF1_CH1_REG Configuration register 1 of TX channel 1 0x0194 R/W AHB_DMA_OUT_PUSH_CH1_REG Push control register of TX channel 1 0x019C varies AHB_DMA_OUT_LINK_CH1_REG Linked list descriptor configuration and control register of TX channel 1 0x01A0 varies AHB_DMA_IN_CONF0_CH2_REG Configuration register 0 of RX channel 2 0x01F0 R/W AHB_DMA_IN_CONF1_CH2_REG Configuration register 1 of RX channel 2 0x01F4 R/W AHB_DMA_IN_POP_CH2_REG Pop control register of RX channel 2 0x01FC varies Espressif Systems 105 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) Name Description Address Access AHB_DMA_IN_LINK_CH2_REG Linked list descriptor configuration and control register of RX channel 2 0x0200 varies AHB_DMA_OUT_CONF0_CH2_REG Configuration register 0 of TX channel 2 0x0250 R/W AHB_DMA_OUT_CONF1_CH2_REG Configuration register 1 of TX channel 2 0x0254 R/W AHB_DMA_OUT_PUSH_CH2_REG Push control register of TX channel 2 0x025C varies AHB_DMA_OUT_LINK_CH2_REG Linked list descriptor configuration and control register of TX channel 2 0x0260 varies AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG TX channel 0 arbitration weight configuration register 0x02DC R/W AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_REG TX channel 0 weight arbitration optimization enable register 0x02E0 R/W AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG TX channel 1 arbitration weight configuration register 0x0304 R/W AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_REG TX channel 1 weight arbitration optimization enable register 0x0308 R/W AHB_DMA_TX_CH_ARB_WEIGH_CH2_REG TX channel 2 arbitration weight configuration register 0x032C R/W AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_REG TX channel 2 weight arbitration optimization enable register 0x0330 R/W AHB_DMA_RX_CH_ARB_WEIGH_CH0_REG RX channel 0 arbitration weight configuration register 0x0354 R/W AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_REG RX channel 0 weight arbitration optimization enable register 0x0358 R/W AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG RX channel 1 arbitration weight configuration register 0x037C R/W AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_REG RX channel 1 weight arbitration optimization enable register 0x0380 R/W AHB_DMA_RX_CH_ARB_WEIGH_CH2_REG RX channel 2 arbitration weight configuration register 0x03A4 R/W AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_REG RX channel 2 weight arbitration optimization enable register 0x03A8 R/W AHB_DMA_IN_LINK_ADDR_CH0_REG Linked list descriptor configuration register of RX channel 0 0x03AC R/W AHB_DMA_IN_LINK_ADDR_CH1_REG Linked list descriptor configuration register of RX channel 1 0x03B0 R/W Espressif Systems 106 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) Name Description Address Access AHB_DMA_IN_LINK_ADDR_CH2_REG Linked list descriptor configuration register of RX channel 2 0x03B4 R/W AHB_DMA_OUT_LINK_ADDR_CH0_REG Linked list descriptor configuration register of TX channel 0 0x03B8 R/W AHB_DMA_OUT_LINK_ADDR_CH1_REG Linked list descriptor configuration register of TX channel 1 0x03BC R/W AHB_DMA_OUT_LINK_ADDR_CH2_REG Linked list descriptor configuration register of TX channel 2 0x03C0 R/W AHB_DMA_INTR_MEM_START_ADDR_REG Accessible address space start address configuration register 0x03C4 R/W AHB_DMA_INTR_MEM_END_ADDR_REG Accessible address space end address configuration register 0x03C8 R/W AHB_DMA_ARB_TIMEOUT_REG Weight arbitration timeout configuration register 0x03DC R/W AHB_DMA_WEIGHT_EN_REG Weight arbitration enable register 0x0400 R/W Version Registers AHB_DMA_DATE_REG Version control register 0x0068 R/W Status Registers AHB_DMA_INFIFO_STATUS_CH0_REG RX channel 0 FIFO status 0x0078 RO AHB_DMA_IN_STATE_CH0_REG RX channel 0 status 0x0084 RO AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0_REG Receive descriptor address when EOF occurs on RX channel 0 0x0088 RO AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_REG Receive descriptor address when errors occur on RX channel 0 0x008C RO AHB_DMA_IN_DSCR_CH0_REG Address of the next receive descriptor pointed by the current pre-read receive descriptor on RX channel 0 0x0090 RO AHB_DMA_IN_DSCR_BF0_CH0_REG Address of the current pre-read receive descriptor on RX channel 0 0x0094 RO AHB_DMA_IN_DSCR_BF1_CH0_REG Address of the previous pre-read receive descriptor on RX channel 0 0x0098 RO Espressif Systems 107 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) Name Description Address Access AHB_DMA_OUTFIFO_STATUS_CH0_REG TX channel 0 FIFO status 0x00D8 RO AHB_DMA_OUT_STATE_CH0_REG TX channel 0 status 0x00E4 RO AHB_DMA_OUT_EOF_DES_ADDR_CH0_REG Transmit descriptor address when EOF occurs on TX channel 0 0x00E8 RO AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG The last transmit descriptor address when EOF oc- curs on TX channel 0 0x00EC RO AHB_DMA_OUT_DSCR_CH0_REG Address of the next transmit descriptor pointed by the current pre-read transmit descriptor on TX channel 0 0x00F0 RO AHB_DMA_OUT_DSCR_BF0_CH0_REG Address of the current pre-read transmit descriptor on TX channel 0 0x00F4 RO AHB_DMA_OUT_DSCR_BF1_CH0_REG Address of the previous pre-read transmit descriptor on TX channel 0 0x00F8 RO AHB_DMA_INFIFO_STATUS_CH1_REG RX channel 1 FIFO status 0x0138 RO AHB_DMA_IN_STATE_CH1_REG RX channel 1 status 0x0144 RO AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_REG Receive descriptor address when EOF occurs on RX channel 1 0x0148 RO AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_REG Receive descriptor address when errors occur on RX channel 1 0x014C RO AHB_DMA_IN_DSCR_CH1_REG Address of the next receive descriptor pointed by the current pre-read receive descriptor on RX channel 1 0x0150 RO AHB_DMA_IN_DSCR_BF0_CH1_REG Address of the current pre-read receive descriptor on RX channel 1 0x0154 RO AHB_DMA_IN_DSCR_BF1_CH1_REG Address of the previous pre-read receive descriptor on RX channel 1 0x0158 RO AHB_DMA_OUTFIFO_STATUS_CH1_REG TX channel 1 FIFO status 0x0198 RO AHB_DMA_OUT_STATE_CH1_REG TX channel 1 status 0x01A4 RO AHB_DMA_OUT_EOF_DES_ADDR_CH1_REG Transmit descriptor address when EOF occurs on TX channel 1 0x01A8 RO Espressif Systems 108 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) Name Description Address Access AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG The last transmit descriptor address when EOF oc- curs on TX channel 1 0x01AC RO AHB_DMA_OUT_DSCR_CH1_REG Address of the next transmit descriptor pointed by the current pre-read transmit descriptor on TX channel 1 0x01B0 RO AHB_DMA_OUT_DSCR_BF0_CH1_REG Address of the current pre-read transmit descriptor on TX channel 1 0x01B4 RO AHB_DMA_OUT_DSCR_BF1_CH1_REG Address of the previous pre-read transmit descriptor on TX channel 1 0x01B8 RO AHB_DMA_INFIFO_STATUS_CH2_REG RX channel 2 FIFO status 0x01F8 RO AHB_DMA_IN_STATE_CH2_REG RX channel 2 status 0x0204 RO AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_REG Receive descriptor address when EOF occurs on RX channel 2 0x0208 RO AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_REG Receive descriptor address when errors occur on RX channel 2 0x020C RO AHB_DMA_IN_DSCR_CH2_REG Address of the next receive descriptor pointed by the current pre-read receive descriptor on RX channel 2 0x0210 RO AHB_DMA_IN_DSCR_BF0_CH2_REG Address of the current pre-read receive descriptor on RX channel 2 0x0214 RO AHB_DMA_IN_DSCR_BF1_CH2_REG Address of the previous pre-read receive descriptor on RX channel 2 0x0218 RO AHB_DMA_OUTFIFO_STATUS_CH2_REG TX channel 2 FIFO status 0x0258 RO AHB_DMA_OUT_STATE_CH2_REG TX channel 2 status 0x0264 RO AHB_DMA_OUT_EOF_DES_ADDR_CH2_REG Transmit descriptor address when EOF occurs on TX channel 2 0x0268 RO AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG The last transmit descriptor address when EOF oc- curs on TX channel 2 0x026C RO AHB_DMA_OUT_DSCR_CH2_REG Address of the next transmit descriptor pointed by the current pre-read transmit descriptor on TX channel 2 0x0270 RO Espressif Systems 109 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) Name Description Address Access AHB_DMA_OUT_DSCR_BF0_CH2_REG Address of the current pre-read transmit descriptor on TX channel 2 0x0274 RO AHB_DMA_OUT_DSCR_BF1_CH2_REG Address of the previous pre-read transmit descriptor on TX channel 2 0x0278 RO Priority Registers AHB_DMA_IN_PRI_CH0_REG Priority register of RX channel 0 0x009C R/W AHB_DMA_OUT_PRI_CH0_REG Priority register of TX channel 0 0x00FC R/W AHB_DMA_IN_PRI_CH1_REG Priority register of RX channel 1 0x015C R/W AHB_DMA_OUT_PRI_CH1_REG Priority register of TX channel 1 0x01BC R/W AHB_DMA_IN_PRI_CH2_REG Priority register of RX channel 2 0x021C R/W AHB_DMA_OUT_PRI_CH2_REG Priority register of TX channel 2 0x027C R/W Peripheral Selection Registers AHB_DMA_IN_PERI_SEL_CH0_REG Peripheral selection register of RX channel 0 0x00A0 R/W AHB_DMA_OUT_PERI_SEL_CH0_REG Peripheral selection register of TX channel 0 0x0100 R/W AHB_DMA_IN_PERI_SEL_CH1_REG Peripheral selection register of RX channel 1 0x0160 R/W AHB_DMA_OUT_PERI_SEL_CH1_REG Peripheral selection register of TX channel 1 0x01C0 R/W AHB_DMA_IN_PERI_SEL_CH2_REG Peripheral selection register of RX channel 2 0x0220 R/W AHB_DMA_OUT_PERI_SEL_CH2_REG Peripheral selection register of TX channel 2 0x0280 R/W Espressif Systems 110 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) 3.9 Registers The addresses in this section are relative to GDMA base address provided in Table 4.3-2 in Chapter 4 System and Memory. For how to program reserved fields, please refer to Section Programming Reserved Register Field. Register 3.1. AHB_DMA_IN_INT_RAW_CHn_REG (n: 0-2) (0x0000+0x10*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 7 AHB_DMA_INFIFO_UDF_CHn_INT_RAW 0 6 AHB_DMA_INFIFO_OVF_CHn_INT_RAW 0 5 AHB_DMA_IN_DSCR_EMPTY_CHn_INT_RAW 0 4 AHB_DMA_IN_DSCR_ERR_CHn_INT_RAW 0 3 AHB_DMA_IN_ERR_EOF_CHn_INT_RAW 0 2 AHB_DMA_IN_SUC_EOF_CHn_INT_RAW 0 1 AHB_DMA_IN_DONE_CHn_INT_RAW 0 0 Reset AHB_DMA_IN_DONE_CHn_INT_RAW The raw interrupt status of AHB_DMA_IN_DONE_CHn_INT. (R/WTC/SS) AHB_DMA_IN_SUC_EOF_CHn_INT_RAW The raw interrupt status of AHB_DMA_IN_SUC_EOF_CHn_INT. For UHCI, this bit turns to 1 when the last data byte pointed by one receive descriptor has been received and no data error is detected for RX channel n. (R/WTC/SS) AHB_DMA_IN_ERR_EOF_CHn_INT_RAW The raw interrupt status of AHB_DMA_IN_ERR_EOF_CHn_INT. Valid only for UHCI. (R/WTC/SS) AHB_DMA_IN_DSCR_ERR_CHn_INT_RAW The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CHn_INT. (R/WTC/SS) AHB_DMA_IN_DSCR_EMPTY_CHn_INT_RAW The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CHn_INT. (R/WTC/SS) AHB_DMA_INFIFO_OVF_CHn_INT_RAW The raw interrupt status of AHB_DMA_INFIFO_OVF_CHn_INT. (R/WTC/SS) AHB_DMA_INFIFO_UDF_CHn_INT_RAW The raw interrupt status of AHB_DMA_INFIFO_UDF_CHn_INT. (R/WTC/SS) Espressif Systems 111 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) Register 3.2. AHB_DMA_IN_INT_ST_CHn_REG (n: 0-2) (0x0004+0x10*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 7 AHB_DMA_INFIFO_UDF_CHn_INT_ST 0 6 AHB_DMA_INFIFO_OVF_CHn_INT_ST 0 5 AHB_DMA_IN_DSCR_EMPTY_CHn_INT_ST 0 4 AHB_DMA_IN_DSCR_ERR_CHn_INT_ST 0 3 AHB_DMA_IN_ERR_EOF_CHn_INT_ST 0 2 AHB_DMA_IN_SUC_EOF_CHn_INT_ST 0 1 AHB_DMA_IN_DONE_CHn_INT_ST 0 0 Reset AHB_DMA_IN_DONE_CHn_INT_ST The masked interrupt status of AHB_DMA_IN_DONE_CHn_INT. (RO) AHB_DMA_IN_SUC_EOF_CHn_INT_ST The masked interrupt status of AHB_DMA_IN_SUC_EOF_CHn_INT. (RO) AHB_DMA_IN_ERR_EOF_CHn_INT_ST The masked interrupt status of AHB_DMA_IN_ERR_EOF_CHn_INT. (RO) AHB_DMA_IN_DSCR_ERR_CHn_INT_ST The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CHn_INT. (RO) AHB_DMA_IN_DSCR_EMPTY_CHn_INT_ST The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CHn_INT. (RO) AHB_DMA_INFIFO_OVF_CHn_INT_ST The masked interrupt status of AHB_DMA_INFIFO_OVF_CHn_INT. (RO) AHB_DMA_INFIFO_UDF_CHn_INT_ST The masked interrupt status of AHB_DMA_INFIFO_UDF_CHn_INT. (RO) Espressif Systems 112 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) Register 3.3. AHB_DMA_IN_INT_ENA_CHn_REG (n: 0-2) (0x0008+0x10*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 7 AHB_DMA_INFIFO_UDF_CHn_INT_ENA 0 6 AHB_DMA_INFIFO_OVF_CHn_INT_ENA 0 5 AHB_DMA_IN_DSCR_EMPTY_CHn_INT_ENA 0 4 AHB_DMA_IN_DSCR_ERR_CHn_INT_ENA 0 3 AHB_DMA_IN_ERR_EOF_CHn_INT_ENA 0 2 AHB_DMA_IN_SUC_EOF_CHn_INT_ENA 0 1 AHB_DMA_IN_DONE_CHn_INT_ENA 0 0 Reset AHB_DMA_IN_DONE_CHn_INT_ENA Write 1 to enable AHB_DMA_IN_DONE_CHn_INT. (R/W) AHB_DMA_IN_SUC_EOF_CHn_INT_ENA Write 1 to enable AHB_DMA_IN_SUC_EOF_CHn_INT. (R/W) AHB_DMA_IN_ERR_EOF_CHn_INT_ENA Write 1 to enable AHB_DMA_IN_ERR_EOF_CHn_INT. (R/W) AHB_DMA_IN_DSCR_ERR_CHn_INT_ENA Write 1 to enable AHB_DMA_IN_DSCR_ERR_CHn_INT. (R/W) AHB_DMA_IN_DSCR_EMPTY_CHn_INT_ENA Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CHn_INT. (R/W) AHB_DMA_INFIFO_OVF_CHn_INT_ENA Write 1 to enable AHB_DMA_INFIFO_OVF_CHn_INT. (R/W) AHB_DMA_INFIFO_UDF_CHn_INT_ENA Write 1 to enable AHB_DMA_INFIFO_UDF_CHn_INT. (R/W) Espressif Systems 113 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) Register 3.4. AHB_DMA_IN_INT_CLR_CHn_REG (n: 0-2) (0x000C+0x10*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 7 AHB_DMA_INFIFO_UDF_CHn_INT_CLR 0 6 AHB_DMA_INFIFO_OVF_CHn_INT_CLR 0 5 AHB_DMA_IN_DSCR_EMPTY_CHn_INT_CLR 0 4 AHB_DMA_IN_DSCR_ERR_CHn_INT_CLR 0 3 AHB_DMA_IN_ERR_EOF_CHn_INT_CLR 0 2 AHB_DMA_IN_SUC_EOF_CHn_INT_CLR 0 1 AHB_DMA_IN_DONE_CHn_INT_CLR 0 0 Reset AHB_DMA_IN_DONE_CHn_INT_CLR Write 1 to clear AHB_DMA_IN_DONE_CHn_INT. (WT) AHB_DMA_IN_SUC_EOF_CHn_INT_CLR Write 1 to clear AHB_DMA_IN_SUC_EOF_CHn_INT. (WT) AHB_DMA_IN_ERR_EOF_CHn_INT_CLR Write 1 to clear AHB_DMA_IN_ERR_EOF_CHn_INT. (WT) AHB_DMA_IN_DSCR_ERR_CHn_INT_CLR Write 1 to clear AHB_DMA_IN_DSCR_ERR_CHn_INT. (WT) AHB_DMA_IN_DSCR_EMPTY_CHn_INT_CLR Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CHn_INT. (WT) AHB_DMA_INFIFO_OVF_CHn_INT_CLR Write 1 to clear AHB_DMA_INFIFO_OVF_CHn_INT. (WT) AHB_DMA_INFIFO_UDF_CHn_INT_CLR Write 1 to clear AHB_DMA_INFIFO_UDF_CHn_INT. (WT) Espressif Systems 114 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) Register 3.5. AHB_DMA_OUT_INT_RAW_CHn_REG (n: 0-2) (0x0030+0x10*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 6 AHB_DMA_OUTFIFO_UDF_CHn_INT_RAW 0 5 AHB_DMA_OUTFIFO_OVF_CHn_INT_RAW 0 4 AHB_DMA_OUT_TOTAL_EOF_CHn_INT_RAW 0 3 AHB_DMA_OUT_DSCR_ERR_CHn_INT_RAW 0 2 AHB_DMA_OUT_EOF_CHn_INT_RAW 0 1 AHB_DMA_OUT_DONE_CHn_INT_RAW 0 0 Reset AHB_DMA_OUT_DONE_CHn_INT_RAW The raw interrupt status of AHB_DMA_OUT_DONE_CHn_INT. (R/WTC/SS) AHB_DMA_OUT_EOF_CHn_INT_RAW The raw interrupt status of AHB_DMA_OUT_EOF_CHn_INT. (R/WTC/SS) AHB_DMA_OUT_DSCR_ERR_CHn_INT_RAW The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CHn_INT. (R/WTC/SS) AHB_DMA_OUT_TOTAL_EOF_CHn_INT_RAW The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CHn_INT. (R/WTC/SS) AHB_DMA_OUTFIFO_OVF_CHn_INT_RAW The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CHn_INT. (R/WTC/SS) AHB_DMA_OUTFIFO_UDF_CHn_INT_RAW The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CHn_INT. (R/WTC/SS) Espressif Systems 115 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) Register 3.6. AHB_DMA_OUT_INT_ST_CHn_REG (n: 0-2) (0x0034+0x10*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 6 AHB_DMA_OUTFIFO_UDF_CHn_INT_ST 0 5 AHB_DMA_OUTFIFO_OVF_CHn_INT_ST 0 4 AHB_DMA_OUT_TOTAL_EOF_CHn_INT_ST 0 3 AHB_DMA_OUT_DSCR_ERR_CHn_INT_ST 0 2 AHB_DMA_OUT_EOF_CHn_INT_ST 0 1 AHB_DMA_OUT_DONE_CHn_INT_ST 0 0 Reset AHB_DMA_OUT_DONE_CHn_INT_ST The masked interrupt status of AHB_DMA_OUT_DONE_CHn_INT. (RO) AHB_DMA_OUT_EOF_CHn_INT_ST The masked interrupt status of AHB_DMA_OUT_EOF_CHn_INT. (RO) AHB_DMA_OUT_DSCR_ERR_CHn_INT_ST The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CHn_INT. (RO) AHB_DMA_OUT_TOTAL_EOF_CHn_INT_ST The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CHn_INT. (RO) AHB_DMA_OUTFIFO_OVF_CHn_INT_ST The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CHn_INT. (RO) AHB_DMA_OUTFIFO_UDF_CHn_INT_ST The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CHn_INT. (RO) Espressif Systems 116 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) Register 3.7. AHB_DMA_OUT_INT_ENA_CHn_REG (n: 0-2) (0x0038+0x10*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 6 AHB_DMA_OUTFIFO_UDF_CHn_INT_ENA 0 5 AHB_DMA_OUTFIFO_OVF_CHn_INT_ENA 0 4 AHB_DMA_OUT_TOTAL_EOF_CHn_INT_ENA 0 3 AHB_DMA_OUT_DSCR_ERR_CHn_INT_ENA 0 2 AHB_DMA_OUT_EOF_CHn_INT_ENA 0 1 AHB_DMA_OUT_DONE_CHn_INT_ENA 0 0 Reset AHB_DMA_OUT_DONE_CHn_INT_ENA Write 1 to enable AHB_DMA_OUT_DONE_CHn_INT. (R/W) AHB_DMA_OUT_EOF_CHn_INT_ENA Write 1 to enable AHB_DMA_OUT_EOF_CHn_INT. (R/W) AHB_DMA_OUT_DSCR_ERR_CHn_INT_ENA Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CHn_INT. (R/W) AHB_DMA_OUT_TOTAL_EOF_CHn_INT_ENA Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CHn_INT. (R/W) AHB_DMA_OUTFIFO_OVF_CHn_INT_ENA Write 1 to enable AHB_DMA_OUTFIFO_OVF_CHn_INT. (R/W) AHB_DMA_OUTFIFO_UDF_CHn_INT_ENA Write 1 to enable AHB_DMA_OUTFIFO_UDF_CHn_INT. (R/W) Espressif Systems 117 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) Register 3.8. AHB_DMA_OUT_INT_CLR_CHn_REG (n: 0-2) (0x003C+0x10*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 6 AHB_DMA_OUTFIFO_UDF_CHn_INT_CLR 0 5 AHB_DMA_OUTFIFO_OVF_CHn_INT_CLR 0 4 AHB_DMA_OUT_TOTAL_EOF_CHn_INT_CLR 0 3 AHB_DMA_OUT_DSCR_ERR_CHn_INT_CLR 0 2 AHB_DMA_OUT_EOF_CHn_INT_CLR 0 1 AHB_DMA_OUT_DONE_CHn_INT_CLR 0 0 Reset AHB_DMA_OUT_DONE_CHn_INT_CLR Write 1 to clear AHB_DMA_OUT_DONE_CHn_INT. (WT) AHB_DMA_OUT_EOF_CHn_INT_CLR Write 1 to clear AHB_DMA_OUT_EOF_CHn_INT. (WT) AHB_DMA_OUT_DSCR_ERR_CHn_INT_CLR Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CHn_INT. (WT) AHB_DMA_OUT_TOTAL_EOF_CHn_INT_CLR Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CHn_INT. (WT) AHB_DMA_OUTFIFO_OVF_CHn_INT_CLR Write 1 to clear AHB_DMA_OUTFIFO_OVF_CHn_INT. (WT) AHB_DMA_OUTFIFO_UDF_CHn_INT_CLR Write 1 to clear AHB_DMA_OUTFIFO_UDF_CHn_INT. (WT) Register 3.9. AHB_DMA_AHB_TEST_REG (0x0060) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 6 AHB_DMA_AHB_TESTADDR 0 5 4 (reserved) 0 3 AHB_DMA_AHB_TESTMODE 0 2 0 Reset AHB_DMA_AHB_TESTMODE Reserved. (R/W) AHB_DMA_AHB_TESTADDR Reserved. (R/W) Espressif Systems 118 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) Register 3.10. AHB_DMA_MISC_CONF_REG (0x0064) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 4 AHB_DMA_CLK_EN 0 3 AHB_DMA_ARB_PRI_DIS 0 2 (reserved) 0 1 AHB_DMA_AHBM_RST_INTER 0 0 Reset AHB_DMA_AHBM_RST_INTER Write 1 and then 0 to reset the internal AHB FSM. (R/W) AHB_DMA_ARB_PRI_DIS Configures whether to disable the priority arbitration. 0: Enable 1: Disable (R/W) AHB_DMA_CLK_EN Configures AHB DMA clock gating. 0: Support clock only when the application writes registers 1: Always force the clock on for registers (R/W) Espressif Systems 119 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) Register 3.11. AHB_DMA_IN_CONF0_CHn_REG (n: 0-2) (0x0070+0xC0*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 AHB_DMA_IN_DATA_BURST_MODE_SEL_CHn 0 7 6 AHB_DMA_IN_ETM_EN_CHn 0 5 AHB_DMA_MEM_TRANS_EN_CHn 0 4 (reserved) 0 3 AHB_DMA_INDSCR_BURST_EN_CHn 0 2 AHB_DMA_IN_LOOP_TEST_CHn 0 1 AHB_DMA_IN_RST_CHn 0 0 Reset AHB_DMA_IN_RST_CHn Write 1 and then 0 to reset RX channel n FSM and RX FIFO pointer. (R/W) AHB_DMA_IN_LOOP_TEST_CHn Configures the owner bit value for inlink write-back. (R/W) AHB_DMA_INDSCR_BURST_EN_CHn Configures whether to enable INCR burst transfer for RX channel n to read descriptors. 0: Disable 1: Enable (R/W) AHB_DMA_MEM_TRANS_EN_CHn Configures whether to enable memory-to-memory data trans- fer. 0: Disable 1: Enable (R/W) AHB_DMA_IN_ETM_EN_CHn Configures whether to enable ETM control for RX channeln. 0: Disable 1: Enable (R/W) AHB_DMA_IN_DATA_BURST_MODE_SEL_CHn Configures maximum burst length for RX chan- neln. 0: SINGLE 1: INCR4 2: INCR8 3: Reserved (R/W) Espressif Systems 120 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) Register 3.12. AHB_DMA_IN_CONF1_CHn_REG (n: 0-2) (0x0074+0xC0*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 13 AHB_DMA_IN_CHECK_OWNER_CHn 0 12 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 11 0 Reset AHB_DMA_IN_CHECK_OWNER_CHn Configures whether to enable owner bit check for RX channel n. 0: Disable 1: Enable (R/W) Register 3.13. AHB_DMA_IN_POP_CHn_REG (n: 0-2) (0x007C+0xC0*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 13 AHB_DMA_INFIFO_POP_CHn 0 12 AHB_DMA_INFIFO_RDATA_CHn 0x800 11 0 Reset AHB_DMA_INFIFO_RDATA_CHn Represents the data popped from AHB DMA RX FIFO. (RO) AHB_DMA_INFIFO_POP_CHn Configures whether to pop data from AHB DMA RX FIFO. 0: Invalid. No effect 1: Pop (WT) Espressif Systems 121 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) Register 3.14. AHB_DMA_IN_LINK_CHn_REG (n: 0-2) (0x0080+0xC0*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 5 AHB_DMA_INLINK_PARK_CHn 1 4 AHB_DMA_INLINK_RESTART_CHn 0 3 AHB_DMA_INLINK_START_CHn 0 2 AHB_DMA_INLINK_STOP_CHn 0 1 AHB_DMA_INLINK_AUTO_RET_CHn 1 0 Reset AHB_DMA_INLINK_AUTO_RET_CHn Configures whether to return to the current receive descrip- tor’s address when there are some errors in current receiving data. 0: Not return 1: Return (R/W) AHB_DMA_INLINK_STOP_CHn Configures whether to stop RX channel n from receiving data. 0: Invalid. No effect 1: Stop (WT) AHB_DMA_INLINK_START_CHn Configures whether to enable RX channel n for data transfer. 0: Disable 1: Enable (WT) AHB_DMA_INLINK_RESTART_CHn Configures whether to restart RX channel n for AHB DMA trans- fer. 0: Invalid. No effect 1: Restart (WT) AHB_DMA_INLINK_PARK_CHn Represents the status of the receive descriptor’s FSM. 0: Running 1: Idle (RO) Espressif Systems 122 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) Register 3.15. AHB_DMA_OUT_CONF0_CHn_REG (n: 0-2) (0x00D0+0xC0*(n-1)) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 10 AHB_DMA_OUT_DATA_BURST_MODE_SEL_CHn 0 9 8 (reserved) 0 7 AHB_DMA_OUT_ETM_EN_CHn 0 6 (reserved) 0 5 AHB_DMA_OUTDSCR_BURST_EN_CHn 0 4 AHB_DMA_OUT_EOF_MODE_CHn 1 3 AHB_DMA_OUT_AUTO_WRBACK_CHn 0 2 AHB_DMA_OUT_LOOP_TEST_CHn 0 1 AHB_DMA_OUT_RST_CHn 0 0 Reset AHB_DMA_OUT_RST_CHn Configures the reset state of TX channel n FSM and TX FIFO pointer. 0: Release reset 1: Reset (R/W) AHB_DMA_OUT_LOOP_TEST_CHn Configures the owner bit value for outlink write-back. (R/W) AHB_DMA_OUT_AUTO_WRBACK_CHn Configures whether to enable automatic outlink write-back when all the data in TX FIFO has been transmitted. 0: Disable 1: Enable (R/W) AHB_DMA_OUT_EOF_MODE_CHn Configures when to generate EOF flag. 0: EOF flag for TX channel n is generated when data to be transmitted has been pushed into FIFO in AHB DMA. 1: EOF flag for TX channel n is generated when data to be transmitted has been popped from FIFO in AHB DMA. (R/W) AHB_DMA_OUTDSCR_BURST_EN_CHn Configures whether to enable INCR burst transfer for TX channel n reading descriptors. 0: Disable 1: Enable (R/W) AHB_DMA_OUT_ETM_EN_CHn Configures whether to enable ETM control for TX channel n. 0: Disable 1: Enable (R/W) AHB_DMA_OUT_DATA_BURST_MODE_SEL_CHn Configures maximum burst length for TX chan- neln. 0: SINGLE 1: INCR4 2: INCR8 3: Reserved (R/W) Espressif Systems 123 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) Register 3.16. AHB_DMA_OUT_CONF1_CHn_REG (n: 0-2) (0x00D4+0xC0*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 13 AHB_DMA_OUT_CHECK_OWNER_CHn 0 12 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 11 0 Reset AHB_DMA_OUT_CHECK_OWNER_CHn Configures whether to enable owner bit check for TX chan- nel n. 0: Disable 1: Enable (R/W) Register 3.17. AHB_DMA_OUT_PUSH_CHn_REG (n: 0-2) (0x00DC+0xC0*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 10 AHB_DMA_OUTFIFO_PUSH_CHn 0 9 AHB_DMA_OUTFIFO_WDATA_CHn 0x0 8 0 Reset AHB_DMA_OUTFIFO_WDATA_CHn Represents the data that need to be pushed into AHB DMA TX FIFO. (R/W) AHB_DMA_OUTFIFO_PUSH_CHn Configures whether to push data into AHB DMA TX FIFO. 0: Invalid. No effect 1: Push (WT) Espressif Systems 124 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) Register 3.18. AHB_DMA_OUT_LINK_CHn_REG (n: 0-2) (0x00E0+0xC0*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 4 AHB_DMA_OUTLINK_PARK_CHn 1 3 AHB_DMA_OUTLINK_RESTART_CHn 0 2 AHB_DMA_OUTLINK_START_CHn 0 1 AHB_DMA_OUTLINK_STOP_CHn 0 0 Reset AHB_DMA_OUTLINK_STOP_CHn Configures whether to stop TX channel n from transmitting data. 0: Invalid. No effect 1: Stop (WT) AHB_DMA_OUTLINK_START_CHn Configures whether to enable TX channel n for data transfer. 0: Disable 1: Enable (WT) AHB_DMA_OUTLINK_RESTART_CHn Configures whether to restart TX channel n for AHB DMA transfer. 0: Invalid. No effect 1: Restart (WT) AHB_DMA_OUTLINK_PARK_CHn Represents the status of the transmit descriptor’s FSM. 0: Running 1: Idle (RO) Register 3.19. AHB_DMA_TX_CH_ARB_WEIGH_CHn_REG (n: 0-2) (0x02DC+0x28*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 4 AHB_DMA_TX_CH_ARB_WEIGH_CHn 0x0 3 0 Reset AHB_DMA_TX_CH_ARB_WEIGH_CHn Configures the weight (i.e the number of tokens) of TX chan- neln. Value range: 0 15. (R/W) Espressif Systems 125 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) Register 3.20. AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CHn_REG (n: 0-2) (0x02E0+0x28*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CHn 0 0 Reset AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CHn Configures whether to enable weight optimization for TX channel n. 0: Disable 1: Enable (R/W) Register 3.21. AHB_DMA_RX_CH_ARB_WEIGH_CHn_REG (n: 0-2) (0x0354+0x28*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 4 AHB_DMA_RX_CH_ARB_WEIGH_CHn 0x0 3 0 Reset AHB_DMA_RX_CH_ARB_WEIGH_CHn Configures the weight (i.e the number of tokens) of RX chan- neln. Value range: 0 15. (R/W) Espressif Systems 126 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) Register 3.22. AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CHn_REG (n: 0-2) (0x0358+0x28*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CHn 0 0 Reset AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CHn Configures whether to enable weight optimization for RX channel n. 0: Disable 1: Enable (R/W) Register 3.23. AHB_DMA_IN_LINK_ADDR_CHn_REG (n: 0-2) (0x03AC+0x4*n) AHB_DMA_INLINK_ADDR_CHn 0x000000 31 0 Reset AHB_DMA_INLINK_ADDR_CHn Represents the first receive descriptor’s address. (R/W) Register 3.24. AHB_DMA_OUT_LINK_ADDR_CHn_REG (n: 0-2) (0x03B8+0x4*n) AHB_DMA_OUTLINK_ADDR_CHn 0x000000 31 0 Reset AHB_DMA_OUTLINK_ADDR_CHn Represents the first transmit descriptor’s address. (R/W) Espressif Systems 127 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) Register 3.25. AHB_DMA_INTR_MEM_START_ADDR_REG (0x03C4) AHB_DMA_ACCESS_INTR_MEM_START_ADDR 0x000000 31 0 Reset AHB_DMA_ACCESS_INTR_MEM_START_ADDR Configures the start address of accessible ad- dress space. (R/W) Register 3.26. AHB_DMA_INTR_MEM_END_ADDR_REG (0x03C8) AHB_DMA_ACCESS_INTR_MEM_END_ADDR 0xffffffff 31 0 Reset AHB_DMA_ACCESS_INTR_MEM_END_ADDR Configures the end address of accessible address space. (R/W) Register 3.27. AHB_DMA_ARB_TIMEOUT_REG (0x03DC) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 AHB_DMA_ARB_TIMEOUT 0x00 15 0 Reset AHB_DMA_ARB_TIMEOUT Configures the time slot of weight arbitration. Measurement unit: AHB bus clock cycle. (R/W) Espressif Systems 128 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) Register 3.28. AHB_DMA_WEIGHT_EN_REG (0x0400) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 AHB_DMA_WEIGHT_EN 0 0 Reset AHB_DMA_WEIGHT_EN Configures whether to enable weight arbitration. 0: Disable 1: Enable (R/W) Register 3.29. AHB_DMA_DATE_REG (0x0068) AHB_DMA_DATE 0x2311290 31 0 Reset AHB_DMA_DATE Version control register. (R/W) Espressif Systems 129 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) Register 3.30. AHB_DMA_INFIFO_STATUS_CHn_REG (n: 0-2) (0x0078+0xC0*n) (reserved) 0 0 0 0 31 28 AHB_DMA_IN_BUF_HUNGRY_CHn 0 27 AHB_DMA_IN_REMAIN_UNDER_4B_CHn 1 26 AHB_DMA_IN_REMAIN_UNDER_3B_CHn 1 25 AHB_DMA_IN_REMAIN_UNDER_2B_CHn 1 24 AHB_DMA_IN_REMAIN_UNDER_1B_CHn 1 23 (reserved) 0 0 0 0 0 0 0 0 22 15 AHB_DMA_INFIFO_CNT_CHn 0 14 8 (reserved) 0 0 0 0 0 0 7 2 AHB_DMA_INFIFO_EMPTY_CHn 1 1 AHB_DMA_INFIFO_FULL_CHn 1 0 Reset AHB_DMA_INFIFO_FULL_CHn Represents whether L1 RX FIFO is full. 0: Not Full 1: Full (RO) AHB_DMA_INFIFO_EMPTY_CHn Represents whether L1 RX FIFO is empty. 0: Not empty 1: Empty (RO) AHB_DMA_INFIFO_CNT_CHn Represents the number of data bytes in L1 RX FIFO for RX channel n. (RO) AHB_DMA_IN_REMAIN_UNDER_1B_CHn Reserved. (RO) AHB_DMA_IN_REMAIN_UNDER_2B_CHn Reserved. (RO) AHB_DMA_IN_REMAIN_UNDER_3B_CHn Reserved. (RO) AHB_DMA_IN_REMAIN_UNDER_4B_CHn Reserved. (RO) AHB_DMA_IN_BUF_HUNGRY_CHn Reserved. (RO) Espressif Systems 130 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) Register 3.31. AHB_DMA_IN_STATE_CHn_REG (n: 0-2) (0x0084+0xC0*n) (reserved) 0 0 0 0 0 0 0 0 0 31 23 AHB_DMA_IN_STATE_CHn 0 22 20 AHB_DMA_IN_DSCR_STATE_CHn 0 19 18 AHB_DMA_INLINK_DSCR_ADDR_CHn 0 17 0 Reset AHB_DMA_INLINK_DSCR_ADDR_CHn Represents the lower 18 bits of the next receive descriptor address that is pre-read (but not processed yet). If the current receive descriptor is the last de- scriptor, then this field represents the address of the current receive descriptor. (RO) AHB_DMA_IN_DSCR_STATE_CHn Reserved. (RO) AHB_DMA_IN_STATE_CHn Reserved. (RO) Register 3.32. AHB_DMA_IN_SUC_EOF_DES_ADDR_CHn_REG (n: 0-2) (0x0088+0xC0*n) AHB_DMA_IN_SUC_EOF_DES_ADDR_CHn 0x000000 31 0 Reset AHB_DMA_IN_SUC_EOF_DES_ADDR_CHn Represents the address of the receive descriptor when the EOF bit in this descriptor is 1. (RO) Espressif Systems 131 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) Register 3.33. AHB_DMA_IN_ERR_EOF_DES_ADDR_CHn_REG (n: 0-2) (0x008C+0xC0*n) AHB_DMA_IN_ERR_EOF_DES_ADDR_CHn 0x000000 31 0 Reset AHB_DMA_IN_ERR_EOF_DES_ADDR_CHn Represents the address of the receive descriptor when there are some errors in the currently received data. Valid only for UHCI. (RO) Register 3.34. AHB_DMA_IN_DSCR_CHn_REG (n: 0-2) (0x0090+0xC0*n) AHB_DMA_INLINK_DSCR_CHn 0 31 0 Reset AHB_DMA_INLINK_DSCR_CHn Represents the address of the next receive descriptor x+1 pointed by the current receive descriptor that is pre-read. (RO) Register 3.35. AHB_DMA_IN_DSCR_BF0_CHn_REG (n: 0-2) (0x0094+0xC0*n) AHB_DMA_INLINK_DSCR_BF0_CHn 0 31 0 Reset AHB_DMA_INLINK_DSCR_BF0_CHn Represents the address of the current receive descriptor x that is pre-read. (RO) Espressif Systems 132 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) Register 3.36. AHB_DMA_IN_DSCR_BF1_CHn_REG (n: 0-2) (0x0098+0xC0*n) AHB_DMA_INLINK_DSCR_BF1_CHn 0 31 0 Reset AHB_DMA_INLINK_DSCR_BF1_CHn Represents the address of the previous receive descriptor x-1 that is pre-read. (RO) Register 3.37. AHB_DMA_OUTFIFO_STATUS_CHn_REG (n: 0-2) (0x00D8+0xC0*n) (reserved) 0 0 0 0 0 31 27 AHB_DMA_OUT_REMAIN_UNDER_4B_CHn 1 26 AHB_DMA_OUT_REMAIN_UNDER_3B_CHn 1 25 AHB_DMA_OUT_REMAIN_UNDER_2B_CHn 1 24 AHB_DMA_OUT_REMAIN_UNDER_1B_CHn 1 23 (reserved) 0 0 0 0 0 0 0 0 22 15 AHB_DMA_OUTFIFO_CNT_CHn 0 14 8 (reserved) 0 0 0 0 0 0 7 2 AHB_DMA_OUTFIFO_EMPTY_CHn 1 1 AHB_DMA_OUTFIFO_FULL_CHn 0 0 Reset AHB_DMA_OUTFIFO_FULL_CHn Represents whether L1 TX FIFO is full. 0: Not Full 1: Full (RO) AHB_DMA_OUTFIFO_EMPTY_CHn Represents whether L1 TX FIFO is empty. 0: Not empty 1: Empty (RO) AHB_DMA_OUTFIFO_CNT_CHn Represents the number of data bytes in L1 TX FIFO for TX channel n. (RO) AHB_DMA_OUT_REMAIN_UNDER_1B_CHn Reserved. (RO) AHB_DMA_OUT_REMAIN_UNDER_2B_CHn Reserved. (RO) AHB_DMA_OUT_REMAIN_UNDER_3B_CHn Reserved. (RO) AHB_DMA_OUT_REMAIN_UNDER_4B_CHn Reserved. (RO) Espressif Systems 133 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) Register 3.38. AHB_DMA_OUT_STATE_CHn_REG (n: 0-2) (0x00E4+0xC0*n) (reserved) 0 0 0 0 0 0 0 0 0 31 23 AHB_DMA_OUT_STATE_CHn 0 22 20 AHB_DMA_OUT_DSCR_STATE_CHn 0 19 18 AHB_DMA_OUTLINK_DSCR_ADDR_CHn 0 17 0 Reset AHB_DMA_OUTLINK_DSCR_ADDR_CHn Represents the lower 18 bits of the next transmit descrip- tor address that is pre-read (but not processed yet). If the current transmit descriptor is the last descriptor, then this field represents the address of the current transmit descriptor. (RO) AHB_DMA_OUT_DSCR_STATE_CHn Reserved. (RO) AHB_DMA_OUT_STATE_CHn Reserved. (RO) Register 3.39. AHB_DMA_OUT_EOF_DES_ADDR_CHn_REG (n: 0-2) (0x00E8+0xC0*n) AHB_DMA_OUT_EOF_DES_ADDR_CHn 0x000000 31 0 Reset AHB_DMA_OUT_EOF_DES_ADDR_CHn Represents the address of the transmit descriptor when the EOF bit in this descriptor is 1. (RO) Espressif Systems 134 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) Register 3.40. AHB_DMA_OUT_EOF_BFR_DES_ADDR_CHn_REG (n: 0-2) (0x00EC+0xC0*n) AHB_DMA_OUT_EOF_BFR_DES_ADDR_CHn 0x000000 31 0 Reset AHB_DMA_OUT_EOF_BFR_DES_ADDR_CHn Represents the address of the transmit descriptor before the last transmit descriptor. (RO) Register 3.41. AHB_DMA_OUT_DSCR_CHn_REG (n: 0-2) (0x00F0+0xC0*n) AHB_DMA_OUTLINK_DSCR_CHn 0 31 0 Reset AHB_DMA_OUTLINK_DSCR_CHn Represents the address of the next transmit descriptor y+1 pointed by the current transmit descriptor that is pre-read. (RO) Register 3.42. AHB_DMA_OUT_DSCR_BF0_CHn_REG (n: 0-2) (0x00F4+0xC0*n) AHB_DMA_OUTLINK_DSCR_BF0_CHn 0 31 0 Reset AHB_DMA_OUTLINK_DSCR_BF0_CHn Represents the address of the current transmit descriptor y that is pre-read. (RO) Espressif Systems 135 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) Register 3.43. AHB_DMA_OUT_DSCR_BF1_CHn_REG (n: 0-2) (0x00F8+0xC0*n) AHB_DMA_OUTLINK_DSCR_BF1_CHn 0 31 0 Reset AHB_DMA_OUTLINK_DSCR_BF1_CHn Represents the address of the previous transmit descriptor y-1 that is pre-read. (RO) Register 3.44. AHB_DMA_IN_PRI_CHn_REG (n: 0-2) (0x009C+0xC0*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 4 AHB_DMA_RX_PRI_CHn 0 3 0 Reset AHB_DMA_RX_PRI_CHn Configures the priority of RX channel n. The larger the value, the higher the priority. Value range: 0 5 (R/W) Register 3.45. AHB_DMA_OUT_PRI_CHn_REG (n: 0-2) (0x00FC+0xC0*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 4 AHB_DMA_TX_PRI_CHn 0 3 0 Reset AHB_DMA_TX_PRI_CHn Configures the priority of TX channel n. The larger the value, the higher the priority. Value range: 0 5 (R/W) Espressif Systems 136 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) Register 3.46. AHB_DMA_IN_PERI_SEL_CHn_REG (n: 0-2) (0x00A0+0xC0*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 6 AHB_DMA_PERI_IN_SEL_CHn 0x3f 5 0 Reset AHB_DMA_PERI_IN_SEL_CHn Configures the peripheral connected to RX channel n. 0: Dummy 1: GP-SPI 2: UHCI 3: I2S 4: Dummy 5: Dummy 6: AES 7: SHA 8: ADC 9: PARLIO 10: Dummy 11 15: Dummy 16 63: Invalid (R/W) Espressif Systems 137 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 3 GDMA Controller (GDMA) Register 3.47. AHB_DMA_OUT_PERI_SEL_CHn_REG (n: 0-2) (0x0100+0xC0*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 6 AHB_DMA_PERI_OUT_SEL_CHn 0x3f 5 0 Reset AHB_DMA_PERI_OUT_SEL_CHn Configures the peripheral connected to TX channel n. 0: Dummy 1: GP-SPI 2: UHCI 3: I2S 4: Dummy 5: Dummy 6: AES 7: SHA 8: ADC 9: PARLIO 10: Dummy 11 15: Dummy 16 63: Invalid (R/W) Espressif Systems 138 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Part II Memory Organization This part provides insights into the system’s memory structure, discussing the organization and mapping of RAM, ROM, eFuse, and external memories, offering a framework for understanding memory-related subsystems. Espressif Systems 139 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 4 System and Memory Chapter 4 System and Memory 4.1 Overview ESP32-C5 has an ultra-low power and highly-integrated system with two processors: • a high-performance 32-bit RISC-V processor (HP CPU), five-stage pipeline, clock frequency up to 240 MHz. • a low-power 32-bit RISC-V processor (LP CPU), two-stage pipeline, clock frequency up to 40 MHz or 48 MHz (See the note below). Note: ESP32-C5 supports selection of crystal frequencies, see Chapter 7 Reset and Clock. All internal memory, external memory, and peripherals are located on the HP CPU and LP CPU buses. 4.2 Features • Address Space – 720 KB of internal memory address space, accessible by the instruction bus or data bus – 832 KB of peripheral address space – 32 MB of virtual address space for external memory, accessible by the instruction bus or data bus – 384 KB of internal DMA address space – 32 MB of external DMA address space • Internal Memory – 320 KB of ROM – 384 KB of HP SRAM – 16 KB of LP SRAM • External Memory – Up to 32 MB of external flash – Up to 32 MB of external RAM • Peripheral Space – 61 modules/peripherals in total Espressif Systems 140 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 4 System and Memory • GDMA – 7 GDMA-supported modules/peripherals 4.3 Functional Description 4.3.1 Address Mapping Figure 4.3-1 illustrates the system structure and address mapping. All the non-reserved addresses are accessible via both the instruction bus and the data bus, meaning that the instruction bus and the data bus share the same address space. Both the data bus and instruction bus of the HP CPU and LP CPU are little-endian. All buses have a 32-bit data width. HP CPU and LP CPU can access data via the data bus using single-byte, double-byte, and 4-byte alignment. The HP CPU has the following access capabilities: • Direct access to internal memory via both the data bus and instruction bus – 384 KB HP SRAM (0x4080_0000 0x4085_FFFF) – 16 KB LP SRAM (0x5000_0000 0x5000_3FFF) • Access to internal memory via ROM-Cache – 320 KB ROM (0x4000_0000 0x4004_FFFF) Note: Software can access the ROM addresses in two ways: cache-able access or noncache-able access, depending on the control of CPU Physical Memory Attribution (PMA). Cache-able access is done via cache. Noncache-able access is done without cache. • Access to external memory through the cache The virtual address is mapped to the physical address space of the external memory through the MMU. – Up to 32 MB external flash (0×4200_0000 0×43FF_FFFF) – Up to 32 MB external RAM (0×4200_0000 0×43FF_FFFF) • Direct access to modules/peripherals via the data bus, including: – HP CPU Peripherals – HP Peripherals – LP Peripherals The LP CPU has the following access capabilities: • Direct access to HP SRAM and LP SRAM via both the data bus and instruction bus – 384 KB HP SRAM (0x4080_0000 0x4085_FFFF) – 16 KB LP SRAM (0x5000_0000 0x5000_3FFF) • Direct access to modules/peripherals via the data bus, including: Espressif Systems 141 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 4 System and Memory – HP Peripherals – LP Peripherals Figure 4.3-1. System Structure and Address Mapping Note: • The range of addresses available in the address space may be larger than the actual available memory of a particular type. • For CPU Sub-system, please refer to Chapter 1 High-Performance CPU [to be added later]. • Some of the address space can only be accessed by the HP CPU, not by the LP CPU, as indicated in Figure 4.3-1. This part of the address space will not be specifically distinguished in the following sections. Table 4.3-1 lists the address ranges on the data bus and instruction bus and their corresponding target memories. Table 4.3-1. Memory Address Mapping Boundary Address Bus Type Low Address High Address Size Target 0x0000_0000 0x3FFF_FFFF Reserved Data/Instruction bus 0x4000_0000 0x4004_FFFF 320 KB ROM * 0x4005_0000 0x407F_FFFF Reserved Data/Instruction bus 0x4080_0000 0x4085_FFFF 384 KB HP SRAM * Cont’d on next page Espressif Systems 142 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 4 System and Memory Table 4.3-1 – cont’d from previous page Boundary Address Bus Type Low Address High Address Size Target 0x4086_0000 0x41FF_FFFF Reserved Data/Instruction bus 0x4200_0000 0x43FF_FFFF 32 MB External memory 0x4400_0000 0x4FFF_FFFF Reserved Data/Instruction bus 0x5000_0000 0x5000_3FFF 16 KB LP SRAM * 0x5000_4000 0x5FFF_FFFF Reserved Data/Instruction bus 0x6000_0000 0x600C_FFFF 832 KB Peripherals 0x600D_0000 0xFFFF_FFFF Reserved * All of the internal memories are managed by Permission Control module. An internal memory can only be accessed when it is allowed by Permission Control, then the inter- nal memory can be available to the HP CPU and LP CPU. For more information about Permission Control, please refer to Chapter 15 Permission Control (PMS). 4.3.2 Internal Memory ESP32-C5 has various types of internal memory: • ROM (320 KB): The ROM is a read-only memory and can not be programmable. It contains the ROM code of some low-level system software and read-only data. Note that this memory can only be accessed by HP CPU. • HP SRAM (384 KB): The HP SRAM is a volatile memory that can be quickly accessed by the HP CPU or LP CPU (generally within a single HP CPU clock cycle for HP CPU). • LP SRAM (16 KB): The LP SRAM is also a volatile memory, however, in Deep-sleep mode, data stored in the LP SRAM will not be lost. The LP SRAM can be accessed by the HP CPU or LP CPU and is usually used to store program instructions and data that need to be kept in sleep mode. 4.3.2.1 ROM This 320 KB ROM is a read-only memory, accessed by the HP CPU directly through the instruction bus or through the data bus via 0x4000_0000 0x4004_FFFF or via ROM-Cache, see Table 4.3-1. As shown in Figure 4.3-2, ESP32-C5 is able to access ROM via ROM-Cache. This 4 KB ROM-Cache is two-way set associative, with a block size of 64 bytes. Both the instruction bus and the data bus can access the ROM-Cache at the same time, and the ROM-Cache responds to one or the other through arbitration. If data missing happens, ROM-Cache controller initiates a request to the ROM. Espressif Systems 143 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 4 System and Memory �: flow of control signals Figure 4.3-2. ROM-Cache Structure 4.3.2.2 HP SRAM This 384 KB HP SRAM is a read-and-write memory, accessed by the HP CPU and LP CPU through the instruction bus or data bus via their shared addresses 0×4080_0000 ∼ 0×4085_FFFF, see Table 4.3-1. 4.3.2.3 LP SRAM This 16 KB LP SRAM is a read-and-write memory, accessed by the HP CPU or LP CPU through the instruction bus or data bus via their shared addresses 0x5000_0000 0x5000_3FFF, see Table 4.3-1. LP SRAM can be accessed by the following modes: • high-speed mode, i.e., the LP SRAM is accessed in HP CPU clock frequency. In this case, HP CPU can access the LP SRAM without any latency. But the latency of LP CPU accessing LP SRAM ranges from a few dozen to dozens of LP CPU cycles. • low-speed mode, i.e., the LP SRAM is accessed in LP CPU clock frequency. In this case, LP CPU can access the LP SRAM without any latency. But the latency of HP CPU accessing LP SRAM ranges from a few dozen to dozens of HP CPU cycles. Switch the modes based on application scenarios. • If the LP CPU is not working, switch to high-speed mode to improve the access speed of the HP CPU. • If the LP CPU is executing code in the LP SRAM, switch to the low-speed mode. • If the HP CPU is in sleep mode, it is a must to switch to the low-speed mode. Mode Switch Configuration • Configure LP_AON_FAST_MEM_MUX_SEL to select the mode needed: – 0: low-speed mode – 1: high-speed mode • Set LP_AON_FAST_MEM_MUX_SEL_UPDATE to start mode switch. • Read LP_AON_FAST_MEM_MUX_SEL_STATUS to check if mode switch is done: – 0: mode is switched Espressif Systems 144 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 4 System and Memory – 1: mode is not switched 4.3.3 External Memory ESP32-C5 supports SPI, Dual SPI, Quad SPI, and QPI interfaces that allow connection to external flash and RAM. ESP32-C5 also supports hardware manual encryption and automatic decryption based on XTS-AES algorithm to protect users’ programs and data in the external flash and RAM. 4.3.3.1 External Memory Address Mapping The external memory can be accessed by HP CPU via the cache or accessed by the GDMA. According to information inside the MMU (Memory Management Unit), the cache maps the HP CPU and GDMA’s address (0x4200_0000 0x43FF_FFFF) into a physical address of the external memory. With this address mapping, ESP32-C5 can address up to 32 MB external flash and 32 MB external RAM. Note that the instruction bus shares the same address space (32 MB) with the data bus to access the external memory. 4.3.3.2 Cache As shown in Figure 4.3-3, ESP32-C5 has a shared four-way set-associative cache. Its size is 32 KB and its block size is 32 bytes. The instruction bus and data bus can access the cache simultaneously, but the cache can only respond to one of them at a time through arbitration. If a data missing happens, cache controller initiates a request to the external memory. �: flow of control signals Figure 4.3-3. Cache Structure 4.3.3.3 Cache Operations ESP32-C5 cache supports the following operations: 1. Write-back • Clears dirty bits in the tag memory and updates new data to external memory. • After the write-back operation, the new data is updated to external memory. Espressif Systems 145 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 4 System and Memory • Users can choose whether to invalidate the data in the cache. • If the data is not invalidated, HP CPU will read/write data directly from/to the cache where data missing will not occur. 2. Clean • Clears dirty bits in the tag memory without updating data to external memory. • After the clean operation, old data remains in external memory, while the cache holds the new one (unaware of it). • HP CPU can then read/write the data directly from/to the cache, where data missing will not occur. 3. Invalidate • Clean the valid bits in tag memory. This is to remove valid data from the cache. • Once this operation is done, the deleted data is stored only in external memory. • HP CPU needs to access external memory if it wants to access the data again. • Two types of invalidate operation: – Manual-Invalidate: is performed only on data in the specified cache area. – Invalidate-All: is performed on all data in the cache. 4. Preload • Loads instructions and data into the cache in advance. • Minimum unit of preload operation is one block. • Two types of preload operation: – Manual-Preload: involves the hardware prefetching continuous data based on the virtual address specified by the software. – Auto-Preload: involves the hardware prefetching continuous data based on the current address where the cache hits or misses (configuration-dependent). 5. Lock/Unlock • Lock operation prevents easily replacing data in the cache. • Two types of lock: – Prelock: locks data in the specified area when filling missing data to cache memory, leaving the data outside the specified area unlocked. – Manual Lock: checks data in the cache memory and locks data only if it falls in the specified area, leaving data outside the specified area unlocked. • When there is missing data, the cache replaces the data in the unlocked way first, ensuring that the data in the locked way remains in the cache and will not be replaced. • When all ways within the cache are locked, the cache will replace data, as if it was not locked. • Unlocking is the reverse of locking and can only be done manually. Espressif Systems 146 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 4 System and Memory • Manual-Invalidate operation only works on the unlocked data. If you plan to perform this operation on the locked data, please unlock them first. 4.3.4 GDMA Address Space The General Direct Memory Access (GDMA) peripheral in ESP32-C5 consisting of three TX channels and three RX channels provides Direct Memory Access (DMA) service, including: • data transfers between different locations of internal memory • data transfers between modules/peripherals and internal memory • data transfers between different locations of external memory • data transfers between modules/peripherals and external memory • data transfers between internal memory and external memory GDMA uses the same addresses as the data bus to access HP SRAM and external RAM, i.e., GDMA uses address range 0x4080_0000 0x4085_FFFF to access HP SRAM, and 0x4200_0000 0x43FF_FFFF to external RAM. Seven modules/peripherals in ESP32-C5 work together with GDMA. As shown in Figure 4.3-4, seven vertical lines correspond to these seven modules/peripherals with GDMA function. The horizontal line represents a certain channel of GDMA (can be any channel), and the intersection of the vertical line and the horizontal line indicates that a module/peripheral has the ability to access the corresponding channel of GDMA. Figure 4.3-4. Modules/peripherals that can work with GDMA These modules/peripherals can access any memory available to GDMA. For more information, please refer to Chapter 3 GDMA Controller (GDMA). Espressif Systems 147 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 4 System and Memory Note: When accessing a memory via GDMA, a corresponding access permission is needed, otherwise this access may fail. For more information about permission control, please refer to Chapter 15 Permission Control (PMS). 4.3.5 Modules/Peripherals Address Mapping Table 4.3-2 lists all the modules/peripherals and their respective address ranges. Note that the address space of specific modules/peripherals is defined by “Boundary Address” (including both Low Address and High Address). Table 4.3-2. Module/Peripheral Address Mapping Boundary Address Target Low Address High Address Size (KB) UART Controller 0 (UART0) 0x6000_0000 0x6000_0FFF 4 UART Controller 1 (UART1) 0x6000_1000 0x6000_1FFF 4 External Memory Encryption and Decryption (XTS_AES) 1 0x6000_2000 0x6000_2FFF 4 SPI Controller 0 (SPI0) 1 0x6000_2000 0x6000_2FFF 4 SPI Controller 1 (SPI1) 0x6000_3000 0x6000_3FFF 4 I2C Controller (I2C) 0x6000_4000 0x6000_4FFF 4 UHCI Controller (UHCI) 0x6000_5000 0x6000_5FFF 4 Remote Control Peripheral (RMT) 0x6000_6000 0x6000_6FFF 4 LED PWM Controller (LEDC) 0x6000_7000 0x6000_7FFF 4 Timer Group 0 (TIMG0) 0x6000_8000 0x6000_8FFF 4 Timer Group 1 (TIMG1) 0x6000_9000 0x6000_9FFF 4 System Timer (SYSTIMER) 0x6000_A000 0x6000_AFFF 4 Two-wire Automotive Interface 0 (TWAI0) 0x6000_B000 0x6000_BFFF 4 I2S Controller (I2S) 0x6000_C000 0x6000_CFFF 4 Two-Wire Automotive Interface 1 (TWAI1) 0x6000_D000 0x6000_DFFF 4 SAR ADC 0x6000_E000 0x6000_EFFF 4 Temperature Sensor 0x6000_E000 0x6000_EFFF 4 USB Serial/JTAG Controller (USB_SERIAL_JTAG) 0x6000_F000 0x6000_FFFF 4 Interrupt Matrix (INTMTX) 0x6001_0000 0x6001_0FFF 4 Reserved 0x6001_1000 0x6001_1FFF Pulse Count Controller (PCNT) 0x6001_2000 0x6001_2FFF 4 Event Task Matrix (SOC_ETM) 0x6001_3000 0x6001_3FFF 4 Motor Controller (MCPWM) 0x6001_4000 0x6001_4FFF 4 Parallel IO Controller (PARL_IO) 0x6001_5000 0x6001_5FFF 4 SDIO HINF 2 0x6001_6000 0x6001_6FFF 4 SDIO SLC 2 0x6001_7000 0x6001_7FFF 4 SDIO SLCHOST 2 0x6001_8000 0x6001_8FFF 4 Reserved 0x6001_6000 0x6001_9FFF Cont’d on next page Espressif Systems 148 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 4 System and Memory Table 4.3-2 – cont’d from previous page Boundary Address Target Low Address High Address Size (KB) Memory Access Monitor 2 (PSARM_MEM_MONITOR) 2 0x6001_A000 0x6001_AFFF 4 Reserved 0x6001_B000 0x6007_FFFF General DMA Controller (GDMA) 0x6008_0000 0x6008_0FFF 4 General Purpose SPI2 Controller (GP-SPI2) 0x6008_1000 0x6008_1FFF 4 Bit-scrambler (BITSCRAMBLER) 0x6008_2000 0x6008_2FFF 4 Reserved 0x6008_3000 0x6008_6FFF AES Accelerator (AES) 0x6008_8000 0x6008_8FFF 4 SHA Accelerator (SHA) 0x6008_9000 0x6008_9FFF 4 RSA Accelerator (RSA) 0x6008_A000 0x6008_AFFF 4 ECC Accelerator (ECC) 0x6008_B000 0x6008_BFFF 4 Digital Signature (DS) 0x6008_C000 0x6008_CFFF 4 HMAC Accelerator (HMAC) 0x6008_D000 0x6008_DFFF 4 ECDSA Accelerator (ECDSA) 0x6008_E000 0x6008_EFFF 4 Reserved 0x6008_F000 0x6008_FFFF IO MUX 0x6009_0000 0x6009_0FFF 4 GPIO Matrix 0x6009_1000 0x6009_1FFF 4 Memory Access Monitor 1 (TCM_MEM_MONITOR) 2 0x6009_2000 0x6009_2FFF 4 Reserved 0x6009_3000 0x6009_4FFF High-Performance System Registers (HP_SYSREG) 0x6009_5000 0x6009_5FFF 4 Power/Clock/Reset Registers (PCR) 0x6009_6000 0x6009_6FFF 4 Reserved 0x6009_7000 0x6009_7FFF Trusted Execution Environment (TEE) 2 0x6009_8000 0x6009_8FFF 4 High-Performance Access Permission Man- agement (HP_APM) 0x6009_9000 0x6009_97FF 2 Low-Power Access Permission Management (LP_APM0) 0x6009_9800 0x6009_9FFF 2 CPU Access Permission Management (CPU_APM) 0x6009_A000 0x6009_AFFF 4 Reserved 0x6009_B000 0x600A_FFFF Power Management Unit (PMU) 0x600B_0000 0x600B_03FF 1 Low-Power Clock/Reset Registers (LP_CLKRST) 0x600B_0400 0x600B_07FF 1 Reserved 0x600B_0800 0x600B_0BFF Low-Power Timer (LP_TIMER) 0x600B_0C00 0x600B_0FFF 1 Low-Power Always-on Registers (LP_AON) 0x600B_1000 0x600B_13FF 1 Low-Power UART (LP_UART) 0x600B_1400 0x600B_17FF 1 Low-Power I2C (LP_I2C) 0x600B_1800 0x600B_1BFF 1 Low-Power Watchdog Timer (LP_WDT) 0x600B_1C00 0x600B_1FFF 1 Cont’d on next page Espressif Systems 149 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 4 System and Memory Table 4.3-2 – cont’d from previous page Boundary Address Target Low Address High Address Size (KB) Reserved 0x600B_2000 0x600B_23FF I2C Analog Master (I2C_ANA_MST) 0x600B_2400 0x600B_27FF 1 Low-Power Peripherals (LPPERI) 0x600B_2800 0x600B_2BFF 1 Low-Power Analog Peripherals (LP_ANA_PERI) 0x600B_2C00 0x600B_2FFF 1 Low-Power Trusted Execution Environment (LP_TEE) 2 0x600B_3400 0x600B_37FF 1 Low-Power Access Permission Management (LP_APM) 2 0x600B_3800 0x600B_3BFF 1 Reserved 0x600B_3C00 0x600B_3FFF Low-Power IO MUX (LP_IO_MUX) 0x600B_4000 0x600B_43FF 1 Low-Power GPIO Matrix (LP_GPIO) 0x600B_4400 0x600B_47FF 1 eFuse Controller 0x600B_4800 0x600B_4FFF 2 Reserved 0x600B_5000 0x600B_FFFF RISC-V Trace Encoder (TRACE) 0x600C_0000 0x600C_0FFF 4 Reserved 0x600C_1000 0x600C_1FFF Bus Access Monitor (BUS_MONITOR) 2 0x600C_2000 0x600C_2FFF 4 Reserved 0x600C_3000 0x600C_4FFF Interrupt Priority Registers (INTPRI) 0x600C_5000 0x600C_5FFF 4 Reserved 0x600C_6000 0x600C_7FFF Cache 0x600C_8000 0x600C_8FFF 4 Reserved 0x600C_9000 0x600C_FFFF 1 The registers of External Memory Encryption and Decryption (XTS_AES) module share the same address range of 0x6000_2000 ∼ 0x6000_2FFF with SPI0 controller. 2 The address space of this module/peripheral is not continuous. Note: As shown in Figure 4.3-1, • HP CPU can access all peripherals listed in Table 4.3-2. • LP CPU can access all peripherals listed in Table 4.3-2, except RISC-V Trace Encoder (TRACE), DEBUG ASSIST (ASSIST_DEBUG), Interrupt Priority Registers (INTPRI), and Cache. Espressif Systems 150 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Chapter 5 eFuse Controller (eFuse) 5.1 Overview ESP32-C5 contains a 4096-bit eFuse memory to store parameters and user data. The parameters include control parameters for some hardware modules, system data parameters and keys used for the encryption/decryption module. Once an eFuse bit is programmed to 1, it can never be reverted to 0. The eFuse controller programs bits in eFuse according to user configurations. From outside the chip, eFuse data can only be read via the eFuse controller. For some data, such as some keys stored in eFuse for internal use by hardware cryptography modules (e.g., digital signature, HMAC), if read protection is not enabled, the data can be read from outside the chip; if read protection is enabled, the data cannot be read from outside the chip. 5.2 Features • 4096-bit one-time programmable memory (including up to 1792 bits reserved for custom use; depending on whether the EFUSE_KEY_PURPOSE_n parameters are set to 0. For more information, see Table 5.3-2.) • Configurable write protection • Configurable read protection • Various hardware encoding schemes against data corruption 5.3 Functional Description 5.3.1 Structure The eFuse system consists of the eFuse controller and eFuse memory. Data flow in this system is shown in Figure 5.3-1. Users can program bits in the eFuse memory via the eFuse controller by writing the data to the programming register and executing the programming instruction. For detailed programming steps, please refer to Section 5.3.2. Users cannot directly read the data programmed in the eFuse memory, so they need to read the programmed data into the Reading Data Register of the corresponding address segment through the eFuse controller. During the reading process, if the data is inconsistent with that in the eFuse memory, the eFuse controller can automatically correct it through the hardware encoding mechanism (see Section 5.3.1.3 for details), and send the error message to the error report register. For detailed steps to read parameters, please refer to the Section 5.3.3. Espressif Systems 151 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Figure 5.3-1. Data Flow in eFuse Data in eFuse memory is organized in 11 blocks (BLOCK0 BLOCK10). BLOCK0 holds most parameters for software and hardware uses. Table 5.3-1 lists all the parameters accessible (readable and usable) to users in BLOCK0 and their bit widths, accessibility by hardware, write protection, and brief function description. For more description on the parameters, please click the link of the corresponding parameter in the table. The EFUSE_WR_DIS parameter is used to control write protection of other parameters in BLOCK0–BLOCK10. EFUSE_RD_DIS is used to control read protection of BLOCK4 BLOCK10. For more information on these two parameters, please see Section 5.3.1.1 and Section 5.3.1.2. Espressif Systems 152 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Table 5.3-1. Parameters in eFuse BLOCK0 Parameters Bit Width Accessible by Hardware Write Protection by EFUSE_WR_DIS Bit Number Description EFUSE_WR_DIS 32 Y N/A Represents whether programming of individual eFuse mem- ory bit is disabled. EFUSE_RD_DIS 7 Y 0 Represents whether reading of individual eFuse block (BLOCK4 BLOCK10) is disabled. EFUSE_BOOTLOADER_ANTI_ROLLBACK_- SECURE_VERSION_HI 1 N N/A Represents the anti-rollback secure version of the 2nd stage bootloader used by the ROM bootloader (the high part of the field). EFUSE_DIS_ICACHE 1 Y 2 Represents whether cache is disabled. EFUSE_DIS_USB_JTAG 1 Y 2 Represents whether the USB-to-JTAG function in USB Se- rial/JTAG is disabled. EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN 1 N N/A Represents whether the ani-rollback check for the 2nd stage bootloader is enabled. EFUSE_DIS_FORCE_DOWNLOAD 1 Y 2 Represents whether the function that forces chip into Down- load mode is disabled. EFUSE_SPI_DOWNLOAD_MSPI_DIS 1 Y 2 Represents whether SPI0 controller during boot_mode_download is disabled. EFUSE_DIS_TWAI 1 Y 2 Represents whether TWAI ® function is disabled. EFUSE_JTAG_SEL_ENABLE 1 Y 2 Represents whether the selection of a JTAG signal source through the strapping pin value is enabled when all of EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are configured to 0. For more information, please refer to Chap- ter 8 Chip Boot Control. EFUSE_SOFT_DIS_JTAG 3 Y 31 Represents whether PAD JTAG is disabled in the soft way. It can be restarted via HMAC. Cont’d on next page Espressif Systems 153 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Table 5.3-1 – cont’d from previous page Parameters Bit Width Accessible by Hardware Write Protection by EFUSE_WR_DIS Bit Number Description EFUSE_DIS_PAD_JTAG 1 Y 2 Represents whether PAD JTAG is disabled in the hard way (permanently). EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT 1 Y 2 Represents whether flash encryption is disabled (except in SPI boot mode). EFUSE_USB_EXCHG_PINS 1 Y 30 Represents whether the D+ and D- pins is exchanged. EFUSE_VDD_SPI_AS_GPIO 1 Y 30 Represents whether VDD SPI pin is functioned as GPIO. EFUSE_WDT_DELAY_SEL 2 Y 3 Represents RTC watchdog timeout threshold. EFUSE_BOOTLOADER_ANTI_ROLLBACK_- SECURE_VERSION_LO 3 N N/A Represents the anti-rollback secure version of the second stage bootloader used by the first stage (ROM bootloader (the low part of the field). EFUSE_KM_DISABLE_DEPLOY_MODE 4 Y 1 Represents whether the new key deployment of key man- ager is disabled. EFUSE_KM_RND_SWITCH_CYCLE 2 Y 1 Represents the cycle at which the Key Manager switches random numbers. EFUSE_KM_DEPLOY_ONLY_ONCE 4 Y 1 Represents whether the corresponding key can be deployed only once. EFUSE_FORCE_USE_KEY_MANAGER_KEY 4 Y 1 Represents whether the corresponding key must come from Key Manager. EFUSE_FORCE_DISABLE_SW_INIT_KEY 1 Y 1 Represents whether to disable the use of the initialization key written by software and instead force use efuse_init_key. EFUSE_BOOTLOADER_ANTI_ROLLBACK_- UPDATE_IN_ROM 1 N N/A Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM bootloader. EFUSE_SPI_BOOT_CRYPT_CNT 3 Y 4 Represents whether SPI boot encryption/decryption is en- abled. EFUSE_SECURE_BOOT_KEY_REVOKE0 1 N 5 Represents whether revoking Secure Boot key digest 0 is enabled. Cont’d on next page Espressif Systems 154 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Table 5.3-1 – cont’d from previous page Parameters Bit Width Accessible by Hardware Write Protection by EFUSE_WR_DIS Bit Number Description EFUSE_SECURE_BOOT_KEY_REVOKE1 1 N 6 Represents whether revoking Secure Boot key digest 1 is enabled. EFUSE_SECURE_BOOT_KEY_REVOKE2 1 N 7 Represents whether revoking Secure Boot key digest 2 is enabled. EFUSE_KEY_PURPOSE_0 5 Y 8 Represents the purpose of Key0. See Table 5.3-2. EFUSE_KEY_PURPOSE_1 5 Y 9 Represents the purpose of Key1. See Table 5.3-2. EFUSE_KEY_PURPOSE_2 5 Y 10 Represents the purpose of Key2. See Table 5.3-2. EFUSE_KEY_PURPOSE_3 5 Y 11 Represents the purpose of Key3. See Table 5.3-2. EFUSE_KEY_PURPOSE_4 5 Y 12 Represents the purpose of Key4. See Table 5.3-2. EFUSE_KEY_PURPOSE_5 5 Y 13 Represents the purpose of Key5. See Table 5.3-2. EFUSE_SEC_DPA_LEVEL 2 Y 14 Represents the security level of anti-DPA attack. The level is adjusted by configuring the clock random frequency division mode. EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI 3 N N/A Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM boot- loader If the primary bootloader fails. 0 and 0xFFF - this fea- ture is disabled. (The high part of the field). EFUSE_SECURE_BOOT_EN 1 N 15 Represents whether Secure Boot is enabled. EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE 1 N 16 Represents whether aggressive revocation of Secure Boot is enabled. EFUSE_KM_XTS_KEY_LENGTH_256 1 N 1 Represents which key flash encryption uses. EFUSE_FLASH_TPUW 4 N 18 Represents the flash waiting time after power-up. Measure- ment unit: ms. When the value is less than 15, the waiting time is the programmed value. Otherwise, the waiting time is a fixed value, i.e. 30 ms. EFUSE_DIS_DOWNLOAD_MODE 1 N 18 Represents whether Download mode is disabled. Cont’d on next page Espressif Systems 155 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Table 5.3-1 – cont’d from previous page Parameters Bit Width Accessible by Hardware Write Protection by EFUSE_WR_DIS Bit Number Description EFUSE_DIS_DIRECT_BOOT 1 N 18 Represents whether direct boot mode is disabled. EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT 1 N 18 Represents whether print from USB-Serial-JTAG is disabled. EFUSE_LOCK_KM_KEY 1 N 1 Represents whether the keys in the Key Manager are locked after deployment. EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE 1 N 18 Represents whether the USB-Serial-JTAG download func- tion is disabled. EFUSE_ENABLE_SECURITY_DOWNLOAD 1 N 18 Represents whether security download is enabled. Only downloading into flash is supported. Reading/writing RAM or registers is not supported (i.e. stub download is not sup- ported). EFUSE_UART_PRINT_CONTROL 2 N 18 Represents the type of UART printing. EFUSE_FORCE_SEND_RESUME 1 N 18 Represents whether ROM code is forced to send a resume command during SPI boot. EFUSE_SECURE_VERSION 9 N 18 Represents the app security version used by ESP-IDF anti- rollback feature. EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE 1 N 18 Represents whether FAST VERIFY ON WAKE is disabled when Secure Boot is enabled. EFUSE_HYS_EN_PAD 1 Y 2 Represents whether the hysteresis function of PAD0 – PAD27 is enabled. EFUSE_XTS_DPA_PSEUDO_LEVEL 2 Y 14 Represents the pseudo round level of XTS-AES anti-DPA at- tack. EFUSE_XTS_DPA_CLK_ENABLE 1 Y 14 Represents whether XTS-AES anti-DPA attack clock is en- abled. EFUSE_ECDSA_P384_ENABLE 1 N 14 Represents if the chip supports ECDSA P384 EFUSE_HUK_GEN_STATE 9 Y 19 Represents whether the HUK generate mode is valid. Cont’d on next page Espressif Systems 156 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Table 5.3-1 – cont’d from previous page Parameters Bit Width Accessible by Hardware Write Protection by EFUSE_WR_DIS Bit Number Description EFUSE_XTAL_48M_SEL 3 Y 17 Determines the frequency of the XTAL clock alone in SPI Boot mode, or together with EFUSE_XTAL_48M_SEL_MODE in Joint Download Boot mode. For more information, please refer to Chapter 8 Chip Boot Control. EFUSE_XTAL_48M_SEL_MODE 1 Y 17 Represents what determines the XTAL frequency in Joint Download Boot mode. For more information, please refer to Chapter 8 Chip Boot Control. EFUSE_ECC_FORCE_CONST_TIME 1 Y 14 Represents whether to force ECC to use constant-time mode for point multiplication calculation. EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO 9 N N/A Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM boot- loader If the primary bootloader fails. 0 and 0xFFF - this fea- ture is disabled. (The low part of the field). Espressif Systems 157 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Table 5.3-2 lists all key purposes and their values. Setting the eFuse parameter EFUSE_KEY_PURPOSE_n declares the purpose of KEYn (n: 0 5). Table 5.3-2. Secure Key Purpose Values Key Purpose Values Purposes 0 User purposes 1 ECDSA_KEY 2 XTS_AES_256_KEY_1 3 XTS_AES_256_KEY_2 4 XTS_AES_128_KEY (flash/SRAM encryption and decryption) 5 HMAC Downstream mode (both JTAG and DS) 6 JTAG in HMAC Downstream mode 7 Digital Signature peripheral in HMAC Downstream mode 8 HMAC Upstream mode 9 SECURE_BOOT_DIGEST0 (secure boot key digest) 10 SECURE_BOOT_DIGEST1 (secure boot key digest) 11 SECURE_BOOT_DIGEST2 (secure boot key digest) Table 5.3-3 provides the details of parameters in BLOCK1 BLOCK10. Espressif Systems 158 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Table 5.3-3. Parameters in BLOCK1 to BLOCK10 BLOCK Parameters Bit Width Accessible by Hardware Write Protection by EFUSE_WR_DIS Bit Number Read Protection by EFUSE_RD_DIS Bit Number Description BLOCK1 EFUSE_MAC 48 N 20 N/A MAC address EFUSE_MAC_EXT 16 N 20 N/A Extended MAC address EFUSE_SYS_DATA_PART0 78 N 20 N/A System data BLOCK2 EFUSE_SYS_DATA_PART1 256 N 21 N/A System data BLOCK3 EFUSE_USR_DATA 256 N 22 N/A User data BLOCK4 EFUSE_KEY0_DATA 256 Y 23 0 KEY0 or user data BLOCK5 EFUSE_KEY1_DATA 256 Y 24 1 KEY1 or user data BLOCK6 EFUSE_KEY2_DATA 256 Y 25 2 KEY2 or user data BLOCK7 EFUSE_KEY3_DATA 256 Y 26 3 KEY3 or user data BLOCK8 EFUSE_KEY4_DATA 256 Y 27 4 KEY4 or user data BLOCK9 EFUSE_KEY5_DATA 256 Y 28 5 KEY5 or user data BLOCK10 EFUSE_SYS_DATA_PART2 256 N 29 6 System data Espressif Systems 159 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Among these blocks, BLOCK4 9 can be used to store KEY0 5. Up to six 256-bit keys can be written into eFuse. Whenever a key is written, its purpose value should also be written (see table 5.3-2). For example, when a key for the JTAG function in HMAC Downstream mode is written to KEY3 (i.e., BLOCK7), its key purpose value 6 should also be written to EFUSE_KEY_PURPOSE_3. BLOCK1 BLOCK10 use the Reed-Solomon (RS) coding scheme, so there are some limitations on writing to these parameters. For more detailed information, please refer to Section 5.3.1.3 and Section 5.3.2. 5.3.1.1 EFUSE_WR_DIS Parameter EFUSE_WR_DIS determines whether individual eFuse parameters are write-protected. After EFUSE_WR_DIS has been programmed, execute an eFuse read operation so the new values would take effect. Column “Write Protection by EFUSE_WR_DIS Bit Number” in Table 5.3-1 and Table 5.3-3 lists the specific bits in EFUSE_WR_DIS that disable writing. When the write protection bit of a parameter is set to 0, it means that this parameter is not write-protected and can be programmed, unless it has been programmed before. When the write protection bit of a parameter is set to 1, it means that this parameter is write-protected and none of its bits can be modified, with non-programmed bits always remaining 0 and programmed bits always remaining 1. That is to say, if a parameter is write-protected, it will always remain in this state and cannot be changed. 5.3.1.2 EFUSE_RD_DIS Only the parameters in BLOCK4 BLOCK10 can be set to be read-protected from users, as shown in column “Read Protection by EFUSE_RD_DIS Bit Number” of Table 5.3-3. After EFUSE_RD_DIS has been programmed, execute an eFuse read operation so the new values would take effect. If the corresponding EFUSE_RD_DIS bit is 0, the parameter controlled by this bit is not read-protected from users. If it is 1, the parameter controlled by it is read-protected from users. Other parameters that are not in BLOCK4 BLOCK10 can always be read by users. When BLOCK4 BLOCK10 are set to be read-protected, the data in them can still be read by hardware cryptography modules if the EFUSE_KEY_PURPOSE_n bit is set accordingly. 5.3.1.3 Data Storage Internally, eFuse uses the hardware encoding scheme to protect data from corruption. The scheme and the encoding process are invisible to users. All BLOCK0 parameters except for EFUSE_WR_DIS are stored with four backups, meaning each bit is stored four times. This backup scheme is not visible to users. In BLOCK0, EFUSE_WR_DIS occupies 32 bits, and other parameters takes 152 bits each. So, the eFuse memory space occupied by BLOCK0 is 32 + 152 * 4 = 640 bits. BLOCK1 BLOCK10 use RS (44, 32) coding scheme that supports up to 6 bytes of automatic error correction. The primitive polynomial of RS (44, 32) is p(x) = x 8 + x 4 + x 3 + x 2 + 1. Espressif Systems 160 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Figure 5.3-2. Shift Register Circuit (first 32 output) Figure 5.3-3. Shift Register Circuit (last 12 output) The shift register circuit shown in Figure 5.3-2 and 5.3-3 processes 32 data bytes using RS (44, 32). This coding scheme encodes 32 bytes of data into 44 bytes: • Bytes [0:31] are the data bytes itself • Bytes [32:43] are the encoded parity bytes stored in 8-bit flip-flops DFF1, DFF2, ..., DFF12 (gf_mul_n is the result of multiplying a byte of data in GF (2 8 ) by α n , where n is an integer). After that, the hardware programs into eFuse the 44-byte codeword consisting of the data bytes and the parity bytes. When the eFuse block is read, the eFuse controller automatically decodes the codeword and applies error correction if needed. Because the RS check codes are generated on the entire 32-byte eFuse block, each block can only be written once. Since the size of BLOCK1 is less than 32 bytes, the unused bytes will be treated as 0 by hardware during the RS (44, 32) encoding. Thus, the final coding result will not be affected. Among blocks using the RS (44, 32) coding scheme, the parameters in BLOCK1 is 24 bytes, and the RS check code is 12 bytes, so BLOCK1 occupies 24 + 12 = 36 bytes in eFuse memory. The parameter in other blocks (Block2 10) is 32 bytes respectively, and the RS check code is 12 bytes, so they occupy (32 + 12) * 9 = 396 bytes in eFuse memory. Espressif Systems 161 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) 5.3.2 Programming of Parameters The eFuse controller can only program eFuse parameters in one block at a time. BLOCK0 BLOCK10 share the same address range to store the parameters to be programmed. Configure parameter EFUSE_BLK_NUM to indicate which block to program. Each programming register corresponds to a reading register (see Table 5.3-4 for details). To find the data’s programming location, refer to the parameter’s location in the reading registers. For example, to program EFUSE_USB_EXCHG_PINS in BLOCK0: 1. Identify its location in the reading data registers, which is the 25th bit in EFUSE_RD_REPEAT_DATA0_REG 2. Set the 25th bit in EFUSE_PGM_DATA1_REG to 1. 3. Follow the steps below to program the bit in eFuse memory. Programming preparation • Check clock frequency – When the external crystal oscillator frequency of the chip is 40 MHz, the eFuse controller operates at 20 MHz. Set EFUSE_TPGM to 0xC8. – When the external crystal oscillator frequency of the chip is 48 MHz, the eFuse controller operates at 24 MHz. Set EFUSE_TPGM to 0xF0. • Program BLOCK0 1. Set EFUSE_BLK_NUM to 0. 2. Write into EFUSE_PGM_DATA0_REG EFUSE_PGM_DATA5_REG the data to be programmed to BLOCK0. The data in EFUSE_PGM_DATA6_REG EFUSE_PGM_DATA7_REG and EFUSE_PGM_CHECK_VALUE0_REG EFUSE_PGM_CHECK_VALUE2_REG does not affect the programming of BLOCK0. • BLOCK1 cannot be programmed by users as it has been programmed at manufacturing. • Program BLOCK2 10 1. Set EFUSE_BLK_NUM to the block number. 2. Write into EFUSE_PGM_DATA0_REG EFUSE_PGM_DATA7_REG the data to be programmed. Write into EFUSE_PGM_CHECK_VALUE0_REG EFUSE_PGM_CHECK_VALUE2_REG the corresponding RS code. Programming process The process of programming parameters is as follows: 1. Configure the value of parameter EFUSE_BLK_NUM to determine the block to be programmed. 2. Write parameters to be programmed to registers EFUSE_PGM_DATA0_REG EFUSE_PGM_DATA7_REG and EFUSE_PGM_CHECK_VALUE0_REG EFUSE_PGM_CHECK_VALUE2_REG. 3. Make sure the eFuse programming voltage VDDQ is configured correctly as described in Section 5.3.4. 4. Configure the field EFUSE_OP_CODE of register EFUSE_CONF_REG to 0x5A5A. Espressif Systems 162 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) 5. Configure the field EFUSE_PGM_CMD of register EFUSE_CMD_REG to 1. 6. Poll register EFUSE_CMD_REG until it is 0x0, or wait for a PGM_DONE interrupt. For more information on how to identify a PGM_DONE or READ_DONE interrupt, please see the end of Section 5.3.3. 7. Clear the parameters in EFUSE_PGM_DATA0_REG EFUSE_PGM_DATA7_REG and EFUSE_PGM_CHECK_VALUE0_REG EFUSE_PGM_CHECK_VALUE2_REG. 8. Trigger an eFuse read operation (see Section 5.3.3) to update eFuse registers with the new values. 9. Check error record registers. If the values read in error record registers are not 0, the programming process should be performed again following above steps 1 7. Please check the following error record registers for different eFuse blocks: • BLOCK0: EFUSE_RD_REPEAT_DATA_ERR0_REG EFUSE_RD_REPEAT_DATA_ERR4_REG • BLOCK1: EFUSE_RD_MAC_SYS_ERR_NUM, EFUSE_RD_MAC_SYS_FAIL • BLOCK2: EFUSE_RD_SYS_PART1_DATA_ERR_NUM, EFUSE_RD_SYS_PART1_DATA_FAIL • BLOCK3: EFUSE_RD_USR_DATA_ERR_NUM, EFUSE_RD_USR_DATA_FAIL • BLOCK4: EFUSE_RD_KEY0_DATA_ERR_NUM, EFUSE_RD_KEY0_DATA_FAIL • BLOCK5: EFUSE_RD_KEY1_DATA_ERR_NUM, EFUSE_RD_KEY1_DATA_FAIL • BLOCK6: EFUSE_RD_KEY2_DATA_ERR_NUM, EFUSE_RD_KEY2_DATA_FAIL • BLOCK7: EFUSE_RD_KEY3_DATA_ERR_NUM, EFUSE_RD_KEY3_DATA_FAIL • BLOCK8: EFUSE_RD_KEY4_DATA_ERR_NUM, EFUSE_RD_KEY4_DATA_FAIL • BLOCK9: EFUSE_RD_KEY5_DATA_ERR_NUM, EFUSE_RD_KEY5_DATA_FAIL • BLOCK10: EFUSE_RD_SYS_PART2_DATA_ERR_NUM, EFUSE_RD_SYS_PART2_DATA_FAIL Limitations In BLOCK0, each bit can be programmed separately. However, we recommend to minimize programming cycles and program all the bits of a parameter in one programming action. In addition, after all parameters controlled by a certain bit of EFUSE_WR_DIS are programmed, that bit should be immediately programmed. The programming of parameters controlled by a certain bit of EFUSE_WR_DIS, and the programming of the bit itself can even be completed at the same time in one programming action. BLOCK1 cannot be programmed by users as it has been programmed at manufacturing. BLOCK2 10 can only be programmed once. Repeated programming is not allowed. 5.3.3 Reading of Parameters Users cannot read eFuse bits directly. The eFuse controller hardware reads all eFuse bits and stores the results to their corresponding registers in its memory space. Then, users can read eFuse bits by reading the registers that start with EFUSE_RD_. Details are provided in Table 5.3-4. Espressif Systems 163 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Table 5.3-4. Registers Information BLOCK Read Registers Registers When Programming This Block 0 EFUSE_RD_WR_DIS0_REG EFUSE_PGM_DATA0_REG 0 EFUSE_RD_REPEAT_DATAn_REG (n: 0 4) EFUSE_PGM_DATAn_REG (n: 1 5) 1 EFUSE_RD_MAC_SYS_n_REG (n: 0 5) EFUSE_PGM_DATAn_REG (n: 0 5) 2 EFUSE_RD_SYS_PART1_DATAn_REG (n: 0 7) EFUSE_PGM_DATAn_REG (n: 0 7) 3 EFUSE_RD_USR_DATAn_REG (n: 0 7) EFUSE_PGM_DATAn_REG (n: 0 7) 4-9 EFUSE_RD_KEYn_DATAm_REG (n: 0 5) (m: 0 7) EFUSE_PGM_DATAn_REG (n: 0 7) 10 EFUSE_RD_SYS_PART2_DATAn_REG (n: 0 7) EFUSE_PGM_DATAn_REG (n: 0 7) Updating reading data registers The eFuse controller reads eFuse memory to update corresponding registers. This read operation happens at system reset and can also be triggered manually by users as needed (e.g., if new eFuse values have been programmed). The process of triggering a read operation by users is as follows: 1. Configure the field EFUSE_OP_CODE in register EFUSE_CONF_REG to 0x5AA5. 2. Configure the field EFUSE_READ_CMD in register EFUSE_CMD_REG to 1. 3. Poll register EFUSE_CMD_REG until it is 0x0, or wait for a READ_DONE interrupt. Information on how to identify a PGM_DONE or READ_DONE interrupt is provided below in this section. 4. Read the values of each parameter from eFuse memory. The eFuse read registers will hold all values until the next read operation. Error detection The programming error record registers allow users to check the integrity of parameters stored in the eFuse memory. For instance, they can help detect whether the four-backup parameters are consistent and whether parameters protected by RS encoding are decoded successfully. Registers EFUSE_RD_REPEAT_DATA_ERRn_REG (n: 0 3) indicate if there are any errors in programming parameters (except EFUSE_WR_DIS) to BLOCK0. The value 1 indicates an error is detected in programming the corresponding bit. The value 0 indicates no error. Registers EFUSE_RD_RS_DATA_ERRn_REG (n: 0 1) store the number of corrected bytes as well as the result of RS decoding when eFuse controller reads BLOCK1 BLOCK10. The values of the above registers will be updated every time the reading data registers of eFuse controller have been updated. Identifying completion of program or read operations The methods to identify the completion of a program/read operation are described below. Please note that bit 1 corresponds to a program operation, and bit 0 corresponds to a read operation. • Method one: Poll bit 1/0 in register EFUSE_INT_RAW_REG until it becomes 1, which represents the completion of a program/read operation. • Method two: 1. Set bit 1/0 in register EFUSE_INT_ENA_REG to 1 to enable the eFuse controller to post a PGM_DONE or READ_DONE interrupt. Espressif Systems 164 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) 2. Configure the Interrupt Matrix to enable the CPU to respond to eFuse interrupt signals. See Chapter 9 Interrupt Matrix. 3. Wait for the PGM_DONE or READ_DONE interrupt. 4. Set bit 1/0 in register EFUSE_INT_CLR_REG to 1 to clear the PGM_DONE or READ_DONE interrupt. Note When eFuse controller is updating its registers, it will use EFUSE_PGM_DATAn_REG (n=0, 1, ... ,7) again to store data. So please do not write important data into these registers before this updating process is initiated. During the chip boot process, eFuse controller will automatically update data from eFuse memory into the registers that can be accessed by users. Users can get programmed eFuse data by reading corresponding registers. Thus, there is no need to update the reading data registers in such case. 5.3.4 eFuse VDDQ Timing In the eFuse controller, the timing parameters of the programming voltage VDDQ should be configured as follows: • EFUSE_DAC_NUM (the rising period of VDDQ): The default value of VDDQ is 2.5 V and the voltage increases by 0.01 V in each clock cycle. The default value of this parameter is 255. • EFUSE_DAC_CLK_DIV (the clock divisor of VDDQ): The clock period to program VDDQ should be larger than 1 µs. • EFUSE_PWR_ON_NUM (the power-up time for VDDQ): The programming voltage should be stabilized after this time, which means the value of this parameter should be configured to exceed the result of EFUSE_DAC_CLK_DIV times EFUSE_DAC_NUM. • EFUSE_PWR_OFF_NUM (the power-out time for VDDQ): The value of this parameter should be larger than 10 µs. The default configuration of VDDQ timing parameters is shown in Table 5.3-5. Table 5.3-5. Default Configuration of VDDQ Timing Parameters EFUSE_DAC_NUM EFUSE_DAC_CLK_DIV EFUSE_PWR_ON_NUM EFUSE_PWR_OFF_NUM 0xFF 0x28 0x3000 0x190 5.3.5 Parameters Used by Hardware Modules Some hardware modules are directly connected to the eFuse peripheral in order to use the parameters that are marked with “Y” in columns “Accessible by Hardware” of Table 5.3-1 and Table 5.3-3. Users cannot intervene in this process. 5.4 Interrupts ESP32-C5’s eFuse controller can generate the following interrupt signal that will be sent to the Interrupt Matrix. • EFUSE_INT Espressif Systems 165 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) There are several internal interrupt sources from eFuse controller that can generate the above interrupt signal. The interrupt sources from eFuse controller are listed with their trigger conditions and the resulted interrupt signal in Table 5.4-1. Table 5.4-1. eFuse’s Internal Interrupt Sources Internal Interrupt Source Trigger Condition Interrupt Signal EFUSE_PGM_DONE_INT Programming of eFuse completes EFUSE_INT EFUSE_READ_DONE_INT Reading of eFuse completes Note: For definitions of interrupt, interrupt signal, interrupt source, and their correlations, please refer to Chapter 9 Interrupt Matrix > Section 9.2 Terminology. Each interrupt source can be configured by a common set of registers that are described in Section Interrupt Configuration Registers. The specific registers can be found in Section 5.5 Register Summary. Espressif Systems 166 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) 5.5 Register Summary The addresses in this section are relative to eFuse controller base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Programming Data Registers EFUSE_PGM_DATA0_REG Register 0 that stores data to be pro- grammed 0x0000 R/W EFUSE_PGM_DATA1_REG Register 1 that stores data to be pro- grammed 0x0004 R/W EFUSE_PGM_DATA2_REG Register 2 that stores data to be pro- grammed 0x0008 R/W EFUSE_PGM_DATA3_REG Register 3 that stores data to be pro- grammed 0x000C R/W EFUSE_PGM_DATA4_REG Register 4 that stores data to be pro- grammed 0x0010 R/W EFUSE_PGM_DATA5_REG Register 5 that stores data to be pro- grammed 0x0014 R/W EFUSE_PGM_DATA6_REG Register 6 that stores data to be pro- grammed 0x0018 R/W EFUSE_PGM_DATA7_REG Register 7 that stores data to be pro- grammed 0x001C R/W EFUSE_PGM_CHECK_VALUE0_REG Register 0 that stores the RS code to be programmed 0x0020 R/W EFUSE_PGM_CHECK_VALUE1_REG Register 1 that stores the RS code to be programmed 0x0024 R/W EFUSE_PGM_CHECK_VALUE2_REG Register 2 that stores the RS code to be programmed 0x0028 R/W Reading Data Registers for BLOCK0 EFUSE_RD_WR_DIS_REG BLOCK0 data register 0 that repre- sents whether programming of individual eFuse memory bit is disabled 0x002C RO EFUSE_RD_REPEAT_DATA0_REG BLOCK0 data register 1 0x0030 RO EFUSE_RD_REPEAT_DATA1_REG BLOCK0 data register 2 0x0034 RO EFUSE_RD_REPEAT_DATA2_REG BLOCK0 data register 3 0x0038 RO EFUSE_RD_REPEAT_DATA3_REG BLOCK0 data register 4 0x003C RO EFUSE_RD_REPEAT_DATA4_REG BLOCK0 data register 5 0x0040 RO Reading Data Registers for BLOCK1 EFUSE_RD_MAC_SYS0_REG Register 0 for BLOCK1 0x0044 RO EFUSE_RD_MAC_SYS1_REG Register 1 for BLOCK1 0x0048 RO EFUSE_RD_MAC_SYS3_REG Register 3 for BLOCK1 0x0050 RO EFUSE_RD_MAC_SYS4_REG Register 4 for BLOCK1 0x0054 RO Espressif Systems 167 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Name Description Address Access EFUSE_RD_MAC_SYS5_REG Register 5 for BLOCK1 0x0058 RO Reading Data Registers for BLOCK2 EFUSE_RD_SYS_PART1_DATA0_REG Register 0 for BLOCK2 (system) 0x005C RO EFUSE_RD_SYS_PART1_DATA1_REG Register 1 for BLOCK2 (system) 0x0060 RO EFUSE_RD_SYS_PART1_DATA2_REG Register 2 for BLOCK2 (system) 0x0064 RO EFUSE_RD_SYS_PART1_DATA3_REG Register 3 for BLOCK2 (system) 0x0068 RO EFUSE_RD_SYS_PART1_DATA4_REG Register 4 for BLOCK2 (system) 0x006C RO EFUSE_RD_SYS_PART1_DATA5_REG Register 5 for BLOCK2 (system) 0x0070 RO EFUSE_RD_SYS_PART1_DATA6_REG Register 6 for BLOCK2 (system) 0x0074 RO EFUSE_RD_SYS_PART1_DATA7_REG Register 7 for BLOCK2 (system) 0x0078 RO Reading Data Registers for BLOCK3 EFUSE_RD_USR_DATA0_REG Register 0 for BLOCK3 (user) 0x007C RO EFUSE_RD_USR_DATA1_REG Register 1 for BLOCK3 (user) 0x0080 RO EFUSE_RD_USR_DATA2_REG Register 2 for BLOCK3 (user) 0x0084 RO EFUSE_RD_USR_DATA3_REG Register 3 for BLOCK3 (user) 0x0088 RO EFUSE_RD_USR_DATA4_REG Register 4 for BLOCK3 (user) 0x008C RO EFUSE_RD_USR_DATA5_REG Register 5 for BLOCK3 (user) 0x0090 RO EFUSE_RD_USR_DATA6_REG Register 6 for BLOCK3 (user) 0x0094 RO EFUSE_RD_USR_DATA7_REG Register 7 for BLOCK3 (user) 0x0098 RO Reading Data Registers for BLOCK4 EFUSE_RD_KEY0_DATA0_REG Register 0 for BLOCK4 (KEY0) 0x009C RO EFUSE_RD_KEY0_DATA1_REG Register 1 for BLOCK4 (KEY0) 0x00A0 RO EFUSE_RD_KEY0_DATA2_REG Register 2 for BLOCK4 (KEY0) 0x00A4 RO EFUSE_RD_KEY0_DATA3_REG Register 3 for BLOCK4 (KEY0) 0x00A8 RO EFUSE_RD_KEY0_DATA4_REG Register 4 for BLOCK4 (KEY0) 0x00AC RO EFUSE_RD_KEY0_DATA5_REG Register 5 for BLOCK4 (KEY0) 0x00B0 RO EFUSE_RD_KEY0_DATA6_REG Register 6 for BLOCK4 (KEY0) 0x00B4 RO EFUSE_RD_KEY0_DATA7_REG Register 7 for BLOCK4 (KEY0) 0x00B8 RO Reading Data Registers for BLOCK5 EFUSE_RD_KEY1_DATA0_REG Register 0 for BLOCK5 (KEY1) 0x00BC RO EFUSE_RD_KEY1_DATA1_REG Register 1 for BLOCK5 (KEY1) 0x00C0 RO EFUSE_RD_KEY1_DATA2_REG Register 2 for BLOCK5 (KEY1) 0x00C4 RO EFUSE_RD_KEY1_DATA3_REG Register 3 for BLOCK5 (KEY1) 0x00C8 RO EFUSE_RD_KEY1_DATA4_REG Register 4 for BLOCK5 (KEY1) 0x00CC RO EFUSE_RD_KEY1_DATA5_REG Register 5 for BLOCK5 (KEY1) 0x00D0 RO EFUSE_RD_KEY1_DATA6_REG Register 6 for BLOCK5 (KEY1) 0x00D4 RO EFUSE_RD_KEY1_DATA7_REG Register 7 for BLOCK5 (KEY1) 0x00D8 RO Reading Data Registers for BLOCK6 EFUSE_RD_KEY2_DATA0_REG Register 0 for BLOCK6 (KEY2) 0x00DC RO EFUSE_RD_KEY2_DATA1_REG Register 1 for BLOCK6 (KEY2) 0x00E0 RO EFUSE_RD_KEY2_DATA2_REG Register 2 for BLOCK6 (KEY2) 0x00E4 RO EFUSE_RD_KEY2_DATA3_REG Register 3 for BLOCK6 (KEY2) 0x00E8 RO EFUSE_RD_KEY2_DATA4_REG Register 4 for BLOCK6 (KEY2) 0x00EC RO Espressif Systems 168 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Name Description Address Access EFUSE_RD_KEY2_DATA5_REG Register 5 for BLOCK6 (KEY2) 0x00F0 RO EFUSE_RD_KEY2_DATA6_REG Register 6 for BLOCK6 (KEY2) 0x00F4 RO EFUSE_RD_KEY2_DATA7_REG Register 7 for BLOCK6 (KEY2) 0x00F8 RO Reading Data Registers for BLOCK7 EFUSE_RD_KEY3_DATA0_REG Register 0 for BLOCK7 (KEY3) 0x00FC RO EFUSE_RD_KEY3_DATA1_REG Register 1 for BLOCK7 (KEY3) 0x0100 RO EFUSE_RD_KEY3_DATA2_REG Register 2 for BLOCK7 (KEY3) 0x0104 RO EFUSE_RD_KEY3_DATA3_REG Register 3 for BLOCK7 (KEY3) 0x0108 RO EFUSE_RD_KEY3_DATA4_REG Register 4 for BLOCK7 (KEY3) 0x010C RO EFUSE_RD_KEY3_DATA5_REG Register 5 for BLOCK7 (KEY3) 0x0110 RO EFUSE_RD_KEY3_DATA6_REG Register 6 for BLOCK7 (KEY3) 0x0114 RO EFUSE_RD_KEY3_DATA7_REG Register 7 for BLOCK7 (KEY3) 0x0118 RO Reading Data Registers for BLOCK8 EFUSE_RD_KEY4_DATA0_REG Register 0 for BLOCK8 (KEY4) 0x011C RO EFUSE_RD_KEY4_DATA1_REG Register 1 for BLOCK8 (KEY4) 0x0120 RO EFUSE_RD_KEY4_DATA2_REG Register 2 for BLOCK8 (KEY4) 0x0124 RO EFUSE_RD_KEY4_DATA3_REG Register 3 for BLOCK8 (KEY4) 0x0128 RO EFUSE_RD_KEY4_DATA4_REG Register 4 for BLOCK8 (KEY4) 0x012C RO EFUSE_RD_KEY4_DATA5_REG Register 5 for BLOCK8 (KEY4) 0x0130 RO EFUSE_RD_KEY4_DATA6_REG Register 6 for BLOCK8 (KEY4) 0x0134 RO EFUSE_RD_KEY4_DATA7_REG Register 7 for BLOCK8 (KEY4) 0x0138 RO Reading Data Registers for BLOCK9 EFUSE_RD_KEY5_DATA0_REG Register 0 for BLOCK9 (KEY5) 0x013C RO EFUSE_RD_KEY5_DATA1_REG Register 1 for BLOCK9 (KEY5) 0x0140 RO EFUSE_RD_KEY5_DATA2_REG Register 2 for BLOCK9 (KEY5) 0x0144 RO EFUSE_RD_KEY5_DATA3_REG Register 3 for BLOCK9 (KEY5) 0x0148 RO EFUSE_RD_KEY5_DATA4_REG Register 4 for BLOCK9 (KEY5) 0x014C RO EFUSE_RD_KEY5_DATA5_REG Register 5 for BLOCK9 (KEY5) 0x0150 RO EFUSE_RD_KEY5_DATA6_REG Register 6 for BLOCK9 (KEY5) 0x0154 RO EFUSE_RD_KEY5_DATA7_REG Register 7 for BLOCK9 (KEY5) 0x0158 RO Reading Data Registers for BLOCK10 EFUSE_RD_SYS_PART2_DATA0_REG Register 0 for BLOCK10 (system) 0x015C RO EFUSE_RD_SYS_PART2_DATA1_REG Register 1 for BLOCK10 (system) 0x0160 RO EFUSE_RD_SYS_PART2_DATA2_REG Register 2 for BLOCK10 (system) 0x0164 RO EFUSE_RD_SYS_PART2_DATA3_REG Register 3 for BLOCK10 (system) 0x0168 RO EFUSE_RD_SYS_PART2_DATA4_REG Register 4 for BLOCK10 (system) 0x016C RO EFUSE_RD_SYS_PART2_DATA5_REG Register 5 for BLOCK10 (system) 0x0170 RO EFUSE_RD_SYS_PART2_DATA6_REG Register 6 for BLOCK10 (system) 0x0174 RO EFUSE_RD_SYS_PART2_DATA7_REG Register 7 for BLOCK10 (system) 0x0178 RO Error Report Registers for BLOCK0 EFUSE_RD_REPEAT_DATA_ERR0_REG Programming error record register 0 for BLOCK0 0x017C RO Espressif Systems 169 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Name Description Address Access EFUSE_RD_REPEAT_DATA_ERR1_REG Programming error record register 1 for BLOCK0 0x0180 RO EFUSE_RD_REPEAT_DATA_ERR2_REG Programming error record register 2 for BLOCK0 0x0184 RO EFUSE_RD_REPEAT_DATA_ERR3_REG Programming error record register 3 for BLOCK0 0x0188 RO EFUSE_RD_REPEAT_DATA_ERR4_REG Programming error record register 4 for BLOCK0 0x018C RO Error Report Registers for RS Block EFUSE_RD_RS_DATA_ERR0_REG Programming error record register 0 for BLOCK1-10 0x0190 RO EFUSE_RD_RS_DATA_ERR1_REG Programming error record register 1 for BLOCK1-10 0x0194 RO eFuse Version Register EFUSE_DATE_REG eFuse version control register 0x0198 R/W eFuse Clock Register EFUSE_CLK_REG eFuse clock configuration register 0x01C8 R/W eFuse Configuration Registers EFUSE_CONF_REG Configures eFuse operation mode 0x01CC R/W EFUSE_DAC_CONF_REG Configures the eFuse programming volt- age 0x01EC R/W EFUSE_RD_TIM_CONF_REG Configures read timing parameters 0x01F0 R/W EFUSE_WR_TIM_CONF1_REG Configures eFuse programming timing parameters 0x01F4 R/W EFUSE_WR_TIM_CONF2_REG Configures eFuse programming timing parameters 0x01F8 R/W EFUSE_WR_TIM_CONF0_RS_BYPASS_REG Configures register0 of eFuse program- ming time parameters and RS bypass operation 0x01FC varies eFuse ECDSA Configure Registers EFUSE_ECDSA_REG eFuse status register. 0x01D0 varies eFuse Status Registers EFUSE_STATUS_REG eFuse status register 0x01D4 RO eFuse Command Registers EFUSE_CMD_REG eFuse command register 0x01D4 varies eFuse Interrupt Registers EFUSE_INT_RAW_REG eFuse raw interrupt register 0x01DC R/SS/WTC EFUSE_INT_ST_REG eFuse interrupt status register 0x01E0 RO EFUSE_INT_ENA_REG eFuse interrupt enable register 0x01E4 R/W EFUSE_INT_CLR_REG eFuse interrupt clear register 0x01E8 WT Espressif Systems 170 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) 5.6 Registers The addresses in this section are relative to eFuse controller base address provided in Table 4.3-2 in Chapter 4 System and Memory. For how to program reserved fields, please refer to Section Programming Reserved Register Field. Register 5.1. EFUSE_PGM_DATAn_REG (n: 0-7) (0x0000+0x4*n) EFUSE_PGM_DATA_n 0x000000 31 0 Reset EFUSE_PGM_DATA_n Configures the nth 32-bit data to be programmed. (R/W) Register 5.2. EFUSE_PGM_CHECK_VALUEn_REG (n: 0-2) (0x0020+0x4*n) EFUSE_PGM_RS_DATA_n 0x000000 31 0 Reset EFUSE_PGM_RS_DATA_n Configures the nth RS code to be programmed. (R/W) Register 5.3. EFUSE_RD_WR_DIS_REG (0x002C) EFUSE_WR_DIS 0x000000 31 0 Reset EFUSE_WR_DIS Represents whether programming of individual eFuse memory bit is disabled. For mapping between the bits of this field and the eFuse memory bits, please refer to Table 5.3-1 and Table 5.3-3. 1: Disabled 0: Enabled (RO) Espressif Systems 171 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Register 5.4. EFUSE_RD_REPEAT_DATA0_REG (0x0030) EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO 0x0 31 29 EFUSE_WDT_DELAY_SEL 0x0 28 27 EFUSE_VDD_SPI_AS_GPIO 0 26 EFUSE_USB_EXCHG_PINS 0 25 (reserved) 0 0 0 0 24 21 EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT 0 20 EFUSE_DIS_PAD_JTAG 0 19 EFUSE_SOFT_DIS_JTAG 0x0 18 16 EFUSE_JTAG_SEL_ENABLE 0 15 EFUSE_DIS_TWAI 0 14 EFUSE_SPI_DOWNLOAD_MSPI_DIS 0 13 EFUSE_DIS_FORCE_DOWNLOAD 0 12 (reserved) 0 11 EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN 0 10 EFUSE_DIS_USB_JTAG 0 9 EFUSE_DIS_ICACHE 0 8 EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI 0 7 EFUSE_RD_DIS 0x0 6 0 Reset EFUSE_RD_DIS Represents whether reading of individual eFuse block (BLOCK4 BLOCK10) is dis- abled. For mapping between the bits of this field and the eFuse blocks, please refer to Table 5.3-3. 1: Disabled 0: Enabled (RO) EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI Represents the anti-rollback secure version of the second stage bootloader used by the first stage (ROM) bootloader (the high part of the field). (RO) EFUSE_DIS_ICACHE Represents whether cache is disabled. 1: Disabled 0: Enabled (RO) EFUSE_DIS_USB_JTAG Represents whether the USB-to-JTAG function in USB Serial/JTAG is dis- abled. Note that EFUSE_DIS_USB_JTAG is available only when EFUSE_DIS_USB_SERIAL_JTAG is configured to 0. For more information, please refer to Chapter 8 Chip Boot Control. 1: Disabled 0: Enabled (RO) EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN Represents whether the anti-rollback check for the 2nd stage bootloader is enabled. 1: Enabled 0: Disabled (RO) EFUSE_DIS_FORCE_DOWNLOAD Represents whether the function that forces chip into Download mode is disabled. 1: Disabled 0: Enabled (RO) Continued on the next page... Espressif Systems 172 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Register 5.4. EFUSE_RD_REPEAT_DATA0_REG (0x0030) Continued from the previous page... EFUSE_SPI_DOWNLOAD_MSPI_DIS Represents whether SPI0 controller during boot_mode_download is disabled. 0: Enabled 1: Disabled (RO) EFUSE_DIS_TWAI Represents whether TWAI ® function is disabled. 1: Disabled 0: Enabled (RO) EFUSE_JTAG_SEL_ENABLE Represents whether the selection of a JTAG signal source through the strapping pin value is enabled when EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are con- figured to 0. For more information, please refer to Chapter 8 Chip Boot Control. 1: Enabled 0: Disabled (RO) EFUSE_SOFT_DIS_JTAG Represents whether PAD JTAG is disabled in the soft way. It can be restarted via HMAC. Odd count of bits with a value of 1: Disabled Even count of bits with a value of 1: Enabled (RO) EFUSE_DIS_PAD_JTAG Represents whether PAD JTAG is disabled in the hard way (permanently). 1: Disabled 0: Enabled (RO) EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT Represents whether flash encryption is disabled (except in SPI boot mode). 1: Disabled 0: Enabled (RO) EFUSE_USB_EXCHG_PINS Represents whether the USB D+ and D- pins is exchanged. 1: Exchanged 0: Not exchanged (RO) EFUSE_VDD_SPI_AS_GPIO Represents whether VDD SPI pin is functioned as GPIO. 1: Functioned 0: Not functioned (RO) Continued on the next page... Espressif Systems 173 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Register 5.4. EFUSE_RD_REPEAT_DATA0_REG (0x0030) Continued from the previous page... EFUSE_WDT_DELAY_SEL Represents RTC watchdog timeout threshold. 0: The originally configured STG0 threshold × 2 1: The originally configured STG0 threshold × 4 2: The originally configured STG0 threshold × 8 3: The originally configured STG0 threshold × 16 (RO) EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO Represents the anti-rollback secure version of the 2nd stage bootloader used by the ROM bootloader (the low part of the field). (RO) Espressif Systems 174 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Register 5.5. EFUSE_RD_REPEAT_DATA1_REG (0x0034) EFUSE_KEY_PURPOSE_1 0x0 31 27 EFUSE_KEY_PURPOSE_0 0x0 26 22 EFUSE_SECURE_BOOT_KEY_REVOKE2 0 21 EFUSE_SECURE_BOOT_KEY_REVOKE1 0 20 EFUSE_SECURE_BOOT_KEY_REVOKE0 0 19 EFUSE_SPI_BOOT_CRYPT_CNT 0x0 18 16 EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM 0 15 EFUSE_FORCE_DISABLE_SW_INIT_KEY 0 14 EFUSE_FORCE_USE_KEY_MANAGER_KEY 0x0 13 10 EFUSE_KM_DEPLOY_ONLY_ONCE 0x0 9 6 EFUSE_KM_RND_SWITCH_CYCLE 0x0 5 4 EFUSE_KM_DISABLE_DEPLOY_MODE 0x0 3 0 Reset EFUSE_KM_DISABLE_DEPLOY_MODE Represents whether the new key deployment of key man- ager is disabled. Bit0: Represents whether the new ECDSA key deployment is disabled 0: Enabled 1: Disabled Bit1: Represents whether the new XTS-AES (flash and PSRAM) key deployment is disabled 0: Enabled 1: Disabled Bit2: Represents whether the new HMAC key deployment is disabled 0: Enabled 1: Disabled Bit3: Represents whether the new DS key deployment is disabled 0: Enabled 1: Disabled (RO) EFUSE_KM_RND_SWITCH_CYCLE Represents the cycle at which the Key Manager switches ran- dom numbers. 0: Controlled by the KEYMNG_RND_SWITCH_CYCLE register. 1: 8 Key Manager clock cycles 2: 16 Key Manager clock cycles 3: 32 Key Manager clock cycles (RO) Continued on the next page... Espressif Systems 175 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Register 5.5. EFUSE_RD_REPEAT_DATA1_REG (0x0034) Continued from the previous page... EFUSE_KM_DEPLOY_ONLY_ONCE Represents whether the corresponding key can be deployed only once. Bit0: Represents whether the ECDSA key can be deployed only once 0: The key can be deployed multiple times 1: The key can be deployed only once Bit1: Represents whether the XTS-AES (flash and PSRAM) key can be deployed only once 0: The key can be deployed multiple times 1: The key can be deployed only once Bit2: Represents whether the HMAC key can be deployed only once 0: The key can be deployed multiple times 1: The key can be deployed only once Bit3: Represents whether the DS key can be deployed only once 0: The key can be deployed multiple times 1: The key can be deployed only once (RO) EFUSE_FORCE_USE_KEY_MANAGER_KEY Represents whether the corresponding key must come from Key Manager. Bit0: Represents whether the ECDSA key must come from Key Manager. 0: The key does not need to come from Key Manager 1: The key must come from Key Manager Bit1: Represents whether the XTS-AES (flash and PSRAM) key must come from Key Manager. 0: The key does not need to come from Key Manager 1: The key must come from Key Manager Bit2: Represents whether the HMAC key must come from Key Manager. 0: The key does not need to come from Key Manager 1: The key must come from Key Manager Bit3: Represents whether the DS key must come from Key Manager. 0: The key does not need to come from Key Manager 1: The key must come from Key Manager (RO) EFUSE_FORCE_DISABLE_SW_INIT_KEY Represents whether to disable the use of the initialization key written by software and instead force use efuse_init_key. 0: Enable 1: Disable (RO) Continued on the next page... Espressif Systems 176 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Register 5.5. EFUSE_RD_REPEAT_DATA1_REG (0x0034) Continued from the previous page... EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM Represents whether the anti- rollback SECURE_VERSION will be updated from the ROM bootloader. 1: Enable 0: Disable (RO) EFUSE_SPI_BOOT_CRYPT_CNT Represents whether SPI boot encryption/decryption is enabled. Odd count of bits with a value of 1: Enabled Even count of bits with a value of 1: Disabled (RO) EFUSE_SECURE_BOOT_KEY_REVOKE0 Represents whether revoking Secure Boot key digest 0 is enabled. 1: Enabled 0: Disabled (RO) EFUSE_SECURE_BOOT_KEY_REVOKE1 Represents whether revoking Secure Boot key digest 1 is enabled. 1: Enabled 0: Disabled (RO) EFUSE_SECURE_BOOT_KEY_REVOKE2 Represents whether revoking Secure Boot key digest 2 is enabled. 1: Enabled 0: Disabled (RO) EFUSE_KEY_PURPOSE_0 Represents the purpose of Key0. See Table 5.3-2. (RO) EFUSE_KEY_PURPOSE_1 Represents the purpose of Key1. See Table 5.3-2. (RO) Espressif Systems 177 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Register 5.6. EFUSE_RD_REPEAT_DATA2_REG (0x0038) EFUSE_FLASH_TPUW 0x0 31 28 EFUSE_KM_XTS_KEY_LENGTH_256 0 27 EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE 0 26 EFUSE_SECURE_BOOT_EN 0 25 EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI 0x0 24 22 EFUSE_SEC_DPA_LEVEL 0x0 21 20 EFUSE_KEY_PURPOSE_5 0x0 19 15 EFUSE_KEY_PURPOSE_4 0x0 14 10 EFUSE_KEY_PURPOSE_3 0x0 9 5 EFUSE_KEY_PURPOSE_2 0x0 4 0 Reset EFUSE_KEY_PURPOSE_2 Represents the purpose of Key2. See Table 5.3-2. (RO) EFUSE_KEY_PURPOSE_3 Represents the purpose of Key3. See Table 5.3-2. (RO) EFUSE_KEY_PURPOSE_4 Represents the purpose of Key4. See Table 5.3-2. (RO) EFUSE_KEY_PURPOSE_5 Represents the purpose of Key5. See Table 5.3-2. (RO) EFUSE_SEC_DPA_LEVEL Represents the security level of anti-DPA attack. The level is adjusted by configuring the clock random frequency division mode. 0: Security level is SEC_DPA_OFF 1: Security level is SEC_DPA_LOW 2: Security level is SEC_DPA_MIDDLE 3: Security level is SEC_DPA_HIGH For more information, please refer to Chapter 16 System Registers > Section 16.3.2 Anti-DPA Attack Security Control. (RO) EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the pri- mary bootloader fails. 0 and 0xFFF - this feature is disabled. (The high part of the field). (RO) EFUSE_SECURE_BOOT_EN Represents whether Secure Boot is enabled. 1: Enabled 0: Disabled (RO) EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE Represents whether aggressive revocation of Secure Boot is enabled. 1: Enabled 0: Disabled (RO) EFUSE_KM_XTS_KEY_LENGTH_256 Represents which key flash encryption uses. 0: XTS-AES-256 key 1: XTS-AES-128 key (RO) Continued on the next page... Espressif Systems 178 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Register 5.6. EFUSE_RD_REPEAT_DATA2_REG (0x0038) Continued from the previous page... EFUSE_FLASH_TPUW Represents the flash waiting time after power-up. Measurement unit: ms. When the value is less than 15, the waiting time is the programmed value. Otherwise, the waiting time is a fixed value, i.e. 30 ms. (RO) Espressif Systems 179 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Register 5.7. EFUSE_RD_REPEAT_DATA3_REG (0x003C) EFUSE_ECDSA_P384_ENABLE 0 31 (reserved) 0 30 EFUSE_XTS_DPA_CLK_ENABLE 0 29 EFUSE_XTS_DPA_PSEUDO_LEVEL 0x0 28 27 EFUSE_HYS_EN_PAD 0 26 EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE 0 25 (reserved) 0 0 0 0 0 0 0 24 18 EFUSE_SECURE_VERSION 0x0 17 9 EFUSE_FORCE_SEND_RESUME 0 8 EFUSE_UART_PRINT_CONTROL 0x0 7 6 EFUSE_ENABLE_SECURITY_DOWNLOAD 0 5 EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE 0 4 EFUSE_LOCK_KM_KEY 0 3 EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT 0 2 EFUSE_DIS_DIRECT_BOOT 0 1 EFUSE_DIS_DOWNLOAD_MODE 0 0 Reset EFUSE_DIS_DOWNLOAD_MODE Represents whether all Download modes are disabled. 1: Disabled 0: Enabled (RO) EFUSE_DIS_DIRECT_BOOT Represents whether direct boot mode is disabled. 1: Disabled 0: Enabled (RO) EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT Represents whether print from USB-Serial-JTAG during ROM boot is disabled. 1: Disabled 0: Enabled (RO) EFUSE_LOCK_KM_KEY Represents whether the keys in the Key Manager are locked after deploy- ment. 0: Not locked 1: Locked (RO) EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE Represents whether the USB-Serial-JTAG download function is disabled. 1: Disabled 0: Enabled (RO) Continued on the next page... Espressif Systems 180 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Register 5.7. EFUSE_RD_REPEAT_DATA3_REG (0x003C) Continued from the previous page... EFUSE_ENABLE_SECURITY_DOWNLOAD Represents whether security download is enabled. Only downloading into flash is supported. Reading/writing RAM or registers is not supported (i.e. stub download is not supported). 1: Enabled 0: Disabled (RO) EFUSE_UART_PRINT_CONTROL Represents the type of UART printing. 0: Force enable printing. 1: Enable printing when GPIO27 is reset at low level. 2: Enable printing when GPIO27 is reset at high level. 3: Force disable printing. (RO) EFUSE_FORCE_SEND_RESUME Represents whether ROM code is forced to send a resume com- mand during SPI boot. 1: Forced. 0: Not forced. (RO) EFUSE_SECURE_VERSION Represents the security version used by ESP-IDF anti-rollback feature. (RO) EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE Represents whether FAST VERIFY ON WAKE is disabled when Secure Boot is enabled. 1: Disabled 0: Enabled (RO) EFUSE_HYS_EN_PAD Represents whether the hysteresis function of PAD0 – PAD27 is enabled. 1: Enabled 0: Disabled (RO) EFUSE_XTS_DPA_PSEUDO_LEVEL Represents the pseudo round level of XTS-AES anti-DPA at- tack. 0: Disabled 1: Low 2: Moderate 3: High (RO) EFUSE_XTS_DPA_CLK_ENABLE Represents whether XTS-AES anti-DPA attack clock is enabled. 0: Disable 1: Enabled (RO) EFUSE_ECDSA_P384_ENABLE Represents whether the chip supports ECDSA P384. (RO) Espressif Systems 181 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Register 5.8. EFUSE_RD_REPEAT_DATA4_REG (0x0040) (reserved) 0 0 0 0 0 0 0 0 0 31 23 EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO 0x0 22 14 EFUSE_ECC_FORCE_CONST_TIME 0 13 EFUSE_XTAL_48M_SEL_MODE 0 12 EFUSE_XTAL_48M_SEL 0x0 11 9 EFUSE_HUK_GEN_STATE 0x0 8 0 Reset EFUSE_HUK_GEN_STATE Represents whether the HUK generate mode is valid. Odd count of bits with a value of 1: Invalid Even count of bits with a value of 1: Valid (RO) EFUSE_XTAL_48M_SEL Determines the frequency of the XTAL clock alone in SPI Boot mode, or together with EFUSE_XTAL_48M_SEL_MODE in Joint Download Boot mode. For more informa- tion, please refer to Chapter 8 Chip Boot Control. Odd count of bits with a value of 1: 48 MHz Even count of bits with a value of 1: 40 MHz (RO) EFUSE_XTAL_48M_SEL_MODE Represents what determines the XTAL frequency in Joint Down- load Boot mode. For more information, please refer to Chapter 8 Chip Boot Control. 0: Strapping PAD state 1: EFUSE_XTAL_48M_SEL in eFuse (RO) EFUSE_ECC_FORCE_CONST_TIME Represents whether to force ECC to use constant-time mode for point multiplication calculation. 0: Not force 1: Force (RO) EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the pri- mary bootloader fails. 0 and 0xFFF - this feature is disabled. (The low part of the field). (RO) Espressif Systems 182 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Register 5.9. EFUSE_RD_MAC_SYS0_REG (0x0044) EFUSE_MAC_0 0x000000 31 0 Reset EFUSE_MAC_0 Represents the lower 32 bits of MAC address. (RO) Register 5.10. EFUSE_RD_MAC_SYS1_REG (0x0048) EFUSE_MAC_EXT 0x00 31 16 EFUSE_MAC_1 0x00 15 0 Reset EFUSE_MAC_1 Represents the higher 16 bits of MAC address. (RO) EFUSE_MAC_EXT Represents the extended bits of MAC address. (RO) Register 5.11. EFUSE_RD_MAC_SYS3_REG (0x0050) EFUSE_SYS_DATA_PART0_0 0x00 31 18 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 0 Reset EFUSE_SYS_DATA_PART0_0 Represents the first 14 bits of the zeroth part of system data. (RO) Espressif Systems 183 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Register 5.12. EFUSE_RD_MAC_SYS4_REG (0x0054) EFUSE_SYS_DATA_PART0_1 0x000000 31 0 Reset EFUSE_SYS_DATA_PART0_1 Represents the first 32 bits of the zeroth part of system data. (RO) Register 5.13. EFUSE_RD_MAC_SYS5_REG (0x0058) EFUSE_SYS_DATA_PART0_2 0x000000 31 0 Reset EFUSE_SYS_DATA_PART0_2 Represents the second 32 bits of the zeroth part of system data. (RO) Register 5.14. EFUSE_RD_SYS_PART1_DATAn_REG (n: 0-7) (0x005C+0x4*n) EFUSE_SYS_DATA_PART1_n 0x000000 31 0 Reset EFUSE_SYS_DATA_PART1_n Represents the nth 32 bits of the first part of system data. (RO) Espressif Systems 184 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Register 5.15. EFUSE_RD_USR_DATAn_REG (n: 0-7) (0x007C+0x4*n) EFUSE_USR_DATAn 0x000000 31 0 Reset EFUSE_USR_DATAn Represents the nth 32-bit of BLOCK3 (user). (RO) Register 5.16. EFUSE_RD_KEY0_DATAn_REG (n: 0-7) (0x009C+0x4*n) EFUSE_KEY0_DATAn 0x000000 31 0 Reset EFUSE_KEY0_DATAn Represents the nth 32 bits of key0. (RO) Register 5.17. EFUSE_RD_KEY1_DATAn_REG (n: 0-7) (0x00BC+0x4*n) EFUSE_KEY1_DATAn 0x000000 31 0 Reset EFUSE_KEY1_DATAn Represents the nth 32-bit of key1. (RO) Register 5.18. EFUSE_RD_KEY2_DATAn_REG (n: 0-7) (0x00DC+0x4*n) EFUSE_KEY2_DATAn 0x000000 31 0 Reset EFUSE_KEY2_DATAn Represents the nth 32 bits of key2. (RO) Espressif Systems 185 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Register 5.19. EFUSE_RD_KEY3_DATAn_REG (n: 0-7) (0x00FC+0x4*n) EFUSE_KEY3_DATAn 0x000000 31 0 Reset EFUSE_KEY3_DATAn Represents the nth 32-bit of key3. (RO) Register 5.20. EFUSE_RD_KEY4_DATAn_REG (n: 0-7) (0x011C+0x4*n) EFUSE_KEY4_DATAn 0x000000 31 0 Reset EFUSE_KEY4_DATAn Represents the nth 32 bits of key4. (RO) Register 5.21. EFUSE_RD_KEY5_DATAn_REG (n: 0-7) (0x013C+0x4*n) EFUSE_KEY5_DATAn 0x000000 31 0 Reset EFUSE_KEY5_DATAn Represents the nth 32-bit of key5. (RO) Register 5.22. EFUSE_RD_SYS_PART2_DATAn_REG (n: 0-7) (0x015C+0x4*n) EFUSE_SYS_DATA_PART2_n 0x000000 31 0 Reset EFUSE_SYS_DATA_PART2_n Represents the nth 32 bits of the 2nd part of system data. (RO) Espressif Systems 186 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Register 5.23. EFUSE_RD_REPEAT_DATA_ERR0_REG (0x017C) EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO_ERR 0x0 31 29 EFUSE_WDT_DELAY_SEL_ERR 0x0 28 27 EFUSE_VDD_SPI_AS_GPIO_ERR 0 26 EFUSE_USB_EXCHG_PINS_ERR 0 25 (reserved) 0 0 0 0 24 21 EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR 0 20 EFUSE_DIS_PAD_JTAG_ERR 0 19 EFUSE_SOFT_DIS_JTAG_ERR 0x0 18 16 EFUSE_JTAG_SEL_ENABLE_ERR 0 15 EFUSE_DIS_TWAI_ERR 0 14 EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR 0 13 EFUSE_DIS_FORCE_DOWNLOAD_ERR 0 12 (reserved) 0 11 EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR 0 10 EFUSE_DIS_USB_JTAG_ERR 0 9 EFUSE_DIS_ICACHE_ERR 0 8 EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI_ERR 0 7 EFUSE_RD_DIS_ERR 0x0 6 0 Reset EFUSE_RD_DIS_ERR Represents the programming error of EFUSE_RD_DIS (RO) EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI_ERR Represents the pro- gramming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI (RO) EFUSE_DIS_ICACHE_ERR Represents the programming error of EFUSE_DIS_ICACHE (RO) EFUSE_DIS_USB_JTAG_ERR Represents the programming error of EFUSE_DIS_USB_JTAG (RO) EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN (RO) EFUSE_DIS_FORCE_DOWNLOAD_ERR Represents the programming error of EFUSE_DIS_FORCE_DOWNLOAD (RO) EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR Represents the programming error of EFUSE_SPI_DOWNLOAD_MSPI_DIS (RO) EFUSE_DIS_TWAI_ERR Represents the programming error of EFUSE_DIS_TWAI (RO) EFUSE_JTAG_SEL_ENABLE_ERR Represents the programming error of EFUSE_JTAG_SEL_ENABLE (RO) EFUSE_SOFT_DIS_JTAG_ERR Represents the programming error of EFUSE_SOFT_DIS_JTAG (RO) EFUSE_DIS_PAD_JTAG_ERR Represents the programming error of EFUSE_DIS_PAD_JTAG (RO) EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR Represents the programming error of EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (RO) EFUSE_USB_EXCHG_PINS_ERR Represents the programming error of EFUSE_USB_EXCHG_PINS (RO) EFUSE_VDD_SPI_AS_GPIO_ERR Represents the programming error of EFUSE_VDD_SPI_AS_GPIO (RO) Continued on the next page... Espressif Systems 187 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Register 5.23. EFUSE_RD_REPEAT_DATA_ERR0_REG (0x017C) Continued from the previous page... EFUSE_WDT_DELAY_SEL_ERR Represents the programming error of EFUSE_WDT_DELAY_SEL (RO) EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO_ERR Represents the pro- gramming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO (RO) Espressif Systems 188 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Register 5.24. EFUSE_RD_REPEAT_DATA_ERR1_REG (0x0180) EFUSE_KEY_PURPOSE_1_ERR 0x0 31 27 EFUSE_KEY_PURPOSE_0_ERR 0x0 26 22 EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR 0 21 EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR 0 20 EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR 0 19 EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x0 18 16 EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR 0 15 EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR 0 14 EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR 0x0 13 10 EFUSE_KM_DEPLOY_ONLY_ONCE_ERR 0x0 9 6 EFUSE_KM_RND_SWITCH_CYCLE_ERR 0x0 5 4 EFUSE_KM_DISABLE_DEPLOY_MODE_ERR 0x0 3 0 Reset EFUSE_KM_DISABLE_DEPLOY_MODE_ERR Represents the programming error of EFUSE_KM_DISABLE_DEPLOY_MODE (RO) EFUSE_KM_RND_SWITCH_CYCLE_ERR Represents the programming error of EFUSE_KM_RND_SWITCH_CYCLE (RO) EFUSE_KM_DEPLOY_ONLY_ONCE_ERR Represents the programming error of EFUSE_KM_DEPLOY_ONLY_ONCE (RO) EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR Represents the programming error of EFUSE_FORCE_USE_KEY_MANAGER_KEY (RO) EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR Represents the programming error of EFUSE_FORCE_DISABLE_SW_INIT_KEY (RO) EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR Represents the program- ming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM (RO) EFUSE_SPI_BOOT_CRYPT_CNT_ERR Represents the programming error of EFUSE_SPI_BOOT_CRYPT_CNT (RO) EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE0 (RO) EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE1 (RO) EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE2 (RO) EFUSE_KEY_PURPOSE_0_ERR Represents the programming error of EFUSE_KEY_PURPOSE_0 (RO) EFUSE_KEY_PURPOSE_1_ERR Represents the programming error of EFUSE_KEY_PURPOSE_1 (RO) Espressif Systems 189 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Register 5.25. EFUSE_RD_REPEAT_DATA_ERR2_REG (0x0184) EFUSE_FLASH_TPUW_ERR 0x0 31 28 EFUSE_KM_XTS_KEY_LENGTH_256_ERR 0 27 EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR 0 26 EFUSE_SECURE_BOOT_EN_ERR 0 25 EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI_ERR 0x0 24 22 EFUSE_SEC_DPA_LEVEL_ERR 0x0 21 20 EFUSE_KEY_PURPOSE_5_ERR 0x0 19 15 EFUSE_KEY_PURPOSE_4_ERR 0x0 14 10 EFUSE_KEY_PURPOSE_3_ERR 0x0 9 5 EFUSE_KEY_PURPOSE_2_ERR 0x0 4 0 Reset EFUSE_KEY_PURPOSE_2_ERR Any bit of this field being 1 represents a programming error of EFUSE_KEY_PURPOSE_2. (RO) EFUSE_KEY_PURPOSE_3_ERR Any bit of this field being 1 represents a programming error of EFUSE_KEY_PURPOSE_3. (RO) EFUSE_KEY_PURPOSE_4_ERR Any bit of this field being 1 represents a programming error of EFUSE_KEY_PURPOSE_4. (RO) EFUSE_KEY_PURPOSE_5_ERR Any bit of this field being 1 represents a programming error of EFUSE_KEY_PURPOSE_5. (RO) EFUSE_SEC_DPA_LEVEL_ERR Any bit of this field being 1 represents a programming error of EFUSE_SEC_DPA_LEVEL. (RO) EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI_ERR Represents the programming er- ror of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI (RO) EFUSE_SECURE_BOOT_EN_ERR This bit being 1 represents a programming error of EFUSE_SECURE_BOOT_EN. (RO) EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR This bit being 1 represents a programming error of EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE. (RO) EFUSE_KM_XTS_KEY_LENGTH_256_ERR Represents the programming error of EFUSE_KM_XTS_KEY_LENGTH_256 (RO) EFUSE_FLASH_TPUW_ERR This bit being 1 represents a programming error of EFUSE_FLASH_TPUW. (RO) Espressif Systems 190 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Register 5.26. EFUSE_RD_REPEAT_DATA_ERR3_REG (0x0188) EFUSE_ECDSA_P384_ENABLE_ERR 0 31 (reserved) 0 30 EFUSE_XTS_DPA_CLK_ENABLE_ERR 0 29 EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR 0x0 28 27 EFUSE_HYS_EN_PAD_ERR 0 26 EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR 0 25 (reserved) 0 0 0 0 0 0 0 24 18 EFUSE_SECURE_VERSION_ERR 0x0 17 9 EFUSE_FORCE_SEND_RESUME_ERR 0 8 EFUSE_UART_PRINT_CONTROL_ERR 0x0 7 6 EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR 0 5 EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR 0 4 EFUSE_LOCK_KM_KEY_ERR 0 3 EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR 0 2 EFUSE_DIS_DIRECT_BOOT_ERR 0 1 EFUSE_DIS_DOWNLOAD_MODE_ERR 0 0 Reset EFUSE_DIS_DOWNLOAD_MODE_ERR This bit being 1 represents a programming error of EFUSE_DIS_DOWNLOAD_MODE. (RO) EFUSE_DIS_DIRECT_BOOT_ERR This bit being 1 represents a programming error of EFUSE_DIS_DIRECT_BOOT. (RO) EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR This bit being 1 represents a programming error of EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR. (RO) EFUSE_LOCK_KM_KEY_ERR Represents the programming error of EFUSE_LOCK_KM_KEY (RO) EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR This bit being 1 represents a pro- gramming error of EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. (RO) EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR This bit being 1 represents a programming error of EFUSE_ENABLE_SECURITY_DOWNLOAD. (RO) EFUSE_UART_PRINT_CONTROL_ERR Any bit of this field being 1 represents a programming error of EFUSE_UART_PRINT_CONTROL. (RO) EFUSE_FORCE_SEND_RESUME_ERR This bit being 1 represents a programming error of EFUSE_FORCE_SEND_RESUME. (RO) EFUSE_SECURE_VERSION_ERR Any bit of this field being 1 represents a programming error of EFUSE_SECURE_VERSION. (RO) EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR This bit being 1 represents a programming error of EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE. (RO) EFUSE_HYS_EN_PAD_ERR This bit being 1 represents a programming error of EFUSE_HYS_EN_PAD. (RO) EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR Represents the programming error of EFUSE_XTS_DPA_PSEUDO_LEVEL (RO) EFUSE_XTS_DPA_CLK_ENABLE_ERR Represents the programming error of EFUSE_XTS_DPA_CLK_ENABLE (RO) EFUSE_ECDSA_P384_ENABLE_ERR Represents the programming error of EFUSE_ECDSA_P384_ENABLE (RO) Espressif Systems 191 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Register 5.27. EFUSE_RD_REPEAT_DATA_ERR4_REG (0x018C) (reserved) 0 0 0 0 0 0 0 0 0 31 23 EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_ERR 0x0 22 14 EFUSE_ECC_FORCE_CONST_TIME_ERR 0 13 EFUSE_XTAL_48M_SEL_MODE_ERR 0 12 EFUSE_XTAL_48M_SEL_ERR 0x0 11 9 EFUSE_HUK_GEN_STATE_ERR 0x0 8 0 Reset EFUSE_HUK_GEN_STATE_ERR Represents the programming error of EFUSE_HUK_GEN_STATE (RO) EFUSE_XTAL_48M_SEL_ERR Represents the programming error of EFUSE_XTAL_48M_SEL (RO) EFUSE_XTAL_48M_SEL_MODE_ERR Represents the programming error of EFUSE_XTAL_48M_SEL_MODE (RO) EFUSE_ECC_FORCE_CONST_TIME_ERR Represents the programming error of EFUSE_ECC_FORCE_CONST_TIME (RO) EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_ERR Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO (RO) Espressif Systems 192 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Register 5.28. EFUSE_RD_RS_DATA_ERR0_REG (0x0190) EFUSE_RD_KEY4_DATA_FAIL 0 31 EFUSE_RD_KEY4_DATA_ERR_NUM 0x0 30 28 EFUSE_RD_KEY3_DATA_FAIL 0 27 EFUSE_RD_KEY3_DATA_ERR_NUM 0x0 26 24 EFUSE_RD_KEY2_DATA_FAIL 0 23 EFUSE_RD_KEY2_DATA_ERR_NUM 0x0 22 20 EFUSE_RD_KEY1_DATA_FAIL 0 19 EFUSE_RD_KEY1_DATA_ERR_NUM 0x0 18 16 EFUSE_RD_KEY0_DATA_FAIL 0 15 EFUSE_RD_KEY0_DATA_ERR_NUM 0x0 14 12 EFUSE_RD_USR_DATA_FAIL 0 11 EFUSE_RD_USR_DATA_ERR_NUM 0x0 10 8 EFUSE_RD_SYS_PART1_DATA_FAIL 0 7 EFUSE_RD_SYS_PART1_DATA_ERR_NUM 0x0 6 4 EFUSE_RD_MAC_SYS_FAIL 0 3 EFUSE_RD_MAC_SYS_ERR_NUM 0x0 2 0 Reset EFUSE_RD_MAC_SYS_ERR_NUM Represents the number of error bytes. (RO) EFUSE_RD_MAC_SYS_FAIL Represents whether programming RD_MAC_SYS failed. 0: No failure and the data of RD_MAC_SYS is reliable. 1: Programming user data failed and the number of error bytes is over 6. (RO) EFUSE_RD_SYS_PART1_DATA_ERR_NUM Represents the number of error bytes. (RO) EFUSE_RD_SYS_PART1_DATA_FAIL Represents whether programming system part1 data failed. 0: No failure and the data of RD_SYS_PART1_DATA is reliable. 1: Programming user data RD_SYS_PART1_DATA failed and the number of error bytes is over 6. (RO) EFUSE_RD_USR_DATA_ERR_NUM Represents the number of error bytes. (RO) EFUSE_RD_USR_DATA_FAIL Represents whether programming user data failed. 0: No failure and the user data is reliable. 1: Programming user data failed and the number of error bytes is over 6. (RO) EFUSE_RD_KEY0_DATA_ERR_NUM Represents the number of error bytes. (RO) EFUSE_RD_KEY0_DATA_FAIL Represents whether programming key0 data failed. 0: No failure and the data of RD_KEY0_DATA is reliable. 1: Programming RD_KEY0_DATA failed and the number of error bytes is over 6. (RO) EFUSE_RD_KEY1_DATA_ERR_NUM Represents the number of error bytes. (RO) EFUSE_RD_KEY1_DATA_FAIL Represents whether programming key1 data failed. 0: No failure and the data of RD_KEY1_DATA is reliable. 1: Programming RD_KEY1_DATA failed and the number of error bytes is over 6. (RO) EFUSE_RD_KEY2_DATA_ERR_NUM Represents the number of error bytes. (RO) Continued on the next page... Espressif Systems 193 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Register 5.28. EFUSE_RD_RS_DATA_ERR0_REG (0x0190) Continued from the previous page... EFUSE_RD_KEY2_DATA_FAIL Represents whether programming key2 data failed. 0: No failure and the data of RD_KEY2_DATA is reliable. 1: Programming RD_KEY2_DATA failed and the number of error bytes is over 6. (RO) EFUSE_RD_KEY3_DATA_ERR_NUM Represents the number of error bytes. (RO) EFUSE_RD_KEY3_DATA_FAIL Represents whether programming key3 data failed. 0: No failure and the data of RD_KEY3_DATA is reliable. 1: Programming RD_KEY3_DATA failed and the number of error bytes is over 6. (RO) EFUSE_RD_KEY4_DATA_ERR_NUM Represents the number of error bytes. (RO) EFUSE_RD_KEY4_DATA_FAIL Represents whether programming key4 data failed. 0: No failure and the data ofRD_KEY4_DATA is reliable. 1: Programming RD_KEY4_DATA failed and the number of error bytes is over 6. (RO) Espressif Systems 194 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Register 5.29. EFUSE_RD_RS_DATA_ERR1_REG (0x0194) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 EFUSE_RD_SYS_PART2_DATA_FAIL 0 7 EFUSE_RD_SYS_PART2_DATA_ERR_NUM 0x0 6 4 EFUSE_RD_KEY5_DATA_FAIL 0 3 EFUSE_RD_KEY5_DATA_ERR_NUM 0x0 2 0 Reset EFUSE_RD_KEY5_DATA_ERR_NUM Represents the number of error bytes in RD_KEY5_DATA. (RO) EFUSE_RD_KEY5_DATA_FAIL Represents whether programming key5 data failed. 0: No failure and the data of RD_KEY5_DATA is reliable. 1: Programming RD_KEY5_DATA failed and the number of error bytes is over 6. (RO) EFUSE_RD_SYS_PART2_DATA_ERR_NUM Represents the number of error bytes. (RO) EFUSE_RD_SYS_PART2_DATA_FAIL Represents whether programming system part2 data failed. 0: No failure and the data of RD_SYS_PART2_DATA is reliable. 1: Programming RD_SYS_PART2_DATA failed and the number of error bytes is over 6. (RO) Register 5.30. EFUSE_DATE_REG (0x0198) (reserved) 0 0 0 0 31 28 EFUSE_DATE 0x2411250 27 0 Reset EFUSE_DATE Version control register. (R/W) Espressif Systems 195 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Register 5.31. EFUSE_CLK_REG (0x01C8) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 17 EFUSE_CLK_EN 0 16 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 15 3 EFUSE_MEM_FORCE_PU 0 2 EFUSE_MEM_CLK_FORCE_ON 1 1 EFUSE_MEM_FORCE_PD 0 0 Reset EFUSE_MEM_FORCE_PD Configures whether to force power down eFuse SRAM. 1: Force 0: No effect (R/W) EFUSE_MEM_CLK_FORCE_ON Configures whether to force activate clock signal of eFuse SRAM. 1: Force activate 0: No effect (R/W) EFUSE_MEM_FORCE_PU Configures whether to force power up eFuse SRAM. 1: Force 0: No effect (R/W) EFUSE_CLK_EN Configures whether to force enable eFuse register configuration clock signal. 1: Force 0: The clock is enabled only during the reading and writing of registers (R/W) Register 5.32. EFUSE_CONF_REG (0x01CC) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 EFUSE_OP_CODE 0x00 15 0 Reset EFUSE_OP_CODE Configures operation command type. 0x5A5A: Program operation command 0x5AA5: Read operation command Other values: No effect (R/W) Espressif Systems 196 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Register 5.33. EFUSE_DAC_CONF_REG (0x01EC) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 18 EFUSE_OE_CLR 0 17 EFUSE_DAC_NUM 255 16 9 EFUSE_DAC_CLK_PAD_SEL 0 8 EFUSE_DAC_CLK_DIV 19 7 0 Reset EFUSE_DAC_CLK_DIV Configures the division factor of the rising clock of the programming voltage. (R/W) EFUSE_DAC_NUM Configures clock cycles for programming voltage to rise. Measurement unit: a clock cycle divided by EFUSE_DAC_CLK_DIV. (R/W) EFUSE_OE_CLR Configures whether to reduce the power supply of programming voltage. 0: Not reduce 1: Reduce (R/W) Register 5.34. EFUSE_RD_TIM_CONF_REG (0x01F0) EFUSE_READ_INIT_NUM 0x12 31 24 EFUSE_TSUR_A 0x1 23 16 EFUSE_TRD 0x2 15 8 EFUSE_THR_A 0x1 7 0 Reset EFUSE_THR_A Configures the read hold time. Measurement unit: One cycle of the eFuse core clock. (R/W) EFUSE_TRD Configures the read time. Measurement unit: One cycle of the eFuse core clock. (R/W) EFUSE_TSUR_A Configures the read setup time. Measurement unit: One cycle of the eFuse core clock. (R/W) EFUSE_READ_INIT_NUM Configures the waiting time of reading eFuse memory. Measurement unit: One cycle of the eFuse core clock. (R/W) Espressif Systems 197 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Register 5.35. EFUSE_WR_TIM_CONF1_REG (0x01F4) EFUSE_THP_A 0x1 31 24 EFUSE_PWR_ON_NUM 0x2667 23 8 EFUSE_TSUP_A 0x1 7 0 Reset EFUSE_TSUP_A Configures the programming setup time. Measurement unit: One cycle of the eFuse core clock. (R/W) EFUSE_PWR_ON_NUM Configures the power up time for VDDQ. Measurement unit: One cycle of the eFuse core clock. (R/W) EFUSE_THP_A Configures the programming hold time. Measurement unit: One cycle of the eFuse core clock. (R/W) Register 5.36. EFUSE_WR_TIM_CONF2_REG (0x01F4) EFUSE_TPGM 0xc8 31 16 EFUSE_PWR_OFF_NUM 0x190 15 0 Reset EFUSE_PWR_OFF_NUM Configures the power outage time for VDDQ. Measurement unit: One cycle of the eFuse core clock. (R/W) EFUSE_TPGM Configures the active programming time. Measurement unit: One cycle of the eFuse core clock. (R/W) Espressif Systems 198 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Register 5.37. EFUSE_WR_TIM_CONF0_RS_BYPASS_REG (0x01FC) (reserved) 0 0 0 0 0 0 0 0 0 0 0 31 21 EFUSE_TPGM_INACTIVE 0x1 20 13 EFUSE_UPDATE 0 12 EFUSE_BYPASS_RS_BLK_NUM 0x0 11 1 EFUSE_BYPASS_RS_CORRECTION 0 0 Reset EFUSE_BYPASS_RS_CORRECTION Configures whether to bypass the Reed-Solomon (RS) cor- rection step. 0: Not bypass 1: Bypass (R/W) EFUSE_BYPASS_RS_BLK_NUM Configures which block number to bypass the Reed-Solomon (RS) correction step. (R/W) EFUSE_UPDATE Configures whether to update multi-bit register signals. 1: Update 0: No effect (WT) EFUSE_TPGM_INACTIVE Configures the inactive programming time. Measurement unit: One cycle of the eFuse core clock. (R/W) Espressif Systems 199 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Register 5.38. EFUSE_ECDSA_REG (0x01D0) EFUSE_CUR_ECDSA_P384_H_BLK 0x0 31 28 EFUSE_CUR_ECDSA_P384_L_BLK 0x0 27 24 EFUSE_CUR_ECDSA_P256_BLK 0x0 23 20 EFUSE_CUR_ECDSA_P192_BLK 0x0 19 16 EFUSE_CFG_ECDSA_P384_H_BLK 0x0 15 12 EFUSE_CFG_ECDSA_P384_L_BLK 0x0 11 8 EFUSE_CFG_ECDSA_P256_BLK 0x0 7 4 EFUSE_CFG_ECDSA_P192_BLK 0x0 3 0 Reset EFUSE_CFG_ECDSA_P192_BLK Configures which block to use for ECDSA P192 key output. (R/W) EFUSE_CFG_ECDSA_P256_BLK Configures which block to use for ECDSA P256 key output. (R/W) EFUSE_CFG_ECDSA_P384_L_BLK Configures which block to use for ECDSA P384 key low part output. (R/W) EFUSE_CFG_ECDSA_P384_H_BLK Configures which block to use for ECDSA P256 key high part output. (R/W) EFUSE_CUR_ECDSA_P192_BLK Represents which block is used for ECDSA P192 key output. (RO) EFUSE_CUR_ECDSA_P256_BLK Represents which block is used for ECDSA P256 key output. (RO) EFUSE_CUR_ECDSA_P384_L_BLK Represents which block is used for ECDSA P384 key low part output. (RO) EFUSE_CUR_ECDSA_P384_H_BLK Represents which block is used for ECDSA P384 key high part output. (RO) Espressif Systems 200 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Register 5.39. EFUSE_STATUS_REG (0x01D4) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 31 20 EFUSE_BLK0_VALID_BIT_CNT 0x0 19 10 (reserved) 0 0 0 0 0 0 9 4 EFUSE_STATE 0x0 3 0 Reset EFUSE_STATE Represents the state of the eFuse state machine. 0: Reset state, the initial state after power-up 1: Idle state Other values: Non-idle state (RO) EFUSE_BLK0_VALID_BIT_CNT Represents the number of block valid bit. (RO) Register 5.40. EFUSE_CMD_REG (0x01D8) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 6 EFUSE_BLK_NUM 0x0 5 2 EFUSE_PGM_CMD 0 1 EFUSE_READ_CMD 0 0 Reset EFUSE_READ_CMD Configures whether to send read commands. 1: Send 0: No effect (R/W/SC) EFUSE_PGM_CMD Configures whether to send programming commands. 1: Send 0: No effect (R/W/SC) EFUSE_BLK_NUM Configures the serial number of the block to be programmed. Value 0-10 corre- sponds to block number 0-10, respectively. (R/W) Espressif Systems 201 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Register 5.41. EFUSE_INT_RAW_REG (0x01DC) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 2 EFUSE_PGM_DONE_INT_RAW 0 1 EFUSE_READ_DONE_INT_RAW 0 0 Reset EFUSE_READ_DONE_INT_RAW The raw interrupt status of EFUSE_READ_DONE_INT. (R/SS/WTC) EFUSE_PGM_DONE_INT_RAW The raw interrupt status of EFUSE_PGM_DONE_INT. (R/SS/WTC) Register 5.42. EFUSE_INT_ST_REG (0x01E0) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 2 EFUSE_PGM_DONE_INT_ST 0 1 EFUSE_READ_DONE_INT_ST 0 0 Reset EFUSE_READ_DONE_INT_ST The masked interrupt status of EFUSE_READ_DONE_INT. (RO) EFUSE_PGM_DONE_INT_ST The masked interrupt status of EFUSE_PGM_DONE_INT. (RO) Register 5.43. EFUSE_INT_ENA_REG (0x01E4) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 2 EFUSE_PGM_DONE_INT_ENA 0 1 EFUSE_READ_DONE_INT_ENA 0 0 Reset EFUSE_READ_DONE_INT_ENA Write 1 to enable EFUSE_READ_DONE_INT. (R/W) EFUSE_PGM_DONE_INT_ENA Write 1 to enable EFUSE_PGM_DONE_INT. (R/W) Espressif Systems 202 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 5 eFuse Controller (eFuse) Register 5.44. EFUSE_INT_CLR_REG (0x01E8) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 2 EFUSE_PGM_DONE_INT_CLR 0 1 EFUSE_READ_DONE_INT_CLR 0 0 Reset EFUSE_READ_DONE_INT_CLR Write 1 to clear EFUSE_READ_DONE_INT. (WT) EFUSE_PGM_DONE_INT_CLR Write 1 to clear EFUSE_PGM_DONE_INT. (WT) Espressif Systems 203 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Part III System Component Encompassing a range of system-level functionalities, this part describes components related to system boot, clocks, GPIO, timers, watchdogs, debug assistance, event and interrupt handling, low-power management, and various system registers. Espressif Systems 204 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Chapter 6 GPIO Matrix and IO MUX 6.1 Overview GPIO matrix is a hardware structure that allows dynamic remapping between the GPIO pins and peripheral input/output signals to provide greater flexibility. IO MUX (Input/Output Multiplexing) is a technology that allows the same pin to perform different functions at different times, allowing dynamic switching of pin functions through configuration. ESP32-C5 provides two groups of GPIO matrix and IO MUX: • HP GPIO matrix and HP IO MUX • LP GPIO matrix and LP IO MUX The ESP32-C5 chip features 29 GPIO pins, numbered from GPIO0 to GPIO28, including • 7 LP GPIO pins (GPIO0∼GPIO6) for either HP or LP peripherals. • 14 HP GPIO pins (GPIO7∼GPIO14, GPIO23∼GPIO28) for HP peripherals only. • 8 dedicated GPIO pins (GPIO15∼GPIO22) for external flash and PSRAM. These pins can not be used for other purpose, and therefore are not described in subsequent sections. For more information regarding these pins, please refer to ESP32-C5 Datasheet > Section Pin Mapping Between Chip and Flash/PSRAM. Each pin can be used as a general-purpose I/O, or be connected to an internal peripheral signal. Together these modules provide highly configurable I/O. • Through HP GPIO matrix and HP IO MUX, HP peripheral input signals can be from any GPIO pins, and HP peripheral output signals can be routed to any GPIO pins. • Through LP GPIO matrix and LP IO MUX, LP peripheral input signals can be from any LP GPIO pins, and LP peripheral output signals can be routed to any LP GPIO pins. Unless otherwise specified, GPIO matrix refers to both LP GPIO matrix and HP GPIO matrix, so as to IO MUX. 6.2 Features 6.2.1 HP GPIO Matrix and HP IO MUX HP GPIO matrix has the following features: • A full-switching matrix between HP peripheral input/output signals and the GPIO pins • 76 HP peripheral input signals sourced from the input of any GPIO pins Espressif Systems 205 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX • 77 HP peripheral output signals routed to the output of any GPIO pins • Signal synchronization for HP peripheral inputs based on HP IO MUX operating clock • GPIO Filter hardware for input signal filtering • Glitch Filter hardware for second-time filtering on input signal • Sigma delta modulated (SDM) output • GPIO simple input and output • HP GPIO Wakeup HP IO MUX has the following features: • Control of 21 GPIOs (GPIO0∼GPIO14, GPIO23∼GPIO28) for HP peripherals. • A configuration register IO_MUX_GPIOn_REG provided for each GPIO pin, to control the pin’s input/output, pull-up/pull-down, drive strength, and function selection. • Better high-frequency digital performance achieved by routing some digital signals (such as SPI) directly from HP IO MUX to peripherals. 6.2.2 LP GPIO Matrix and LP IO MUX LP GPIO matrix has the following features: • GPIO simple input and output • LP GPIO Wakeup LP IO MUX has the following feature: • Control of 7 LP GPIO pins (GPIO0∼GPIO6) for LP peripherals. • A configuration register LP_IO_MUX_GPIOn_REG provided for each LP GPIO pin, to control the pin’s input/output, pull-up/pull-down, drive strength, and function selection. • A field LP_AON_GPIO_MUX_SEL provided to select the source of the pin control signals, from HP IO MUX or LP IO MUX. 6.3 Architectural Overview Figure 6.3-1 shows in details how HP GPIO matrix, HP IO MUX, LP GPIO matrix, and LP IO MUX route signals from pins to peripherals, and from peripherals to pins. Espressif Systems 206 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Figure 6.3-1. Architecture of HP GPIO Matrix, HP IO MUX, LP GPIO Matrix, and LP IO MUX The following points explain the areas marked numerically in the figure above, taking the HP system as an example. 1  Peripheral input signals marked “yes” in column “Direct input through HP IO MUX” in Table 6.12-1 can be routed to the peripherals via HP IO MUX, or via HP GPIO matrix, while the other input signals can only be routed to the peripherals via HP GPIO matrix. 2  There are only 21 inputs from GPIO SYNC to HP GPIO matrix, since ESP32-C5 provides 21 GPIO pins available for users in total. 3  The pins are controlled by the signals: IE, OE, WPU, and WPD. 4  Peripheral outputs marked “yes” in column “Direct output through HP IO MUX” in Table 6.12-1 can be routed to pins via HP IO MUX or via HP GPIO matrix, while the other output signals can only be routed to pins via HP GPIO matrix. 5  There are 29 outputs (corresponding to GPIO pin X: 0∼14, 23∼28) from HP GPIO matrix to HP IO MUX. Espressif Systems 207 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX 6  There are peripheral inputs only through HP IO MUX. 7  There are peripheral outputs only through HP IO MUX. Figure 6.3-2 shows the internal structure of a pad, which is an electrical interface between the chip logic and the GPIO pin. The structure is applicable to all GPIO pins and can be controlled using IE, OE, WPU, and WPD signals. For the configuration of these signals, see IO_MUX_GPIOx_REG or LP_IO_MUX_GPIOx_REG. Figure 6.3-2. Internal Structure of a Pad • IE: input enable • OE: output enable • WPU: internal weak pull-up resistor • WPD: internal weak pull-down resistor • Bonding pad: a terminal point of the chip logic used to make a physical connection from the chip die to GPIO pin in the chip package 6.4 Peripheral Input via GPIO Matrix 6.4.1 Overview To receive a peripheral input signal via HP GPIO matrix, • Configure the matrix to source the peripheral input signal from one of the 21 GPIOs (0∼14, 23∼28), see Table 6.12-1. • Configure the peripheral signal to receive input signal via HP GPIO matrix. • Configure the GPIO pin to be controlled by HP IO MUX. For detailed configuration, see Figure 6.3-1 and Section 6.4.7. Espressif Systems 208 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX As shown in Figure 6.3-1, when GPIO matrix is used to input a signal from the pin, all external input signals are sourced from the GPIO pins and then filtered by the GPIO Filter, as shown in Step 2 in Section 6.4.7. The Glitch Filter is only available in HP GPIO matrix. The Glitch Filter hardware can filter eight of the output signals from the GPIO Filter, and the other unselected signals go directly to the GPIO SYNC hardware, as shown in Step 3 in Section 6.4.7. All signals filtered by the GPIO Filter hardware or the Glitch Filter hardware are synchronized by the GPIO SYNC hardware to IO MUX operating clock and then enter the GPIO matrix, see Section 6.4.2. Such signal filtering and synchronization features apply to all GPIO matrix signals but do not apply when using the IO MUX. 6.4.2 Signal Synchronization Only HP GPIO matrix supports this signal synchronization function. Figure 6.4-1 shows the functionality of GPIO SYNC. In the figure, negative sync and positive sync mean GPIO input is synchronized on falling edge and on rising edge of HP IO MUX operating clock respectively. GPIO Input GPIO Input Synchronization 0 1 GPIO_PINx_SYNC1_BYPASS[0] GPIO_PINx_SYNC1_BYPASS[1] GPIO_PINx_SYNC2_BYPASS[0] GPIO_PINx_SYNC2_BYPASS[1] negative sync positive sync 0 1 0 1 negative sync positive sync 0 1 First-level synchronizer Second-level synchronizer Figure 6.4-1. GPIO Input Synchronized on Rising Edge or on Falling Edge of HP IO MUX Operating Clock The synchronization function is disabled by default by the synchronizer. But when an asynchronous peripheral signal is connected to the pin, the signal should be synchronized by the two-level synchronizer (i.e., the first-level synchronizer and the second-level synchronizer as shown in Figure 6.4-1) to lower the probability of causing metastability. 6.4.3 GPIO Filter Only HP GPIO matrix supports this GPIO Filter function. When this function is enabled, only signals with a valid width of more than two clock cycles can be sampled, as illustrated in Figure 6.4-2. Espressif Systems 209 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Figure 6.4-2. GPIO Filter Timing of GPIO Input Signals 6.4.4 Glitch Filter The Glitch Filter function is exclusive to the HP GPIO matrix. The Glitch Filter hardware supports eight channels, each of which selects one signal from the 21 (0∼14, 23∼28) output signals generated by the GPIO Filter hardware. It then conducts a second round of filtering on the selected signal. This Glitch Filter hardware can be used to filter slow-speed signals. For more information, see Step 3 in Section 6.4.7.1. 6.4.5 Simple GPIO Input Both the HP GPIO matrix and LP GPIO matrix support the Simple GPIO Input function. Enabling this function allows the direct reading of the input value of a GPIO pin at any time, without the need to route the GPIO input to any peripherals. For HP GPIO matrix, to implement simple GPIO input, follow the steps below: • Set IO_MUX_GPIOx_MCU_IE in IO_MUX_GPIOx_REG, to enable pin input. • Read the GPIO input from GPIO_IN_REG[x]. For LP GPIO matrix, to implement simple GPIO input, follow the steps below: • Set LP_IOMUX_PADx_FUN_IE in LP_IO_MUX_GPIOx_REG, to enable pin input. • Read the GPIO input from LP_GPIO_IN_REG[x]. 6.4.6 GPIO Wakeup 6.4.6.1 HP GPIO Wakeup The HP GPIO wakeup feature is designed to awaken the system from Light-sleep. HP GPIO wakeup is not available when the HP system is powered down. GPIO0∼GPIO14 and GPIO23∼GPIO28 can be used to generate HP GPIO wakeup by enabling GPIO_PINx_WAKEUP_ENABLE (x: 0∼14, 23∼ 28). HP GPIO wakeup supports both high-voltage and low-voltage triggers, depending on the configuration of GPIO_PINx_INT_TYPE. Table 6.4-1. HP GPIO Wakeup Signal Trigger and Clear Conditions GPIO_PINx_INT_TYPE 1,2 Wakeup is generated when Wakeup is cleared when 5 GPIO input is high-level GPIO input is low-level Espressif Systems 210 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX 4 GPIO input is low-level GPIO input is high-level 1 x ranges from 0 to 14, 23 to 28. 2 If the field is configured to any other value, HP GPIO wakeup feature is disabled. 6.4.6.2 LP GPIO Wakeup The LP GPIO wakeup feature is designed to awaken the system from Deep-sleep. LP GPIO wakeup is not available when the LP peripherals are powered down. GPIO0∼GPIO6 can be used to generate LP GPIO wakeup by enabling LP_GPIO_PINx_WAKEUP_ENABLE (x: 0∼6). LP GPIO wakeup supports the following types, depending on the configuration of LP_GPIO_PINx_INT_TYPE: • posedge sensitive • negedge sensitive • both posedge and negedge sensitive • high-voltage sensitive and low-voltage sensitive Table 6.4-2. LP GPIO Wakeup Signal Trigger and Clear Conditions LP_GPIO_PINx_INT_TYPE 1,2 Wakeup is generated when Wakeup is cleared when 1 GPIO input toggles from low-level to high-level LP_GPIO_PINx_EDGE_WAKEUP_CLR is set 2 GPIO input toggles from high- level to low-level LP_GPIO_PINx_EDGE_WAKEUP_CLR is set 3 GPIO input toggles from high- level to low-level, or vice versa LP_GPIO_PINx_EDGE_WAKEUP_CLR is set 4 GPIO input is low-level GPIO input is high-level 5 GPIO input is high-level. GPIO input is low-level 1 x ranges from 0 to 6. 2 If the field is configured to any other value, LP GPIO wakeup feature is disabled. 6.4.7 Programming Procedure 6.4.7.1 HP GPIO Matrix To read GPIO pin X 1 into HP peripheral signal Y, follow the steps below: 1. Configure GPIO_FUNCy_IN_SEL_CFG_REG corresponding to HP peripheral signal Y in HP GPIO matrix: • Set GPIO_SIGy_IN_SEL to enable peripheral signal input via HP GPIO matrix. • Set GPIO_FUNCy_IN_SEL to the desired GPIO pin, i.e., X here. Note: some peripheral signals have no valid GPIO_SIGy_IN_SEL bit, namely, these peripherals can only receive input signals via HP GPIO matrix. Espressif Systems 211 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX 2. Optionally enable the GPIO Filter for pin input signals by setting IO_MUX_GPIOx_FILTER_EN. 3. Enable Glitch Filter feature as follows: • Configure GPIO_EXT_FILTER_CHn_INPUT_IO_NUM to m. n (0∼7) represents the channel number. m (0∼14, 23∼28) represents the GPIO pin number. • Configure GPIO_EXT_FILTER_CHn_WINDOW_WIDTH to VALUE1 and GPIO_EXT_FILTER_CHn_WINDOW_THRES to VALUE2. During VALUE1 + 1 cycles, if there are VALUE2 + 1 input signals that do not match the current output signal value, the Glitch Filter hardware inverts the output signal. GPIO_EXT_FILTER_CHn_WINDOW_WIDTH and GPIO_EXT_FILTER_CHn_WINDOW_THRES can be configured to the same value VALUE3, then only signals with a width greater than VALUE3 + 1 clock cycles will be sampled. • Set GPIO_EXT_FILTER_CHn_EN to enable channel n. An example is shown in Figure 6.4-3, where GPIO_EXT_FILTER_CHn_WINDOW_WIDTH is configured to 3 and GPIO_EXT_FILTER_CHn_WINDOW_THRES to 2. The output signal value (signal_out) keeps as “0” in the four clock cycles before T1. The input signal value (signal_in) has been “1” for three clock cycles in the same period, then the output signal is inverted to “1” after T1. Figure 6.4-3. Glitch Filter Timing Example 4. Synchronize GPIO input signals. To do so, please set GPIO_PINx_REG corresponding to GPIO pin X as follows: • Set GPIO_PINx_SYNC1_BYPASS to enable input signal synchronized on rising edge or on falling edge in the first-level synchronization, see Figure 6.4-1. • Set GPIO_PINx_SYNC2_BYPASS to enable input signal synchronized on rising edge or on falling edge in the second-level synchronization, see Figure 6.4-1. 5. Configure HP IO MUX register to enable pin input. For this end, please set IO_MUX_GPIOx_REG corresponding to GPIO pin X as follows: • Set IO_MUX_GPIOx_FUN_IE to enable input 2,3 . • Set or clear IO_MUX_GPIOx_FUN_WPU and IO_MUX_GPIOx_FUN_WPD as desired to enable or disable pull-up and pull-down resistors. Note: 1. One input pin can be connected to multiple peripheral input signals. 2. The input signal can be inverted by configuring GPIO_FUNCy_IN_INV_SEL. Espressif Systems 212 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX 3. It is possible to have an HP peripheral read a constantly low or constantly high input value without connecting this input to a pin. This can be done by selecting a special GPIO_FUNCy_IN_SEL input, instead of a GPIO number: • When GPIO_FUNCy_IN_SEL is set to 0x40, input signal is always 0. • When GPIO_FUNCy_IN_SEL is set to 0x60, input signal is always 1. Programming Example To connect UART0 RXD input signal (UORXD_in, signal index 6) to GPIO7, please follow the steps below. 1. Set GPIO_SIG6_IN_SEL in GPIO_FUNC6_IN_SEL_CFG_REG to enable peripheral signal input via HP GPIO matrix. 2. Set GPIO_FUNC6_IN_SEL in GPIO_FUNC6_IN_SEL_CFG_REG to 7, i.e., select GPIO7. 3. Set IO_MUX_GPIO7_FUN_IE in IO_MUX_GPIO7_REG to enable pin input. 6.4.7.2 LP GPIO Matrix For inputs, LP GPIO matrix only supports the GPIO wakeup function. For LP GPIO input wakeup programming, please refer to Section 6.4.6.2. 6.5 Peripheral Output via GPIO Matrix 6.5.1 Overview To output a signal from a peripheral via GPIO matrix: • Configure the HP GPIO matrix to route HP peripheral output signals (only signals with a name assigned in the column “Output signal” in Table 6.12-1) to one of the 21 GPIOs (0∼14, 23∼28). • Then the output signal is routed from the peripheral into GPIO matrix and then into IO MUX. IO MUX must be configured to set the chosen pin to GPIO function. This enables the GPIO output signal to be connected to the pin. For the detailed programming procedure, see Section 6.5.4.1. Note: There is a range of peripheral output signals (97∼100 in Table 6.12-1) which are not connected to any peripheral, but to the input signals (97∼100) directly. 6.5.2 Simple GPIO Output GPIO matrix can also be used for simple GPIO output. For this case, one GPIO pin can be configured to directly output the desired value, without routing any peripheral output to this pin. Follow the steps below to configure HP GPIO matrix for simple GPIO output: • Set GPIO_FUNCx_OUT_SEL with a special peripheral index 256 (0x100). • Configure the corresponding bit in GPIO_OUT_REG to the desired GPIO output value. Note: Espressif Systems 213 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX • The bits GPIO_OUT_REG[0∼14, 23∼28] correspond to GPIO0∼GPIO14, GPIO23∼GPIO28. • Recommended operation: use GPIO_OUT_W1TS and GPIO_OUT_W1TC to set or clear GPIO_OUT_REG. LP GPIO matrix supports only the Simple GPIO Output function. There is no need to configure function selection registers. Just configure the corresponding bit in LP_GPIO_OUT_REG to the desired GPIO output value. Note: • The bits LP_GPIO_OUT_REG[0∼6] correspond to GPIO0∼GPIO6. • Recommended operation: use LP_GPIO_OUT_DATA_W1TS and LP_GPIO_OUT_DATA_W1TC to set or clear LP_GPIO_ OUT_REG. 6.5.3 Sigma Delta Modulated Output (SDM) 6.5.3.1 Functional Description Four HP peripheral output signals (index: 76∼79 in Table 6.12-1) support 1-bit second-order sigma delta modulation. By default the output is enabled for these four channels. This Sigma Delta modulator can also output PDM (pulse density modulation) signal with configurable duty cycle. The function is: H(z) = X(z)z −1 + E(z)(1-z −1 ) 2 E(z) is quantization error and X(z) is the input. This modulator supports scaling down of IO MUX operating clock by divider 1∼256: • Set GPIO_EXT_SIGMADELTA_CLK_EN to enable the modulator clock. • Configure GPIO_EXT_SDn_PRESCALE (n = 0∼3 for the four channels). After scaling, the clock cycle is equal to one pulse output cycle from the modulator. GPIO_EXT_SDn_IN is a signed number with a range of [-128, 127] and is used to control the duty cycle 1 of PDM output signal. • GPIO_EXT_SDn_IN = -128, the duty cycle of the output signal is 0%. • GPIO_EXT_SDn_IN = 0, the duty cycle of the output signal is near 50%. • GPIO_EXT_SDn_IN = 127, the duty cycle of the output signal is near 100%. The formula for calculating PDM signal duty cycle is shown as below: Duty_Cycle = GP IO_EXT _SDn_IN + 128 256 Note: For PDM signals, duty cycle refers to the percentage of high level cycles to the whole statistical period (several pulse cycles, for example, 256 pulse cycles). Espressif Systems 214 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX 6.5.3.2 SDM Configuration The configuration of SDM is shown below: • Route one of SDM outputs to a pin via HP GPIO matrix, see Section 6.5.4.1. • Enable the modulator clock by setting GPIO_EXT_SIGMADELTA_CLK_EN. • Configure the divider value by setting GPIO_EXT_SDn_PRESCALE. • Configure the duty cycle of SDM output signal by setting GPIO_EXT_SDn_IN. 6.5.4 Programming Procedure 6.5.4.1 HP GPIO Matrix The output signals with a name assigned in the column “Output signal” in Table 6.12-1 can be set to go through the HP GPIO matrix into HP IO MUX and then to a pin. Figure 6.3-1 illustrates the configuration. To output peripheral signal Y to a particular GPIO pin X, follow the steps below: 1. Configure GPIO_FUNCx_OUT_SEL_CFG_REG and GPIO_ENABLE_REG[x] corresponding to GPIO pin X in HP GPIO matrix. Recommended operation: use corresponding W1TS (write 1 to set) and W1TC (write 1 to clear) registers to set or clear GPIO_ENABLE_REG. • Set the GPIO_FUNCx_OUT_SEL field in register GPIO_FUNCx_OUT_SEL_CFG_REG to the index of the desired peripheral output signal Y. • If the signal should always be enabled as an output, set the bit GPIO_FUNCx_OE_SEL and the corresponding bit in GPIO_ENABLE_W1TS_REG. To have the output enable signal decided by internal logic (for example, the SPIQ_oe in column “Output enable signal when GPIO_FUNCn_OE_SEL = 0” in Table 6.12-1), clear the GPIO_FUNCx_OE_SEL bit instead. • Set the corresponding bit in register GPIO_ENABLE_W1TC_REG to disable the output from the GPIO pin. 2. For an open drain output, set the field GPIO_PINx_PAD_DRIVER. 3. Configure HP IO MUX register to enable output via HP GPIO matrix. Set IO_MUX_GPIOx_REG corresponding to GPIO pin X as follows: • Set the field IO_MUX_GPIOx_MCU_SEL to desired HP IO MUX function corresponding to GPIO pin X. This is Function 1 (GPIO function), numeric value 1, for all pins. • Set the IO_MUX_GPIOx_FUN_DRV field to the desired value for output strength (0∼3). The higher the drive strength, the more current can be sourced/sunk from the pin. • If using open drain mode, set or clear the IO_MUX_GPIOx_FUN_WPU and IO_MUX_GPIOx_FUN_WPD bits to enable or disable the internal pull-up and pull-down resistors. 4. Enable hysteresis function: • See Section 6.10. Note: • The output signal from a single peripheral can be sent to multiple pins simultaneously. Espressif Systems 215 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX • The output signal can be inverted by setting GPIO_FUNCx_OUT_INV_SEL. 6.5.4.2 LP GPIO Matrix For outputs, LP GPIO matrix only supports the Simple GPIO Output function. For the detailed programming, please refer to Section 6.5.2. 6.6 Direct Input and Output via IO MUX 6.6.1 Overview Some digital signals such as SPI and JTAG can bypass GPIO matrix for better high-frequency digital performance. In this case, IO MUX is used to connect these pins directly to peripherals. This option is less flexible than routing signals via GPIO matrix, as the IO MUX register for each GPIO pin can only select from a limited number of functions, but high-frequency digital performance can be improved. ESP32-C5 provides 7 GPIO pins (GPIO0∼GPIO6) with low power (LP) capabilities. These pins can be controlled by either HP IO MUX or LP IO MUX. If controlled by LP IO MUX, these pins will bypass HP IO MUX and HP GPIO matrix for the use by peripherals in LP system. When configured as LP GPIOs, the pins can still be controlled by the peripherals in LP system during chip Deep-sleep, and wake up the chip from Deep-sleep. 6.6.2 Functional Description The pins with LP functions (GPIO0∼GPIO6) are controlled by bit[n] of LP_AON_GPIO_MUX_SEL in LP_AON_GPIO_MUX_REG (n = 0∼6). By default, all these bits are set to 0, routing all input/output signals via HP IO MUX. If bit[n] is set to 1 in LP_AON_GPIO_MUX_SEL, then input/output signals are controlled by LP IO MUX. In this mode, LP_IO_MUX_GPIOn_REG is used to control the LP GPIO pins. See 6.14-1 for the LP functions of each LP GPIO pin. Note that LP_IO_MUX_GPIOn_REG applies the LP GPIO pin numbering. In ESP32-C5, the numbering of LP GPIO pins is the same as that of the HP GPIO pins. 6.6.2.1 HP IO MUX Two fields must be configured in order to bypass HP GPIO matrix for HP peripheral input signals: 1. IO_MUX_GPIOn_MCU_SEL for the GPIO pin must be set to the required pin function. For the list of pin functions, please refer to Table 6.13-1. 2. Clear GPIO_SIGn_IN_SEL to route the input directly to the peripheral. To bypass HP GPIO matrix for HP peripheral output signals, IO_MUX_GPIOn_MCU_SEL for the GPIO pin must be set to the required pin function. 6.6.2.2 LP IO MUX To bypass LP GPIO matrix for LP peripheral input/output signals, LP_IO_MUX_GPIOn_MCU_SEL for the GPIO pin must be set to the required pin function. For the list of pin functions, please refer to Table 6.14-1. Espressif Systems 216 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Note: Not all signals can be directly connected to peripheral via IO MUX. Some input/output signals can only be connected to peripheral via GPIO matrix. See Table 6.12-1. 6.7 Analog Functions 6.7.1 Overview ESP32-C5 provides 11 GPIO pins (GPIO0∼GPIO6, GPIO8∼GPIO9, GPIO13∼GPIO14) with analog functions, including 6 LP GPIO pins and 5 HP GPIO pins. See Table 6.15-1. 6.7.2 Analog Functions When the pin is used for analog purpose, make sure this pin is left floating by configuring registers. By such way, the external analog signal is directly connected to internal analog signal via GPIO pin. The configuration is as follows: • Clear IO_MUX_GPIOn_FUN_IE, IO_MUX_GPIOn_FUN_WPU, and IO_MUX_GPIOn_FUN_WPD, to set the pin floating. • Write 1 to the corresponding bit in GPIO_ENABLE_W1TC, to clear output enable. To use these functions listed in Table 6.15-1, please refer to the following related chapters: • For XTAL_32K related functions, see Chapter 2 Low-power Management [to be added later]. • For ADC related functions, see Chapter 41 ADC Controller. • For voltage comparator related functions, see Chapter 42 Analog Voltage Comparator. Note: GPIO1 has two different analog functions, which can be used simultaneously. 6.8 Pin Functions in Light-sleep Pins may provide different functions when ESP32-C5 is in Light-sleep mode. If IO_MUX_GPIOn_SLP_SEL in register IO_MUX_GPIOn_REG for a GPIO pin is set to 1, a different set of bits will be used to control the pin when the chip is in Light-sleep mode. Table 6.8-1. Bit Used to Control IO MUX Functions in Light-sleep Mode Normal Execution Light-sleep Mode IO MUX Function OR IO_MUX_GPIOn_SLP_SEL = 0 AND IO_MUX_GPIOn_SLP_SEL = 1 Output Drive Strength IO_MUX_GPIOn_FUN_DRV IO_MUX_GPIOn_MCU_DRV Pull-up Resistor IO_MUX_GPIOn_FUN_WPU IO_MUX_GPIOn_MCU_WPU Pull-down Resistor IO_MUX_GPIOn_FUN_WPD IO_MUX_GPIOn_MCU_WPD Cont’d on next page Espressif Systems 217 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Table 6.8-1 – cont’d from previous page Normal Execution Light-sleep Mode IO MUX Function OR IO_MUX_GPIOn_SLP_SEL = 0 AND IO_MUX_GPIOn_SLP_SEL = 1 Input Enable IO_MUX_GPIOn_FUN_IE IO_MUX_GPIOn_MCU_IE Output Enable OE_SEL from GPIO matrix ∗ IO_MUX_GPIOn_MCU_OE * If IO_MUX_GPIOn_SLP_SEL is set to 0, pin functions remain the same in both normal execution and in Light-sleep mode. Please refer to Section 6.5.4.1 for how to enable output in normal execution. 6.9 Pin Hold Feature Each GPIO pin has an individual hold function controlled by Power Management Unit (PMU) or registers. When the pin is set to hold, the state is latched at that moment and will not change no matter how the internal signals change or how the IO MUX/GPIO configuration is modified. Users can use the Hold function for the pins to retain the pin state through a core reset triggered by watchdog time-out or Deep-sleep events. The Hold state of each GPIO pin is controlled by the result of OR operation of the pin’s Hold enable signal and the global Hold enable signal. • Hold signal of each individual pin: – LP_AON_GPIO_HOLD0_REG[n] (n = 0∼14, 23∼28) controls the Hold signal of each pin. • Global Hold signal: – Global Hold signal of HP GPIO pins: * PMU_TIE_HIGH_HP_PAD_HOLD_ALL: enables the global Hold signal of all HP GPIO pins. * PMU_TIE_LOW_HP_PAD_HOLD_ALL: disables the global Hold signal of all HP GPIO pins. – Global Hold signal of LP GPIO pins: * PMU_TIE_HIGH_LP_PAD_HOLD_ALL: enables the global Hold signal of all LP GPIO pins. * PMU_TIE_LOW_LP_PAD_HOLD_ALL: disables the global Hold signal of all LP GPIO pins. Enable or disable the Hold feature of the pins by one of the following ways: • Method 1: enable or disable the Hold feature of individual pins: To maintain the pin’s input/output status in Deep-sleep, set LP_AON_GPIO_HOLD0_REG[n] (where n = 0∼14, 23∼28 corresponds to GPIO0∼GPIO14, GPIO23∼GPIO28). To disable the hold function after waking up, clear the bit[n]. • Method 2: enable or disable the Hold feature of all HP/LP pins: – HP Pins Set PMU_TIE_HIGH_HP_PAD_HOLD_ALL to maintain the input/output status of all HP pins and set PMU_TIE_LOW_HP_PAD_HOLD_ALL to disable the hold function for all HP pins. – LP Pins Set PMU_TIE_HIGH_LP_PAD_HOLD_ALL to maintain the input/output status of all LP pins and set PMU_TIE_LOW_LP_PAD_HOLD_ALL to disable the hold function for all LP pins. • Method 3: Use PMU Task Espressif Systems 218 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Configure the PMU task to hold the HP pins before Deep-sleep. In Deep-sleep, the HP pins would be hold automatically by the PMU. 6.10 Hysteresis Characteristics Each GPIO pin has hysteresis functionality. When hysteresis is not enabled, as shown in Figure 6.10-1, the level flip of the signal (C) input to the chip from the PAD has only one threshold (Vt, about 1.7 V). When the voltage on the PAD is higher than Vt, the level on the C is high. Otherwise, it is low. However, noise on the PAD may affect the signal on C. Figure 6.10-1. Example of Level Flip on the Chip Pad — Hysteresis Function Not Enabled When hysteresis is enabled, as shown in Figure 6.10-2, the level flip of C has two thresholds, high-level threshold (Vth, about 1.7 V) and low-level threshold (Vtl, about 1.4 V). When the voltage of pad goes from low to high, if the voltage is higher than Vth, the level of C is high. When the voltage of PAD goes from high to low, if the voltage is lower than Vtl, the level of C is low. When the voltage of PAD is between Vth and Vtl, the level of C does not change. The hysteresis function plays an anti-interference role by mitigating the impact of noise, consequently reducing the level flip time of C. Figure 6.10-2. Example of Level Flip on the Chip Pad — Hysteresis Function Enabled To enable the hysteresis function, follow the steps below: • IO_MUX_GPIOn_HYS_SEL = 0 (n = 0∼14, 23∼28, corresponding to GPIO0∼GPIO14, GPIO23∼GPIO28) – Set EFUSE_HYS_EN_PAD to enable the hysteresis function for GPIO0∼GPIO14 and GPIO23∼GPIO28. – Or clear EFUSE_HYS_EN_PAD to disable the hysteresis function for GPIO0∼GPIO14 and GPIO23∼GPIO28. • IO_MUX_GPIOn_HYS_SEL = 1 (n = 0∼14, 23∼28, corresponding to GPIO0∼GPIO14, GPIO23∼GPIO28) Espressif Systems 219 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX – Set IO_MUX_GPIOn_HYS_EN to enable the hysteresis function for GPIOn. – Clear IO_MUX_GPIOn_HYS_EN to disable the hysteresis function for GPIOn. Recommended Operation: • Set IO_MUX_GPIOn_HYS_SEL. • Then enable or disable the the hysteresis function for GPIOn using IO_MUX_GPIOn_HYS_EN. 6.11 Power Supplies and Management of GPIO Pins 6.11.1 Power Supplies of GPIO Pins For more information on the power supply for GPIO pins, please refer to Pin Definition in ESP32-C5 Datasheet. All the pins can be used to wake up the chip from Light-sleep, but only the pins (GPIO0∼GPIO6) in VDDPST1 domain can be used to wake up the chip from Deep-sleep. 6.11.2 Power Supply Management Each ESP32-C5 pin is connected to one of the following power domains. • VDDPST1: the input power supply for LP GPIO pins • VDDPST2: the input power supply for HP GPIO pins 6.12 HP Peripheral Signal List Table 6.12-1 shows the peripheral input/output signals via HP GPIO matrix. Please pay attention to the configuration of the bit GPIO_FUNCn_OE_SEL: • GPIO_FUNCn_OE_SEL = 1: the output enable is controlled by the corresponding bit n of GPIO_ENABLE_REG: – GPIO_ENABLE_REG = 0: output is disabled. – GPIO_ENABLE_REG = 1: output is enabled. • GPIO_FUNCn_OE_SEL = 0: use the output enable signal from peripheral, for example SPIQ_oe in the column “Output enable signal when GPIO_FUNCn_OE_SEL = 0” of Table 6.12-1. Note that the signals such as SPIQ_oe can be 1 (1’d1) or 0 (1’d0), depending on the configuration of corresponding peripherals. If it’s 1’d1 in column “Output enable signal when GPIO_FUNCn_OE_SEL = 0”, it indicates that once GPIO_FUNCn_OE_SEL is cleared, the output signal is always enabled by default. Note: Signals are numbered consecutively, but not all signals are valid. • Only the signals with a name assigned in the column “Input signal” in Table 6.12-1 are valid input signals. • Only the signals with a name assigned in the column “Output signal” in Table 6.12-1 are valid output signals. Espressif Systems 220 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Table 6.12-1. Peripheral Signals via HP GPIO Matrix Signal No. Input Signal Default Value Direct Input via HP IO MUX Output Signal Output Enable Signal when GPIO_FUNCn_OE_SEL = 0 Direct Output via HP IO MUX 0 — - - ledc_ls_sig_out0 1’d1 no 1 — — — ledc_ls_sig_out1 1’d1 no 2 — — — ledc_ls_sig_out2 1’d1 no 3 — — — ledc_ls_sig_out3 1’d1 no 4 — — — ledc_ls_sig_out4 1’d1 no 5 — — — ledc_ls_sig_out5 1’d1 no 6 U0RXD_in 0 yes U0TXD_out 1’d1 yes 7 U0CTS_in 0 no U0RTS_out 1’d1 no 8 U0DSR_in 0 no U0DTR_out 1’d1 no 9 U1RXD_in 1 no U1TXD_out 1’d1 no 10 U1CTS_in 0 no U1RTS_out 1’d1 no 11 U1DSR_in 0 no U1DTR_out 1’d1 no 12 I2S_MCLK_in 0 no I2S_MCLK_out 1’d1 no 13 I2SO_BCK_in 0 no I2SO_BCK_out 1’d1 no 14 I2SO_WS_in 0 no I2SO_WS_out 1’d1 no 15 I2SI_SD_in 0 no I2SO_SD_out 1’d1 no 16 I2SI_BCK_in 0 no I2SI_BCK_out 1’d1 no 17 I2SI_WS_in 0 no I2SI_WS_out 1’d1 no 18 — — — I2SO_SD1_out 1’d1 no 19 — — — — — — 20 — — — — — — 21 — — — — — — 22 — — — — — — 23 — — — — — — 24 — — — — — — 25 — — — — — — 26 — — — — — — Espressif Systems 221 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Signal No. Input Signal Default Value Direct Input via HP IO MUX Output Signal Output Enable Signal when GPIO_FUNCn_OE_SEL = 0 Direct Output via HP IO MUX 27 cpu_gpio_in0 0 no cpu_gpio_out0 cpu_gpio_out_oen0 no 28 cpu_gpio_in1 0 no cpu_gpio_out1 cpu_gpio_out_oen1 no 29 cpu_gpio_in2 0 no cpu_gpio_out2 cpu_gpio_out_oen2 no 30 cpu_gpio_in3 0 no cpu_gpio_out3 cpu_gpio_out_oen3 no 31 cpu_gpio_in4 0 no cpu_gpio_out4 cpu_gpio_out_oen4 no 32 cpu_gpio_in5 0 no cpu_gpio_out5 cpu_gpio_out_oen5 no 33 cpu_gpio_in6 0 no cpu_gpio_out6 cpu_gpio_out_oen6 no 34 cpu_gpio_in7 0 no cpu_gpio_out7 cpu_gpio_out_oen7 no 35 usb_jtag_tdo_bridge 0 no — — — 36 — — — — — — 37 — — — — — — 38 — — — — — — 39 — — — — — — 40 — — — — — — 41 — — — — — — 42 — — — — — — 43 — — — — — — 44 — — — — — — 45 — — — — — — 46 I2CEXT0_SCL_in 1 no I2CEXT0_SCL_out I2CEXT0_SCL_oe no 47 I2CEXT0_SDA_in 1 no I2CEXT0_SDA_out I2CEXT0_SDA_oe no 48 parl_rx_data0 0 no parl_tx_data0 1’d1 no 49 parl_rx_data1 0 no parl_tx_data1 1’d1 no 50 parl_rx_data2 0 no parl_tx_data2 1’d1 no 51 parl_rx_data3 0 no parl_tx_data3 1’d1 no 52 parl_rx_data4 0 no parl_tx_data4 1’d1 no 53 parl_rx_data5 0 no parl_tx_data5 1’d1 no 54 parl_rx_data6 0 no parl_tx_data6 1’d1 no Espressif Systems 222 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Signal No. Input Signal Default Value Direct Input via HP IO MUX Output Signal Output Enable Signal when GPIO_FUNCn_OE_SEL = 0 Direct Output via HP IO MUX 55 parl_rx_data7 0 no parl_tx_data7 1’d1 no 56 FSPICLK_in 0 yes FSPICLK_out_mux FSPICLK_oe yes 57 FSPIQ_in 0 yes FSPIQ_out FSPIQ_oe yes 58 FSPID_in 0 yes FSPID_out FSPID_oe yes 59 FSPIHD_in 0 yes FSPIHD_out FSPIHD_oe yes 60 FSPIWP_in 0 yes FSPIWP_out FSPIWP_oe yes 61 FSPICS0_in 0 yes FSPICS0_out FSPICS0_oe yes 62 parl_rx_clk_in 0 no parl_rx_clk_out 1’d1 no 63 parl_tx_clk_in 0 no parl_tx_clk_out 1’d1 no 64 rmt_sig_in0 0 no rmt_sig_out0 1’d1 no 65 rmt_sig_in1 0 no rmt_sig_out1 1’d1 no 66 twai0_rx 1 no twai0_tx 1’d1 no 67 — — — twai0_bus_off_on 1’d1 no 68 — — — twai0_clkout 1’d1 no 69 — — — twai0_standby 1’d1 no 70 twai1_rx 1 no twai1_tx 1’d1 no 71 — — — twai1_bus_off_on 1’d1 no 72 — — — twai1_clkout 1’d1 no 73 — — — twai1_standby 1’d1 no 74 — — — — — — 75 — — — — — — 76 pcnt_rst_in0 0 no gpio_sd0_out 1’d1 no 77 pcnt_rst_in1 0 no gpio_sd1_out 1’d1 no 78 pcnt_rst_in2 0 no gpio_sd2_out 1’d1 no 79 pcnt_rst_in3 0 no gpio_sd3_out 1’d1 no 80 pwm0_sync0_in 0 no pwm0_out0a 1’d1 no 81 pwm0_sync1_in 0 no pwm0_out0b 1’d1 no 82 pwm0_sync2_in 0 no pwm0_out1a 1’d1 no Espressif Systems 223 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Signal No. Input Signal Default Value Direct Input via HP IO MUX Output Signal Output Enable Signal when GPIO_FUNCn_OE_SEL = 0 Direct Output via HP IO MUX 83 pwm0_f0_in 0 no pwm0_out1b 1’d1 no 84 pwm0_f1_in 0 no pwm0_out2a 1’d1 no 85 pwm0_f2_in 0 no pwm0_out2b 1’d1 no 86 pwm0_cap0_in 0 no parl_tx_cs_o 1’d1 no 87 pwm0_cap1_in 0 no — — — 88 pwm0_cap2_in 0 no — — — 89 — — — — — — 90 — — — — — — 91 — — — — — — 92 — — — — — — 93 — — — — — — 94 — — — — — — 95 — — — — — — 96 — — — — — — 97 sig_in_func_97 0 no sig_in_func97 1’d1 no 98 sig_in_func_98 0 no sig_in_func98 1’d1 no 99 sig_in_func_99 0 no sig_in_func99 1’d1 no 100 sig_in_func_100 0 no sig_in_func100 1’d1 no 101 pcnt_sig_ch0_in0 0 no FSPICS1_out FSPICS1_oe yes 102 pcnt_sig_ch1_in0 0 no FSPICS2_out FSPICS2_oe yes 103 pcnt_ctrl_ch0_in0 0 no FSPICS3_out FSPICS3_oe yes 104 pcnt_ctrl_ch1_in0 0 no FSPICS4_out FSPICS4_oe yes 105 pcnt_sig_ch0_in1 0 no FSPICS5_out FSPICS5_oe yes 106 pcnt_sig_ch1_in1 0 no — — — 107 pcnt_ctrl_ch0_in1 0 no — — — 108 pcnt_ctrl_ch1_in1 0 no — — — 109 pcnt_sig_ch0_in2 0 no — — — 110 pcnt_sig_ch1_in2 0 no — — — Espressif Systems 224 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Signal No. Input Signal Default Value Direct Input via HP IO MUX Output Signal Output Enable Signal when GPIO_FUNCn_OE_SEL = 0 Direct Output via HP IO MUX 111 pcnt_ctrl_ch0_in2 0 no — — — 112 pcnt_ctrl_ch1_in2 0 no — — — 113 pcnt_sig_ch0_in3 0 no — — — 114 pcnt_sig_ch1_in3 0 no — — — 115 pcnt_ctrl_ch0_in3 0 no — — — 116 pcnt_ctrl_ch1_in3 0 no — — — 117 ∼ 255 — — — — — — 6.13 HP IO MUX Function List Table 6.13-1 shows the HP IO MUX functions and default states of each HP GPIO pin. Table 6.13-1. HP IO MUX Pin Functions GPIO No. Name Function 0 Function 1* Function 2 Function 3 DRV Reset Notes 0 XTAL_32K_P GPIO0 GPIO0 — — 2 0 R 1 XTAL_32K_N GPIO1 GPIO1 — — 2 0 R 2 MTMS MTMS GPIO2 FSPIQ — 2 1 R 3 MTDI MTDI GPIO3 — — 2 1 R 4 MTCK MTCK GPIO4 FSPIHD — 2 1* R 5 MTDO MTDO GPIO5 FSPIWP — 2 1 R 6 GPIO6 GPIO6 GPIO6 FSPICLK — 2 0 R 7 GPIO7 SDIO_DATA1 GPIO7 FSPID — 2 1 Cont’d on next page Espressif Systems 225 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Table 6.13-1 – cont’d from previous page GPIO No. Name Function 0 Function 1* Function 2 Function 3 DRV Reset Notes 8 GPIO8 SDIO_DATA0 GPIO8 — — 2 0 — 9 GPIO9 SDIO_CLK GPIO9 — — 2 0 — 10 GPIO10 SDIO_CMD GPIO10 FSPICS0 — 2 0 — 11 U0TXD U0TXD GPIO11 — — 2 4 — 12 U0RXD U0RXD GPIO12 — — 2 1 — 13 GPIO13 SDIO_DATA3 GPIO13 — — 3 1 USB 14 GPIO14 SDIO_DATA2 GPIO14 — — 3 3* USB 23 GPIO23 GPIO23 GPIO23 — — 2 0 — 24 GPIO24 GPIO24 GPIO24 — — 2 0 — 25 GPIO25 GPIO25 GPIO25 — — 2 1 — 26 GPIO26 GPIO26 GPIO26 — — 2 1 — 27 GPIO27 GPIO27 GPIO27 — — 2 3 — 28 GPIO28 GPIO28 GPIO28 — — 2 3 — * In HP IO MUX, unused pins must be configured to GPIO function. Espressif Systems 226 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Drive Strength “DRV” column shows the drive strength of each pin after reset: • 0 - Drive current = ∼5 mA • 1 - Drive current = ∼10 mA • 2 - Drive current = ∼20 mA • 3 - Drive current = ∼40 mA Reset The default configuration of each pin after reset: • 0 - IE = 0 (input disabled) • 1 - IE = 1 (input enabled) • 3 - IE = 1, WPU = 1 (input enabled, pull-up resistor enabled) • 4 - IE = 1, OE = 1 (input enabled, output enabled) • 1* - If EFUSE_DIS_PAD_JTAG = 1, the pin MTCK is left floating after reset, i.e., IE = 1. If EFUSE_DIS_PAD_JTAG = 0, the pin MTCK is connected to internal pull-up resistor, i.e., IE = 1, WPU = 1. • 3* - IE = 1, WPU = 0. The default value of GPIO14’s USB pull-up is 1, which means the pull-up resistor is enabled. For details, please refer to the Notes below. Notes • R - LP pins. Some LP pins have analog functions. For details, see 6.15-1. • USB - USB pull-up resistor enabled – By default, the USB function is enabled for USB pins (i.e., GPIO13 and GPIO14), and the pin pull-up is decided by the USB pull-up. The USB pull-up is controlled by USB_SERIAL_JTAG_DP/DM_PULLUP and the pull-up resistor value is controlled by USB_SERIAL_JTAG_PULLUP_VALUE. For details, see ESP32-C5 Technical Reference Manual > Chapter USB Serial/JTAG Controller. – When the USB function is disabled, USB pins are used as regular GPIOs and the pin’s internal weak pull-up and pull-down resistors are disabled by default (configurable by IO_MUX_GPIOn_MCU_WPU/WPD). 6.14 LP IO MUX Function List Table 6.14-1 shows the LP IO MUX functions of each GPIO pin. GPIO pins are default controlled by HP IO MUX, so Table 6.14-1 only show functions of LP IO MUX. Table 6.14-1. LP IO MUX Pin Functions LP IO Name Function 0 Function 1* Function 2 Function 3 GPIO0 LP_UART_DTRN LP_GPIO0 — — GPIO1 LP_UART_DSRN LP_GPIO1 — — GPIO2 LP_UART_RTSN LP_GPIO2 — LP_I2C_SDA GPIO3 LP_UART_CTSN LP_GPIO3 — LP_I2C_SCL Espressif Systems 227 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX LP IO Name Function 0 Function 1* Function 2 Function 3 GPIO4 LP_UART_RXD_PAD LP_GPIO4 — — GPIO5 LP_UART_TXD_PAD LP_GPIO5 — — GPIO6 — LP_GPIO6 — — Notice: • Hardware flow control of LP_UART cannot be used with LP_I2C at the same time. • In LP IO MUX, unused pins must be configured to LP_GPIO function. • This column lists the LP GPIO names, since LP functions are configured with LP GPIO registers that use LP GPIO numbering. 6.15 GPIO Pin Analog Function List Table 6.15-1 shows the GPIO pins and their corresponding analog functions. Table 6.15-1. GPIO Pin Analog Functions Name Analog Function 0 Analog Function 1 XTAL_32K_P XTAL_32K_P XTAL_32K_N XTAL_32K_N ADC1_CH0 MTMS — ADC1_CH1 MTDI — ADC1_CH2 MTCK — ADC1_CH3 MTDO — ADC1_CH4 GPIO6 — ADC1_CH5 GPIO8 ZCD0* — GPIO9 ZCD1* — GPIO13 USB_D- — GPIO14 USB_D+ — * ZCD0 and ZCD1 are analog PAD voltage comparator functions. See Chapter 42 Analog Voltage Comparator for details. 6.16 Event Task Matrix Function In ESP32-C5, GPIO supports ETM function, that is, the ETM task of GPIO can be triggered by the ETM event of any peripheral, or the ETM task of any peripheral can be triggered by the ETM event of GPIO. For more details about ETM, please refer to Chapter 10 Event Task Matrix (ETM). Only ETM tasks and ETM events related to GPIO are introduced here. The GPIO ETM provides eight task channels x (0∼7). The ETM tasks that each task channel can receive are: • GPIO_TASK_CHx_SET: GPIO goes high when triggered. Espressif Systems 228 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX • GPIO_TASK_CHx_CLEAR: GPIO goes low when triggered. • GPIO_TASK_CHx_TOGGLE: GPIO toggles level when triggered. Below is an example to configure task channel x to control GPIOy: • Configure IO_MUX_GPIOy_MCU_SEL to 1, to select Function 1 listed in Table 6.13-1. • Configure GPIO_ENABLE_REG[y] to 1. • Configure GPIO_EXT_ETM_TASK_GPIOy_SEL to x. • Set GPIO_EXT_ETM_TASK_GPIOy_EN, to enable ETM task channel x to control GPIOy. Note: • One task channel can be selected by one or more GPIOs. • When two or three of the signals GPIO_TASK_CHx_SET, GPIO_TASK_CHx_CLEAR, and GPIO_TASK_CHx_TOGGLE of the task channel x selected by GPIOy are valid at the same time, then GPIO_TASK_CHx_SET has the highest priority, GPIO_TASK_CHx_CLEAR takes the second higher priority, and GPIO_TASK_CHx_TOGGLE has the lowest priority. • When GPIOy is controlled by ETM task channel, the values of GPIO_OUT_REG, GPIO_FUNCn_OUT_INV_SEL, and GPIO_FUNCn_OUT_SEL may be modified by the hardware. For such reason, it’s recommended to reconfigure these registers when the GPIO is free from the control of ETM task channel. GPIO has eight event channels, and the ETM events that each event channel can generate are: • GPIO_EVT_CHx_RISE_EDGE: Indicates that the output signal of the corresponding GPIO Filter (see Figure 6.3-1) has a rising edge. • GPIO_EVT_CHx_FALL_EDGE: Indicates that the output signal of the corresponding GPIO Filter (see Figure 6.3-1) has a falling edge. • GPIO_EVT_CHx_ANY_EDGE: Indicates that the output signal of the corresponding GPIO Filter (see Figure 6.3-1) is reversed. The specific configuration of the event channel is as follows: • Set GPIO_EXT_ETM_CHx_EVENT_EN to enable event channel x (0∼7). • Configure GPIO_EXT_ETM_CHx_EVENT_SEL to y (0∼14, 23∼28), i.e., select one from the 21 GPIOs. Note: One GPIO can be selected by one or more event channels. In some applications, GPIO ETM events can be used to trigger GPIO ETM tasks. For example, event channel 0 selects GPIO0, GPIO1 selects task channel 0, and the GPIO_EVT_CH0_RISE_EDGE event is used to trigger the GPIO_TASK_CH0_TOGGLE task. When a square wave signal is input to the chip through GPIO0, the chip outputs a square wave signal with a frequency divided by 2 through GPIO1. Espressif Systems 229 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX 6.17 Interrupts ESP32-C5’s HP IO MUX and HP GPIO matrix can generate the following interrupt signals that will be sent to the Interrupt Matrix. • GPIO_EXT_REG_INT • GPIO_PROCPU_INT Several internal interrupt sources from HP IO MUX and HP GPIO matrix can generate the above interrupt signals. The interrupt sources from HP IO MUX and HP GPIO matrix are listed with their trigger conditions and the resulted interrupt signals in Table 6.17-1. Table 6.17-1. HP IO MUX and HP GPIO Matrix’s Internal Interrupt Sources Internal Interrupt Source Trigger Condition Interrupt Signal GPIO_EXT_COMP_0_ALL_INT See Chapter 42 Analog Voltage Comparator GPIO_EXT_REG_INT GPIO_EXT_COMP_0_NEG_INT See Chapter 42 Analog Voltage Comparator GPIO_EXT_REG_INT GPIO_EXT_COMP_0_POS_INT See Chapter 42 Analog Voltage Comparator GPIO_EXT_REG_INT GPIO_REG_INTR GPIO_STATUS_INTERRUPT[n] & GPIO_PINn_INT_ENA[0] (n: 0∼12,23∼28) GPIO_PROCPU_INT ESP32-C5’s LP IO MUX and GPIO matrix can generate the following interrupt signal that will be sent to the LP_CORE. • LP_GPIO_INTR0 The interrupt source from LP IO MUX and LP GPIO matrix is listed with its trigger condition and the resulted interrupt signal in Table 6.17-2. Table 6.17-2. LP IO MUX and LP GPIO Matrix’s Internal Interrupt Sources Internal Interrupt Source Trigger Condition Interrupt Signal LP_GPIO_REG_INTR LP_GPIO_STATUS_INTERRUPT[n] (n: 0∼6) LP_GPIO_INTR 6.18 Register Summary 6.18.1 HP GPIO Matrix Register Summary The addresses in this section are relative to HP GPIO matrix base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Configuration Registers GPIO_STRAP_REG Strapping pin register 0x0000 RO GPIO_OUT_REG GPIO output register 0x0004 R/W/SC/WTC GPIO_OUT_W1TS_REG GPIO output set register 0x0008 WT Espressif Systems 230 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Name Description Address Access GPIO_OUT_W1TC_REG GPIO output clear register 0x000C WT GPIO_ENABLE_REG GPIO output enable register 0x0034 R/W/WTC GPIO_ENABLE_W1TS_REG GPIO output enable set register 0x0038 WT GPIO_ENABLE_W1TC_REG GPIO output enable clear register 0x003C WT GPIO_IN_REG GPIO input register 0x0064 RO GPIO_PROCPU_INT_REG CPU interrupt status register for GPIO0∼GPIO14, GPIO23∼GPIO28 0x00A4 RO Interrupt Status Registers GPIO_STATUS_REG GPIO interrupt status register 0x0074 R/W/WTC GPIO_STATUS_W1TS_REG GPIO interrupt status set register 0x0078 WT GPIO_STATUS_W1TC_REG GPIO interrupt status clear register 0x007C WT GPIO_STATUS_NEXT_REG GPIO interrupt source register 0x00B4 RO Pin Configuration Registers GPIO_PIN0_REG GPIO0 configuration register 0x00C4 R/W GPIO_PIN1_REG GPIO1 configuration register 0x00C8 R/W GPIO_PIN2_REG GPIO2 configuration register 0x00CC R/W GPIO_PIN3_REG GPIO3 configuration register 0x00D0 R/W GPIO_PIN4_REG GPIO4 configuration register 0x00D4 R/W GPIO_PIN5_REG GPIO5 configuration register 0x00D8 R/W GPIO_PIN6_REG GPIO6 configuration register 0x00DC R/W GPIO_PIN7_REG GPIO7 configuration register 0x00E0 R/W GPIO_PIN8_REG GPIO8 configuration register 0x00E4 R/W GPIO_PIN9_REG GPIO9 configuration register 0x00E8 R/W GPIO_PIN10_REG GPIO10 configuration register 0x00EC R/W GPIO_PIN11_REG GPIO11 configuration register 0x00F0 R/W GPIO_PIN12_REG GPIO12 configuration register 0x00F4 R/W GPIO_PIN13_REG GPIO13 configuration register 0x00F8 R/W GPIO_PIN14_REG GPIO14 configuration register 0x00FC R/W GPIO_PIN23_REG GPIO23 configuration register 0x0120 R/W GPIO_PIN24_REG GPIO24 configuration register 0x0124 R/W GPIO_PIN25_REG GPIO25 configuration register 0x0128 R/W GPIO_PIN26_REG GPIO26 configuration register 0x012C R/W GPIO_PIN27_REG GPIO27 configuration register 0x0130 R/W GPIO_PIN28_REG GPIO28 configuration register 0x0134 R/W Input Configuration Registers GPIO_FUNC6_IN_SEL_CFG_REG Configuration register for input signal 6 0x02DC R/W GPIO_FUNC7_IN_SEL_CFG_REG Configuration register for input signal 7 0x02E0 R/W GPIO_FUNC8_IN_SEL_CFG_REG Configuration register for input signal 8 0x02E4 R/W GPIO_FUNC9_IN_SEL_CFG_REG Configuration register for input signal 9 0x02E8 R/W GPIO_FUNC10_IN_SEL_CFG_REG Configuration register for input signal 10 0x02EC R/W GPIO_FUNC11_IN_SEL_CFG_REG Configuration register for input signal 11 0x02F0 R/W GPIO_FUNC12_IN_SEL_CFG_REG Configuration register for input signal 12 0x02F4 R/W GPIO_FUNC13_IN_SEL_CFG_REG Configuration register for input signal 13 0x02F8 R/W Espressif Systems 231 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Name Description Address Access GPIO_FUNC14_IN_SEL_CFG_REG Configuration register for input signal 14 0x02FC R/W GPIO_FUNC15_IN_SEL_CFG_REG Configuration register for input signal 15 0x0300 R/W GPIO_FUNC16_IN_SEL_CFG_REG Configuration register for input signal 16 0x0304 R/W GPIO_FUNC17_IN_SEL_CFG_REG Configuration register for input signal 17 0x0308 R/W GPIO_FUNC27_IN_SEL_CFG_REG Configuration register for input signal 27 0x0330 R/W GPIO_FUNC28_IN_SEL_CFG_REG Configuration register for input signal 28 0x0334 R/W GPIO_FUNC29_IN_SEL_CFG_REG Configuration register for input signal 29 0x0338 R/W GPIO_FUNC30_IN_SEL_CFG_REG Configuration register for input signal 30 0x033C R/W GPIO_FUNC31_IN_SEL_CFG_REG Configuration register for input signal 31 0x0340 R/W GPIO_FUNC32_IN_SEL_CFG_REG Configuration register for input signal 32 0x0344 R/W GPIO_FUNC33_IN_SEL_CFG_REG Configuration register for input signal 33 0x0348 R/W GPIO_FUNC34_IN_SEL_CFG_REG Configuration register for input signal 34 0x034C R/W GPIO_FUNC35_IN_SEL_CFG_REG Configuration register for input signal 35 0x0350 R/W GPIO_FUNC46_IN_SEL_CFG_REG Configuration register for input signal 46 0x037C R/W GPIO_FUNC47_IN_SEL_CFG_REG Configuration register for input signal 47 0x0380 R/W GPIO_FUNC48_IN_SEL_CFG_REG Configuration register for input signal 48 0x0384 R/W GPIO_FUNC49_IN_SEL_CFG_REG Configuration register for input signal 49 0x0388 R/W GPIO_FUNC50_IN_SEL_CFG_REG Configuration register for input signal 50 0x038C R/W GPIO_FUNC51_IN_SEL_CFG_REG Configuration register for input signal 51 0x0390 R/W GPIO_FUNC52_IN_SEL_CFG_REG Configuration register for input signal 52 0x0394 R/W GPIO_FUNC53_IN_SEL_CFG_REG Configuration register for input signal 53 0x0398 R/W GPIO_FUNC54_IN_SEL_CFG_REG Configuration register for input signal 54 0x039C R/W GPIO_FUNC55_IN_SEL_CFG_REG Configuration register for input signal 55 0x03A0 R/W GPIO_FUNC56_IN_SEL_CFG_REG Configuration register for input signal 56 0x03A4 R/W GPIO_FUNC57_IN_SEL_CFG_REG Configuration register for input signal 57 0x03A8 R/W GPIO_FUNC58_IN_SEL_CFG_REG Configuration register for input signal 58 0x03AC R/W GPIO_FUNC59_IN_SEL_CFG_REG Configuration register for input signal 59 0x03B0 R/W GPIO_FUNC60_IN_SEL_CFG_REG Configuration register for input signal 60 0x03B4 R/W GPIO_FUNC61_IN_SEL_CFG_REG Configuration register for input signal 61 0x03B8 R/W GPIO_FUNC62_IN_SEL_CFG_REG Configuration register for input signal 62 0x03BC R/W GPIO_FUNC63_IN_SEL_CFG_REG Configuration register for input signal 63 0x03C0 R/W GPIO_FUNC64_IN_SEL_CFG_REG Configuration register for input signal 64 0x03C4 R/W GPIO_FUNC65_IN_SEL_CFG_REG Configuration register for input signal 65 0x03C8 R/W GPIO_FUNC66_IN_SEL_CFG_REG Configuration register for input signal 66 0x03CC R/W GPIO_FUNC70_IN_SEL_CFG_REG Configuration register for input signal 70 0x03DC R/W GPIO_FUNC75_IN_SEL_CFG_REG Configuration register for input signal 75 0x03F0 R/W GPIO_FUNC76_IN_SEL_CFG_REG Configuration register for input signal 76 0x03F4 R/W GPIO_FUNC77_IN_SEL_CFG_REG Configuration register for input signal 77 0x03F8 R/W GPIO_FUNC78_IN_SEL_CFG_REG Configuration register for input signal 78 0x03FC R/W GPIO_FUNC79_IN_SEL_CFG_REG Configuration register for input signal 79 0x0400 R/W GPIO_FUNC80_IN_SEL_CFG_REG Configuration register for input signal 80 0x0404 R/W GPIO_FUNC81_IN_SEL_CFG_REG Configuration register for input signal 81 0x0408 R/W GPIO_FUNC82_IN_SEL_CFG_REG Configuration register for input signal 82 0x040C R/W Espressif Systems 232 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Name Description Address Access GPIO_FUNC83_IN_SEL_CFG_REG Configuration register for input signal 83 0x0410 R/W GPIO_FUNC84_IN_SEL_CFG_REG Configuration register for input signal 84 0x0414 R/W GPIO_FUNC85_IN_SEL_CFG_REG Configuration register for input signal 85 0x0418 R/W GPIO_FUNC86_IN_SEL_CFG_REG Configuration register for input signal 86 0x041C R/W GPIO_FUNC87_IN_SEL_CFG_REG Configuration register for input signal 87 0x0420 R/W GPIO_FUNC88_IN_SEL_CFG_REG Configuration register for input signal 88 0x0424 R/W GPIO_FUNC97_IN_SEL_CFG_REG Configuration register for input signal 97 0x0448 R/W GPIO_FUNC98_IN_SEL_CFG_REG Configuration register for input signal 98 0x044C R/W GPIO_FUNC99_IN_SEL_CFG_REG Configuration register for input signal 99 0x0450 R/W GPIO_FUNC100_IN_SEL_CFG_REG Configuration register for input signal 100 0x0454 R/W GPIO_FUNC101_IN_SEL_CFG_REG Configuration register for input signal 101 0x0458 R/W GPIO_FUNC102_IN_SEL_CFG_REG Configuration register for input signal 102 0x045C R/W GPIO_FUNC103_IN_SEL_CFG_REG Configuration register for input signal 103 0x0460 R/W GPIO_FUNC104_IN_SEL_CFG_REG Configuration register for input signal 104 0x0464 R/W GPIO_FUNC105_IN_SEL_CFG_REG Configuration register for input signal 105 0x0468 R/W GPIO_FUNC106_IN_SEL_CFG_REG Configuration register for input signal 106 0x046C R/W GPIO_FUNC107_IN_SEL_CFG_REG Configuration register for input signal 107 0x0470 R/W GPIO_FUNC108_IN_SEL_CFG_REG Configuration register for input signal 108 0x0474 R/W GPIO_FUNC109_IN_SEL_CFG_REG Configuration register for input signal 109 0x0478 R/W GPIO_FUNC110_IN_SEL_CFG_REG Configuration register for input signal 110 0x047C R/W GPIO_FUNC111_IN_SEL_CFG_REG Configuration register for input signal 111 0x0480 R/W GPIO_FUNC112_IN_SEL_CFG_REG Configuration register for input signal 112 0x0484 R/W GPIO_FUNC113_IN_SEL_CFG_REG Configuration register for input signal 113 0x0488 R/W GPIO_FUNC114_IN_SEL_CFG_REG Configuration register for input signal 114 0x048C R/W GPIO_FUNC115_IN_SEL_CFG_REG Configuration register for input signal 115 0x0490 R/W GPIO_FUNC116_IN_SEL_CFG_REG Configuration register for input signal 116 0x0494 R/W Output Configuration Registers GPIO_FUNC0_OUT_SEL_CFG_REG Configuration register for GPIO0 output 0x0AC4 varies GPIO_FUNC1_OUT_SEL_CFG_REG Configuration register for GPIO1 output 0x0AC8 varies GPIO_FUNC2_OUT_SEL_CFG_REG Configuration register for GPIO2 output 0x0ACC varies GPIO_FUNC3_OUT_SEL_CFG_REG Configuration register for GPIO3 output 0x0AD0 varies GPIO_FUNC4_OUT_SEL_CFG_REG Configuration register for GPIO4 output 0x0AD4 varies GPIO_FUNC5_OUT_SEL_CFG_REG Configuration register for GPIO5 output 0x0AD8 varies GPIO_FUNC6_OUT_SEL_CFG_REG Configuration register for GPIO6 output 0x0ADC varies GPIO_FUNC7_OUT_SEL_CFG_REG Configuration register for GPIO7 output 0x0AE0 varies GPIO_FUNC8_OUT_SEL_CFG_REG Configuration register for GPIO8 output 0x0AE4 varies GPIO_FUNC9_OUT_SEL_CFG_REG Configuration register for GPIO9 output 0x0AE8 varies GPIO_FUNC10_OUT_SEL_CFG_REG Configuration register for GPIO10 output 0x0AEC varies GPIO_FUNC11_OUT_SEL_CFG_REG Configuration register for GPIO11 output 0x0AF0 varies GPIO_FUNC12_OUT_SEL_CFG_REG Configuration register for GPIO12 output 0x0AF4 varies GPIO_FUNC13_OUT_SEL_CFG_REG Configuration register for GPIO13 output 0x0AF8 varies GPIO_FUNC14_OUT_SEL_CFG_REG Configuration register for GPIO14 output 0x0AFC varies GPIO_FUNC23_OUT_SEL_CFG_REG Configuration register for GPIO23 output 0x0B20 varies Espressif Systems 233 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Name Description Address Access GPIO_FUNC24_OUT_SEL_CFG_REG Configuration register for GPIO24 output 0x0B24 varies GPIO_FUNC25_OUT_SEL_CFG_REG Configuration register for GPIO25 output 0x0B28 varies GPIO_FUNC26_OUT_SEL_CFG_REG Configuration register for GPIO26 output 0x0B2C varies GPIO_FUNC27_OUT_SEL_CFG_REG Configuration register for GPIO27 output 0x0B30 varies GPIO_FUNC28_OUT_SEL_CFG_REG Configuration register for GPIO28 output 0x0B34 varies Clock Gate Register GPIO_CLOCK_GATE_REG GPIO clock gate register 0x0DF8 R/W Version Register GPIO_DATE_REG GPIO version register 0x0DFC R/W 6.18.2 HP IO MUX Register Summary The addresses in this section are relative to the HP IO MUX base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Configuration Registers IO_MUX_GPIO0_REG IO MUX configuration register for GPIO0 0x0000 R/W IO_MUX_GPIO1_REG IO MUX configuration register for GPIO1 0x0004 R/W IO_MUX_GPIO2_REG IO MUX configuration register for GPIO2 0x0008 R/W IO_MUX_GPIO3_REG IO MUX configuration register for GPIO3 0x000C R/W IO_MUX_GPIO4_REG IO MUX configuration register for GPIO4 0x0010 R/W IO_MUX_GPIO5_REG IO MUX configuration register for GPIO5 0x0014 R/W IO_MUX_GPIO6_REG IO MUX configuration register for GPIO6 0x0018 R/W IO_MUX_GPIO7_REG IO MUX configuration register for GPIO7 0x001C R/W IO_MUX_GPIO8_REG IO MUX configuration register for GPIO8 0x0020 R/W IO_MUX_GPIO9_REG IO MUX configuration register for GPIO9 0x0024 R/W IO_MUX_GPIO10_REG IO MUX configuration register for GPIO10 0x0028 R/W IO_MUX_GPIO11_REG IO MUX configuration register for GPIO11 0x002C R/W IO_MUX_GPIO12_REG IO MUX configuration register for GPIO12 0x0030 R/W IO_MUX_GPIO13_REG IO MUX configuration register for GPIO13 0x0034 R/W IO_MUX_GPIO14_REG IO MUX configuration register for GPIO14 0x0038 R/W IO_MUX_GPIO23_REG IO MUX configuration register for GPIO23 0x005C R/W IO_MUX_GPIO24_REG IO MUX configuration register for GPIO24 0x0060 R/W IO_MUX_GPIO25_REG IO MUX configuration register for GPIO25 0x0064 R/W IO_MUX_GPIO26_REG IO MUX configuration register for GPIO26 0x0068 R/W IO_MUX_GPIO27_REG IO MUX configuration register for GPIO27 0x006C R/W IO_MUX_GPIO28_REG IO MUX configuration register for GPIO28 0x0070 R/W Version Register IO_MUX_DATE_REG Version control register 0x01FC R/W Espressif Systems 234 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX 6.18.3 GPIO EXT Register Summary GPIO EXT registers consist of SDM registers, Glitch Filter registers, and ETM registers. The addresses in this section are relative to (HP GPIO matrix base address + 0x0F00). GPIO base address is provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access SDM Configuration Registers GPIO_EXT_SIGMADELTA_MISC_REG MISC Register 0x0004 R/W GPIO_EXT_SIGMADELTA0_REG Duty cycle configuration register for SDM channel 0 0x0008 R/W GPIO_EXT_SIGMADELTA1_REG Duty cycle configuration register for SDM channel 1 0x000C R/W GPIO_EXT_SIGMADELTA2_REG Duty cycle configuration register for SDM channel 2 0x0010 R/W GPIO_EXT_SIGMADELTA3_REG Duty cycle configuration register for SDM channel 3 0x0014 R/W PAD Comparator Configuration Registers GPIO_EXT_PAD_COMP_CONFIG_0_REGConfiguration register for zero-crossing de- tection 0x0058 R/W GPIO_EXT_PAD_COMP_FILTER_0_REG Configuration register for interrupt source mask period of zero-crossing detection 0x005C R/W Glitch Filter Configuration Registers GPIO_EXT_GLITCH_FILTER_CH0_REG Configuration register of channel 0 0x00D8 R/W GPIO_EXT_GLITCH_FILTER_CH1_REG Configuration register of channel 1 0x00DC R/W GPIO_EXT_GLITCH_FILTER_CH2_REG Configuration register of channel 2 0x00E0 R/W GPIO_EXT_GLITCH_FILTER_CH3_REG Configuration register of channel 3 0x00E4 R/W GPIO_EXT_GLITCH_FILTER_CH4_REG Configuration register of channel 4 0x00E8 R/W GPIO_EXT_GLITCH_FILTER_CH5_REG Configuration register of channel 5 0x00EC R/W GPIO_EXT_GLITCH_FILTER_CH6_REG Configuration register of channel 6 0x00F0 R/W GPIO_EXT_GLITCH_FILTER_CH7_REG Configuration register of channel 7 0x00F4 R/W ETM Configuration Registers GPIO_EXT_ETM_EVENT_CH0_CFG_REGConfiguration register of channel 0 0x0118 R/W GPIO_EXT_ETM_EVENT_CH1_CFG_REGConfiguration register of channel 1 0x011C R/W GPIO_EXT_ETM_EVENT_CH2_CFG_REGConfiguration register of channel 2 0x0120 R/W GPIO_EXT_ETM_EVENT_CH3_CFG_REGConfiguration register of channel 3 0x0124 R/W GPIO_EXT_ETM_EVENT_CH4_CFG_REGConfiguration register of channel 4 0x0128 R/W GPIO_EXT_ETM_EVENT_CH5_CFG_REGConfiguration register of channel 5 0x012C R/W GPIO_EXT_ETM_EVENT_CH6_CFG_REGConfiguration register of channel 6 0x0130 R/W GPIO_EXT_ETM_EVENT_CH7_CFG_REGConfiguration register of channel 7 0x0134 R/W GPIO_EXT_ETM_TASK_P0_CFG_REG GPIO selection register 0 0x0158 R/W GPIO_EXT_ETM_TASK_P1_CFG_REG GPIO selection register 1 0x015C R/W GPIO_EXT_ETM_TASK_P2_CFG_REG GPIO selection register 2 0x0160 R/W Espressif Systems 235 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Name Description Address Access GPIO_EXT_ETM_TASK_P3_CFG_REG GPIO selection register 3 0x0164 R/W GPIO_EXT_ETM_TASK_P4_CFG_REG GPIO selection register 4 0x0168 R/W GPIO_EXT_ETM_TASK_P5_CFG_REG GPIO selection register 5 0x016C R/W Interrupt Registers GPIO_EXT_INT_RAW_REG GPIO_EXT interrupt raw register 0x01D0 RO/WTC/SS GPIO_EXT_INT_ST_REG GPIO_EXT interrupt masked register 0x01D4 RO GPIO_EXT_INT_ENA_REG GPIO_EXT interrupt enable register 0x01D8 R/W GPIO_EXT_INT_CLR_REG GPIO_EXT interrupt clear register 0x01DC WT Version Register GPIO_EXT_VERSION_REG Version Control Register 0x01FC R/W 6.18.4 LP GPIO Matrix Register Summary The addresses in this section are relative to LP GPIO matrix base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Configuration Registers LP_GPIO_OUT_REG LP GPIO output register 0x0004 R/W/WTC LP_GPIO_OUT_W1TS_REG LP GPIO output set register 0x0008 WT LP_GPIO_OUT_W1TC_REG LP GPIO output clear register 0x000C WT LP_GPIO_ENABLE_REG LP GPIO output enable register 0x0010 R/W/WTC LP_GPIO_ENABLE_W1TS_REG LP GPIO output enable set register 0x0014 WT LP_GPIO_ENABLE_W1TC_REG LP GPIO output enable clear register 0x0018 WT LP_GPIO_IN_REG LP GPIO input register 0x001C RO LP_GPIO_STATUS_REG LP GPIO interrupt status register 0x0020 R/W/WTC LP_GPIO_STATUS_W1TS_REG LP GPIO interrupt status set register 0x0024 WT LP_GPIO_STATUS_W1TC_REG LP GPIO interrupt status clear register 0x0028 WT LP_GPIO_STATUS_NEXT_REG LP GPIO interrupt source register 0x002C RO LP_GPIO_PIN0_REG LP GPIO0 configuration register 0x0030 varies LP_GPIO_PIN1_REG LP GPIO1 configuration register 0x0034 varies LP_GPIO_PIN2_REG LP GPIO2 configuration register 0x0038 varies LP_GPIO_PIN3_REG LP GPIO3 configuration register 0x003C varies LP_GPIO_PIN4_REG LP GPIO4 configuration register 0x0040 varies LP_GPIO_PIN5_REG LP GPIO5 configuration register 0x0044 varies LP_GPIO_PIN6_REG LP GPIO6 configuration register 0x0048 varies LP_GPIO_PIN7_REG LP GPIO7 configuration register 0x004C varies LP_GPIO_FUNC0_OUT_SEL_CFG_REGConfiguration register for GPIO0 output 0x02B0 R/W LP_GPIO_FUNC1_OUT_SEL_CFG_REGConfiguration register for GPIO1 output 0x02B4 R/W LP_GPIO_FUNC2_OUT_SEL_CFG_REGConfiguration register for GPIO2 output 0x02B8 R/W LP_GPIO_FUNC3_OUT_SEL_CFG_REGConfiguration register for GPIO3 output 0x02BC R/W LP_GPIO_FUNC4_OUT_SEL_CFG_REGConfiguration register for GPIO4 output 0x02C0 R/W Espressif Systems 236 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Name Description Address Access LP_GPIO_FUNC5_OUT_SEL_CFG_REGConfiguration register for GPIO5 output 0x02C4 R/W LP_GPIO_FUNC6_OUT_SEL_CFG_REGConfiguration register for GPIO6 output 0x02C8 R/W LP_GPIO_CLOCK_GATE_REG GPIO clock gate register 0x03F8 R/W Version Register LP_GPIO_DATE_REG Version control register 0x03FC R/W 6.18.5 LP IO MUX Register Summary The addresses in this section are relative to LP IO MUX base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Configure Registers LP_IO_MUX_GPIO0_REG LP IO MUX configuration register for pin GPIO0 0x0000 R/W LP_IO_MUX_GPIO1_REG LP IO MUX configuration register for pin GPIO1 0x0004 R/W LP_IO_MUX_GPIO2_REG LP IO MUX configuration register for pin GPIO2 0x0008 R/W LP_IO_MUX_GPIO3_REG LP IO MUX configuration register for pin GPIO3 0x000C R/W LP_IO_MUX_GPIO4_REG LP IO MUX configuration register for pin GPIO4 0x0010 R/W LP_IO_MUX_GPIO5_REG LP IO MUX configuration register for pin GPIO5 0x0014 R/W LP_IO_MUX_GPIO6_REG LP IO MUX configuration register for pin GPIO6 0x0018 R/W Version Register LP_IO_MUX_DATE_REG Version control register 0x01FC R/W 6.19 Registers 6.19.1 HP GPIO Matrix Registers The addresses in this section are relative to HP GPIO matrix base address provided in Table 4.3-2 in Chapter 4 System and Memory. For how to program reserved fields, please refer to Section VII . Espressif Systems 237 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.1. GPIO_STRAP_REG (0x0000) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 GPIO_STRAPPING 0x00 15 0 Reset GPIO_STRAPPING Represents the values of GPIO strapping pins. - Bit[0]: GPIO26 - Bit[1]: MTMS - Bit[2]: MTDI - Bit[3]: GPIO27 - Bit[4]: GPIO28 - Bit[5]: GPIO7 - Bit[6]: GPIO25 - Bit[7]∼bit[15]: Invalid For more information about the functions controlled by strapping pins, see Chapter 8 Chip Boot Control. (RO) Register 6.2. GPIO_OUT_REG (0x0004) GPIO_OUT_DATA_ORIG 0x000000 31 0 Reset GPIO_OUT_DATA_ORIG Configures the output value of GPIO0∼GPIO14 and GPIO23∼GPIO28 out- put in simple GPIO output mode. 0: Low level 1: High level The value of bit[0]∼bit[14] and bit[23]∼bit[28] corresponds to the output value of GPIO0∼GPIO14 and GPIO23∼GPIO28 respectively. (R/W/SC/WTC) Espressif Systems 238 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.3. GPIO_OUT_W1TS_REG (0x0008) GPIO_OUT_W1TS 0x000000 31 0 Reset GPIO_OUT_W1TS Configures whether or not to set the output register GPIO_OUT_REG of GPIO0 ∼ GPIO14 and GPIO23 ∼ GPIO28. 0: Not set 1: The corresponding bit in GPIO_OUT_REG will be set to 1 Bit[0]∼bit[14] and bit[23]∼bit[28] are corresponding to GPIO0∼GPIO14 and GPIO23∼GPIO28. Recommended operation: use this register to set GPIO_OUT_REG. (WT) Register 6.4. GPIO_OUT_W1TC_REG (0x000C) GPIO_OUT_W1TC 0x000000 31 0 Reset GPIO_OUT_W1TC Configures whether or not to clear the output register GPIO_OUT_REG of GPIO0∼GPIO14 and GPIO23∼GPIO28 output. 0: Not clear 1: The corresponding bit in GPIO_OUT_REG will be cleared. Bit[0]∼bit[14] and bit[23]∼bit[28] are corresponding to GPIO0∼GPIO14 and GPIO23∼GPIO28. Recommended operation: use this register to clear GPIO_OUT_REG. (WT) Espressif Systems 239 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.5. GPIO_ENABLE_REG (0x0034) GPIO_ENABLE_DATA 0x000000 31 0 Reset GPIO_ENABLE_DATA Configures whether or not to enable the output of GPIO0∼GPIO14 and GPIO23∼GPIO28. 0: Not enable 1: Enable Bit[0]∼bit[14] and bit[23]∼bit[28] are corresponding to GPIO0∼GPIO14 and GPIO23∼GPIO28. (R/W/WTC) Register 6.6. GPIO_ENABLE_W1TS_REG (0x0038) GPIO_ENABLE_W1TS 0x000000 31 0 Reset GPIO_ENABLE_W1TS Configures whether or not to set the output enable register GPIO_ENABLE_REG of GPIO0∼GPIO14 and GPIO23∼GPIO28. 0: Not set 1: The corresponding bit in GPIO_ENABLE_REG will be set to 1 Bit[0]∼bit[14] and bit[23]∼bit[28] are corresponding to GPIO0∼GPIO14 and GPIO23∼GPIO28. Recommended operation: use this register to set GPIO_ENABLE_REG. (WT) Espressif Systems 240 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.7. GPIO_ENABLE_W1TC_REG (0x003C) GPIO_ENABLE_W1TC 0x000000 31 0 Reset GPIO_ENABLE_W1TC Configures whether or not to clear the output enable register GPIO_ENABLE_REG of GPIO0∼GPIO14 and GPIO23∼GPIO28. 0: Not clear 1: The corresponding bit in GPIO_ENABLE_REG will be cleared Bit[0]∼bit[14] and bit[23]∼bit[28] are corresponding to GPIO0∼GPIO14 and GPIO23∼GPIO28. Recommended operation: use this register to clear GPIO_ENABLE_REG. (WT) Register 6.8. GPIO_IN_REG (0x0064) GPIO_IN_DATA_NEXT 0x000000 31 0 Reset GPIO_IN_DATA_NEXT Represents the input value of GPIO0∼GPIO14 and GPIO23∼GPIO28. Each bit represents a pin input value: 0: Low level 1: High level Bit[0]∼bit[14] and bit[23]∼bit[28] are corresponding to GPIO0∼GPIO14 and GPIO23∼GPIO28. (RO) Espressif Systems 241 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.9. GPIO_PROCPU_INT_REG (0x00A4) GPIO_PROCPU_INT 0x000000 31 0 Reset GPIO_PROCPU_INT Represents the CPU interrupt status of GPIO0∼GPIO14 and GPIO23∼GPIO28. Bit[0]∼bit[14] and bit[23]∼bit[28] are corresponding to GPIO0∼GPIO14 and GPIO23∼GPIO28. Each bit represents: 0: Represents CPU interrupt is not enabled, or the GPIO does not generate the interrupt configured by GPIO_PINn_INT_TYPE. 1: Represents the GPIO generates an interrupt configured by GPIO_PINn_INT_TYPE after the CPU interrupt is enabled. This interrupt status is corresponding to the bit in GPIO_STATUS_REG when assert (high) enable signal (bit13 of GPIO_PINn_REG). (RO) Register 6.10. GPIO_STATUS_REG (0x0074) GPIO_STATUS_INTERRUPT 0x000000 31 0 Reset GPIO_STATUS_INTERRUPT The interrupt status of GPIO0∼ GPIO14 and GPIO23∼GPIO28, can be configured by the software. Bit[0]∼bit[14] and bit[23]∼bit[28] are corresponding to GPIO0∼GPIO14 and GPIO23∼GPIO28. Each bit represents the status of its corresponding GPIO: - 0: Represents the GPIO does not generate the interrupt configured by GPIO_PINn_INT_TYPE, or this bit is configured to 0 by the software. - 1: Represents the GPIO generates the interrupt configured by GPIO_PINn_INT_TYPE, or this bit is configured to 1 by the software. (R/W/WTC) Espressif Systems 242 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.11. GPIO_STATUS_W1TS_REG (0x0078) GPIO_STATUS_W1TS 0x000000 31 0 Reset GPIO_STATUS_W1TS Configures whether or not to set the interrupt status register GPIO_STATUS_INTERRUPT of GPIO0∼GPIO14 and GPIO23∼GPIO28. Bit[0]∼bit[14] and bit[23]∼bit[28] are corresponding to GPIO0∼GPIO14 and GPIO23∼GPIO28. The value of each bit can be: 0: Not set 1: The corresponding bit in GPIO_STATUS_INTERRUPT will be set to 1. Recommended operation: use this register to set GPIO_STATUS_INTERRUPT. (WT) Register 6.12. GPIO_STATUS_W1TC_REG (0x007C) GPIO_STATUS_W1TC 0x000000 31 0 Reset GPIO_STATUS_W1TC Configures whether or not to clear the interrupt status register GPIO_STATUS_INTERRUPT of GPIO0∼GPIO14 and GPIO23∼GPIO28. Bit[0]∼bit[14] and bit[23]∼bit[28] are corresponding to GPIO0∼GPIO14 and GPIO23∼GPIO28. The value of each bit can be: 0: Not clear 1: The corresponding bit in GPIO_STATUS_INTERRUPT will be cleared. Recommended operation: use this register to clear GPIO_STATUS_INTERRUPT. (WT) Espressif Systems 243 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.13. GPIO_STATUS_NEXT_REG (0x00B4) GPIO_STATUS_INTERRUPT_NEXT 0x000000 31 0 Reset GPIO_STATUS_INTERRUPT_NEXT Represents the interrupt source signal of GPIO0∼GPIO14 and GPIO23∼GPIO28. Each bit represents: 0: The GPIO does not generate the interrupt configured by GPIO_PINn_INT_TYPE. 1: The GPIO generates an interrupt configured by GPIO_PINn_INT_TYPE. The interrupt could be rising edge interrupt, falling edge interrupt, level sensitive interrupt and any edge interrupt. (RO) Espressif Systems 244 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.14. GPIO_PINn_REG (n: 0-28) (0x00C4+0x4*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 18 GPIO_PINn_INT_ENA 0x0 17 13 (reserved) 0 0 12 11 GPIO_PINn_WAKEUP_ENABLE 0 10 GPIO_PINn_INT_TYPE 0x0 9 7 (reserved) 0 0 6 5 GPIO_PINn_SYNC1_BYPASS 0x0 4 3 GPIO_PINn_PAD_DRIVER 0 2 GPIO_PINn_SYNC2_BYPASS 0x0 1 0 Reset GPIO_PINn_SYNC2_BYPASS Configures whether or not to synchronize GPIO input data on either edge of IO MUX operating clock for the second-level synchronization. 0: Not synchronize 1: Synchronize on falling edge 2: Synchronize on rising edge 3: Synchronize on rising edge (R/W) GPIO_PINn_PAD_DRIVER Configures to select pin drive mode. 0: Normal output 1: Open drain output (R/W) GPIO_PINn_SYNC1_BYPASS Configures whether or not to synchronize GPIO input data on either edge of IO MUX operating clock for the first-level synchronization. 0: Not synchronize 1: Synchronize on falling edge 2: Synchronize on rising edge 3: Synchronize on rising edge (R/W) GPIO_PINn_INT_TYPE Configures GPIO interrupt type. 0: GPIO interrupt disabled 1: Rising edge trigger 2: Falling edge trigger 3: Any edge trigger 4: Low level trigger 5: High level trigger (R/W) GPIO_PINn_WAKEUP_ENABLE Configures whether or not to enable GPIO wakeup function. 0: Disable 1: Enable This function only wakes up the CPU from Light-sleep. (R/W) Continued on the next page... Espressif Systems 245 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.14. GPIO_PINn_REG (n: 0-28) (0x00C4+0x4*n) Continued from the previous page... GPIO_PINn_INT_ENA Configures whether or not to enable CPU interrupt or CPU non-maskable in- terrupt. - Bit[13]: Configures whether or not to enable CPU interrupt: 0: Disable 1: Enable - Bit[14]∼bit[17]: Invalid (R/W) Register 6.15. GPIO_FUNCm_IN_SEL_CFG_REG (m: 6-17) (0x02DC+0x4*(m-6)) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 9 GPIO_SIGm_IN_SEL 0 8 GPIO_FUNCm_IN_INV_SEL 0 7 GPIO_FUNCm_IN_SEL 0x60 6 0 Reset GPIO_FUNCm_IN_SEL Configures to select a pin from the 21 GPIO pins (GPIO0∼GPIO14, GPIO23∼GPIO28) to connect the input signal m. 0x0: Select GPIO0 0x1: Select GPIO1 ...... 0x1B: Select GPIO27 0x1C: Select GPIO28 Or 0x40: A constantly high input 0x60: A constantly low input (R/W) GPIO_FUNCm_IN_INV_SEL Configures whether or not to invert the input value. 0: Not invert 1: Invert (R/W) GPIO_SIGm_IN_SEL Configures whether or not to route signals via GPIO matrix. 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in IO MUX. 1: Route signals via GPIO matrix. (R/W) Espressif Systems 246 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.16. GPIO_FUNCp_IN_SEL_CFG_REG (p: 27-35) (0x0330+0x4*(p-27)) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 9 GPIO_SIGp_IN_SEL 0 8 GPIO_FUNCp_IN_INV_SEL 0 7 GPIO_FUNCp_IN_SEL 0x60 6 0 Reset GPIO_FUNCp_IN_SEL Configures to select a pin from the 21 GPIO pins (GPIO0∼GPIO14, GPIO23∼GPIO28) to connect the input signal p. 0x0: Select GPIO0 0x1: Select GPIO1 ...... 0x1B: Select GPIO27 0x1C: Select GPIO28 Or 0x40: A constantly high input 0x60: A constantly low input (R/W) GPIO_FUNCp_IN_INV_SEL Configures whether or not to invert the input value. 0: Not invert 1: Invert (R/W) GPIO_SIGp_IN_SEL Configures whether or not to route signals via GPIO matrix. 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in IO MUX. 1: Route signals via GPIO matrix. (R/W) Espressif Systems 247 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.17. GPIO_FUNCr_IN_SEL_CFG_REG (r: 46-66) (0x037C+0x4*(r-46)) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 9 GPIO_SIGr_IN_SEL 0 8 GPIO_FUNCr_IN_INV_SEL 0 7 GPIO_FUNCr_IN_SEL 0x40 6 0 Reset GPIO_FUNCr_IN_SEL Configures to select a pin from the 21 GPIO pins (GPIO0∼GPIO14, GPIO23∼GPIO28) to connect the input signal r. 0x0: Select GPIO0 0x1: Select GPIO1 ...... 0x1B: Select GPIO27 0x1C: Select GPIO28 Or 0x40: A constantly high input 0x60: A constantly low input (R/W) GPIO_FUNCr_IN_INV_SEL Configures whether or not to invert the input value. 0: Not invert 1: Invert (R/W) GPIO_SIGr_IN_SEL Configures whether or not to route signals via GPIO matrix. 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in IO MUX. 1: Route signals via GPIO matrix. (R/W) Espressif Systems 248 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.18. GPIO_FUNC70_IN_SEL_CFG_REG (0x03DC) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 9 GPIO_SIG70_IN_SEL 0 8 GPIO_FUNC70_IN_INV_SEL 0 7 GPIO_FUNC70_IN_SEL 0x40 6 0 Reset GPIO_FUNC70_IN_SEL Configures to select a pin from the 21 GPIO pins (GPIO0∼GPIO14, GPIO23∼GPIO28) to connect the input signal 70. 0x0: Select GPIO0 0x1: Select GPIO1 ...... 0x1B: Select GPIO27 0x1C: Select GPIO28 Or 0x40: A constantly high input 0x60: A constantly low input (R/W) GPIO_FUNC70_IN_INV_SEL Configures whether or not to invert the input value. 0: Not invert 1: Invert (R/W) GPIO_SIG70_IN_SEL Configures whether or not to route signals via GPIO matrix. 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in IO MUX. 1: Route signals via GPIO matrix. (R/W) Espressif Systems 249 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.19. GPIO_FUNCt_IN_SEL_CFG_REG (t: 76-88) (0x03F4+0x4*(t-76)) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 9 GPIO_SIGt_IN_SEL 0 8 GPIO_FUNCt_IN_INV_SEL 0 7 GPIO_FUNCt_IN_SEL 0x60 6 0 Reset GPIO_FUNCt_IN_SEL Configures to select a pin from the 21 GPIO pins (GPIO0∼GPIO14, GPIO23∼GPIO28) to connect the input signal t. 0x0: Select GPIO0 0x1: Select GPIO1 ...... 0x1B: Select GPIO27 0x1C: Select GPIO28 Or 0x40: A constantly high input 0x60: A constantly low input (R/W) GPIO_FUNCt_IN_INV_SEL Configures whether or not to invert the input value. 0: Not invert 1: Invert (R/W) GPIO_SIGt_IN_SEL Configures whether or not to route signals via GPIO matrix. 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in IO MUX. 1: Route signals via GPIO matrix. (R/W) Espressif Systems 250 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.20. GPIO_FUNCu_IN_SEL_CFG_REG (u: 97-116) (0x0448+0x4*(u-97)) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 9 GPIO_SIGu_IN_SEL 0 8 GPIO_FUNCu_IN_INV_SEL 0 7 GPIO_FUNCu_IN_SEL 0x60 6 0 Reset GPIO_FUNCu_IN_SEL Configures to select a pin from the 21 GPIO pins (GPIO0∼GPIO14, GPIO23∼GPIO28) to connect the input signal u. 0x0: Select GPIO0 0x1: Select GPIO1 ...... 0x1B: Select GPIO27 0x1C: Select GPIO28 Or 0x40: A constantly high input 0x60: A constantly low input (R/W) GPIO_FUNCu_IN_INV_SEL Configures whether or not to invert the input value. 0: Not invert 1: Invert (R/W) GPIO_SIGu_IN_SEL Configures whether or not to route signals via GPIO matrix. 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in IO MUX. 1: Route signals via GPIO matrix. (R/W) Espressif Systems 251 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.21. GPIO_FUNCn_OUT_SEL_CFG_REG (n: 0-14, 23-28) (0x0AC4+0x4*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 12 GPIO_FUNCn_OE_INV_SEL 0 11 GPIO_FUNCn_OE_SEL 0 10 GPIO_FUNCn_OUT_INV_SEL 0 9 GPIO_FUNCn_OUT_SEL 0x100 8 0 Reset GPIO_FUNCn_OUT_SEL Configures to select a signal Y (0 <= Y < 256) from peripheral signals to be output from GPIOn. 0: Select signal 0 1: Select signal 1 ...... 254: Select signal 254 255: Select signal 255 Or 256: Bit[n] of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and output enable. For the detailed signal list, see Table 6.12-1. (R/W/SC) GPIO_FUNCn_OUT_INV_SEL Configures whether or not to invert the output value. 0: Not invert 1: Invert (R/W/SC) GPIO_FUNCn_OE_SEL Configures to select the source of output enable signal. 0: Use output enable signal from peripheral. 1: Force the output enable signal to be sourced from bit[n] of GPIO_ENABLE_REG. (R/W) GPIO_FUNCn_OE_INV_SEL Configures whether or not to invert the output enable signal. 0: Not invert 1: Invert (R/W) Espressif Systems 252 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.22. GPIO_CLOCK_GATE_REG (0x0DF8) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 GPIO_CLK_EN 1 0 Reset GPIO_CLK_EN Configures whether or not to enable clock gate. 0: Not enable 1: Enable, the clock is free running. (R/W) Register 6.23. GPIO_DATE_REG (0x0DFC) (reserved) 0 0 0 0 31 28 GPIO_DATE 0x2312140 27 0 Reset GPIO_DATE Version control register. (R/W) 6.19.2 HP IO MUX Registers The addresses in this section are relative to the HP IO MUX base address provided in Table 4.3-2 in Chapter 4 System and Memory. For how to program reserved fields, please refer to Section VII . Espressif Systems 253 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.24. IO_MUX_GPIOn_REG (n: 0-14, 23-28) (0x0000+0x4*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 18 IO_MUX_GPIOn_HYS_SEL 0 17 IO_MUX_GPIOn_HYS_EN 0 16 IO_MUX_GPIOn_FILTER_EN 0 15 IO_MUX_GPIOn_MCU_SEL 0x1 14 12 IO_MUX_GPIOn_FUN_DRV 2 11 10 IO_MUX_GPIOn_FUN_IE 0 9 IO_MUX_GPIOn_FUN_WPU 0 8 IO_MUX_GPIOn_FUN_WPD 0 7 IO_MUX_GPIOn_MCU_DRV 0 6 5 IO_MUX_GPIOn_MCU_IE 0 4 IO_MUX_GPIOn_MCU_WPU 0 3 IO_MUX_GPIOn_MCU_WPD 0 2 IO_MUX_GPIOn_SLP_SEL 0 1 IO_MUX_GPIOn_MCU_OE 0 0 Reset IO_MUX_GPIOn_MCU_OE Configures whether or not to enable the output of GPIOn in sleep mode. 0: Disable 1: Enable (R/W) IO_MUX_GPIOn_SLP_SEL Configures whether or not to enter sleep mode for GPIOn. 0: Not enter 1: Enter (R/W) IO_MUX_GPIOn_MCU_WPD Configure whether or not to enable pull-down resistor of GPIOn in sleep mode. 0: Disable 1: Enable (R/W) IO_MUX_GPIOn_MCU_WPU Configures whether or not to enable pull-up resistor of GPIOn during sleep mode. 0: Disable 1: Enable (R/W) IO_MUX_GPIOn_MCU_IE Configures whether or not to enable the input of GPIOn during sleep mode. 0: Disable 1: Enable (R/W) IO_MUX_GPIOn_MCU_DRV Configures the drive strength of GPIOn during sleep mode. 0: 5 mA 1: 10 mA 2: 20 mA 3: 40 mA (R/W) IO_MUX_GPIOn_FUN_WPD Configures whether or not to enable pull-down resistor of GPIOn. 0: Disable 1: Enable (R/W) Continued on the next page... Espressif Systems 254 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.24. IO_MUX_GPIOn_REG (n: 0-14, 23-28) (0x0000+0x4*n) Continued from the previous page... IO_MUX_GPIOn_FUN_WPU Configures whether or not enable pull-up resistor of GPIOn. 0: Disable 1: Enable (R/W) IO_MUX_GPIOn_FUN_IE Configures whether or not to enable input of GPIOn. 0: Disable 1: Enable (R/W) IO_MUX_GPIOn_FUN_DRV Configures the drive strength of GPIOn. 0: 5 mA 1: 10 mA 2: 20 mA 3: 40 mA (R/W) IO_MUX_GPIOn_MCU_SEL Configures to select IO MUX function for this signal. 0: Select Function 0 1: Select Function 1 ...... (R/W) IO_MUX_GPIOn_FILTER_EN Configures whether or not to enable filter for pin input signals. 0: Disable 1: Enable (R/W) IO_MUX_GPIOn_HYS_EN Configures whether or not to enable the hysteresis function of the pin when IO_MUX_GPIOn_HYS_SEL is set to 1. 0: Disable 1: Enable (R/W) IO_MUX_GPIOn_HYS_SEL Configures to choose the signal for enabling the hysteresis function for GPIOn. 0: Choose the output enable signal of eFuse 1: Choose the output enable signal of IO_MUX_GPIOn_HYS_EN (R/W) Espressif Systems 255 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.25. IO_MUX_DATE_REG (0x01FC) (reserved) 0 0 0 0 31 28 IO_MUX_REG_DATE 0x2311270 27 0 Reset IO_MUX_REG_DATE Version control register (R/W) 6.19.3 GPIO EXT Registers The addresses in this section are relative to (HP GPIO matrix base address + 0x0F00). GPIO base address is provided in Table 4.3-2 in Chapter 4 System and Memory. For how to program reserved fields, please refer to Section VII . Register 6.26. GPIO_EXT_SIGMADELTA_MISC_REG (0x0004) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 GPIO_EXT_SIGMADELTA_CLK_EN 0 0 Reset GPIO_EXT_SIGMADELTA_CLK_EN Configures whether or not to enable the clock for sigma delta modulation. 0: Not enable 1: Enable (R/W) Espressif Systems 256 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.27. GPIO_EXT_SIGMADELTAn_REG (n: 0-3) (0x0008+0x4*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 GPIO_EXT_SDn_PRESCALE 0xff 15 8 GPIO_EXT_SDn_IN 0x0 7 0 Reset GPIO_EXT_SDn_IN Configures the duty cycle of sigma delta modulation output. (R/W) GPIO_EXT_SDn_PRESCALE Configures the divider value to divide IO MUX operating clock. 0: Do not divide 1∼255: The clock is divided by 2∼256 (R/W) Espressif Systems 257 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.28. GPIO_EXT_PAD_COMP_CONFIG_0_REG (0x0058) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 5 GPIO_EXT_DREF_COMP_0 0x0 4 2 GPIO_EXT_MODE_COMP_0 0 1 GPIO_EXT_XPD_COMP_0 0 0 Reset GPIO_EXT_XPD_COMP_0 Configures whether to enable the function of analog PAD voltage com- parator. 0: Disable 1: Enable (R/W) GPIO_EXT_MODE_COMP_0 Configures the reference voltage for analog PAD voltage comparator. 0: Reference voltage is the internal reference voltage, meanwhile GPIO8 PAD can be used as a regular GPIO 1: Reference voltage is the voltage on the GPIO8 PAD (R/W) GPIO_EXT_DREF_COMP_0 Configures the internal reference voltage for analog PAD voltage com- parator. 0: Internal reference voltage is 0 * VDDPST1 1: Internal reference voltage is 0.1 * VDDPST1 …... 6: Internal reference voltage is 0.6 * VDDPST1 7: Internal reference voltage is 0.7 * VDDPST1 (R/W) Espressif Systems 258 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.29. GPIO_EXT_PAD_COMP_FILTER_0_REG (0x005C) GPIO_EXT_ZERO_DET_FILTER_CNT_0 0x000000 31 0 Reset GPIO_EXT_ZERO_DET_FILTER_CNT_0 Configures the period of masking new interrupt source for analog PAD voltage comparator. Measurement unit: IO MUX operating clock cycle (R/W) Espressif Systems 259 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.30. GPIO_EXT_GLITCH_FILTER_CHn_REG (n: 0-7) (0x00D8+0x4*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 31 20 GPIO_EXT_FILTER_CHn_WINDOW_WIDTH 0x0 19 14 GPIO_EXT_FILTER_CHn_WINDOW_THRES 0x0 13 8 (reserved) 0 7 GPIO_EXT_FILTER_CHn_INPUT_IO_NUM 0x0 6 1 GPIO_EXT_FILTER_CHn_EN 0 0 Reset GPIO_EXT_FILTER_CHn_EN Configures whether or not to enable channel n of Glitch Filter. 0: Not enable 1: Enable (R/W) GPIO_EXT_FILTER_CHn_INPUT_IO_NUM Configures to select the input GPIO for Glitch Filter. 0: Select GPIO0 1: Select GPIO1 ...... 27: Select GPIO27 28: Select GPIO28 29∼63: Reserved (R/W) GPIO_EXT_FILTER_CHn_WINDOW_THRES Configures the window threshold for Glitch Filter. The window threshold should be less than or equal to GPIO_EXT_FILTER_CHn_WINDOW_WIDTH. Measurement unit: IO MUX operating clock cycle (R/W) GPIO_EXT_FILTER_CHn_WINDOW_WIDTH Configures the window width for Glitch Filter. The effective value of window width is 0∼63. Measurement unit: IO MUX operating clock cycle (R/W) Espressif Systems 260 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.31. GPIO_EXT_ETM_EVENT_CHn_CFG_REG (n: 0-7) (0x0118+0x4*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 GPIO_EXT_ETM_CHn_EVENT_EN 0 7 (reserved) 0 6 GPIO_EXT_ETM_CHn_EVENT_SEL 0x0 5 0 Reset GPIO_EXT_ETM_CHn_EVENT_SEL Configures to select GPIO for ETM event channel. 0: Select GPIO0 1: Select GPIO1 ...... 27: Select GPIO27 28: Select GPIO28 29∼63: Reserved (R/W) GPIO_EXT_ETM_CHn_EVENT_EN Configures whether or not to enable ETM event send. 0: Not enable 1: Enable (R/W) Espressif Systems 261 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.32. GPIO_EXT_ETM_TASK_P0_CFG_REG (0x0158) (reserved) 0 0 31 30 GPIO_EXT_ETM_TASK_GPIO4_EN 0 29 (reserved) 0 0 28 27 GPIO_EXT_ETM_TASK_GPIO4_SEL 0x0 26 24 GPIO_EXT_ETM_TASK_GPIO3_EN 0 23 (reserved) 0 0 22 21 GPIO_EXT_ETM_TASK_GPIO3_SEL 0x0 20 18 GPIO_EXT_ETM_TASK_GPIO2_EN 0 17 (reserved) 0 0 16 15 GPIO_EXT_ETM_TASK_GPIO2_SEL 0x0 14 12 GPIO_EXT_ETM_TASK_GPIO1_EN 0 11 (reserved) 0 0 10 9 GPIO_EXT_ETM_TASK_GPIO1_SEL 0x0 8 6 GPIO_EXT_ETM_TASK_GPIO0_EN 0 5 (reserved) 0 0 4 3 GPIO_EXT_ETM_TASK_GPIO0_SEL 0x0 2 0 Reset GPIO_EXT_ETM_TASK_GPIO0_SEL Configures to select an ETM task channel for GPIO0. 0: Select channel 0 1: Select channel 1 ...... 7: Select channel 7 GPIO_EXT_ETM_TASK_GPIO0_EN Configures whether or not to enable GPIO0 to response ETM task. 0: Not enable 1: Enable (R/W) GPIO_EXT_ETM_TASK_GPIO1_SEL Configures to select an ETM task channel for GPIO1. 0: Select channel 0 1: Select channel 1 ...... 7: Select channel 7 GPIO_EXT_ETM_TASK_GPIO1_EN Configures whether or not to enable GPIO1 to response ETM task. 0: Not enable 1: Enable (R/W) GPIO_EXT_ETM_TASK_GPIO2_SEL Configures to select an ETM task channel for GPIO2. 0: Select channel 0 1: Select channel 1 ...... 7: Select channel 7 GPIO_EXT_ETM_TASK_GPIO2_EN Configures whether or not to enable GPIO2 to response ETM task. 0: Not enable 1: Enable (R/W) Continued on the next page... Espressif Systems 262 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.32. GPIO_EXT_ETM_TASK_P0_CFG_REG (0x0158) Continued from the previous page... GPIO_EXT_ETM_TASK_GPIO3_SEL Configures to select an ETM task channel for GPIO3. 0: Select channel 0 1: Select channel 1 ...... 7: Select channel 7 GPIO_EXT_ETM_TASK_GPIO3_EN Configures whether or not to enable GPIO3 to response ETM task. 0: Not enable 1: Enable (R/W) GPIO_EXT_ETM_TASK_GPIO4_SEL Configures to select an ETM task channel for GPIO4. 0: Select channel 0 1: Select channel 1 ...... 7: Select channel 7 GPIO_EXT_ETM_TASK_GPIO4_EN Configures whether or not to enable GPIO4 to response ETM task. 0: Not enable 1: Enable (R/W) Espressif Systems 263 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.33. GPIO_EXT_ETM_TASK_P1_CFG_REG (0x015C) (reserved) 0 0 31 30 GPIO_EXT_ETM_TASK_GPIO9_EN 0 29 (reserved) 0 0 28 27 GPIO_EXT_ETM_TASK_GPIO9_SEL 0x0 26 24 GPIO_EXT_ETM_TASK_GPIO8_EN 0 23 (reserved) 0 0 22 21 GPIO_EXT_ETM_TASK_GPIO8_SEL 0x0 20 18 GPIO_EXT_ETM_TASK_GPIO7_EN 0 17 (reserved) 0 0 16 15 GPIO_EXT_ETM_TASK_GPIO7_SEL 0x0 14 12 GPIO_EXT_ETM_TASK_GPIO6_EN 0 11 (reserved) 0 0 10 9 GPIO_EXT_ETM_TASK_GPIO6_SEL 0x0 8 6 GPIO_EXT_ETM_TASK_GPIO5_EN 0 5 (reserved) 0 0 4 3 GPIO_EXT_ETM_TASK_GPIO5_SEL 0x0 2 0 Reset GPIO_EXT_ETM_TASK_GPIO5_SEL Configures to select an ETM task channel for GPIO5. 0: Select channel 0 1: Select channel 1 ...... 7: Select channel 7 GPIO_EXT_ETM_TASK_GPIO5_EN Configures whether or not to enable GPIO5 to response ETM task. 0: Not enable 1: Enable (R/W) GPIO_EXT_ETM_TASK_GPIO6_SEL Configures to select an ETM task channel for GPIO6. 0: Select channel 0 1: Select channel 1 ...... 7: Select channel 7 GPIO_EXT_ETM_TASK_GPIO6_EN Configures whether or not to enable GPIO6 to response ETM task. 0: Not enable 1: Enable (R/W) GPIO_EXT_ETM_TASK_GPIO7_SEL Configures to select an ETM task channel for GPIO7. 0: Select channel 0 1: Select channel 1 ...... 7: Select channel 7 GPIO_EXT_ETM_TASK_GPIO7_EN Configures whether or not to enable GPIO7 to response ETM task. 0: Not enable 1: Enable (R/W) Continued on the next page... Espressif Systems 264 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.33. GPIO_EXT_ETM_TASK_P1_CFG_REG (0x015C) Continued from the previous page... GPIO_EXT_ETM_TASK_GPIO8_SEL Configures to select an ETM task channel for GPIO8. 0: Select channel 0 1: Select channel 1 ...... 7: Select channel 7 GPIO_EXT_ETM_TASK_GPIO8_EN Configures whether or not to enable GPIO8 to response ETM task. 0: Not enable 1: Enable (R/W) GPIO_EXT_ETM_TASK_GPIO9_SEL Configures to select an ETM task channel for GPIO9. 0: Select channel 0 1: Select channel 1 ...... 7: Select channel 7 GPIO_EXT_ETM_TASK_GPIO9_EN Configures whether or not to enable GPIO9 to response ETM task. 0: Not enable 1: Enable (R/W) Espressif Systems 265 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.34. GPIO_EXT_ETM_TASK_P2_CFG_REG (0x0160) (reserved) 0 0 31 30 GPIO_EXT_ETM_TASK_GPIO14_EN 0 29 (reserved) 0 0 28 27 GPIO_EXT_ETM_TASK_GPIO14_SEL 0x0 26 24 GPIO_EXT_ETM_TASK_GPIO13_EN 0 23 (reserved) 0 0 22 21 GPIO_EXT_ETM_TASK_GPIO13_SEL 0x0 20 18 GPIO_EXT_ETM_TASK_GPIO12_EN 0 17 (reserved) 0 0 16 15 GPIO_EXT_ETM_TASK_GPIO12_SEL 0x0 14 12 GPIO_EXT_ETM_TASK_GPIO11_EN 0 11 (reserved) 0 0 10 9 GPIO_EXT_ETM_TASK_GPIO11_SEL 0x0 8 6 GPIO_EXT_ETM_TASK_GPIO10_EN 0 5 (reserved) 0 0 4 3 GPIO_EXT_ETM_TASK_GPIO10_SEL 0x0 2 0 Reset GPIO_EXT_ETM_TASK_GPIO10_SEL Configures to select an ETM task channel for GPIO10. 0: Select channel 0 1: Select channel 1 ...... 7: Select channel 7 GPIO_EXT_ETM_TASK_GPIO10_EN Configures whether or not to enable GPIO10 to response ETM task. 0: Not enable 1: Enable (R/W) GPIO_EXT_ETM_TASK_GPIO11_SEL Configures to select an ETM task channel for GPIO11. 0: Select channel 0 1: Select channel 1 ...... 7: Select channel 7 GPIO_EXT_ETM_TASK_GPIO11_EN Configures whether or not to enable GPIO11 to response ETM task. 0: Not enable 1: Enable (R/W) GPIO_EXT_ETM_TASK_GPIO12_SEL Configures to select an ETM task channel for GPIO12. 0: Select channel 0 1: Select channel 1 ...... 7: Select channel 7 GPIO_EXT_ETM_TASK_GPIO12_EN Configures whether or not to enable GPIO12 to response ETM task. 0: Not enable 1: Enable (R/W) Continued on the next page... Espressif Systems 266 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.34. GPIO_EXT_ETM_TASK_P2_CFG_REG (0x0160) Continued from the previous page... GPIO_EXT_ETM_TASK_GPIO13_SEL Configures to select an ETM task channel for GPIO13. 0: Select channel 0 1: Select channel 1 ...... 7: Select channel 7 GPIO_EXT_ETM_TASK_GPIO13_EN Configures whether or not to enable GPIO13 to response ETM task. 0: Not enable 1: Enable (R/W) GPIO_EXT_ETM_TASK_GPIO14_SEL Configures to select an ETM task channel for GPIO14. 0: Select channel 0 1: Select channel 1 ...... 7: Select channel 7 GPIO_EXT_ETM_TASK_GPIO14_EN Configures whether or not to enable GPIO14 to response ETM task. 0: Not enable 1: Enable (R/W) Espressif Systems 267 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.35. GPIO_EXT_ETM_TASK_P4_CFG_REG (0x0168) (reserved) 0 0 31 30 GPIO_EXT_ETM_TASK_GPIO24_EN 0 29 (reserved) 0 0 28 27 GPIO_EXT_ETM_TASK_GPIO24_SEL 0x0 26 24 GPIO_EXT_ETM_TASK_GPIO23_EN 0 23 (reserved) 0 0 22 21 GPIO_EXT_ETM_TASK_GPIO23_SEL 0x0 20 18 (reserved) 0 17 (reserved) 0 0 16 15 (reserved) 0x0 14 12 (reserved) 0 11 (reserved) 0 0 10 9 (reserved) 0x0 8 6 (reserved) 0 5 (reserved) 0 0 4 3 (reserved) 0x0 2 0 Reset GPIO_EXT_ETM_TASK_GPIO23_SEL Configures to select an ETM task channel for GPIO23. 0: Select channel 0 1: Select channel 1 ...... 7: Select channel 7 GPIO_EXT_ETM_TASK_GPIO23_EN Configures whether or not to enable GPIO23 to response ETM task. 0: Not enable 1: Enable (R/W) GPIO_EXT_ETM_TASK_GPIO24_SEL Configures to select an ETM task channel for GPIO24. 0: Select channel 0 1: Select channel 1 ...... 7: Select channel 7 GPIO_EXT_ETM_TASK_GPIO24_EN Configures whether or not to enable GPIO24 to response ETM task. 0: Not enable 1: Enable (R/W) Espressif Systems 268 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.36. GPIO_EXT_ETM_TASK_P5_CFG_REG (0x016C) (reserved) 0 0 0 0 0 0 0 0 31 24 GPIO_EXT_ETM_TASK_GPIO28_EN 0 23 (reserved) 0 0 22 21 GPIO_EXT_ETM_TASK_GPIO28_SEL 0x0 20 18 GPIO_EXT_ETM_TASK_GPIO27_EN 0 17 (reserved) 0 0 16 15 GPIO_EXT_ETM_TASK_GPIO27_SEL 0x0 14 12 GPIO_EXT_ETM_TASK_GPIO26_EN 0 11 (reserved) 0 0 10 9 GPIO_EXT_ETM_TASK_GPIO26_SEL 0x0 8 6 GPIO_EXT_ETM_TASK_GPIO25_EN 0 5 (reserved) 0 0 4 3 GPIO_EXT_ETM_TASK_GPIO25_SEL 0x0 2 0 Reset GPIO_EXT_ETM_TASK_GPIO25_SEL Configures to select an ETM task channel for GPIO25. 0: Select channel 0 1: Select channel 1 ...... 7: Select channel 7 GPIO_EXT_ETM_TASK_GPIO25_EN Configures whether or not to enable GPIO25 to response ETM task. 0: Not enable 1: Enable (R/W) GPIO_EXT_ETM_TASK_GPIO26_SEL Configures to select an ETM task channel for GPIO26. 0: Select channel 0 1: Select channel 1 ...... 7: Select channel 7 GPIO_EXT_ETM_TASK_GPIO26_EN Configures whether or not to enable GPIO26 to response ETM task. 0: Not enable 1: Enable (R/W) GPIO_EXT_ETM_TASK_GPIO27_SEL Configures to select an ETM task channel for GPIO27. 0: Select channel 0 1: Select channel 1 ...... 7: Select channel 7 GPIO_EXT_ETM_TASK_GPIO27_EN Configures whether or not to enable GPIO27 to response ETM task. 0: Not enable 1: Enable (R/W) Continued on the next page... Espressif Systems 269 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.36. GPIO_EXT_ETM_TASK_P5_CFG_REG (0x016C) Continued from the previous page... GPIO_EXT_ETM_TASK_GPIO28_SEL Configures to select an ETM task channel for GPIO28. 0: Select channel 0 1: Select channel 1 ...... 7: Select channel 7 GPIO_EXT_ETM_TASK_GPIO28_EN Configures whether or not to enable GPIO28 to response ETM task. 0: Not enable 1: Enable (R/W) Register 6.37. GPIO_EXT_INT_RAW_REG (0x01D0) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 GPIO_EXT_COMP_ALL_0_INT_RAW 0 2 GPIO_EXT_COMP_POS_0_INT_RAW 0 1 GPIO_EXT_COMP_NEG_0_INT_RAW 0 0 Reset GPIO_EXT_COMP_NEG_0_INT_RAW The raw interrupt status of GPIO_EXT_COMP_NEG_0_INT. (RO/WTC/SS) GPIO_EXT_COMP_POS_0_INT_RAW The raw interrupt status of GPIO_EXT_COMP_POS_0_INT. (RO/WTC/SS) GPIO_EXT_COMP_ALL_0_INT_RAW The raw interrupt status of GPIO_EXT_COMP_ALL_0_INT. (RO/WTC/SS) Espressif Systems 270 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.38. GPIO_EXT_INT_ST_REG (0x01D4) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 GPIO_EXT_COMP_ALL_0_INT_ST 0 2 GPIO_EXT_COMP_POS_0_INT_ST 0 1 GPIO_EXT_COMP_NEG_0_INT_ST 0 0 Reset GPIO_EXT_COMP_NEG_0_INT_ST The interrupt status of GPIO_EXT_COMP_NEG_0_INT. (RO) GPIO_EXT_COMP_POS_0_INT_ST The interrupt status of GPIO_EXT_COMP_POS_0_INT. (RO) GPIO_EXT_COMP_ALL_0_INT_ST The interrupt status of GPIO_EXT_COMP_ALL_0_INT. (RO) Register 6.39. GPIO_EXT_INT_ENA_REG (0x01D8) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 GPIO_EXT_COMP_ALL_0_INT_ENA 1 2 GPIO_EXT_COMP_POS_0_INT_ENA 1 1 GPIO_EXT_COMP_NEG_0_INT_ENA 1 0 Reset GPIO_EXT_COMP_NEG_0_INT_ENA Write 1 to enable GPIO_EXT_COMP_NEG_0_INT. (R/W) GPIO_EXT_COMP_POS_0_INT_ENA Write 1 to enable GPIO_EXT_COMP_POS_0_INT. (R/W) GPIO_EXT_COMP_ALL_0_INT_ENA Write 1 to enable GPIO_EXT_COMP_ALL_0_INT. (R/W) Espressif Systems 271 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.40. GPIO_EXT_INT_CLR_REG (0x01DC) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 GPIO_EXT_COMP_ALL_0_INT_CLR 0 2 GPIO_EXT_COMP_POS_0_INT_CLR 0 1 GPIO_EXT_COMP_NEG_0_INT_CLR 0 0 Reset GPIO_EXT_COMP_NEG_0_INT_CLR Write 1 to clear GPIO_EXT_COMP_NEG_0_INT. (R/W) GPIO_EXT_COMP_POS_0_INT_CLR Write 1 to clear GPIO_EXT_COMP_POS_0_INT. (R/W) GPIO_EXT_COMP_ALL_0_INT_CLR Write 1 to clear GPIO_EXT_COMP_ALL_0_INT. (R/W) Register 6.41. GPIO_EXT_VERSION_REG (0x01FC) (reserved) 0 0 0 0 31 28 GPIO_EXT_DATE 0x2312140 27 0 Reset GPIO_EXT_DATE Version control register. (R/W) 6.19.4 LP GPIO Matrix Registers The addresses in this section are relative to LP GPIO matrix base address provided in Table 4.3-2 in Chapter 4 System and Memory. For how to program reserved fields, please refer to Section VII . Espressif Systems 272 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.42. LP_GPIO_OUT_REG (0x0004) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 LP_GPIO_OUT_DATA_ORIG 0x0 7 0 Reset LP_GPIO_OUT_DATA_ORIG Configures the output of GPIO0∼GPIO6. The value of each bit can be: 0: Low level 1: High level Bit[0]∼bit[6] are corresponding to GPIO0∼GPIO6. (R/W/WTC) Register 6.43. LP_GPIO_OUT_W1TS_REG (0x0008) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 LP_GPIO_OUT_W1TS 0x0 7 0 Reset LP_GPIO_OUT_W1TS Configures whether or not to enable the output register LP_IO_OUT_REG of GPIO0∼GPIO6. The value of each bit can be: 0: Not set 1: The corresponding bit in LP_GPIO_OUT_REG will be set to 1 Bit[0]∼bit[6] are corresponding to GPIO0∼GPIO6. Recommended operation: use this register to set LP_GPIO_OUT_REG. (WT) Espressif Systems 273 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.44. LP_GPIO_OUT_W1TC_REG (0x000C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 LP_GPIO_OUT_W1TC 0x0 7 0 Reset LP_GPIO_OUT_W1TC Configures whether or not to clear the output register LP_GPIO_OUT_REG of GPIO0∼GPIO6. The value of each bit can be: 0: Not clear 1: The corresponding bit in LP_GPIO_OUT_REG will be cleared. Bit[0]∼bit[6] are corresponding to GPIO0∼GPIO6. Recommended operation: use this register to clear LP_GPIO_OUT_REG. (WT) Register 6.45. LP_GPIO_ENABLE_REG (0x0010) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 LP_GPIO_ENABLE_DATA 0x0 7 0 Reset LP_GPIO_ENABLE_DATA Configures whether or not to enable the output of GPIO0∼GPIO6. The value of each bit can be: 0: Not enable 1: Enable Bit[0]∼bit[6] are corresponding to GPIO0∼GPIO6. (R/W/WTC) Espressif Systems 274 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.46. LP_GPIO_ENABLE_W1TS_REG (0x0014) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 LP_GPIO_ENABLE_W1TS 0x0 7 0 Reset LP_GPIO_ENABLE_W1TS Configures whether or not to set the output enable register LP_GPIO_ENABLE_REG of GPIO0∼GPIO6. The value of each bit can be: 0: Not set 1: The corresponding bit in LP_GPIO_ENABLE_REG will be set to 1 Bit[0]∼bit[6] are corresponding to GPIO0∼GPIO6. Recommended operation: use this register to set LP_GPIO_ENABLE_REG. (WT) Register 6.47. LP_GPIO_ENABLE_W1TC_REG (0x0018) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 LP_GPIO_ENABLE_W1TC 0x0 7 0 Reset LP_GPIO_ENABLE_W1TC Configures whether or not to clear the output enable register LP_GPIO_ENABLE_REG of GPIO0∼GPIO6. The value of each bit can be: 0: Not clear 1: The corresponding bit in LP_GPIO_ENABLE_REG will be cleared Bit[0]∼bit[6] are corresponding to GPIO0∼GPIO6. Recommended operation: use this register to clear LP_GPIO_ENABLE_REG. (WT) Espressif Systems 275 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.48. LP_GPIO_IN_REG (0x001C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 LP_GPIO_IN_DATA_NEXT 0x0 7 0 Reset LP_GPIO_IN_DATA_NEXT Represents the input value of GPIO0∼GPIO6. Each bit represents a pin input value: 0: Low level input 1: High level input Bit[0]∼bit[6] are corresponding to GPIO0∼GPIO6. (RO) Register 6.49. LP_GPIO_STATUS_REG (0x0020) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 LP_GPIO_STATUS_INTERRUPT 0x0 7 0 Reset LP_GPIO_STATUS_INTERRUPT Configures the interrupt status of GPIO0∼GPIO6. The value of each bit can be: 0: No interrupt 1: Interrupt is triggered Bit[0]∼bit[6] are corresponding to GPIO0∼GPIO6. This field is used together with LP_GPIO_PINn_INT_TYPE in register LP_GPIO_PINn_REG. (R/W/WTC) Espressif Systems 276 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.50. LP_GPIO_STATUS_W1TS_REG (0x0024) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 LP_GPIO_STATUS_W1TS 0x0 7 0 Reset LP_GPIO_STATUS_W1TS Configures whether or not to set the interrupt status register LP_GPIO_STATUS_INT of GPIO0∼GPIO6. The value of each bit can be: 0: Not set 1: The corresponding bit in LP_GPIO_STATUS_INT will be set Bit[0]∼bit[6] are corresponding to GPIO0∼GPIO6. Recommended operation: use this register to set LP_GPIO_STATUS_INT. (WT) Register 6.51. LP_GPIO_STATUS_W1TC_REG (0x0028) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 LP_GPIO_STATUS_W1TC 0x0 7 0 Reset LP_GPIO_STATUS_W1TC Configures whether or not to clear the interrupt status register LP_GPIO_STATUS_INT of GPIO0∼GPIO6. The value of each bit can be: 0: Not clear 1: The corresponding bit in LP_GPIO_STATUS_INT will be cleared Bit[0]∼bit[6] are corresponding to GPIO0∼GPIO6. Recommended operation: use this register to clear LP_GPIO_STATUS_INT. (WT) Espressif Systems 277 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.52. LP_GPIO_STATUS_NEXT_REG (0x002C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 LP_GPIO_STATUS_INTERRUPT_NEXT 0x0 7 0 Reset LP_GPIO_STATUS_INTERRUPT_NEXT Represents the interrupt source status of GPIO0∼GPIO6. Bit[0]∼bit[6] are corresponding to GPIO0∼7. Each bit represents: 0: Interrupt source status is invalid. 1: Interrupt source status is valid. The interrupt here can be rising-edge triggered, falling-edge triggered, any edge triggered, or level triggered. (RO) Espressif Systems 278 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.53. LP_GPIO_PINn_REG (n: 0-6) (0x0030+0x4*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 11 LP_GPIO_PINn_WAKEUP_ENABLE 0 10 LP_GPIO_PINn_INT_TYPE 0x0 9 7 (reserved) 0 6 LP_GPIO_PINn_EDGE_WAKEUP_CLR 0 5 LP_GPIO_PINn_SYNC1_BYPASS 0x0 4 3 LP_GPIO_PINn_PAD_DRIVER 0 2 LP_GPIO_PINn_SYNC2_BYPASS 0x0 1 0 Reset LP_GPIO_PINn_SYNC2_BYPASS Configures whether or not to synchronize GPIO input data on ei- ther edge of LP IO MUX operating clock for the second-level synchronization. 0: Not synchronize 1: Synchronize on falling edge 2: Synchronize on rising edge 3: Synchronize on rising edge (R/W) LP_GPIO_PINn_PAD_DRIVER Configures to select the pin dirve mode of GPIOn. 0: Normal output 1: Open drain output (R/W) LP_GPIO_PINn_SYNC1_BYPASS Configures whether or not to synchronize GPIO input data on ei- ther edge of LP IO MUX operating clock for the first-level synchronization. 0: Not synchronize 1: Synchronize on falling edge 2: Synchronize on rising edge 3: Synchronize on rising edge (R/W) LP_GPIO_PINn_EDGE_WAKEUP_CLR Configures whether or not to clear the edge wake-up status of GPIO0∼GPIO6. 0: No effect 1: Clear (WT) LP_GPIO_PINn_INT_TYPE Configures GPIOn interrupt type. 0: GPIO interrupt disabled 1: Rising edge trigger 2: Falling edge trigger 3: Any edge trigger 4: Low level trigger 5: High level trigger (R/W) Continued on the next page... Espressif Systems 279 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.53. LP_GPIO_PINn_REG (n: 0-6) (0x0030+0x4*n) Continued from the previous page... LP_GPIO_PINn_WAKEUP_ENABLE Configures whether or not to enable GPIOn wake-up function. 0: Not enable 1: Enable This function is disabled when PD_LP_PERI is powered off. (R/W) Register 6.54. LP_GPIO_FUNCn_OUT_SEL_CFG_REG (n: 0-6) (0x02B0+0x4*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 LP_GPIO_FUNCn_OE_INV_SEL 0 2 (reserved) 0 1 LP_GPIO_FUNCn_OUT_INV_SEL 0 0 Reset LP_GPIO_FUNCn_OUT_INV_SEL Configures whether or not to invert the output value. 0: Not invert 1: Invert (R/W) LP_GPIO_FUNCn_OE_INV_SEL Configures whether or not to invert the output enable signal. 0: Not invert 1: Invert (R/W) Register 6.55. LP_GPIO_CLOCK_GATE_REG (0x03F8) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 LP_GPIO_CLK_EN 1 0 Reset LP_GPIO_CLK_EN Configure to enable the GPIO clock gate or not. 0: Not enable 1: Enable (R/W) Espressif Systems 280 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.56. LP_GPIO_DATE_REG (0x03FC) (reserved) 0 0 0 0 31 28 LP_GPIO_DATE 0x2312010 27 0 Reset LP_GPIO_DATE Version control register. (R/W) 6.19.5 LP IO MUX Registers The addresses in this section are relative to LP IO MUX base address provided in Table 4.3-2 in Chapter 4 System and Memory. For how to program reserved fields, please refer to Section VII . Espressif Systems 281 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.57. LP_IO_MUX_GPIOn_REG (n: 0-6) (0x0000+0x4*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 18 LP_IO_MUX_GPIOn_HYS_SEL 0 17 LP_IO_MUX_GPIOn_HYS_EN 0 16 LP_IO_MUX_GPIOn_FILTER_EN 0 15 LP_IO_MUX_GPIOn_MCU_SEL 0x1 14 12 LP_IO_MUX_GPIOn_FUN_DRV 2 11 10 LP_IO_MUX_GPIOn_FUN_IE 0 9 LP_IO_MUX_GPIOn_FUN_WPU 0 8 LP_IO_MUX_GPIOn_FUN_WPD 0 7 LP_IO_MUX_GPIOn_MCU_DRV 0 6 5 LP_IO_MUX_GPIOn_MCU_IE 0 4 LP_IO_MUX_GPIOn_MCU_WPU 0 3 LP_IO_MUX_GPIOn_MCU_WPD 0 2 LP_IO_MUX_GPIOn_SLP_SEL 0 1 LP_IO_MUX_GPIOn_MCU_OE 0 0 Reset LP_IO_MUX_GPIOn_MCU_OE Configures whether or not to enable the output of GPIOn during sleep mode. 0: Not enable 1: Enable (R/W) LP_IO_MUX_GPIOn_SLP_SEL Configures whether or not to enable the sleep mode for GPIOn. 0: Not enable 1: Enable (R/W) LP_IO_MUX_GPIOn_MCU_WPD Configures whether or not to enable the pull-down resistor of GPIOn during sleep mode. 0: Not enable 1: Enable (R/W) LP_IO_MUX_GPIOn_MCU_WPU Configures whether or not to enable the pull-up resistor of GPIOn during sleep mode. 0: Not enable 1: Enable (R/W) LP_IO_MUX_GPIOn_MCU_IE Configures whether or not to enable the input of GPIOn during sleep mode. 0: Not enable 1: Enable (R/W) LP_IO_MUX_GPIOn_MCU_DRV Configures the drive strength of GPIOn during sleep mode. 0: ∼5 mA 1: ∼10 mA 2: ∼20 mA 3: ∼40 mA (R/W) Continued on the next page... Espressif Systems 282 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.57. LP_IO_MUX_GPIOn_REG (n: 0-7) (0x0000+0x4*n) Continued from the previous page... LP_IO_MUX_GPIOn_FUN_WPD Configures whether or not to enable the pull-down resistor of GPIOn in normal execution mode. 0: Not enable 1: Enable (R/W) LP_IO_MUX_GPIOn_FUN_WPU Configures whether or not to enable the pull-up resistor of GPIOn in normal execution mode. 0: Not enable 1: Enable (R/W) LP_IO_MUX_GPIOn_FUN_IE Configures whether or not to enable the input of GPIOn in normal ex- ecution mode. 0: Not enable 1: Enable (R/W) LP_IO_MUX_GPIOn_FUN_DRV Configures the drive strength of GPIOn in normal execution mode. 0: ∼5 mA 1: ∼10 mA 2: ∼20 mA 3: ∼40 mA (R/W) LP_IO_MUX_GPIOn_MCU_SEL Configures to select the LP IO MUX function for GPIOn in normal execution mode. 0: Select Function 0 1: Select Function 1 ...... (R/W) LP_IO_MUX_GPIOn_FILTER_EN Configures whether or not to enable filter for pin input signals. 0: Disable 1: Enable (R/W) LP_IO_MUX_GPIOn_HYS_EN Configures whether or not to enable the hysteresis function of the pin when LP_IO_MUX_GPIOn_HYS_SEL is set to 1. 0: Disable 1: Enable (R/W) Continued on the next page... Espressif Systems 283 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 6 GPIO Matrix and IO MUX Register 6.57. LP_IO_MUX_GPIOn_REG (n: 0-7) (0x0000+0x4*n) Continued from the previous page... LP_IO_MUX_GPIOn_HYS_SEL Configures to choose the signal for enabling the hysteresis function for GPIOn. 0: Choose the output enable signal of eFuse 1: Choose the output enable signal of LP_IO_MUX_GPIOn_HYS_EN (R/W) Register 6.58. LP_IO_MUX_DATE_REG (0x01FC) (reserved) 0 0 0 0 31 28 LP_IO_MUX_REG_DATE 0x2211270 27 0 Reset LP_IO_MUX_REG_DATE Version control register. (R/W) Espressif Systems 284 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Chapter 7 Reset and Clock 7.1 Reset 7.1.1 Overview ESP32-C5 provides four types of reset that occur at different levels, namely CPU Reset, Core Reset, System Reset, and Chip Reset. All reset types mentioned above (except Chip Reset) preserve the data stored in internal memory. Figure 7.1-1 shows the scopes of affected subsystems by each type of reset. 7.1.2 Architectural Overview Figure 7.1-1. Reset Types ESP32-C5’s Digital System can be divided into two parts: High Performance System (HP system) that includes Digital Core, Wireless Mac and Baseband, and HP SRAM, and Low Power System (LP system) that only includes some low-power peripherals and LP SRAM. See Figure 7.1-1 for details (note that HP SRAM and LP SRAM would not be reset, so they are not shown in the figure). 7.1.3 Features • Four reset types: Espressif Systems 285 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock – CPU Reset: resets CPU core. Once such a reset is released, the instructions from the CPU reset vector (0x40000000) will be executed. – Core Reset: resets the whole digital system except LP system, including CPU, peripherals, digital GPIOs, Wireless MAC and Baseband. – System Reset: resets the whole digital system, including LP system. – Chip Reset: resets the whole chip, including the digital system and analog system. • Software reset and hardware reset: – Software Reset: triggered via software by configuring the corresponding registers of CPU, see Chapter 2 Low-power Management [to be added later]. – Hardware Reset: triggered directly by the hardware. 7.1.4 Functional Description CPU will be reset immediately when any type of reset above occurs. Users can retrieve reset source codes by reading LP_CLKRST_RESET_CAUSE after the reset is released. The current reset source recorded in the LP_CLKRST_RESET_CAUSE register can be cleared by configuring LP_CLKRST_CORE0_RESET_CAUSE_CLR. Table 7.1-1 lists possible reset sources and the types of reset they trigger. When multiple reset sources are active simultaneously, the reset source recorded in LP_CLKRST_RESET_CAUSE is the most top one among the active reset sources listed in Table 7.1-1. When multiple reset sources are active but not at the same time, LP_CLKRST_RESET_CAUSE records the most recent reset source. Table 7.1-1. Reset Source Code Source Reset Type Note 0x1A CPU lockup reset CPU Reset — 0x01 Chip reset 1 Chip Reset — 0x12 Super watchdog reset System Re- set See Chapter 13 Watchdog Timers (WDT) 0x19 Power glitch reset System Re- set See Chapter 18 Power Supply Detector 0x0F Brown-out system re- set Chip Reset or System Reset Triggered by brown-out detector 2 0x10 RWDT system reset System Re- set See Chapter 13 Watchdog Timers (WDT) 0x09 RWDT core reset Core Reset See Chapter 13 Watchdog Timers (WDT) 0x14 eFuse reset Core Reset Triggered by eFuse CRC error check 0x07 MWDT0 core reset Core Reset See Chapter 13 Watchdog Timers (WDT) 0x08 MWDT1 core reset Core Reset See Chapter 13 Watchdog Timers (WDT) 0x15 USB (UART) reset Core Reset Triggered when external USB host sends a specific command to the serial interface of USB Serial/JTAG Controller. See Chapter 33 USB Serial/JTAG Controller Cont’d on next page Espressif Systems 286 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Table 7.1-1 – cont’d from previous page Code Source Reset Type Note 0x16 USB (JTAG) reset Core Reset Triggered when external USB host sends a specific command to the JTAG interface of USB Serial/JTAG Controller. See Chapter 33 USB Serial/JTAG Controller 0x03 Software system reset Core Reset Triggered by configuring LP_AON_HPSYS_SW_RESET 0x0D RWDT CPU reset CPU Reset See Chapter 13 Watchdog Timers (WDT) 0x0C Software CPU reset CPU Reset Triggered by configuring LP_AON_CPU_CORE0_SW_RESET 0x0B MWDT0 CPU reset CPU Reset See Chapter 13 Watchdog Timers (WDT) 0x11 MWDT1 CPU reset CPU Reset See Chapter 13 Watchdog Timers (WDT) 0x18 JTAG CPU reset CPU Reset Triggered when a ”JDB Resetting CPU” instruction is received 0x05 Deep-sleep reset Core Reset See Chapter 2 Low-power Management [to be added later] 1 Chip Reset can be triggered by the following sources: • Chip power-up. • Brown-out detector. 2 Once brown-out status is detected, the detector will trigger System Reset or Chip Reset, depending on the register configuration. See Chapter 2 Low-power Management [to be added later]. 7.1.5 Peripheral Reset Peripherals can be reset individually by configuring corresponding registers, or globally by core reset, system reset, or chip reset. After releasing peripherals from reset, the reset release status registers can be read to determine the reset status. These registers turning to 1 indicates that peripherals have been released from reset and can operate properly. The reset registers of ESP32-C5’s HP system peripherals are controlled by the Power/Clock/Reset (PCR) module. Please see 7.4.1 PCR Register Summary for the reset registers of HP system peripherals and 7.4.2 LP System Clock Register Summary for the clock registers of low-power system peripherals. 7.2 Clock 7.2.1 Overview ESP32-C5 clocks are mainly sourced from oscillator (OSC), RC, and PLL circuits, and then processed by the dividers or selectors. This allows functional modules to select their working clock according to their power consumption and performance requirements. Figure 7.2-1 shows the system clock structure. Espressif Systems 287 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock 7.2.2 Architectural Overview CPU_CLK M U X PLL_F240M_CLK XTAL_CLK CPU PERI MUX CRYPT O_CL K LP SYSTEM RC_SLOW_CLK XTAL32K_CLK OSC_SLOW _CLK XTAL_D2_CLK RC_FAST_CLK CLK_MANAGEMENT DIV OSC 40 MHz PLL XTAL_N XTAL_P RC 20 MHz OSC 32 kHz XTAL_32K_P XTAL_32K_N RC 130 kHz LEDC_SCLK XTAL_CLK RC_FAST_CLK DIV DIV APB_CLK DIV AHB_CLK UART0 /1_CL K PLL_F80M_CLK RC_FAST_CLK XTAL 32kHz MUX MCPWM_CLK XTAL_CLK PLL_F160M_CLK RC_FAST_CLK LP_SLOW_CLK LP_FAST_CLK LP_DYN_FAST_CLK LP_DYN_SLOW_CLK DIV DIV HP_ROOT_CLK (max 240M) PLL_F160M_CLK MUX MUX DIV DIV M U X M U X M U X XTAL_CLK RC_FAST_CLK RC_FAST_CLK XTAL_CLK XTAL_CLK PLL_F480M_CLK PLL_F80M_CLK DIV DIV PLL_F480M_CLK Figure 7.2-1. System Clock 7.2.3 Features ESP32-C5 clocks can be classified into two types depending on their frequencies: • High-performance (HP) clocks for devices working at a higher frequency, such as CPU and digital peripherals – PLL_F480M_CLK (480 MHz): internal PLL clock. Its reference clock is XTAL_CLK – XTAL_CLK (48 MHz/40 MHz): external crystal clock • Low-power (LP) clocks for low-power system and some peripherals working in low-power mode – XTAL32K_CLK (32 kHz): external crystal clock – RC_FAST_CLK (20 MHz by default): internal fast RC oscillator with adjustable frequency – RC_SLOW_CLK (130 kHz by default): internal slow RC oscillator – OSC_SLOW_CLK (32 kHz by default): external slow clock input through XTAL_32K_P. After configuring these two GPIO, also configure the Hold function (see Chapter 6 GPIO Matrix and IO MUX Espressif Systems 288 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock > 6.9 Pin Hold Feature) The crystal frequency of ESP32-C5 can be either 40 MHz or 48 MHz. The boot mode, along with MTMS, EFUSE_XTAL_48M_SEL and EFUSE_XTAL_48M_SEL_MODE, determines the crystal frequency. Table 7.2-1. Crystal Frequency Crystal Frequency Boot Mode eFuse 1 eFuse 2 b MTMS 40 MHz SPI Boot x even number of 1 x d 48 MHz odd number of 1 x 40 MHz Joint Download Boot 1 even number of 1 x 48 MHz odd number of 1 x 40 MHz 0 x 0 c 48 MHz 1 c a eFuse 1: EFUSE_XTAL_48M_SEL_MODE b eFuse 2: EFUSE_XTAL_48M_SEL[2:0] c In the Joint Download Boot mode, the user needs to specify the level of the strapping pin MTMS. d x: values that have no effect on the result and can therefore be ignored. 7.2.4 Functional Description 7.2.4.1 HP System Clock As Figure 7.2-1 shows, CPU_CLK is the master clock for CPU and its frequency can be as high as 240 MHz. Alternatively, CPU can run at lower frequencies, such as at 2 MHz, to achieve lower power consumption. CPU_CLK shares the same clock sources with AHB_CLK and APB_CLK. Users can select from XTAL_CLK, PLL_240M_CLK, PLL_160M_CLK, or RC_FAST_CLK as the clock source of CPU_CLK by configuring PCR_SOC_CLK_SEL. For details, see Table 7.2-2 and Table 7.2-3. By default, the CPU clock is sourced from XTAL_CLK with a division factor of 1. Table 7.2-2. CPU_CLK Clock Source PCR_SOC_CLK_SEL CPU Clock Source 0 XTAL_CLK 1 RC_FAST_CLK 2 PLL_F160M_CLK 3 PLL_F240M_CLK Espressif Systems 289 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Table 7.2-3. Frequency of CPU_CLK, AHB_CLK and HP_ROOT_CLK Clock Source Frequency HP_ROOT_CLK PLL_F240M_CLK 240 MHz PLL_F160M_CLK 160 MHz XTAL_CLK 48 MHz/40 MHz RC_FAST_CLK 20 MHz CPU_CLK 1 HP_ROOT_CLK f HP_ROOT_CLK / ( PCR_CPU_DIV_NUM + 1 ) AHB_CLK 2 HP_ROOT_CLK f HP_ROOT_CLK / ( PCR_AHB_DIV_NUM + 1 ) 1 CPU_CLK frequency must be larger than or equal to AHB_CLK frequency, and must be an integer multiple of AHB_CLK frequency. 2 AHB_CLK frequency can not exceed XTAL_CLK frequency. Note: When selecting the clock source of HP_ROOT_CLK, or configuring the clock divisor for CPU_CLK and AHB_CLK, please also set PCR_BUS_CLOCK_UPDATE to apply the new configuration, and read PCR_BUS_CLOCK_UPDATE to see if new configuration takes effect. As shown in 7.2-1, to generate APB_CLK, AHB_CLK might be divided twice. The first division is compulsory. That is, AHB_CLK is always divided by the divisor (PCR_APB_DIV_NUM + 1). The second division (also called automatic frequency reduction) is optional. When there is no request from the host in the chip to access peripheral registers, AHB_CLK will be further divided by (APB_DECREASE_DIV_NUM + 1) to lower power consumption. If the host initiates a request to access peripheral registers, APB_CLK will be restored to the frequency after the first division. Note that the function of automatic frequency reduction can be disabled (already disabled by default) by configuring APB_DECREASE_DIV_NUM to 0. 7.2.4.2 LP System Clock The LP system can operate when most other clocks are disabled. LP system clocks include LP_SLOW_CLK and LP_FAST_CLK. The clock sources for LP_SLOW_CLK and LP_FAST_CLK are low-frequency clocks: • LP_SLOW_CLK can be derived from: – RC_SLOW_CLK – XTAL32K_CLK – OSC_SLOW_CLK • LP_FAST_CLK can be derived from: – 20 MHz/24 MHz XTAL_D2_CLK, which is XTAL_CLK divided by 2 – RC_FAST_CLK – XTAL_CLK Espressif Systems 290 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock The clock source of LP_DYN_SLOW_CLK is LP_SLOW_CLK. There is no frequency change from the clock source. The clock source of LP_DYN_FAST_CLK depends on the chip’s power mode (see Chapter 2 Low-power Management [to be added later]). • Select LP_FAST_CLK as its clock source in Active and Modem-sleep mode • Select LP_SLOW_CLK as its clock source in Light-sleep and Deep-sleep mode 7.2.4.3 Peripheral Clocks Table 7.2-4, Table 7.2-5, Table 7.2-6, and Table 7.2-7 list the derived HP clock sources, HP clocks for each peripheral, derived LP clock sources and LP clocks for each peripheral. Espressif Systems 291 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Table 7.2-4. Derived HP Clock Source Source Clock Derived Clock Source Clock Derived Clock Source Clock PLL_CLK HP_ROOT_CLK Clock Derived Clock XTAL_CLK 48/40 MHz PLL_F480M_CLK 480 MHz PLL_F240M_CLK 240 MHz PLL_F160M_CLK 160 MHz RC_FAST_CLK 20 MHz RC_SLOW_CLK 130 kHz OSC_SLOW_CLK 32 kHz XTAL32K_CLK 32 kHz 240 MHz/160 MHz/48(/40) MHz/20 MHz CRYPTO_CLK APB_CLK AHB_CLK CPU_CLK LP_DYN_ FAST_CLK LP_DYN_ SLOW_CLK XTAL_D2_CLK 24/20 MHz LP_FAST_CLK Clock from IO PLL_F240M_CLK Y PLL_F160M_CLK Y PLL_F120M_CLK Y PLL_F80M_CLK Y PLL_F48M_CLK Y PLL_F40M_CLK Y HP_ROOT_CLK Y Y Y Y CRYPTO_CLK Y Y Y APB_CLK Y AHB_CLK Y CPU_CLK Y Table 7.2-5. HP Clocks Used by Each Peripheral Source Clock Derived Clock Source Clock Derived Clock Source Clock PLL_CLK HP_ROOT_CLK Peripheral XTAL_CLK 48/40 MHz PLL_F240M_CLK 240 MHz PLL_F160M_CLK 160 MHz PLL_F120M_CLK 120 MHz PLL_F80M_CLK 80 MHz PLL_F48M_CLK 48 MHz RC_FAST_CLK 20 MHz 240 MHz/160 MHz/48(/40) MHz/20 MHz CRYPTO_CLK APB_CLK AHB_CLK CPU_CLK LP_DYN_ FAST_CLK LP_DYN_ SLOW_CLK XTAL_D2_CLK 24/20 MHz LP_FAST_CLK Clock from IO Timer Group (TIMG) Y Y Y Main System Watchdog Timers (MWDT) Y Y Y I2S Controller (I2S) Y Y Y I2S_MCLK_in UART Controller (UART) Y Y Y Remote Control Peripheral (RMT) Y Y Motor Control PWM (MCPWM) Y Y Y I2C Controller (I2C) Y Y SPI2 Y Y Y Y SAR ADC Y Y Y USB Serial/JTAG Controller Y Controller Area Network Flexible Data- Rate [to be added later] Y Y LED PWM Controller (LEDC) Y Y Y System Timer Y Y Parallel IO Controller (PARLIO) Y Y Y parl_rx_clk_in parl_tx_clk_in IO MUX Y Y Y AES Accelerator (AES) SHA Accelerator (SHA) RSA Accelerator (RSA) ECC Accelerator (ECC) Digital Signature Algorithm (DSA) HMAC Accelerator (HMAC) Elliptic Curve Digital Signature Algorithm (ECDSA) Y Interrupt Matrix Y SDIO Slave Controller (SDIO) Y Pulse Count Controller (PCNT) Y Event Task Matrix (ETM) Y GDMA Controller (GDMA) Y UHCI Y Debug Assistant Y Continued on the next page... Espressif Systems 292 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Table 7.2-5 – Continued from the previous page... Source Clock Derived Clock Source Clock Derived Clock Source Clock PLL_CLK HP_ROOT_CLK Clock Peripheral XTAL_CLK 48/40 MHz PLL_F240M_CLK 240 MHz PLL_F160M_CLK 160 MHz PLL_F120M_CLK 120 MHz PLL_F80M_CLK 80 MHz PLL_F48M_CLK 48 MHz RC_FAST_CLK 20 MHz 240 MHz/160 MHz/48(/40) MHz/20 MHz CRYPTO_CLK APB_CLK AHB_CLK CPU_CLK LP_DYN_ FAST_CLK LP_DYN_ SLOW_CLK XTAL_D2_CLK 24/20 MHz LP_FAST_CLK Clock from IO RISC-V Trace Encoder (TRACE) Y Y Interrupt prioprity registers (INTPRI) Y Table 7.2-6. Derived LP Clock Source Source Clock Derived Clock Source Clock Derived Clock Source Clock PLL_CLK HP_ROOT_CLK Clock Derived Clock XTAL_CLK 48/40 MHz PLL_F480M_CLK 480 MHz PLL_F240M_CLK 240 MHz PLL_F160M_CLK 160 MHz RC_FAST_CLK 20 MHz RC_SLOW_CLK 130 kHz OSC_SLOW_CLK 32 kHz XTAL32K_CLK 32 kHz 240 MHz/160 MHz/48(/40) MHz/20 MHz CRYPTO_CLK APB_CLK AHB_CLK CPU_CLK LP_DYN_ FAST_CLK LP_DYN_ SLOW_CLK XTAL_D2_CLK 24/20 MHz LP_FAST_CLK Clock from IO LP_DYN_FAST_CLK Y Y Y Y LP_DYN_SLOW_CLK Y Y Y XTAL_D2_CLK Y LP_FAST_CLK Y Y Y Table 7.2-7. LP Clocks Used by Each Peripheral Source Clock Derived Clock Source Clock Derived Clock Source Clock PLL_CLK HP_ROOT_CLK Clock Derived Clock XTAL_CLK 48/40 MHz PLL_F480M_CLK 480 MHz PLL_F120M_CLK 240 MHz PLL_F160M_CLK 160 MHz RC_FAST_CLK 20 MHz RC_SLOW_CLK 130 kHz OSC_SLOW_CLK 32 kHz XTAL32K_CLK 32 kHz 240 MHz/160 MHz/48(/40) MHz/20 MHz CRYPTO_CLK APB_CLK AHB_CLK CPU_CLK LP_DYN_ FAST_CLK LP_DYN_ SLOW_CLK XTAL_D2_CLK 24/20 MHz LP_FAST_CLK Clock from IO eFuse Controller (eFuse) Y RTC Watchdog Timer (RWDT) Y Y RTC Timer (RTC Timer) Y Y Brownout Detector Y Power Management Unit (PMU) Y Y Y Espressif Systems 293 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock PLL_F480M_CLK PLL_F480M_CLK is a 480 MHz clock. PLL_F240M_CLK, PLL_F160M_CLK, PLL_F80M_CLK, PLL_F48M_CLK and PLL_F40M_CLK are divided from PLL_F480M_CLK. CRYPTO_CLK As shown in Figure 7.2-4, CRYPTO_CLK can be derived from XTAL_CLK, PLL_F480M_CLK, or RC_FAST_CLK, and its frequency is up to 160 MHz. To protect encryption and decryption peripherals from DPA (Differential Power Analysis) attacks, a random divider strategy is implemented for the functional clock of these peripherals. Four security levels are available, depending on the range of random divider. Users can select the security level by configuring HP_SYSTEM_SEC_DPA_CONF_REG. If HP_SYSTEM_SEC_DPA_CFG_SEL is set to 1, the security level is determined by the configuration of EFUSE_SEC_DPA_LEVEL, otherwise, by the value of HP_SYSTEM_SEC_DPA_LEVEL. LED_PWM Clock LEDC module uses PLL_F80M_CLK, RC_FAST_CLK or XTAL_CLK as its clock source. When the system is in low-power mode (APB_CLK is disabled), most peripherals are halted, but LEDC can still work via RC_FAST_CLK. Slow Clock for Timer Group 0 Using XTAL_CLK as a reference, TIMG0 can calculate the frequency of slow clock sources provided by ESP32-C5. The slow clock source can be selected by configuring PCR_32K_SEL: 0: Select XTAL32K_CLK clock 1: Select OSC_SLOW_CLK clock 2: Select RC_SLOW_CLK clock 3: Select RC_FAST_CLK clock Low-Power System Clock Registers See 7.4.2 LP System Clock Register Summary for the clock registers of low-power system peripherals. 7.2.4.4 PMU Control of High-Performance System Clock Gating In various operating modes of ESP32-C5, the following register fields can be pre-configured to enable the Power Management Unit (PMU) to control the clock gating of high-performance system peripherals: • PMU_HP_x_DIG_ICG_APB_EN (x = ACTIVE/MODEM/SLEEP): Controls the clock gating for reading and writing registers of high-performance system peripherals. • PMU_HP_x_DIG_ICG_FUNC_EN (x = ACTIVE/MODEM/SLEEP): Controls the functional clock gating of high-performance system peripherals. For the specific configuration process, please refer to the Chapter 2 Low-power Management [to be added later]. Tables 7.2-8 and 7.2-9 list the correspondence between PMU pre-configured register bits and high-performance system clock gating. Espressif Systems 294 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Table 7.2-8. Mapping between controlling the clock gating of read/write registers and related PMU registers PMU_HP_x_DIG_ICG_APB_EN bit Control the clock gating of read/write registers 0 AES Accelerator (AES) SHA Accelerator (SHA) RSA Accelerator (RSA) ECC Accelerator (ECC) Digital Signature Algorithm (DSA) HMAC Accelerator (HMAC) Elliptic Curve Digital Signature Algorithm (ECDSA) 1 GDMA Controller (GDMA) 2 SPI2 3 Interrupt Matrix 4 I2S Controller (I2S) 6 UART0 7 UART1 8 UHCI 11 Timer Group 0 12 Timer Group 1 13 I2C Controller (I2C) 14 LED PWM Controller (LEDC) 15 Remote Control Peripheral (RMT) 16 System Timer 17 USB Serial/JTAG Controller 18 Two-wire Automotive Interface 0 19 Two-wire Automotive Interface 1 20 Pulse Count Controller (PCNT) 21 Motor Control PWM (MCPWM) 22 Event Task Matrix (ETM) 23 Parallel IO Controller (PARLIO) 25 Debug Assistant 26 GPIO Matrix and IO MUX 28 BitScrambler Espressif Systems 295 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Table 7.2-9. Mapping between controlling the functional clock gating of high-performance system periph- erals and related PMU registers PMU_HP_x_DIG_ICG_FUNC_EN bit control the functional clock gating of high-performance system peripherals 0 GDMA Controller (GDMA) 1 SPI2 2 I2S Receive Side 3 UART0 4 UART1 5 UHCI 6 USB Serial/JTAG Controller 7 I2S Transmit Side 10 MEM_MONITOR 11 SDIO Slave Controller (SDIO) 12 Temperature Sensor 13 Timer Group 0 14 Timer Group 1 16 Event Task Matrix (ETM) 17 High-Performance CPU [to be added later] ASSIST_DEBUG 18 System Timer 19 AES Accelerator (AES) SHA Accelerator (SHA) RSA Accelerator (RSA) ECC Accelerator (ECC) Digital Signature Algorithm (DSA) HMAC Accelerator (HMAC) Elliptic Curve Digital Signature Algorithm (ECDSA) 21 Remote Control Peripheral (RMT) 22 Motor Control PWM (MCPWM) 24 BitScrambler 25 Parallel IO Controller (PARLIO) 27 LED PWM Controller (LEDC) 28 GPIO Matrix and IO MUX 29 I2C Controller (I2C) 30 Two-wire Automotive Interface 0 31 Two-wire Automotive Interface 1 7.3 Programming Procedures 7.3.1 HP System Clock Configuration When configuring PCR_SOC_CLK_SEL to select the clock source of HP_ROOT_CLK, or configuring the clock divisor for CPU_CLK via PCR_CPU_DIV_NUM and AHB_CLK via PCR_AHB_DIV_NUM, please also set the enable register to apply the new configuration. To check whether the new configuration takes effect, read Espressif Systems 296 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock PCR_BUS_CLOCK_UPDATE and see if it is 0. 7.3.2 LP System Clock Configuration The clock source of LP_SLOW_CLK can be configured via LP_CLKRST_SLOW_CLK_SEL. The clock source of LP_FAST_CLK can be configured via LP_CLKRST_FAST_CLK_SEL. 7.3.3 Peripheral Clock Reset and Configuration Notice: ESP32-C5 features low power consumption. This is why some peripheral clocks are gated (disabled) by default. Before using any of these peripherals, it is mandatory to enable the clock for the given peripheral by setting the corresponding CLK_EN bit to 1, and release the peripheral from reset state by setting the RST_EN bit to 0. The clocks of most peripherals can be classified into two types: • Bus clock: used to configure peripheral registers. • Functional clock: such as UART’s reference clock, used by peripherals to operate. The functional clock of most peripherals can be selected from multiple clock sources. For clock gating registers, whether they are used to gate the bus clock (AHB_CLK, APB_CLK) or the functional clock will be stated in the corresponding register descriptions. Bus clock switches, functional clock switches, and configuration registers for clock source selection and clock frequency division are grouped into the PCR module. For more information, see Section 7.4 Register Summary. When a peripheral is not working, users can turn off its functional clock by configuring related PCR registers. Turning off the peripheral’s functional clock does not affect the rest of the system. Take the I2C clock configuration as an example. Figure 7.3-1. Clock Configuration Example Espressif Systems 297 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Figure 7.3-1 shows the clock structure of I2C. The clock structure of other peripherals is similar to this one. CLK_SWITCH is used to select a clock output and CLK_GATE to turn on/off the clock. In scenarios that require low power consumption, when the peripheral is not in use, in addition to turning off the functional clock, the bus clock of the peripheral can also be turned off to further lower the power consumption. Note that if you turn off the bus clock first, the functional clock may continue working. Therefore, when turning off clocks, it is recommended to turn off the functional clock first and then the bus clock; when turning on clocks, it is recommended to turn on the bus clock first and then the functional clock. Note: In this chapter, all divisor configuration registers are configured with the actual divisor minus 1. Espressif Systems 298 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock 7.4 Register Summary 7.4.1 PCR Register Summary The addresses in this section are relative to Power/Clock/Reset (PCR) Register base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Configuration Register PCR_UART0_CONF_REG UART0 configuration register 0x0000 varies PCR_UART0_SCLK_CONF_REG UART0_SCLK configuration register 0x0004 R/W PCR_UART0_PD_CTRL_REG UART0 power control register 0x0008 R/W PCR_UART1_CONF_REG UART1 configuration register 0x000C varies PCR_UART1_SCLK_CONF_REG UART1_SCLK configuration register 0x0010 R/W PCR_UART1_PD_CTRL_REG UART1 power control register 0x0014 R/W PCR_I2C_CONF_REG I2C configuration register 0x0020 R/W PCR_I2C_SCLK_CONF_REG I2C_SCLK configuration register 0x0024 R/W PCR_TWAI0_CONF_REG TWAI0 configuration register 0x0028 varies PCR_TWAI0_FUNC_CLK_CONF_REG TWAI0_FUNC_CLK configuration register 0x002C R/W PCR_TWAI1_CONF_REG TWAI1 configuration register 0x0030 varies PCR_TWAI1_FUNC_CLK_CONF_REG TWAI1_FUNC_CLK configuration register 0x0034 R/W PCR_UHCI_CONF_REG UHCI configuration register 0x0038 varies PCR_RMT_CONF_REG RMT configuration register 0x003C R/W PCR_RMT_SCLK_CONF_REG RMT_SCLK configuration register 0x0040 R/W PCR_RMT_PD_CTRL_REG RMT power control register 0x0044 R/W PCR_LEDC_CONF_REG LEDC configuration register 0x0048 varies PCR_LEDC_SCLK_CONF_REG LEDC_SCLK configuration register 0x004C R/W PCR_LEDC_PD_CTRL_REG LEDC power control register 0x0050 R/W PCR_TIMERGROUP0_CONF_REG TIMERGROUP0 configuration register 0x0054 varies PCR_TIMERGROUP0_TIMER_CLK_CONF_REG TIMERGROUP0_TIMER_CLK configura- tion register 0x0058 R/W PCR_TIMERGROUP0_WDT_CLK_CONF_REG TIMERGROUP0_WDT_CLK configura- tion register 0x005C R/W PCR_TIMERGROUP1_CONF_REG TIMERGROUP1 configuration register 0x0060 varies PCR_TIMERGROUP1_TIMER_CLK_CONF_REG TIMERGROUP1_TIMER_CLK configura- tion register 0x0064 R/W PCR_TIMERGROUP1_WDT_CLK_CONF_REG TIMERGROUP1_WDT_CLK configura- tion register 0x0068 R/W PCR_SYSTIMER_CONF_REG SYSTIMER configuration register 0x006C varies PCR_SYSTIMER_FUNC_CLK_CONF_REG SYSTIMER_FUNC_CLK configuration register 0x0070 R/W PCR_I2S_CONF_REG I2S configuration register 0x0074 varies PCR_I2S_TX_CLKM_CONF_REG I2S_TX_CLKM configuration register 0x0078 R/W Espressif Systems 299 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Name Description Address Access PCR_I2S_TX_CLKM_DIV_CONF_REG I2S_TX_CLKM_DIV configuration register 0x007C R/W PCR_I2S_RX_CLKM_CONF_REG I2S_RX_CLKM configuration register 0x0080 R/W PCR_I2S_RX_CLKM_DIV_CONF_REG I2S_RX_CLKM_DIV configuration register 0x0084 R/W PCR_SARADC_CONF_REG SARADC configuration register 0x0088 R/W PCR_SARADC_CLKM_CONF_REG SARADC_CLKM configuration register 0x008C R/W PCR_TSENS_CLK_CONF_REG TSENS_CLK configuration register 0x0090 R/W PCR_USB_DEVICE_CONF_REG USB_DEVICE configuration register 0x0094 varies PCR_INTMTX_CONF_REG INTMTX configuration register 0x0098 varies PCR_PCNT_CONF_REG PCNT configuration register 0x009C varies PCR_ETM_CONF_REG ETM configuration register 0x00A0 varies PCR_PWM_CONF_REG PWM configuration register 0x00A4 varies PCR_PWM_CLK_CONF_REG PWM_CLK configuration register 0x00A8 R/W PCR_PARL_IO_CONF_REG PARL_IO configuration register 0x00AC varies PCR_PARL_CLK_RX_CONF_REG PARL_CLK_RX configuration register 0x00B0 R/W PCR_PARL_CLK_TX_CONF_REG PARL_CLK_TX configuration register 0x00B4 R/W PCR_GDMA_CONF_REG GDMA configuration register 0x00C0 R/W PCR_SPI2_CONF_REG SPI2 configuration register 0x00C4 varies PCR_SPI2_CLKM_CONF_REG SPI2_CLKM configuration register 0x00C8 R/W PCR_AES_CONF_REG AES configuration register 0x00CC varies PCR_SHA_CONF_REG SHA configuration register 0x00D0 varies PCR_RSA_CONF_REG RSA configuration register 0x00D4 varies PCR_RSA_PD_CTRL_REG RSA power control register 0x00D8 R/W PCR_ECC_CONF_REG ECC configuration register 0x00DC varies PCR_ECC_PD_CTRL_REG ECC power control register 0x00E0 R/W PCR_DS_CONF_REG DS configuration register 0x00E4 varies PCR_HMAC_CONF_REG HMAC configuration register 0x00E8 varies PCR_ECDSA_CONF_REG ECDSA configuration register 0x00EC varies PCR_IOMUX_CONF_REG IOMUX configuration register 0x00F0 R/W PCR_IOMUX_CLK_CONF_REG IOMUX_CLK configuration register 0x00F4 R/W PCR_TRACE_CONF_REG TRACE configuration register 0x00FC R/W PCR_ASSIST_CONF_REG ASSIST configuration register 0x0100 R/W PCR_CACHE_CONF_REG CACHE configuration register 0x0104 R/W PCR_TIMEOUT_CONF_REG TIMEOUT configuration register 0x010C R/W PCR_SYSCLK_CONF_REG SYSCLK configuration register 0x0110 varies PCR_CPU_WAITI_CONF_REG CPU_WAITI configuration register 0x0114 varies PCR_CPU_FREQ_CONF_REG CPU_FREQ configuration register 0x0118 R/W PCR_AHB_FREQ_CONF_REG AHB_FREQ configuration register 0x011C R/W PCR_APB_FREQ_CONF_REG APB_FREQ configuration register 0x0120 R/W PCR_PLL_DIV_CLK_EN_REG SPLL DIV clock-gating configuration reg- ister 0x0128 R/W PCR_CTRL_32K_CONF_REG 32KHz clock configuration register 0x0130 R/W PCR_SEC_CONF_REG Clock source configuration register for Ex- ternal Memory Encryption and Decryption 0x013C R/W Espressif Systems 300 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Name Description Address Access PCR_BUS_CLK_UPDATE_REG Configuration register for applying up- dated high-performance system clock sources 0x0144 R/W/WTC PCR_SAR_CLK_DIV_REG SAR ADC clock divisor configuration reg- ister 0x0148 R/W PCR_BS_CONF_REG BS configuration register 0x0150 R/W PCR_BS_FUNC_CONF_REG BS_FUNC_CLK configuration register 0x0154 R/W PCR_BS_PD_CTRL_REG BS power control register 0x0158 R/W PCR_TIMERGROUP_WDT_CONF_REG TIMERGROUP_WDT configuration regis- ter 0x015C R/W PCR_TIMERGROUP_XTAL_CONF_REG TIMERGROUP1 configuration register 0x0160 R/W PCR_TCM_MEM_MONITOR_CONF_REG TCM_MEM_MONITOR configuration reg- ister 0x016C varies PCR_PSRAM_MEM_MONITOR_CONF_REG PSRAM_MEM_MONITOR configuration register 0x0170 varies PCR_HPCORE_0_PD_CTRL_REG HP CORE0 power control register 0x0178 R/W PCR_SDIO_SLAVE_CONF_REG SDIO_SLAVE configuration register 0x017C R/W Frequency Statistics Register PCR_SYSCLK_FREQ_QUERY_0_REG SYSCLK frequency query 0 register 0x0124 HRO Version Register PCR_DATE_REG Date register. 0x0FFC R/W 7.4.2 LP System Clock Register Summary The addresses of the last two registers with the LPPERI prefix in this section are relative to the Low-power Peripheral Register (LPPERI) base address. The addresses of the third and fourth to last registers with the LP_AON prefix in this section are relative to the Low-power Always-on Register (LP_AON) base address. The other addresses in this section are relative to the Low-power Clock/Reset Register (LP_CLKRST) base address. For base address, please refer to Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Configuration Registers LP_CLKRST_LP_CLK_CONF_REG LP system clock source configuration register 0x0000 R/W LP_CLKRST_LP_CLK_PO_EN_REG Configuration register for gating clock signals to pins 0x0004 R/W LP_CLKRST_LP_CLK_EN_REG Configuration register for gating LP clock source 0x0008 R/W LP_CLKRST_LP_RST_EN_REG Configuration register for LP peripheral software reset 0x000C R/W LP_CLKRST_RESET_CAUSE_REG Reset cause status register 0x0010 varies LP_CLKRST_CPU_RESET_REG CPU reset configuration register 0x0014 R/W LP_CLKRST_FOSC_CNTL_REG RC_FAST_CLK frequency configuration register 0x0018 R/W Espressif Systems 301 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Name Description Address Access LP_CLKRST_CLK_TO_HP_REG Configuration register for gating clock signals to HP system 0x0020 R/W LP_CLKRST_LPMEM_FORCE_REG Configuration register for forcing the gate of LP memory clock 0x0024 R/W LP_CLKRST_LPPERI_REG LP peripheral clock configuration register 0x0028 R/W LP_CLKRST_XTAL32K_REG XTAL32K_CLK configuration register 0x002C R/W LP_CLKRST_DATE_REG Version control register 0x03FC R/W LP_AON_SYS_CFG_REG Software system reset register 0x0034 WT LP_AON_CPUCORE0_CFG_REG Software CPU reset register 0x0038 WT LPPERI_CLK_EN_REG Clock enable register for LP peripherals 0x0000 R/W LPPERI_RESET_EN_REG Reset enable register for LP peripherals 0x0004 R/W Espressif Systems 302 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock 7.5 Registers 7.5.1 PCR Registers The addresses in this section are relative to the Power/Clock/Reset (PCR) Register base address provided in Table 4.3-2 in Chapter 4 System and Memory. Register 7.1. PCR_UART0_CONF_REG (0x0000) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PCR_UART0_READY 1 2 PCR_UART0_RST_EN 0 1 PCR_UART0_CLK_EN 1 0 Reset PCR_UART0_CLK_EN Configures whether or not to enable APB_CLK for UART0. 0: Not enable 1: Enable (R/W) PCR_UART0_RST_EN Configures whether or not to reset UART0. 0: Not reset 1: Reset (R/W) PCR_UART0_READY Represents whether or not UART0 is released from reset. 0: Not released 1: Released (RO) Espressif Systems 303 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.2. PCR_UART0_SCLK_CONF_REG (0x0004) (reserved) 0 0 0 0 0 0 0 0 0 31 23 PCR_UART0_SCLK_EN 1 22 PCR_UART0_SCLK_SEL 3 21 20 PCR_UART0_SCLK_DIV_NUM 0 19 12 PCR_UART0_SCLK_DIV_B 0 11 6 PCR_UART0_SCLK_DIV_A 0 5 0 Reset PCR_UART0_SCLK_DIV_A Configures the denominator of the divisor’s fractional part’s fractional part for UART0 functional clock. (R/W) PCR_UART0_SCLK_DIV_B Configures the numerator of the divisor’s fractional part for UART0 func- tional clock. (R/W) PCR_UART0_SCLK_DIV_NUM Configures the integral part of the divisor for UART0 functional clock. (R/W) PCR_UART0_SCLK_SEL Configures the clock source of UART0. 0: No clock source 1: PLL_F80M_CLK 2: RC_FAST_CLK 3 (default): XTAL_CLK (R/W) PCR_UART0_SCLK_EN Configures whether or not to enable UART0 functional clock. 0: Not enable 1: Enable (R/W) Espressif Systems 304 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.3. PCR_UART0_PD_CTRL_REG (0x0008) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PCR_UART0_MEM_FORCE_PD 0 2 PCR_UART0_MEM_FORCE_PU 1 1 (reserved) 0 0 Reset PCR_UART0_MEM_FORCE_PU Configures whether or not to force power up UART0 memory. 0: Not force power up UART0 memory 1: Force power up UART0 memory (R/W) PCR_UART0_MEM_FORCE_PD Configures whether or not to force power down UART0 memory. 0: Not force power down UART0 memory 1: Force power down UART0 memory (R/W) Register 7.4. PCR_UART1_CONF_REG (0x000C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PCR_UART1_READY 1 2 PCR_UART1_RST_EN 0 1 PCR_UART1_CLK_EN 1 0 Reset PCR_UART1_CLK_EN Configures whether or not to enable APB_CLK for UART1. 0: Not enable 1: Enable (R/W) PCR_UART1_RST_EN Configures whether or not to reset UART1. 0: Not reset 1: Reset (R/W) PCR_UART1_READY Represents whether or not UART1 is released from reset. 0: Not released 1: Released (RO) Espressif Systems 305 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.5. PCR_UART1_SCLK_CONF_REG (0x0010) (reserved) 0 0 0 0 0 0 0 0 0 31 23 PCR_UART1_SCLK_EN 1 22 PCR_UART1_SCLK_SEL 3 21 20 PCR_UART1_SCLK_DIV_NUM 0 19 12 PCR_UART1_SCLK_DIV_B 0 11 6 PCR_UART1_SCLK_DIV_A 0 5 0 Reset PCR_UART1_SCLK_DIV_A Configures the denominator of the divisor’s fractional part for UART1 functional clock. (R/W) PCR_UART1_SCLK_DIV_B Configures the numerator of the divisor’s fractional part for UART1 func- tional clock. (R/W) PCR_UART1_SCLK_DIV_NUM Configures the integral part of the divisor for UART1 functional clock. (R/W) PCR_UART1_SCLK_SEL Configures the clock source of UART1. 0: No clock source 1: PLL_F80M_CLK 2: RC_FAST_CLK 3 (default): XTAL_CLK (R/W) PCR_UART1_SCLK_EN Configures whether or not to enable UART1 functional clock. 0: Not enable 1: Enable (R/W) Espressif Systems 306 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.6. PCR_UART1_PD_CTRL_REG (0x0014) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PCR_UART1_MEM_FORCE_PD 0 2 PCR_UART1_MEM_FORCE_PU 1 1 (reserved) 0 0 Reset PCR_UART1_MEM_FORCE_PU Configures whether or not to force power up UART1 memory. 0: Not force power up UART1 memory 1: Force power up UART1 memory (R/W) PCR_UART1_MEM_FORCE_PD Configures whether or not to force power down UART1 memory. 0: Not force power down UART1 memory 1: Force power down UART1 memory (R/W) Register 7.7. PCR_I2C_CONF_REG (0x0020) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PCR_I2C_READY 1 2 PCR_I2C_RST_EN 0 1 PCR_I2C_CLK_EN 1 0 Reset PCR_I2C_CLK_EN Configures whether or not to enable APB_CLK for I2C. 0: Not enable 1: Enable (R/W) PCR_I2C_RST_EN Configures whether or not to reset I2C. 0: Not reset 1: Reset (R/W) PCR_I2C_READY Represents whether or not I2C is released from reset. 0: Not released 1: Released (RO) Espressif Systems 307 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.8. PCR_I2C_SCLK_CONF_REG (0x0024) (reserved) 0 0 0 0 0 0 0 0 0 31 23 PCR_I2C_SCLK_EN 1 22 (reserved) 0 21 PCR_I2C_SCLK_SEL 0 20 PCR_I2C_SCLK_DIV_NUM 0 19 12 PCR_I2C_SCLK_DIV_B 0 11 6 PCR_I2C_SCLK_DIV_A 0 5 0 Reset PCR_I2C_SCLK_DIV_A Configures the denominator of the divisor’s fractional part for I2C functional clock. (R/W) PCR_I2C_SCLK_DIV_B Configures the numerator of the divisor’s fractional part for I2C functional clock. (R/W) PCR_I2C_SCLK_DIV_NUM Configures the integral part of the divisor for I2C functional clock. (R/W) PCR_I2C_SCLK_SEL Configures the clock source of I2C. 0 (default): XTAL_CLK 1: RC_FAST_CLK (R/W) PCR_I2C_SCLK_EN Configures whether or not to enable I2C functional clock. 0: Not enable 1: Enable (R/W) Espressif Systems 308 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.9. PCR_TWAI0_CONF_REG (0x0028) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PCR_TWAI0_READY 1 2 PCR_TWAI0_RST_EN 0 1 PCR_TWAI0_CLK_EN 1 0 Reset PCR_TWAI0_CLK_EN Configures whether or not to enable TWAI0 APB_CLK. 0: Not enable 1: Enable (R/W) PCR_TWAI0_RST_EN Configures whether or not to reset TWAI0. 0: Not reset 1: Reset (R/W) PCR_TWAI0_READY Represents whether or not TWAI0 is released from reset. 0: Not released 1: Released (RO) Register 7.10. PCR_TWAI0_FUNC_CLK_CONF_REG (0x002C) (reserved) 0 0 0 0 0 0 0 0 0 31 23 PCR_TWAI0_FUNC_CLK_EN 1 22 (reserved) 0 21 PCR_TWAI0_FUNC_CLK_SEL 0 20 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19 0 Reset PCR_TWAI0_FUNC_CLK_SEL Configures the clock source of TWAI0. 0 (default): XTAL_CLK 1: RC_FAST_CLK (R/W) PCR_TWAI0_FUNC_CLK_EN Configures whether or not to enable TWAI0 functional clock. 0: Not enable 1: Enable (R/W) Espressif Systems 309 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.11. PCR_TWAI1_CONF_REG (0x0030) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PCR_TWAI1_READY 1 2 PCR_TWAI1_RST_EN 0 1 PCR_TWAI1_CLK_EN 1 0 Reset PCR_TWAI1_CLK_EN Configures whether or not to enable TWAI1 APB_CLK. 0: Not enable 1: Enable (R/W) PCR_TWAI1_RST_EN Configures whether or not to reset TWAI1. 0: Not reset 1: Reset (R/W) PCR_TWAI1_READY Represents whether or not TWAI1 is released from reset. 0: Not released 1: Released (RO) Register 7.12. PCR_TWAI1_FUNC_CLK_CONF_REG (0x0034) (reserved) 0 0 0 0 0 0 0 0 0 31 23 PCR_TWAI1_FUNC_CLK_EN 1 22 (reserved) 0 21 PCR_TWAI1_FUNC_CLK_SEL 0 20 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19 0 Reset PCR_TWAI1_FUNC_CLK_SEL Configures the clock source of TWAI1. 0 (default): XTAL_CLK 1: RC_FAST_CLK (R/W) PCR_TWAI1_FUNC_CLK_EN Configures whether or not to enable TWAI1 functional clock. 0: Not enable 1: Enable (R/W) Espressif Systems 310 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.13. PCR_UHCI_CONF_REG (0x0038) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PCR_UHCI_READY 1 2 PCR_UHCI_RST_EN 0 1 PCR_UHCI_CLK_EN 1 0 Reset PCR_UHCI_CLK_EN Configures whether or not to enable UHCI clock. 0: Not enable 1: Enable (R/W) PCR_UHCI_RST_EN Configures whether or not to reset UHCI. 0: Not reset 1: Reset (R/W) PCR_UHCI_READY Represents whether or not UCHI is released from reset. 0: Not released 1: Released (RO) Register 7.14. PCR_RMT_CONF_REG (0x003C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PCR_RMT_READY 1 2 PCR_RMT_RST_EN 0 1 PCR_RMT_CLK_EN 1 0 Reset PCR_RMT_CLK_EN Configures whether or not to enable APB_CLK for RMT. 0: Not enable 1: Enable (R/W) PCR_RMT_RST_EN Configures whether or not to reset RMT. 0: Not reset 1: Reset (R/W) PCR_RMT_READY Represents whether or not RMT is released from reset. 0: Not released 1: Released (RO) Espressif Systems 311 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.15. PCR_RMT_SCLK_CONF_REG (0x0040) (reserved) 0 0 0 0 0 0 0 0 0 31 23 PCR_RMT_SCLK_EN 0 22 PCR_RMT_SCLK_SEL 1 21 20 PCR_RMT_SCLK_DIV_NUM 1 19 12 PCR_RMT_SCLK_DIV_B 0 11 6 PCR_RMT_SCLK_DIV_A 0 5 0 Reset PCR_RMT_SCLK_DIV_A Configures the denominator of the divisor’s fractional part for RMT func- tional clock. (R/W) PCR_RMT_SCLK_DIV_B Configures the numerator of the divisor’s fractional part for RMT functional clock. (R/W) PCR_RMT_SCLK_DIV_NUM Configures the integral part of the divisor for RMT functional clock. (R/W) PCR_RMT_SCLK_SEL Configures the clock source of RMT. 0: XTAL_CLK 1 (default): RC_FAST_CLK 2: PLL_F80M_CLK (R/W) PCR_RMT_SCLK_EN Configures whether or not to enable RMT functional clock. 0: Not enable 1: Enable (R/W) Espressif Systems 312 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.16. PCR_RMT_PD_CTRL_REG (0x0044) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PCR_RMT_MEM_FORCE_PD 1 2 PCR_RMT_MEM_FORCE_PU 0 1 (reserved) 0 0 Reset PCR_RMT_MEM_FORCE_PU Configures whether or not to force power up RMT memory. 0: Not force power up 1: Force power up (R/W) PCR_RMT_MEM_FORCE_PD Configures whether or not to force power down RMT memory. 0: Not force power down 1: Force power down (R/W) Register 7.17. PCR_LEDC_CONF_REG (0x0048) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PCR_LEDC_READY 1 2 PCR_LEDC_RST_EN 0 1 PCR_LEDC_CLK_EN 1 0 Reset PCR_LEDC_CLK_EN Configures whether or not to enable APB_CLK for LEDC. 0: Not enable 1: Enable (R/W) PCR_LEDC_RST_EN Configures whether or not to reset LEDC. 0: Not reset 1: Reset (R/W) PCR_LEDC_READY Represents whether or not LEDC is released from reset. 0: Not released 1: Released (RO) Espressif Systems 313 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.18. PCR_LEDC_SCLK_CONF_REG (0x004C) (reserved) 0 0 0 0 0 0 0 0 0 31 23 PCR_LEDC_SCLK_EN 1 22 PCR_LEDC_SCLK_SEL 0 21 20 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19 0 Reset PCR_LEDC_SCLK_SEL Configures the clock source of LEDC. 0 (default): XTAL_CLK 1: RC_FAST_CLK 2: PLL_F80M_CLK 3: No clock source (R/W) PCR_LEDC_SCLK_EN Configures whether or not to enable LEDC functional clock. 0: Not enable 1: Enable (R/W) Register 7.19. PCR_LEDC_PD_CTRL_REG (0x0050) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PCR_LEDC_MEM_FORCE_PD 1 2 PCR_LEDC_MEM_FORCE_PU 0 1 (reserved) 0 0 Reset PCR_LEDC_MEM_FORCE_PU Configures whether or not to force power up LEDC memory. 0: Not force power up 1: Force power up (R/W) PCR_LEDC_MEM_FORCE_PD Configures whether or not to force power down LEDC memory. 0: Not force power down 1: Force power down (R/W) Espressif Systems 314 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.20. PCR_TIMERGROUP0_CONF_REG (0x0054) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 5 PCR_TG0_TIMER1_READY 1 4 PCR_TG0_TIMER0_READY 1 3 PCR_TG0_WDT_READY 1 2 PCR_TG0_RST_EN 0 1 PCR_TG0_CLK_EN 1 0 Reset PCR_TG0_CLK_EN Configures whether or not to enable APB_CLK for Timer Group 0. 0: Not enable 1: Enable (R/W) PCR_TG0_RST_EN Configures whether or not to reset Timer Group 0. 0: Not reset 1: Reset (R/W) PCR_TG0_WDT_READY Represents whether or not the WDT in Timer Group 0 is released from reset. 0: Not released 1: Released (RO) PCR_TG0_TIMER0_READY Represents whether or not Timer 0 in Timer Group 0 is released from reset. 0: Not released 1: Released (RO) PCR_TG0_TIMER1_READY Represents whether or not Timer 1 in Timer Group 0 is released from reset. 0: Not released 1: Released (RO) Espressif Systems 315 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.21. PCR_TIMERGROUP0_TIMER_CLK_CONF_REG (0x0058) (reserved) 0 0 0 0 0 0 0 0 0 31 23 PCR_TG0_TIMER_CLK_EN 1 22 PCR_TG0_TIMER_CLK_SEL 0 21 20 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19 0 Reset PCR_TG0_TIMER_CLK_SEL Configures the clock source of general-purpose timers in Timer Group 0. 0 (default): XTAL_CLK 1: RC_FAST_CLK 2: PLL_F48M_CLK 3: No clock source (R/W) PCR_TG0_TIMER_CLK_EN Configures whether or not to enable the clock of general-purpose timers in Timer Group 0. 0: Not enable 1: Enable (R/W) Register 7.22. PCR_TIMERGROUP0_WDT_CLK_CONF_REG (0x005C) (reserved) 0 0 0 0 0 0 0 0 0 31 23 PCR_TG0_WDT_CLK_EN 1 22 PCR_TG0_WDT_CLK_SEL 0 21 20 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19 0 Reset PCR_TG0_WDT_CLK_SEL Configures the clock source of WDT in Timer Group 0. 0 (default): XTAL_CLK 1: RC_FAST_CLK 2: PLL_F80M_CLK 3: No clock source (R/W) PCR_TG0_WDT_CLK_EN Configures whether or not to enable the clock of WDT in Timer Group 0. 0: Not enable 1: Enable (R/W) Espressif Systems 316 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.23. PCR_TIMERGROUP1_CONF_REG (0x0060) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 5 PCR_TG1_TIMER1_READY 1 4 PCR_TG1_TIMER0_READY 1 3 PCR_TG1_WDT_READY 1 2 PCR_TG1_RST_EN 0 1 PCR_TG1_CLK_EN 1 0 Reset PCR_TG1_CLK_EN Configures whether or not to enable APB_CLK for Timer Group 1. 0: Not enable 1: Enable (R/W) PCR_TG1_RST_EN Configures whether or not to reset Timer Group 1. 0: Not reset 1: Reset (R/W) PCR_TG1_WDT_READY Represents whether or not the WDT in Timer Group 1 is released from reset. 0: Not released 1: Released (RO) PCR_TG1_TIMER0_READY Represents whether or not Timer 0 in Timer Group 1 is released from reset. 0: Not released 1: Released (RO)timer_group0 Timer 0module (RO) PCR_TG1_TIMER1_READY Represents whether or not Timer 1 in Timer Group 1 is released from reset. 0: Not released 1: Released (RO) Espressif Systems 317 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.24. PCR_TIMERGROUP1_TIMER_CLK_CONF_REG (0x0064) (reserved) 0 0 0 0 0 0 0 0 0 31 23 PCR_TG1_TIMER_CLK_EN 1 22 PCR_TG1_TIMER_CLK_SEL 0 21 20 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19 0 Reset PCR_TG1_TIMER_CLK_SEL Configures the clock source of general-purpose timers in Timer Group 1. 0 (default): XTAL_CLK 1: RC_FAST_CLK 2: PLL_F48M_CLK 3: No clock source (R/W) PCR_TG1_TIMER_CLK_EN Configures whether or not to enable the clock of general-purpose timers in Timer Group 1. 0: Not enable 1: Enable (R/W) Register 7.25. PCR_TIMERGROUP1_WDT_CLK_CONF_REG (0x0068) (reserved) 0 0 0 0 0 0 0 0 0 31 23 PCR_TG1_WDT_CLK_EN 1 22 PCR_TG1_WDT_CLK_SEL 0 21 20 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19 0 Reset PCR_TG1_WDT_CLK_SEL Configures the clock source of WDT in Timer Group 1. 0 (default): XTAL_CLK 1: RC_FAST_CLK 2: PLL_F80M_CLK 3: No clock source (R/W) PCR_TG1_WDT_CLK_EN Configures whether or not to enable the clock for WDT in Timer Group 1. 0: Not enable 1: Enable (R/W) Espressif Systems 318 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.26. PCR_SYSTIMER_CONF_REG (0x006C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PCR_SYSTIMER_READY 1 2 PCR_SYSTIMER_RST_EN 0 1 PCR_SYSTIMER_CLK_EN 1 0 Reset PCR_SYSTIMER_CLK_EN Configures whether or not to enable APB_CLK for System Timer. 0: Not enable 1: Enable (R/W) PCR_SYSTIMER_RST_EN Configures whether or not to reset System Timer. 0: Not reset 1: Reset (R/W) PCR_SYSTIMER_READY Represents whether or not the System Timer is released from reset. 0: Not released 1: Released (RO) Register 7.27. PCR_SYSTIMER_FUNC_CLK_CONF_REG (0x0070) (reserved) 0 0 0 0 0 0 0 0 0 31 23 PCR_SYSTIMER_FUNC_CLK_EN 1 22 (reserved) 0 21 PCR_SYSTIMER_FUNC_CLK_SEL 0 20 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19 0 Reset PCR_SYSTIMER_FUNC_CLK_SEL Configures the clock source of System Timer. 0 (default): XTAL_CLK 1: RC_FAST_CLK (R/W) PCR_SYSTIMER_FUNC_CLK_EN Configures whether or not to enable System Timer functional clock. 0: Not enable 1: Enable (R/W) Espressif Systems 319 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.28. PCR_I2S_CONF_REG (0x0074) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 4 PCR_I2S_TX_READY 1 3 PCR_I2S_RX_READY 1 2 PCR_I2S_RST_EN 0 1 PCR_I2S_CLK_EN 1 0 Reset PCR_I2S_CLK_EN Configures whether or not to enable APB_CLK for I2S. 0: Not enable 1: Enable (R/W) PCR_I2S_RST_EN Configures whether or not to reset I2S. 0: Not reset 1: Reset (R/W) PCR_I2S_RX_READY Represents whether or not I2S RX is released from reset. 0: Not released 1: Released (RO) PCR_I2S_TX_READY Represents whether or not I2S TX is released from reset. 0: Not released 1: Released (RO) Espressif Systems 320 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.29. PCR_I2S_TX_CLKM_CONF_REG (0x0078) (reserved) 0 0 0 0 0 0 0 0 0 31 23 PCR_I2S_TX_CLKM_EN 1 22 PCR_I2S_TX_CLKM_SEL 0 21 20 PCR_I2S_TX_CLKM_DIV_NUM 2 19 12 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 11 0 Reset PCR_I2S_TX_CLKM_DIV_NUM Configures the integral part of I2S TX clock divisor. (R/W) PCR_I2S_TX_CLKM_SEL Configures the clock source of I2S TX. 0: XTAL_CLK 1: PLL_F240M_CLK 2: PLL_F160M_CLK 3: I2S_MCLK_in (R/W) PCR_I2S_TX_CLKM_EN Configures whether or not to enable I2S TX functional clock. 0: Not enable 1: Enable (R/W) Espressif Systems 321 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.30. PCR_I2S_TX_CLKM_DIV_CONF_REG (0x007C) (reserved) 0 0 0 0 31 28 PCR_I2S_TX_CLKM_DIV_YN1 0 27 PCR_I2S_TX_CLKM_DIV_X 0 26 18 PCR_I2S_TX_CLKM_DIV_Y 1 17 9 PCR_I2S_TX_CLKM_DIV_Z 0 8 0 Reset PCR_I2S_TX_CLKM_DIV_Z For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a - b). (R/W) PCR_I2S_TX_CLKM_DIV_Y For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b). For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a - b)). (R/W) PCR_I2S_TX_CLKM_DIV_X For b <= a/2, the value of I2S_TX_CLKM_DIV_X is floor(a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is floor(a/(a - b)) - 1. (R/W) PCR_I2S_TX_CLKM_DIV_YN1 For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0. For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1. (R/W) Note: “a” and “b” represent the denominator and the numerator of the fractional divisor, respectively. For more information, see Section 31.6 in Chapter I2S Controller (I2S). Espressif Systems 322 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.31. PCR_I2S_RX_CLKM_CONF_REG (0x0080) (reserved) 0 0 0 0 0 0 0 0 31 24 PCR_I2S_MCLK_SEL 0 23 PCR_I2S_RX_CLKM_EN 1 22 PCR_I2S_RX_CLKM_SEL 0 21 20 PCR_I2S_RX_CLKM_DIV_NUM 2 19 12 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 11 0 Reset PCR_I2S_RX_CLKM_DIV_NUM Configures the integral divisor for I2S clock. (R/W) PCR_I2S_RX_CLKM_SEL Configures the clock source of I2S RX. 0: XTAL_CLK 1: PLL_F240M_CLK 2: PLL_F160M_CLK 3: I2S_MCLK_in (R/W) PCR_I2S_RX_CLKM_EN Configures whether or not to enable I2S RX functional clock. 0: Not enable 1: Enable (R/W) PCR_I2S_MCLK_SEL Configures to select master clock. 0 (default): I2S_RX_CLK 1: I2S_TX_CLK (R/W) Espressif Systems 323 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.32. PCR_I2S_RX_CLKM_DIV_CONF_REG (0x0084) (reserved) 0 0 0 0 31 28 PCR_I2S_RX_CLKM_DIV_YN1 0 27 PCR_I2S_RX_CLKM_DIV_X 0 26 18 PCR_I2S_RX_CLKM_DIV_Y 1 17 9 PCR_I2S_RX_CLKM_DIV_Z 0 8 0 Reset PCR_I2S_RX_CLKM_DIV_Z For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a - b). (R/W) PCR_I2S_RX_CLKM_DIV_Y For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b). For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a - b)). (R/W) PCR_I2S_RX_CLKM_DIV_X For b <= a/2, the value of I2S_RX_CLKM_DIV_X is floor(a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is floor(a/(a-b)) - 1. (R/W) PCR_I2S_RX_CLKM_DIV_YN1 For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0. For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1. (R/W) Note: “a” and “b” represent the denominator and the numerator of the fractional divisor, respectively. For more information, see Section 31.6. Espressif Systems 324 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.33. PCR_SARADC_CONF_REG (0x0088) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 4 PCR_SARADC_REG_RST_EN 0 3 PCR_SARADC_REG_CLK_EN 1 2 PCR_SARADC_RST_EN 0 1 (reserved) 0 0 Reset PCR_SARADC_RST_EN Configures whether or not to reset functional registers of SAR ADC. 0: Not reset 1: Reset (R/W) PCR_SARADC_REG_CLK_EN Configures whether or not to enable APB_CLK for SAR ADC. 0: Not enable 1: Enable (R/W) PCR_SARADC_REG_RST_EN Configures whether or not to reset APB registers of SAR ADC. 0: Not reset 1: Reset (R/W) Espressif Systems 325 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.34. PCR_SARADC_CLKM_CONF_REG (0x008C) (reserved) 0 0 0 0 0 0 0 0 0 31 23 PCR_SARADC_CLKM_EN 1 22 PCR_SARADC_CLKM_SEL 0 21 20 PCR_SARADC_CLKM_DIV_NUM 4 19 12 PCR_SARADC_CLKM_DIV_B 0 11 6 PCR_SARADC_CLKM_DIV_A 0 5 0 Reset PCR_SARADC_CLKM_DIV_A Configures the denominator of the divisor’s fractional part for SAR ADC functional clock. (R/W) PCR_SARADC_CLKM_DIV_B Configures the numerator of the divisor’s fractional part for SAR ADC functional clock. (R/W) PCR_SARADC_CLKM_DIV_NUM Configures the integral part of the divisor for SAR ADC functional clock. (R/W) PCR_SARADC_CLKM_SEL Configures the clock source of SAR ADC. 0 (default): XTAL_CLK 1: RC_FAST_CLK 2: PLL_F80M_CLK 3: No clock source (R/W) PCR_SARADC_CLKM_EN Configures whether or not to enable SAR ADC functional clock. 0: Not enable 1: Enable (R/W) Espressif Systems 326 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.35. PCR_TSENS_CLK_CONF_REG (0x0090) (reserved) 0 0 0 0 0 0 0 0 31 24 PCR_TSENS_RST_EN 0 23 PCR_TSENS_CLK_EN 1 22 (reserved) 0 21 PCR_TSENS_CLK_SEL 0 20 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19 0 Reset PCR_TSENS_CLK_SEL Configures the clock source of the temperature sensor. 0 (default): XTAL_CLK 1: RC_FAST_CLK (R/W) PCR_TSENS_CLK_EN Configures whether or not to enable the clock of the temperature sensor. 0: Not enable 1: Enable (R/W) PCR_TSENS_RST_EN Configures whether or not to reset the temperature sensor. 0: Not reset 1: Reset (R/W) Espressif Systems 327 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.36. PCR_USB_DEVICE_CONF_REG (0x0094) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PCR_USB_DEVICE_READY 1 2 PCR_USB_DEVICE_RST_EN 0 1 PCR_USB_DEVICE_CLK_EN 1 0 Reset PCR_USB_DEVICE_JTAG_CLK_EN Configures whether or not to enable USB Serial/JTAG clock. 0: Not enable 1: Enable (R/W) PCR_USB_DEVICE_JTAG_RST_EN Configures whether or not to reset USB Serial/JTAG. 0: Not reset 1: Reset (R/W) PCR_USB_DEVICE_JTAG_READY Represents whether or not USB Serial/JTAG is released from reset. 0: Not released 1: Released (RO) Espressif Systems 328 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.37. PCR_INTMTX_CONF_REG (0x0098) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PCR_INTMTX_READY 1 2 PCR_INTMTX_RST_EN 0 1 PCR_INTMTX_CLK_EN 1 0 Reset PCR_INTMTX_CLK_EN Configures whether or not to enable Interrupt Matrix clock. 0: Not enable 1: Enable (R/W) PCR_INTMTX_RST_EN Configures whether or not to reset Interrupt Matrix. 0: Not reset 1: Reset (R/W) PCR_INTMTX_READY Represents whether or not Interrupt Matrix is released from reset. 0: Not released 1: Released (RO) Register 7.38. PCR_PCNT_CONF_REG (0x009C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PCR_PCNT_READY 1 2 PCR_PCNT_RST_EN 0 1 PCR_PCNT_CLK_EN 1 0 Reset PCR_PCNT_CLK_EN Configures whether or not to enable PCNT clock. 0: Not enable 1: Enable (R/W) PCR_PCNT_RST_EN Configures whether or not to reset PCNT. 0: Not reset 1: Reset (R/W) PCR_PCNT_READY Represents whether or not PCNT is released from reset. 0: Not released 1: Released (RO) Espressif Systems 329 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.39. PCR_ETM_CONF_REG (0x00A0) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PCR_ETM_READY 1 2 PCR_ETM_RST_EN 0 1 PCR_ETM_CLK_EN 1 0 Reset PCR_ETM_CLK_EN Configures whether or not to enable ETM clock. 0: Not enable 1: Enable (R/W) PCR_ETM_RST_EN Configures whether or not to reset ETM. 0: Reset 1: Not reset (R/W) PCR_ETM_READY Represents whether or not ETM is released from reset. 0: Not released 1: Released (RO) Register 7.40. PCR_PWM_CONF_REG (0x00A4) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PCR_PWM_READY 1 2 PCR_PWM_RST_EN 0 1 PCR_PWM_CLK_EN 1 0 Reset PCR_PWM_CLK_EN Configures whether or not to enable MCPWM bus clock. 0: Not enable 1: Enable (R/W) PCR_PWM_RST_EN Configures whether or not to reset MCPWM. 0: Not reset 1: Reset (R/W) PCR_PWM_READY Represents whether or not MCPWM is released from reset. 0: Not released 1: Released (RO) Espressif Systems 330 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.41. PCR_PWM_CLK_CONF_REG (0x00A8) (reserved) 0 0 0 0 0 0 0 0 0 31 23 PCR_PWM_CLKM_EN 1 22 PCR_PWM_CLKM_SEL 0 21 20 PCR_PWM_DIV_NUM 4 19 12 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 11 0 Reset PCR_PWM_DIV_NUM Configures the integral part of the divisor for MCPWM functional clock. (R/W) PCR_PWM_CLKM_SEL Configures the clock source of MCPWM. 0 (default): XTAL_CLK 1: RC_FAST_CLK 2: PLL_F160M_CLK 3: No clock source (R/W) PCR_PWM_CLKM_EN Configures whether or not to enable MCPWM functional clock. 0: Not enable 1: Enable (R/W) Register 7.42. PCR_PARL_IO_CONF_REG (0x00AC) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PCR_PARL_READY 1 2 PCR_PARL_RST_EN 0 1 PCR_PARL_CLK_EN 1 0 Reset PCR_PARL_CLK_EN Configures whether or not to enable APB_CLK for Parallel IO. 0: Not enable 1: Enable (R/W) PCR_PARL_RST_EN Configures whether or not to reset Parallel IO APB registers. 0: Not reset 1: Reset (R/W) PCR_PARL_READY Represents whether or not Parallel IO is released from reset. 0: Not released 1: Released (RO) Espressif Systems 331 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.43. PCR_PARL_CLK_RX_CONF_REG (0x00B0) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 31 20 PCR_PARL_RX_RST_EN 0 19 PCR_PARL_CLK_RX_EN 1 18 PCR_PARL_CLK_RX_SEL 0 17 16 PCR_PARL_CLK_RX_DIV_NUM 0 15 0 Reset PCR_PARL_CLK_RX_DIV_NUM Configures the integral divisor for Parallel IO RX clock. (R/W) PCR_PARL_CLK_RX_SEL Configures the clock source of Parallel IO RX. 0 (default): XTAL 1: RC_FAST_CLK 2: PLL_F240M_CLK 3: Use the clock from chip pin (R/W) PCR_PARL_CLK_RX_EN Configures whether or not to enable Parallel IO RX clock. 0: Not enable 1: Enable (R/W) PCR_PARL_RX_RST_EN Configures whether or not to reset Parallel IO RX. 0: Not reset 1: Reset (R/W) Espressif Systems 332 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.44. PCR_PARL_CLK_TX_CONF_REG (0x00B4) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 31 20 PCR_PARL_TX_RST_EN 0 19 PCR_PARL_CLK_TX_EN 1 18 PCR_PARL_CLK_TX_SEL 0 17 16 PCR_PARL_CLK_TX_DIV_NUM 0 15 0 Reset PCR_PARL_CLK_TX_DIV_NUM Configures the integral divisor for Parallel IO TX clock. (R/W) PCR_PARL_CLK_TX_SEL Configures the clock source of Parallel IO TX. 0 (default): XTAL 1: RC_FAST_CLK 2: PLL_F240M_CLK 3: Use the clock from chip pin (R/W) PCR_PARL_CLK_TX_EN Configures whether or not to enable Parallel IO TX clock. 0: Not enable 1: Enable (R/W) PCR_PARL_TX_RST_EN Configures whether or not to reset Parallel IO TX. 0: Not reset 1: Reset (R/W) Register 7.45. PCR_GDMA_CONF_REG (0x00C0) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 2 PCR_GDMA_RST_EN 0 1 PCR_GDMA_CLK_EN 1 0 Reset PCR_GDMA_CLK_EN Configures whether or not to enable GDMA clock. 0: Not enable 1: Enable (R/W) PCR_GDMA_RST_EN Configures whether or not to reset GDMA. 0: Not reset 1: Reset (R/W) Espressif Systems 333 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.46. PCR_SPI2_CONF_REG (0x00C4) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PCR_SPI2_READY 1 2 PCR_SPI2_RST_EN 0 1 PCR_SPI2_CLK_EN 1 0 Reset PCR_SPI2_CLK_EN Configures whether or not to enable APB_CLK for SPI2. 0: Not enable 1: Enable (R/W) PCR_SPI2_RST_EN Configures whether or not to reset SPI2. 0: Not reset 1: Reset (R/W) PCR_SPI2_READY Represents whether or not SPI2 is released from reset. 0: Not released 1: Released (RO) Register 7.47. PCR_SPI2_CLKM_CONF_REG (0x00C8) (reserved) 0 0 0 0 0 0 0 0 0 31 23 PCR_SPI2_CLKM_EN 1 22 PCR_SPI2_CLKM_SEL 0 21 20 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19 0 Reset PCR_SPI2_CLKM_SEL Configures the clock source of SPI2. 0 (default): XTAL_CLK 1: PLL_F160M_CLK 2: RC_FAST_CLK 3: PLL_F120M_CLK (R/W) PCR_SPI2_CLKM_EN Configures whether or not to enable SPI2 functional clock. 0: Not enable 1: Enable (R/W) Espressif Systems 334 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.48. PCR_AES_CONF_REG (0x00CC) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PCR_AES_READY 1 2 PCR_AES_RST_EN 0 1 PCR_AES_CLK_EN 1 0 Reset PCR_AES_CLK_EN Configures whether or not to enable AES clock. 0: Not enable 1: Enable (R/W) PCR_AES_RST_EN Configures whether or not to reset AES. 0: Not reset 1: Reset (R/W) PCR_AES_READY Represents whether or not AES is released from reset. 0: Not released 1: Released (RO) Register 7.49. PCR_SHA_CONF_REG (0x00D0) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PCR_SHA_READY 1 2 PCR_SHA_RST_EN 0 1 PCR_SHA_CLK_EN 1 0 Reset PCR_SHA_CLK_EN Configures whether or not to enable SHA clock. 0: Not enable 1: Enable (R/W) PCR_SHA_RST_EN Configures whether or not to reset SHA. 0: Not reset 1: Reset (R/W) PCR_SHA_READY Represents whether or not SHA is released from reset. 0: Not released 1: Released (RO) Espressif Systems 335 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.50. PCR_RSA_CONF_REG (0x00D4) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PCR_RSA_READY 1 2 PCR_RSA_RST_EN 0 1 PCR_RSA_CLK_EN 1 0 Reset PCR_RSA_CLK_EN Configures whether or not to enable RSA clock. 0: Not enable 1: Enable (R/W) PCR_RSA_RST_EN Configures whether or not to reset RSA. 0: Not reset 1: Reset (R/W) PCR_RSA_READY Represents whether or not RSA is released from reset. 0: Not released 1: Released (RO) Espressif Systems 336 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.51. PCR_RSA_PD_CTRL_REG (0x00D8) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PCR_RSA_MEM_FORCE_PD 0 2 PCR_RSA_MEM_FORCE_PU 1 1 PCR_RSA_MEM_PD 0 0 Reset PCR_RSA_MEM_PD Configures whether or not to power down RSA internal memory. 0: Not power down 1: Power down (R/W) PCR_RSA_MEM_FORCE_PU Configures whether or not to force power up RSA internal memory. 0: Not force power up 1: Force power up (R/W) PCR_RSA_MEM_FORCE_PD Configures whether or not to force power down RSA internal memory. 0: Not force power down 1: Force power down (R/W) Espressif Systems 337 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.52. PCR_ECC_CONF_REG (0x00DC) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PCR_ECC_READY 1 2 PCR_ECC_RST_EN 0 1 PCR_ECC_CLK_EN 1 0 Reset PCR_ECC_CLK_EN Configures whether or not to enable ECC clock. 0: Not enable 1: Enable (R/W) PCR_ECC_RST_EN Configures whether or not to reset ECC. 0: Not reset 1: Reset (R/W) PCR_ECC_READY Represents whether or not ECC is released from reset. 0: Not released 1: Released (RO) Espressif Systems 338 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.53. PCR_ECC_PD_CTRL_REG (0x00E0) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PCR_ECC_MEM_FORCE_PD 0 2 PCR_ECC_MEM_FORCE_PU 1 1 PCR_ECC_MEM_PD 0 0 Reset PCR_ECC_MEM_PD Configures whether or not to power down ECC internal memory. 0: Not power down 1: Power down (R/W) PCR_ECC_MEM_FORCE_PU Configures whether or not to force power up ECC internal memory. 0: Not force power up 1: Force power up (R/W) PCR_ECC_MEM_FORCE_PD Configures whether or not to force power down ECC internal memory. 0: Not force power down 1: Force power down (R/W) Espressif Systems 339 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.54. PCR_DS_CONF_REG (0x00E4) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PCR_DS_READY 1 2 PCR_DS_RST_EN 0 1 PCR_DS_CLK_EN 1 0 Reset PCR_DS_CLK_EN Configures whether or not to enable DS clock. 0: Not enable 1: Enable (R/W) PCR_DS_RST_EN Configures whether or not to reset DS. 0: Not reset 1: Reset (R/W) PCR_DS_READY Represents whether or not DS is released from reset. 0: Not released 1: Released (RO) Register 7.55. PCR_HMAC_CONF_REG (0x00E8) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PCR_HMAC_READY 1 2 PCR_HMAC_RST_EN 0 1 PCR_HMAC_CLK_EN 1 0 Reset PCR_HMAC_CLK_EN Configures whether or not to enable HMAC clock. 0: Not enable 1: Enable (R/W) PCR_HMAC_RST_EN Configures whether or not to reset HMAC. 0: Not reset 1: Reset (R/W) PCR_HMAC_READY Represents whether or not HMAC is released from reset. 0: Not released 1: Released (RO) Espressif Systems 340 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.56. PCR_ECDSA_CONF_REG (0x00EC) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PCR_ECDSA_READY 1 2 PCR_ECDSA_RST_EN 0 1 PCR_ECDSA_CLK_EN 1 0 Reset PCR_ECDSA_CLK_EN Configures whether or not to enable ECDSA clock. 0: Not enable 1: Enable (R/W) PCR_ECDSA_RST_EN Configures whether or not to reset ECDSA. 0: Not reset 1: Reset (R/W) PCR_ECDSA_READY Represents whether or not ECDSA is released from reset. 0: Not released 1: Released (RO) Register 7.57. PCR_IOMUX_CONF_REG (0x00F0) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 2 PCR_IOMUX_RST_EN 0 1 PCR_IOMUX_CLK_EN 1 0 Reset PCR_IOMUX_CLK_EN Configures whether or not to enable APB_CLK for IO MUX. 0: Not enable 1: Enable (R/W) PCR_IOMUX_RST_EN Configures whether or not to reset IO MUX. 0: Not reset 1: Reset (R/W) Espressif Systems 341 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.58. PCR_IOMUX_CLK_CONF_REG (0x00F4) (reserved) 0 0 0 0 0 0 0 0 0 31 23 PCR_IOMUX_FUNC_CLK_EN 1 22 PCR_IOMUX_FUNC_CLK_SEL 0 21 20 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19 0 Reset PCR_IOMUX_FUNC_CLK_SEL Configures the clock source of IO MUX. 0: XTAL_CLK 1: RC_FAST_CLK 2: PLL_F48M_CLK 3�No clock source (R/W) PCR_IOMUX_FUNC_CLK_EN Configures whether or not to enable IO MUX functional clock. 0: Not enable 1: Enable (R/W) Register 7.59. PCR_TRACE_CONF_REG (0x00FC) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 2 PCR_TRACE_RST_EN 0 1 PCR_TRACE_CLK_EN 1 0 Reset PCR_TRACE_CLK_EN Configures whether or not to enable the clock of RISC-V Trace Encoder. 0: Not enable 1: Enable (R/W) PCR_TRACE_RST_EN Configures whether or not to reset RISC-V Trace Encoder. 0: Not reset 1: Reset (R/W) Espressif Systems 342 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.60. PCR_ASSIST_CONF_REG (0x0100) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 2 PCR_ASSIST_RST_EN 0 1 PCR_ASSIST_CLK_EN 1 0 Reset PCR_ASSIST_CLK_EN Configures whether or not to enable Debug Assistant clock. 0: Not enable 1: Enable (R/W) PCR_ASSIST_RST_EN Configures whether or not to reset Debug Assistant. 0: Not reset 1: Reset (R/W) Register 7.61. PCR_CACHE_CONF_REG (0x0104) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 2 PCR_CACHE_RST_EN 0 1 PCR_CACHE_CLK_EN 1 0 Reset PCR_CACHE_CLK_EN Configures whether or not to enable Cache clock. 0: Not enable 1: Enable (R/W) PCR_CACHE_RST_EN Configures whether or not to reset Cache. 0: Not reset 1: Reset (R/W) Espressif Systems 343 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.62. PCR_TIMEOUT_CONF_REG (0x010C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PCR_HP_TIMEOUT_RST_EN 0 2 PCR_CPU_TIMEOUT_RST_EN 0 1 (reserved) 0 0 Reset PCR_CPU_TIMEOUT_RST_EN Configures whether or not to reset CPU Peripheral Timeout Protec- tion. 0: Not reset 1: Reset (R/W) PCR_HP_TIMEOUT_RST_EN Configures whether or not to reset HP Peripheral Timeout Protection. 0: Not reset 1: Reset (R/W) Register 7.63. PCR_SYSCLK_CONF_REG (0x0110) (reserved) 0 31 PCR_CLK_XTAL_FREQ 32 30 24 (reserved) 0 0 0 0 0 0 23 18 PCR_SOC_CLK_SEL 0 17 16 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 Reset PCR_SOC_CLK_SEL Configures to select clock source of HP_ROOT_CLK. 0: XTAL_CLK 1: RC_FAST_CLK 2: PLL_F160M_CLK 3: PLL_F240M_CLK �� (R/W) PCR_CLK_XTAL_FREQ Represents the frequency of XTAL. Measurement unit: MHz. (RO) Espressif Systems 344 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.64. PCR_CPU_WAITI_CONF_REG (0x0114) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 PCR_CPU_WAITI_DELAY_NUM 0 7 4 PCR_CPU_WAIT_MODE_FORCE_ON 1 3 (reserved) 0 0 0 2 0 Reset PCR_CPU_WAIT_MODE_FORCE_ON Configures whether or not to force on the gated CPU clock when CPU is in WFI (wait for interrupt) mode. 0: Not force enable 1: Force enable Usually, after executing the WFI instruction, CPU enters the WFI mode, during which the gated CPU clock is turned off until any interrupts occur. In this way, power consumption is saved. If this bit is set, the gated CPU clock is always on and will not be turned off by the WFI instruction. (R/W) PCR_CPU_WAITI_DELAY_NUM Configures the number of delay cycles to turn off the CPU clock after the CPU enters the WFI mode because of WFI instruction. Measurement unit: CPU_CLK cycles. (R/W) Register 7.65. PCR_CPU_FREQ_CONF_REG (0x0118) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 PCR_CPU_DIV_NUM 0 7 0 Reset PCR_CPU_DIV_NUM Configures the divisor of HP_ROOT_CLK to generate CPU_CLK. This field should be used together with PCR_AHB_DIV_NUM. Espressif Systems 345 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.66. PCR_AHB_FREQ_CONF_REG (0x011C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 PCR_AHB_DIV_NUM 0 7 0 Reset PCR_AHB_DIV_NUM Configures the divisor of HP_ROOT_CLK to generate AHB_CLK. This field should be used together with PCR_CPU_DIV_NUM. (R/W) Register 7.67. PCR_APB_FREQ_CONF_REG (0x0120) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 PCR_APB_DIV_NUM 0 15 8 PCR_APB_DECREASE_DIV_NUM 0 7 0 Reset PCR_APB_DECREASE_DIV_NUM Configures the divisor AHB_CLK to generate APB_CLK during the first division. (R/W) PCR_APB_DIV_NUM Configures the divisor of AHB_CLK to generate APB_CLK during the second division. (R/W) Espressif Systems 346 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.68. PCR_PLL_DIV_CLK_EN_REG (0x0128) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 6 PCR_PLL_48M_CLK_EN 1 5 reserved 1 4 PCR_PLL_80M_CLK_EN 1 3 PCR_PLL_120M_CLK_EN 1 2 PCR_PLL_160M_CLK_EN 1 1 PCR_PLL_240M_CLK_EN 1 0 Reset PCR_PLL_240M_CLK_EN Configures whether or not to enable PLL_F240M_CLK. 0: Not enable 1 (default): Enable (R/W) PCR_PLL_160M_CLK_EN Configures whether or not to enable PLL_F160M_CLK. 0: Not enable 1 (default): Enable (R/W) PCR_PLL_120M_CLK_EN Configures whether or not to enable PCR_PLL_120M_CLK. 0: Not enable 1 (default): Enable (R/W) PCR_PLL_80M_CLK_EN Configures whether or not to enable PCR_PLL_80M_CLK. 0: Not enable 1 (default): Enable (R/W) PCR_PLL_48M_CLK_EN Configures whether or not to enable PCR_PLL_48M_CLK. 0: Not enable 1 (default): Enable (R/W) Espressif Systems 347 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.69. PCR_CTRL_32K_CONF_REG (0x0130) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 PCR_FOSC_TICK_NUM 7 15 8 (reserved) 0 0 0 0 0 7 3 PCR_32K_SEL 0 2 0 Reset PCR_32K_SEL Configures the 32 kHz clock for TIMER_GROUP. 0: XTAL32K_CLK 1: OSC_SLOW_CLK 2: RC_SLOW_CLK 2: RC_FAST_CLK (R/W) PCR_FOSC_TICK_NUM Configure the division factor for the RC_FAST_CLK to enter the calibration module. (Effective when PCR_32K_SEL is set to 4). (R/W) Register 7.70. PCR_SEC_CONF_REG (0x013C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PCR_SEC_RST_EN 0 2 PCR_SEC_CLK_SEL 0 1 0 Reset PCR_SEC_CLK_SEL Configures the clock source for the External Memory Encryption and Decryp- tion module. 0 (default): XTAL_CLK 1: RC_FAST_CLK 2: PLL_F480M_CLK 3: No clock source (R/W) PCR_SEC_RST_EN Configures whether or not to reset the SEC. 0: Not reset 1: Reset (R/W) Espressif Systems 348 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.71. PCR_BUS_CLK_UPDATE_REG (0x0144) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 PCR_BUS_CLOCK_UPDATE 0 0 Reset PCR_BUS_CLOCK_UPDATE Configures whether or not to update configurations for CPU_CLK di- vision, AHB_CLK division and HP_ROOT_CLK clock source selection. 0: Not update configurations 1: Update configurations This bit is automatically cleared when configurations have been updated. (R/W/WTC) Register 7.72. PCR_SAR_CLK_DIV_REG (0x0148) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 PCR_SAR1_CLK_DIV_NUM 4 15 8 PCR_SAR2_CLK_DIV_NUM 4 7 0 Reset PCR_SAR2_CLK_DIV_NUM Configures the divisor for SAR ADC2 clock to generate ADC analog control signals. (R/W) PCR_SAR1_CLK_DIV_NUM Configures the divisor for SAR ADC clock to generate ADC analog con- trol signals. (R/W) Espressif Systems 349 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.73. PCR_BS_CONF_REG (0x0150) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 2 PCR_BS_RST_EN 0 1 PCR_BS_CLK_EN 0 0 Reset PCR_BS_CLK_EN Configures whether or not to enable the clock of the Bit Scrambler. 0: Not enable 1: Enable (R/W) PCR_BS_RST_EN Configures whether or not to reset the Bit Scrambler. 0: Not reset 1: Reset (R/W) Register 7.74. PCR_BS_FUNC_CONF_REG (0x0154) (reserved) 0 0 0 0 0 0 0 31 25 PCR_BS_RX_RST_EN 0 24 PCR_BS_TX_RST_EN 0 23 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22 0 Reset PCR_BS_TX_RST_EN Configures whether or not to reset the transmit side of Bit Scrambler. 0: Not reset 1: Reset (R/W) PCR_BS_RX_RST_EN Configures whether or not to reset the receive side of Bit Scrambler. 0: Not reset 1: Reset (R/W) Espressif Systems 350 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.75. PCR_BS_PD_CTRL_REG (0x0158) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PCR_BS_MEM_FORCE_PD 1 2 PCR_BS_MEM_FORCE_PU 0 1 (reserved) 0 0 Reset PCR_BS_MEM_FORCE_PU Configures whether or not to force power up Bit Scrambler memory. 0: Not force power up 1: Force power up (R/W) PCR_BS_MEM_FORCE_PD Configures whether or not to force power down Bit Scrambler memory. 0: Not force power down 1: Force power down (R/W) Register 7.76. PCR_TIMERGROUP_WDT_CONF_REG (0x015C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 2 PCR_TG1_WDT_RST_EN 0 1 PCR_TG0_WDT_RST_EN 0 0 Reset PCR_TG0_WDT_RST_EN Configures whether or not to reset the watchdog of Timer Group 0. 0: Not reset 1: Reset (R/W) PCR_TG1_WDT_RST_EN Configures whether or not to reset the watchdog of Timer Group 1. 0: Not reset 1: Reset (R/W) Espressif Systems 351 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.77. PCR_TIMERGROUP_XTAL_CONF_REG (0x0160) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PCR_TG0_XTAL_CLK_EN 1 2 reserved 0 1 PCR_TG0_XTAL_RST_EN 0 0 Reset PCR_TG0_XTAL_RST_EN Configures whether to reset the clock calibration function of the Timer Group 0. 0: Not reset 1: Reset (R/W) PCR_TG0_XTAL_CLK_EN Configures whether to enable the clock calibration function of the Timer Group 0. 0: Not enable 1: Enable (R/W) Espressif Systems 352 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.78. PCR_TCM_MEM_MONITOR_CONF_REG (0x016C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PCR_TCM_MEM_MONITOR_READY 1 2 PCR_TCM_MEM_MONITOR_RST_EN 0 1 PCR_TCM_MEM_MONITOR_CLK_EN 1 0 Reset PCR_TCM_MEM_MONITOR_CLK_EN Configures whether to enable TCM_MEM_MONITOR_CLK. 0: Not enable 1: Enable (R/W) PCR_TCM_MEM_MONITOR_RST_EN Configures whether to reset the memory monitor. 0: Not reset 1: Reset (R/W) PCR_TCM_MEM_MONITOR_READY Represents whether or not memory monitor is released from reset. 0: Not released 1: Released (RO) Espressif Systems 353 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.79. PCR_PSRAM_MEM_MONITOR_CONF_REG (0x0170) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PCR_PSRAM_MEM_MONITOR_READY 1 2 PCR_PSRAM_MEM_MONITOR_RST_EN 0 1 PCR_PSRAM_MEM_MONITOR_CLK_EN 1 0 Reset PCR_PSRAM_MEM_MONITOR_CLK_EN Configures whether to enable the PSRAM_MEM_MONITOR_CLK. 0: Not enable 1: Enable (R/W) PCR_PSRAM_MEM_MONITOR_RST_EN Configures whether to reset the memory monitor of PSRAM. 0: Not reset 1: Reset (R/W) PCR_PSRAM_MEM_MONITOR_READY Represents whether or not memory monitor of PSRAM is released from reset. 0: Not released 1: Released (RO) Espressif Systems 354 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.80. PCR_HPCORE_0_PD_CTRL_REG (0x0178) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PCR_HPCORE_0_MEM_FORCE_PD 0 2 PCR_HPCORE_0_MEM_FORCE_PU 1 1 (reserved) 0 0 Reset PCR_HPCORE_0_MEM_FORCE_PU Configures whether or not to force power up HP CORE0 mem- ory. 0: Not force power up 1: Force power up (R/W) PCR_HPCORE_0_MEM_FORCE_PD Configures whether or not to force power down Key Manager memory. 0: Not force power down 1: Force power down (R/W) Register 7.81. PCR_SDIO_SLAVE_CONF_REG (0x017C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 2 PCR_SDIO_SLAVE_RST_EN 0 1 PCR_SDIO_SLAVE_CLK_EN 0 0 Reset PCR_SDIO_SLAVE_RST_EN Configures whether to reset the SDIO slave module. 0: Not reset 1: Reset (R/W) PCR_SDIO_SLAVE_CLK_EN Configures whether to enable the SDIO_SLAVE_CLK. 0: Not enable 1: Enable (R/W) Espressif Systems 355 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.82. PCR_SYSCLK_FREQ_QUERY_0_REG (0x0120) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 18 PCR_PLL_FREQ 96 17 8 PCR_FOSC_FREQ 8 7 0 Reset PCR_FOSC_FREQ Represents the frequency of RC_FAST_CLK. Measurement unit: MHz. (HRO) PCR_PLL_FREQ Represents the frequency of PLL_F480M_CLK . Measurement unit: MHz. (HRO) Register 7.83. PCR_DATE_REG (0x0FFC) (reserved) 0 0 0 0 31 28 PCR_DATE 0x2210080 27 0 Reset PCR_DATE Version control register. (R/W) 7.5.2 LP System Clock Registers The addresses of the last two registers with the LPPERI prefix in this section are relative to the Low-power Peripheral Register (LPPERI) base address. The addresses of the third and fourth to last registers with the LP_AON prefix in this section are relative to the Low-power Always-on Register (LP_AON) base address.The other addresses in this section are relative to the Low-power Clock/Reset Register (LP_CLKRST) base address. For base address, please refer to Table 4.3-2 in Chapter 4 System and Memory. Espressif Systems 356 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.84. LP_CLKRST_LP_CLK_CONF_REG (0x0000) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 4 LP_CLKRST_FAST_CLK_SEL 1 3 2 LP_CLKRST_SLOW_CLK_SEL 0 1 0 Reset LP_CLKRST_SLOW_CLK_SEL Configures the source of LP_SLOW_CLK. 0: RC_SLOW_CLK 1: XTAL32K_CLK 2: OSC_SLOW_CLK 3: Invalid. No effect (R/W) LP_CLKRST_FAST_CLK_SEL Configures the source of LP_FAST_CLK. 0: RC_FAST_CLK 1: XTAL_D2_CLK (R/W) Espressif Systems 357 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.85. LP_CLKRST_LP_CLK_PO_EN_REG (0x0004) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 11 LP_CLKRST_LPBUS_OEN 1 10 LP_CLKRST_RNG_OEN 1 9 LP_CLKRST_FAST_OEN 1 8 LP_CLKRST_SLOW_OEN 1 7 LP_CLKRST_CORE_EFUSE_OEN 1 6 LP_CLKRST_XTAL32K_OEN 1 5 (reserved)) 1 4 LP_CLKRST_FOSC_OEN 1 3 LP_CLKRST_SOSC_OEN 1 2 LP_CLKRST_AON_FAST_OEN 1 1 LP_CLKRST_AON_SLOW_OEN 1 0 Reset LP_CLKRST_AON_SLOW_OEN Configures whether to gate the LP_DYN_SLOW_CLK signals to pad. 0: Disable the clock gate 1: Enable the clock gate (R/W) LP_CLKRST_AON_FAST_OEN Configures whether to gate the LP_DYN_FAST_CLK signals to pad. 0: Disable the clock gate 1: Enable the clock gate (R/W) LP_CLKRST_SOSC_OEN Configures whether to gate the OSC_SLOW_CLK signals to pad. 0: Disable the clock gate 1: Enable the clock gate (R/W) LP_CLKRST_FOSC_OEN Configures whether to gate the RC_FAST_CLK signals to pad. 0: Disable the clock gate 1: Enable the clock gate (R/W) LP_CLKRST_XTAL32K_OEN Configures whether to gate the XTAL32K_CLK signals to pad. 0: Disable the clock gate 1: Enable the clock gate (R/W) Continued on the next page... Espressif Systems 358 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.85. LP_CLKRST_LP_CLK_PO_EN_REG (0x0004) Continued from the previous page... LP_CLKRST_CORE_EFUSE_OEN Configures whether to gate the EFUSE_CTRL clock. 0: Disable the clock gate 1: Enable the clock gate (R/W) LP_CLKRST_SLOW_OEN Configures whether to gate the LP_SLOW_CLK signals to pad. 0: Disable the clock gate 1: Enable the clock gate (R/W) LP_CLKRST_FAST_OEN Configures whether to gate the LP_FAST_CLK signals to pad. 0: Disable the clock gate 1: Enable the clock gate (R/W) LP_CLKRST_RNG_OEN Configures whether to gate the RNG clock signals to pad. 0: Disable the clock gate 1: Enable the clock gate (R/W) LP_CLKRST_LPBUS_OEN Configures whether to gate the LP bus clock signals to pad. 0: Disable the clock gate 1: Enable the clock gate (R/W) Register 7.86. LP_CLKRST_LP_CLK_EN_REG (0x0008) LP_CLKRST_FAST_ORI_GATE 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 0 Reset LP_CLKRST_FAST_ORI_GATE Configures the clock gate to LP_FAST_CLK. 0: Invalid. The clock gate controlled by hardware FSM 1: Force the clock to pass the clock gate (R/W) Espressif Systems 359 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.87. LP_CLKRST_LP_RST_EN_REG (0x000C) LP_CLKRST_ANA_PERI_RESET_EN 0 31 LP_CLKRST_WDT_RESET_EN 0 30 LP_CLKRST_LP_TIMER_RESET_EN 0 29 LP_CLKRST_AON_EFUSE_CORE_RESET_EN 0 28 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27 0 Reset LP_CLKRST_AON_EFUSE_CORE_RESET_EN Configures whether to reset the always-on part of EFUSE_CTRL. 0: Invalid. No effect 1: Reset (R/W) LP_CLKRST_LP_TIMER_RESET_EN Configures whether to reset RTC timer. 0: Invalid. No effect 1: Reset (R/W) LP_CLKRST_WDT_RESET_EN Configures whether to reset RWDT and Super Watchdog Timer. 0: Invalid. No effect 1: Reset (R/W) LP_CLKRST_ANA_PERI_RESET_EN Configures whether to reset analog peripherals, including the Brownout Detector. 0: Invalid. No effect 1: Reset (R/W) Espressif Systems 360 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.88. LP_CLKRST_RESET_CAUSE_REG (0x0010) LP_CLKRST_CORE0_RESET_FLAG_CLR 0 31 LP_CLKRST_CORE0_RESET_FLAG_SET 0 30 LP_CLKRST_CORE0_RESET_CAUSE_CLR 0 29 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28 6 LP_CLKRST_CORE0_RESET_FLAG 1 5 LP_CLKRST_RESET_CAUSE 0 4 0 Reset LP_CLKRST_RESET_CAUSE Represents the reset cause. (RO) LP_CLKRST_CORE0_RESET_FLAG Represents whether the reset occurred is recorded in LP_CLKRST_RESET_CAUSE. 0: Illegal reset 1: Recorded reset (RO) LP_CLKRST_CORE0_RESET_CAUSE_CLR Write 1 to clear LP_CLKRST_RESET_CAUSE. (WT) LP_CLKRST_CORE0_RESET_FLAG_SET Write 1 to set LP_CLKRST_CORE0_RESET_FLAG. (WT) LP_CLKRST_CORE0_RESET_FLAG_CLR Write 1 to clear LP_CLKRST_CORE0_RESET_FLAG. (WT) Espressif Systems 361 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.89. LP_CLKRST_CPU_RESET_REG (0x0014) LP_CLKRST_CPU_STALL_EN 0 31 LP_CLKRST_CPU_STALL_WAIT 1 30 26 LP_CLKRST_RTC_WDT_CPU_RESET_EN 0 25 LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH 1 24 22 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21 0 Reset LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH Configures the length of RWDT CPU reset. Measurement unit: LP_DYN_FAST_CLK clock cycles. (R/W) LP_CLKRST_RTC_WDT_CPU_RESET_EN Configures whether or not to enable RWDT CPU reset. 0: Enable RWDT CPU reset. 1: Disable RWDT CPU reset. (R/W) LP_CLKRST_CPU_STALL_WAIT Configure the time interval between CPU stall and reset. Measurement unit: LP_DYN_FAST_CLK clock cycles. (R/W) LP_CLKRST_CPU_STALL_EN Configures whether or not CPU will stall before RWDT and software reset CPU. 0: CPU will not stall. 1: CPU will stall. (R/W) Register 7.90. LP_CLKRST_FOSC_CNTL_REG (0x0018) LP_CLKRST_FOSC_DFREQ 0xac 31 22 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21 0 Reset LP_CLKRST_FOSC_DFREQ Configures the frequency of RC_FAST_CLK frequency. (R/W) Espressif Systems 362 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.91. LP_CLKRST_CLK_TO_HP_REG (0x0020) LP_CLKRST_ICG_HP_FOSC 1 31 (reserved)) 1 30 LP_CLKRST_ICG_HP_SOSC 1 29 LP_CLKRST_ICG_HP_XTAL32K 1 28 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27 0 Reset LP_CLKRST_ICG_HP_XTAL32K Configures whether to gate the XTAL32K_CLK signals to HP sys- tem. 0: Disable the clock gate 1: Enable the clock gate (R/W) LP_CLKRST_ICG_HP_SOSC Configures whether to gate the RC_SLOW_CLK signals to HP system. 0: Disable the clock gate 1: Enable the clock gate (R/W) LP_CLKRST_ICG_HP_FOSC Configures whether to gate the RC_FAST_CLK signals to HP system. 0: Disable the clock gate 1: Enable the clock gate (R/W) Register 7.92. LP_CLKRST_LPMEM_FORCE_REG (0x0024) LP_CLKRST_LPMEM_CLK_FORCE_ON 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 0 Reset LP_CLKRST_LPMEM_CLK_FORCE_ON Configures whether to force enable the gate of LP Memory. 0: Invalid. The clock gate controlled by hardware FSM 1: Force open clock gate of LP Memory (R/W) Espressif Systems 363 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.93. LP_CLKRST_LPPERI_REG (0x0028) (reserved) 0 31 30 LP_CLKRST_LP_SEL_XTAL32K 1 29 LP_CLKRST_LP_SEL_XTAL 0 28 LP_CLKRST_LP_SEL_OSC_FAST 0 27 LP_CLKRST_LP_SEL_OSC_SLOW 0 26 (reserved)) 0 25 24 LP_CLKRST_LP_BLETIMER_DIV_NUM 0 23 12 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 11 0 Reset LP_CLKRST_LP_BLETIMER_DIV_NUM Configures the divisor of the clock divider for RTC BLE Timer. The working clock frequency of RTC BLE Timer is equal to the source clock frequency divided by ((LP_CLKRST_LP_BLETIMER_DIV_NUM - 1) / 2). (R/W) LP_CLKRST_LP_SEL_OSC_SLOW Configures the clock source for RTC BLE Timer. 1: Selects RC_SLOW_CLK as the source clock for RTC BLE Timer. 0: Disables RC_SLOW_CLK as the source clock for RTC BLE Timer. (R/W) LP_CLKRST_LP_SEL_OSC_FAST Configures the clock source for RTC BLE Timer. 1: Selects RC_FAST_CLK as the source clock for RTC BLE Timer. 0: Disables RC_FAST_CLK as the source clock for RTC BLE Timer. (R/W) LP_CLKRST_LP_SEL_XTAL Configures the clock source for RTC BLE Timer. 1: Selects XTAL_CLK as the source clock for RTC BLE Timer. 0: Disables XTAL_CLK as the source clock for RTC BLE Timer. (R/W LP_CLKRST_LP_SEL_XTAL32K Configures the clock source for RTC BLE Timer. 1: Selects XTAL32K_CLK as the source clock for RTC BLE Timer. 0: Disables XTAL32K_CLK as the source clock for RTC BLE Timer. (R/W) Register 7.94. LP_CLKRST_XTAL32K_REG (0x002C) LP_CLKRST_DAC_XTAL32K 3 31 29 LP_CLKRST_DBUF_XTAL32K 0 28 LP_CLKRST_DGM_XTAL32K 3 27 25 LP_CLKRST_DRES_XTAL32K 3 24 22 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21 0 Reset LP_CLKRST_DRES_XTAL32K Configures DRES (R/W) LP_CLKRST_DGM_XTAL32K Configures DGM (R/W) LP_CLKRST_DBUF_XTAL32K Configures DBUF (R/W) LP_CLKRST_DAC_XTAL32K Configures DAC (R/W) Espressif Systems 364 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.95. LP_CLKRST_DATE_REG (0x03FC) LP_CLKRST_CLK_EN 0 31 LP_CLKRST_CLKRST_DATE 0x2207280 30 0 Reset LP_CLKRST_CLKRST_DATE Version control register. (R/W) LP_CLKRST_CLK_EN Configures whether to force enable the clock gate for header registers. 0: Invalid 1: Force enable (R/W) Register 7.96. LP_AON_SYS_CFG_REG (0x0034) LP_AON_HPSYS_SW_RESET 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 0 Reset LP_AON_HPSYS_SW_RESET Configures whether to do software reset of the system. 0: Not reset 1: Reset (WT) Espressif Systems 365 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.97. LP_AON_CPUCORE0_CFG_REG (0x0038) (reserved) 0 31 29 LP_AON_CPU_CORE0_SW_RESET 0 28 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27 0 Reset LP_AON_CPU_CORE0_SW_RESET Configures whether to do software reset of the CPU. 0: Not reset 1: Reset (WT) Register 7.98. LPPERI_CLK_EN_REG (0x0000) (reserved) 0 31 LPPERI_EFUSE_CK_EN 1 30 (reserved) 0 0 0 0 0 29 25 LPPERI_RNG_CK_EN 1 24 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 0 Reset LPPERI_RNG_CK_EN Configures whether to gate the clock signals of RNG module. 0: Disable the clock gate 1: Enable the clock gate (R/W) LPPERI_EFUSE_CK_EN Configures whether to gate the clock signals of eFuse Controller. 0: Disable the clock gate 1: Enable the clock gate (R/W) Espressif Systems 366 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 7 Reset and Clock Register 7.99. LPPERI_RESET_EN_REG (0x0004) (reserved) 0 31 LPPERI_EFUSE_RESET_EN 0 30 (reserved) 0 0 0 0 0 29 25 LPPERI_RNG_RESET_EN 0 24 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 0 Reset LPPERI_RNG_RESET_EN Configures whether to do software reset of the RNG Controller. 0: Not reset 1: Reset (R/W) LPPERI_EFUSE_RESET_EN Configures whether to do software reset of the eFuse Controller. 0: Not reset 1: Reset (R/W) Espressif Systems 367 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 8 Chip Boot Control Chapter 8 Chip Boot Control 8.1 Overview The chip allows for configuring the following boot parameters through strapping pins and eFuse parameters at power-up or a hardware reset, without microcontroller interaction. • Chip boot mode – Strapping pins: GPIO26, GPIO27, and GPIO28 • SDIO sampling and driving clock edge – Strapping pins: GPIO25 and MTDI • ROM messages printing – Strapping pin: GPIO27 – eFuse parameters: EFUSE_UART_PRINT_CONTROL and EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT • JTAG signal source – Strapping pin: GPIO7 – eFuse parameters: EFUSE_DIS_PAD_JTAG, EFUSE_DIS_USB_JTAG, and EFUSE_JTAG_SEL_ENABLE • Crystal frequency selection – Strapping pin: MTMS (effective only in Joint Download Boot mode) – eFuse parameters: EFUSE_XTAL_48M_SEL and EFUSE_XTAL_48M_SEL_MODE The default values of all the above eFuse parameters are 0, which means that they are not burnt. Given that eFuse is one-time programmable, once an eFuse bit is programmed to 1, it can never be reverted to 0. For how to program eFuse bits, please refer to Chapter 5 eFuse Controller (eFuse). During Chip Reset (see Chapter 7 Reset and Clock), hardware captures samples and stores the voltage level of strapping pins as strapping bit of “0” or “1” in latches, and holds these bits until the chip is powered down or next chip reset. Software can read the latch status (strapping value) from GPIO_STRAPPING. 8.2 Functional Description This section introduces chip reset functions and the patterns of the strapping pins and eFuse values to invoke each function. Espressif Systems 368 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 8 Chip Boot Control Notice: Only documented patterns should be used. If an undocumented pattern is used, it may trigger unexpected behaviors. 8.2.1 Default Configuration The default values of the strapping pins, namely the logic levels, are determined by pins’ internal weak pull-up/pull-down resistors at reset if the pins are not connected to any circuit, or connected to an external high-impedance circuit. Table 8.2-1. Default Configuration of Strapping Pins Strapping Pin Default Configuration Bit Value GPIO25 Floating – GPIO26 Floating – GPIO27 Pull-up 1 GPIO28 Pull-up 1 GPIO7 Floating – MTMS Floating – MTDI Floating – To change the strapping bit values, users can apply external pull-down/pull-up resistors, or use host MCU GPIOs to control the voltage level of these pins when powering up ESP32-C5. After the reset is released, the strapping pins work as normal-function pins. 8.2.2 Chip Boot Mode Control GPIO26, GPIO27 and GPIO28 control the boot mode after the reset is released. See Table 8.2-2 Boot Mode Control. Table 8.2-2. Boot Mode Control Boot Mode GPIO26 GPIO27 GPIO28 SPI Boot 1 Any value Any value 1 1 Joint Download Boot 0 2 Any value 1 0 Joint Download Boot 1 3 0 0 0 1 Bold marks the default value and configuration. 2 Joint Download Boot 0 mode supports the following down- load methods: • USB-Serial-JTAG Download Boot • UART Download Boot 3 Joint Download Boot 1 mode supports the following down- load methods: • UART Download Boot • SDIO Download Boot In SPI Boot mode, the ROM bootloader loads and executes the program from SPI flash to boot the Espressif Systems 369 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 8 Chip Boot Control system. In Joint Download Boot 0 mode, users can download binary files into flash using UART0, USB, or SPI Slave interfaces. It is also possible to download binary files into SRAM and execute it from SRAM. In Joint Download Boot 1 mode, users can download binary files into flash using UART0 or SDIO interfaces. It is also possible to download binary files into SRAM and execute it from SRAM. Figure 8.2-1 Chip Boot Flow shows the detailed boot flow of the chip. Figure 8.2-1. Chip Boot Flow The following eFuse parameters control boot mode behaviors: • EFUSE_DIS_FORCE_DOWNLOAD – If this eFuse is 0 (default), software can force switch the chip from SPI Boot mode to Joint Download Boot mode by setting register LP_AON_FORCE_DOWNLOAD_BOOT and triggering a CPU reset. In this case, hardware overwrites GPIO_STRAPPING[4:3] from ”1x” to ”01”. Espressif Systems 370 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 8 Chip Boot Control – If this eFuse is 1, LP_AON_FORCE_DOWNLOAD_BOOT is disabled, and GPIO_STRAPPING can not be overwritten. • EFUSE_DIS_DOWNLOAD_MODE If this eFuse is 1, Joint Download Boot mode is disabled, and GPIO_STRAPPING will not be overwritten by LP_AON_FORCE_DOWNLOAD_BOOT. • EFUSE_ENABLE_SECURITY_DOWNLOAD If this eFuse is 1, Joint Download Boot mode only allows reading, writing, and erasing plaintext flash and does not support any SRAM or register operations. Ignore this eFuse if Joint Download Boot mode is disabled. • EFUSE_DIS_DIRECT_BOOT If this eFuse is 1, Direct Boot mode is disabled. USB Serial/JTAG Controller can also force switch the chip to Joint Download Boot mode from SPI Boot mode, and vice versa. For detailed information, please refer to Chapter 33 USB Serial/JTAG Controller. 8.2.3 SDIO Sampling and Driving Clock Edge Control The strapping pins GPIO25 and MTDI can be used to decide on which clock edge to sample signals and drive output lines. See Table 8.2-3 SDIO Input Sampling Edge/Output Driving Edge Control. Table 8.2-3. SDIO Input Sampling Edge/Output Driving Edge Control Edge behavior GPIO25 MTDI Falling edge sampling, falling edge output 0 0 Falling edge sampling, rising edge output 0 1 Rising edge sampling, falling edge output 1 0 Rising edge sampling, rising edge output 1 1 1 GPIO25 and MTDI are floating by default, so above are not default configurations. 8.2.4 ROM Messages Printing Control During the boot process, the messages by the ROM code can be printed to: • (Default) UART0 and USB Serial/JTAG controller • UART0 • USB Serial/JTAG controller To print ROM messages to UART0 or USB Serial/JTAG controller, see the description below. EFUSE_UART_PRINT_CONTROL and GPIO27 control printing ROM messages to UART0 as shown in Table 8.2-4 UART0 ROM Message Printing Control. Espressif Systems 371 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 8 Chip Boot Control Table 8.2-4. UART0 ROM Message Printing Control UART0 ROM Message Printing Register 2 eFuse 3 GPIO27 ROM messages are always printed to UART0 during boot 0 0 (0b00) x 4 Print is enabled during boot 1 (0b01) 0 Print is disabled during boot 1 Print is disabled during boot 2 (0b10) 0 Print is enabled during boot 1 Print is disabled during boot 3 (0b11) x Print is disabled during boot 1 x x 1 Bold marks the default value and configuration. 2 Register: LP_AON_STORE4_REG[0] 3 eFuse: EFUSE_UART_PRINT_CONTROL 4 x: x indicates that the value has no effect on the result and can be ignored. EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT controls the printing to USB Serial/JTAG controller as shown in Table 8.2-5 USB Serial/JTAG ROM Message Printing Control. Table 8.2-5. USB Serial/JTAG ROM Message Printing Control USB Serial/JTAG ROM Message Printing EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT Enabled 0 Disabled 1 Ignored 1 Bold marks the default value and configuration. 8.2.5 JTAG Signal Source Control The strapping pin GPIO7 can be used to control the JTAG signal source during the early boot process. This pin does not have internal pull-up or pull-down resistors, so its strapping value must be controlled by an external circuit that must not be in a high-impedance state. GPIO7 controls the source of JTAG signals together with EFUSE_DIS_PAD_JTAG, EFUSE_DIS_USB_JTAG and EFUSE_JTAG_SEL_ENABLE. See Table 8.2-6 JTAG Signal Source Control. Espressif Systems 372 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 8 Chip Boot Control Table 8.2-6. JTAG Signal Source Control JTAG Signal Source eFuse 1 2 eFuse 2 3 eFuse 3 4 GPIO7 USB Serial/JTAG Controller 6 0 0 0 x 5 1 1 JTAG pins MTDI, MTCK, MTMS, and MTDO 0 x x x 1 USB Serial/JTAG Controller 6 1 0 JTAG is disabled x 1 1 Bold marks the default value and configuration. 2 eFuse 1: EFUSE_DIS_PAD_JTAG 3 eFuse 2: EFUSE_DIS_USB_JTAG 4 eFuse 3: EFUSE_JTAG_SEL_ENABLE 5 x: x indicates that the value has no effect on the result and can be ignored. 6 In Joint Download Boot 1 mode, the USB Serial/JTAG controller is forcibly disabled, and the JTAG signal only comes from JTAG pins. If PAD_JTAG is also disabled, then JTAG is disabled. 8.2.6 Crystal Frequency Selection ESP32-C5 supports crystal frequencies of 40 MHz and 48 MHz. Chip Boot mode together with MTMS, EFUSE_XTAL_48M_SEL, and EFUSE_XTAL_48M_SEL_MODE collectively control the crystal frequency. Table 8.2-7. Crystal Frequency Selection Crystal Frequency Boot Mode eFuse 1 2 eFuse 2 3 MTMS 40 MHz SPI Boot x 4 Even number of 1s x 48 MHz Odd number of 1s 40 MHz Joint Download Boot 0/1 1 Even number of 1s 48 MHz Odd number of 1s 40 MHz 0 x 0 5 48 MHz 1 5 1 Bold marks the default value and configuration. 2 eFuse 1: EFUSE_XTAL_48M_SEL_MODE 3 eFuse 2: EFUSE_XTAL_48M_SEL 4 x: x indicates that the value has no effect on the result and can be ignored. 5 In Joint Download Boot 0/1 mode, users need to set the signal level on MTMS strapping pin. Espressif Systems 373 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 9 Interrupt Matrix Chapter 9 Interrupt Matrix 9.1 Overview The interrupt matrix embedded in ESP32-C5 routes one or multiple peripheral interrupt sources to any of the ESP-RISC-V CPU’s peripheral interrupts. The ESP32-C5 has 80 peripheral interrupt sources that can be routed to any of the 32 CPU peripheral interrupts using the interrupt matrix. Note: This chapter focuses on how to map peripheral interrupt sources to the CPU interrupts. For information about inter- rupt configuration, vector, and interrupt handling operations recommended by the ISA, please refer to Chapter 1 High- Performance CPU [to be added later] > Section 1.1 Interrupt Control [to be added later]. 9.2 Terminology The following terms related to interrupts are defined in the context of the ESP32-C5 Technical Reference Manual to help readers better understand this document: 9.2.1 Interrupt An interrupt refers to the event or condition that occurs, causing the CPU to temporarily suspend its current execution and handle a higher-priority task. It is a mechanism that allows the CPU to respond to specific events promptly. The ESP32-C5 Technical Reference Manual may use the term “interrupt” in a broader sense to refer to both interrupt signal and interrupt source. 9.2.2 Interrupt Signal/Interrupt Source Interrupt signal and interrupt source are only defined from different perspectives and mean the same thing. From the perspective of peripherals, interrupt signals are generated by the peripheral’s internal interrupt sources and are sent to the interrupt matrix. From the perspective of the interrupt matrix, it receives the interrupt signals sent from the peripheral and considers them interrupt sources. The interrupt matrix then outputs CPU peripheral interrupt signals to the CPU. From the perspective of the CPU, the interrupt signals from the interrupt matrix become sources and are sent to the CPU core together with the core local interrupt sources. Espressif Systems 374 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 9 Interrupt Matrix 9.2.3 Interrupt Flow in ESP32-C5 Figure 9.2-1 shows the interrupt flow in ESP32-C5. Figure 9.2-1. Interrupt Flow in ESP32-C5 9.3 Features The interrupt matrix embedded in the ESP32-C5 has the following features: • 80 peripheral interrupt sources accepted as input • 32 HP CPU peripheral interrupts generated to the HP CPU as output • Current interrupt status query of peripheral interrupt sources • Multiple interrupt sources mapping to a single HP CPU interrupt (i.e., shared interrupts) • Delegation of CPU User Mode interrupts to Machine Mode interrupts 9.4 Architecture Figure 9.4-1 shows the structure of the interrupt matrix. You need to configure the interrupt matrix registers to map the peripheral interrupt sources to the HP CPU interrupts. The Interrupt Matrix Controller in Figure 9.4-1 manages the mapping and sends the interrupt status of each interrupt source to the interrupt status registers which belong to the interrupt matrix registers. Figure 9.4-1. Interrupt Matrix Structure Espressif Systems 375 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 9 Interrupt Matrix 9.5 Functional Description 9.5.1 Peripheral Interrupt Sources The ESP32-C5 has 80 peripheral interrupt sources in total. Table 9.5-1 lists all these sources and their mapping registers, as well as the interrupt status registers. • Column “No.”: Peripheral interrupt source number, can be 0 79. • Column “Chapter”: in which chapter the interrupt source is described in detail. • Column “Interrupt Source”: Name of the peripheral interrupt source. • Column “Interrupt Source Mapping Register”: Registers used to configure the routing of the peripheral interrupt sources to the HP CPU peripheral interrupts. • Column “Interrupt Status Register”: Registers used to reflect the interrupt source status. – Column “Interrupt Status Register - Bit”: Bit position in status registers, indicating the interrupt status. – Column “Interrupt Status Register - Name”: Name of status registers. Espressif Systems 376 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 9 Interrupt Matrix Table 9.5-1. CPU Peripheral Interrupt Source Mapping/Status Registers and Peripheral Interrupt Sources Interrupt Status Register No. Chapter Interrupt Source Interrupt Source Mapping Register Bit Name 0 n/a reserved reserved 0 INTMTX_CORE0_INT_STATUS_0_REG 1 n/a reserved reserved 1 2 n/a reserved reserved 2 3 n/a reserved reserved 3 4 n/a reserved reserved 4 5 n/a reserved reserved 5 6 n/a reserved reserved 6 7 n/a reserved reserved 7 8 n/a reserved reserved 9 9 n/a reserved reserved 9 10 n/a reserved reserved 10 11 n/a reserved reserved 11 12 n/a reserved reserved 12 13 Low-power Management [to be added later] PMU_INTR INTMTX_CORE0_PMU_INTR_MAP_REG 13 14 eFuse Controller (eFuse) EFUSE_INTR INTMTX_CORE0_EFUSE_INTR_MAP_REG 14 15 Low-power Management [to be added later] LP_RTC_TIMER_INTR INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG 15 16 UART Controller (UART) LP_UART_INTR INTMTX_CORE0_LP_UART_INTR_MAP_REG 16 17 I2C Controller (I2C) LP_I2C_INTR INTMTX_CORE0_LP_I2C_INTR_MAP_REG 17 18 Low-power Management [to be added later] LP_WDT_INTR INTMTX_CORE0_LP_WDT_INTR_MAP_REG 18 19 System Registers LP_PERI_TIMEOUT_INTR INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG 19 20 Permission Control (PMS) LP_APM_M0_INTR INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG 20 21 Permission Control (PMS) LP_APM_M1_INTR INTMTX_CORE0_LP_APM_M1_INTR_MAP_REG 21 22 n/a reserved reserved 22 23 Software Interrupt Registers CPU_INTR_FROM_CPU_0 INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG 23 24 Software Interrupt Registers CPU_INTR_FROM_CPU_1 INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG 24 25 Software Interrupt Registers CPU_INTR_FROM_CPU_2 INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG 25 26 High-Performance CPU [to be added later] CPU_INTR_FROM_CPU_3 INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG 26 27 Debug Assistant BUS_MONITOR_INTR INTMTX_CORE0_BUS_MONITOR_INTR_MAP_REG 27 28 High-Performance CPU [to be added later] TRACE_INTR INTMTX_CORE0_TRACE_INTR_MAP_REG 28 29 n/a reserved reserved 29 30 System Registers CPU_PERI_TIMEOUT_INTR INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG 30 31 GPIO Matrix and IO MUX GPIO_INTR_PRO INTMTX_CORE0_GPIO_INTR_PRO_MAP_REG 31 32 GPIO Matrix and IO MUX GPIO_INTR_EXT INTMTX_CORE0_GPIO_INTR_EXT_MAP_REG 0 INTMTX_CORE0_INT_STATUS_1_REG Espressif Systems 377 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 9 Interrupt Matrix Interrupt Status Register No. Chapter Interrupt Source Interrupt Source Mapping Register Bit Name 33 Low-power Management [to be added later] PAU_INTR INTMTX_CORE0_PAU_INTR_MAP_REG 1 34 System Registers HP_PERI_TIMEOUT_INTR INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG 2 35 n/a reserved reserved 3 36 Permission Control (PMS) HP_APM_M0_INTR INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG 4 37 Permission Control (PMS) HP_APM_M1_INTR INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG 5 38 Permission Control (PMS) HP_APM_M2_INTR INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG 6 39 Permission Control (PMS) HP_APM_M3_INTR INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG 7 40 Permission Control (PMS) HP_APM_M4_INTR INTMTX_CORE0_HP_APM_M4_INTR_MAP_REG 8 41 Permission Control (PMS) LP_APM0_INTR INTMTX_CORE0_LP_APM0_INTR_MAP_REG 9 42 Permission Control (PMS) CPU_APM_M0_INTR INTMTX_CORE0_CPU_APM_M0_INTR_MAP_REG 10 43 Permission Control (PMS) CPU_APM_M1_INTR INTMTX_CORE0_CPU_APM_M1_INTR_MAP_REG 11 44 Permission Control (PMS) MSPI_INTR INTMTX_CORE0_MSPI_INTR_MAP_REG 12 45 I2S Controller (I2S) I2S_INTR INTMTX_CORE0_I2S_INTR_MAP_REG 13 46 UART Controller (UART) UHCI0_INTR INTMTX_CORE0_UHCI0_INTR_MAP_REG 14 47 UART Controller (UART) UART0_INTR INTMTX_CORE0_UART0_INTR_MAP_REG 15 48 UART Controller (UART) UART1_INTR INTMTX_CORE0_UART1_INTR_MAP_REG 16 49 LED PWM Controller (LEDC) LEDC_INTR INTMTX_CORE0_LEDC_INTR_MAP_REG 17 50 Controller Area Network Flexible Data-Rate [to be added later] TWAI0_TIMER_INTR INTMTX_CORE0_TWAI0_TIMER_INTR_MAP_REG 18 51 Controller Area Network Flexible Data-Rate [to be added later] TWAI0_INTR INTMTX_CORE0_TWAI0_INTR_MAP_REG 19 52 Controller Area Network Flexible Data-Rate [to be added later] TWAI1_TIMER_INTR INTMTX_CORE0_TWAI1_TIMER_INTR_MAP_REG 20 53 Controller Area Network Flexible Data-Rate [to be added later] TWAI1_INTR INTMTX_CORE0_TWAI1_INTR_MAP_REG 21 54 USB Serial/JTAG Controller USB_SERIAL_JTAG_INTR INTMTX_CORE0_USB_INTR_MAP_REG 22 55 Remote Control Peripheral (RMT) RMT_INTR INTMTX_CORE0_RMT_INTR_MAP_REG 23 56 I2C Controller (I2C) I2C_EXT0_INTR INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG 24 57 Timer Group (TIMG) TG0_T0_INTR INTMTX_CORE0_TG0_T0_INTR_MAP_REG 25 58 Timer Group (TIMG) TG0_WDT_INTR INTMTX_CORE0_TG0_WDT_INTR_MAP_REG 26 59 Timer Group (TIMG) TG1_T0_INTR INTMTX_CORE0_TG1_T0_INTR_MAP_REG 27 60 Timer Group (TIMG) TG1_WDT_INTR INTMTX_CORE0_TG1_WDT_INTR_MAP_REG 28 61 System Timer SYSTIMER_TARGET0_INTR INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG 29 62 System Timer SYSTIMER_TARGET1_INTR INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG 30 63 System Timer SYSTIMER_TARGET2_INTR INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG 31 64 ADC Controller APB_ADC_INTR INTMTX_CORE0_APB_ADC_INTR_MAP_REG 0 INTMTX_CORE0_INT_STATUS_2_REG 65 Motor Control PWM (MCPWM) PWM_INTR INTMTX_CORE0_PWM_INTR_MAP_REG 1 66 Pulse Count Controller (PCNT) PCNT_INTR INTMTX_CORE0_PCNT_INTR_MAP_REG 2 Espressif Systems 378 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 9 Interrupt Matrix Interrupt Status Register No. Chapter Interrupt Source Interrupt Source Mapping Register Bit Name 67 Parallel IO Controller (PARLIO) PARL_IO_TX_INTR INTMTX_CORE0_PARL_IO_TX_INTR_MAP_REG 3 68 Parallel IO Controller (PARLIO) PARL_IO_RX_INTR INTMTX_CORE0_PARL_IO_RX_INTR_MAP_REG 4 69 SDIO Slave Controller (SDIO) SLC0_INTR INTMTX_CORE0_SLC0_INTR_MAP_REG 5 70 SDIO Slave Controller (SDIO) SLC1_INTR INTMTX_CORE0_SLC1_INTR_MAP_REG 6 71 GDMA Controller (GDMA) GDMA_IN_CH0_INTR INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG 7 72 GDMA Controller (GDMA) GDMA_IN_CH1_INTR INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG 8 73 GDMA Controller (GDMA) GDMA_IN_CH2_INTR INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG 9 74 GDMA Controller (GDMA) GDMA_OUT_CH0_INTR INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG 10 75 GDMA Controller (GDMA) GDMA_OUT_CH1_INTR INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG 11 76 GDMA Controller (GDMA) GDMA_OUT_CH2_INTR INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG 12 77 SPI Controller (SPI) GPSPI2_INTR INTMTX_CORE0_GPSPI2_INTR_MAP_REG 13 78 AES Accelerator (AES) AES_INTR INTMTX_CORE0_AES_INTR_MAP_REG 14 79 SHA Accelerator (SHA) SHA_INTR INTMTX_CORE0_SHA_INTR_MAP_REG 15 80 RSA Accelerator (RSA) RSA_INTR INTMTX_CORE0_RSA_INTR_MAP_REG 16 81 ECC Accelerator (ECC) ECC_INTR INTMTX_CORE0_ECC_INTR_MAP_REG 17 82 Elliptic Curve Digital Signature Algorithm (ECDSA) ECDSA_INTR INTMTX_CORE0_ECDSA_INTR_MAP_REG 18 83 n/a reserved reserved 19 Espressif Systems 379 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 9 Interrupt Matrix 9.5.2 HP CPU Interrupts The HP CPU of the ESP32-C5 implements its interrupt mechanism using standard RISC-V (v0.9) Core-Local Interrupt Controller (CLIC) interrupt. The HP CPU supports 2 core local interrupts (CLINT) and 32 peripheral interrupts, which are numbered from 16 to 47. The peripheral interrupt sources are mapped to the 32 HP CPU peripheral interrupts through the interrupt matrix. Each HP CPU peripheral interrupt has the following properties: • Priority levels from 1 (lowest) to 15 (highest). • Configurable as level-triggered or edge-triggered. • Lower-priority interrupts maskable by setting interrupt threshold. Note: For detailed information about the functions and configuration procedures of CPU interrupts, see Chapter 1 High-Performance CPU [to be added later] > Section 1.1Interrupt Control [to be added later]. The configuration registers of CPU interrupts are listed in Section 9.6.2 Software Interrupt Register Summary. 9.5.3 Assign Peripheral Interrupt Source to HP CPU Peripheral Interrupt In this section, the following terms are used to describe the operation of the interrupt matrix. • SOURCE: stands for a peripheral interrupt source in Table 9.5-1. • INTMTX_CORE0_SOURCE_INTR_MAP_REG: stands for the interrupt source mapping register for a SOURCE. • Num_P: stands for the index of HP CPU interrupts which can be 16 47. • Interrupt_P: stands for the HP CPU interrupt numbered as Num_P. 9.5.3.1 Assign One Peripheral Interrupt Source to HP CPU Peripheral Interrupt Setting the corresponding source mapping register INTMTX_CORE0_SOURCE_INTR_MAP_REG of SOURCE to Num_P assigns this interrupt source to Interrupt_P. 9.5.3.2 Assign Multiple Peripheral Interrupt Sources to HP CPU Peripheral Interrupt Setting the corresponding source mapping register INTMTX_CORE0_SOURCE_INTR_MAP_REG of each SOURCE to the same Num_P assigns multiple sources to the same Interrupt_P. Any of these sources can trigger CPU Interrupt_P. When an interrupt signal is generated, the CPU should check the interrupt status registers to figure out which peripheral generated the interrupt. For more information, see Chapter 1 High-Performance CPU [to be added later] > Section 1.1Interrupt Control [to be added later]. 9.5.3.3 Unassign SOURCE Writing 0 to the INTMTX_CORE0_SOURCE_INTR_MAP_REG register disables the corresponding interrupt source. Espressif Systems 380 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 9 Interrupt Matrix 9.5.4 Delegated Interrupts The ESP32-C5 RISC-V CPU supports Machine Mode and User Mode. The 32 external HP CPU interrupts can be configured as either Machine Mode interrupts or User Mode interrupts. When the HP CPU is in Machine Mode, it only responds to Machine Mode interrupts and does not respond to User Mode interrupts. When the HP CPU is in User Mode, it can respond to all interrupts. Under normal conditions, User Mode interrupts are only handled when the CPU is operating in User Mode. However, with the interrupt delegation feature, Machine Mode can be configured to handle certain User Mode interrupts, while the CPU itself remains in Machine Mode. This is achieved by configuring registers to delegate User Mode interrupts to Machine Mode interrupts. • Each interrupt source of the interrupt matrix can independently enable or disable the interrupt delegation feature. • Multiple interrupt sources from the interrupt matrix can enable the interrupt delegation feature at the same time. • Delegation is allowed to only one interrupt signal from the interrupt matrix. Software can configure the INTMTX_CORE0_INT_SIG_IDX_ASSERT_IN_SEC_REG register to n to delegate a User Mode interrupt to a Machine Mode interrupt with interrupt number n. To enable the delegated interrupt function for interrupt source SOURCE in the interrupt matrix, software can set the corresponding bit in the INTMTX_CORE0_SOURCE_INTR_PASS_IN_SEC_REG register to 1. 9.5.5 Query Current Interrupt Status of SOURCE After enabling a SOURCE, you can query its current interrupt status by reading the corresponding bit value in INTMTX_CORE0_INT_STATUS_n_REG (read only). For the mapping between INTMTX_CORE0_INT_STATUS_n_REG and the SOURCE, please refer to Table 9.5-1. Espressif Systems 381 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 9 Interrupt Matrix 9.6 Register Summary 9.6.1 Interrupt Matrix Register Summary The addresses in this section are relative to the interrupt matrix base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Configuration Registers INTMTX_CORE0_PMU_INTR_MAP_REG PMU_INTR mapping register 0x034 R/W INTMTX_CORE0_EFUSE_INTR_MAP_REG EFUSE_INTR mapping register 0x038 R/W INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG LP_RTC_TIMER_INTR mapping register 0x03C R/W INTMTX_CORE0_LP_UART_INTR_MAP_REG LP_UART_INTR mapping register 0x040 R/W INTMTX_CORE0_LP_I2C_INTR_MAP_REG LP_I2C_INTR mapping register 0x044 R/W INTMTX_CORE0_LP_WDT_INTR_MAP_REG LP_WDT_INTR mapping register 0x048 R/W INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG LP_PERI_TIMEOUT_INTR mapping register 0x04C R/W INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG LP_APM_M0_INTR mapping register 0x050 R/W INTMTX_CORE0_LP_APM_M1_INTR_MAP_REG LP_APM_M1_INTR mapping register 0x054 R/W INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG CPU_INTR_FROM_CPU_0 mapping register 0x05C R/W INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG CPU_INTR_FROM_CPU_1 mapping register 0x060 R/W INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG CPU_INTR_FROM_CPU_2 mapping register 0x064 R/W INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG CPU_INTR_FROM_CPU_3 mapping register 0x068 R/W INTMTX_CORE0_BUS_MONITOR_INTR_MAP_REG BUS_MONITOR_INTR mapping register 0x06C R/W INTMTX_CORE0_TRACE_INTR_MAP_REG TRACE_INTR mapping register 0x070 R/W INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG CPU_PERI_TIMEOUT_INTR mapping register 0x078 R/W INTMTX_CORE0_GPIO_INTR_PRO_MAP_REG GPIO_INTR_PRO mapping register 0x07C R/W INTMTX_CORE0_GPIO_INTR_EXT_MAP_REG GPIO_INTR_EXT mapping register 0x080 R/W INTMTX_CORE0_PAU_INTR_MAP_REG PAU_INTR mapping register 0x084 R/W INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG HP_PERI_TIMEOUT_INTR mapping register 0x088 R/W INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG HP_APM_M0_INTR mapping register 0x090 R/W Espressif Systems 382 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 9 Interrupt Matrix Name Description Address Access INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG HP_APM_M1_INTR mapping register 0x094 R/W INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG HP_APM_M2_INTR mapping register 0x098 R/W INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG HP_APM_M3_INTR mapping register 0x09C R/W INTMTX_CORE0_HP_APM_M4_INTR_MAP_REG HP_APM_M4_INTR mapping register 0x0A0 R/W INTMTX_CORE0_LP_APM0_INTR_MAP_REG LP_APM0_INTR mapping register 0x0A4 R/W INTMTX_CORE0_CPU_APM_M0_INTR_MAP_REG CPU_APM_M0_INTR mapping register 0x0A8 R/W INTMTX_CORE0_CPU_APM_M1_INTR_MAP_REG CPU_APM_M1_INTR mapping register 0x0AC R/W INTMTX_CORE0_MSPI_INTR_MAP_REG MSPI_INTR mapping register 0x0B0 R/W INTMTX_CORE0_I2S_INTR_MAP_REG I2S_INTR mapping register 0x0B4 R/W INTMTX_CORE0_UHCI0_INTR_MAP_REG UHCI0_INTR mapping register 0x0B8 R/W INTMTX_CORE0_UART0_INTR_MAP_REG UART0_INTR mapping register 0x0BC R/W INTMTX_CORE0_UART1_INTR_MAP_REG UART1_INTR mapping register 0x0C0 R/W INTMTX_CORE0_LEDC_INTR_MAP_REG LEDC_INTR mapping register 0x0C4 R/W INTMTX_CORE0_TWAI0_INTR_MAP_REG TWAI0_INTR mapping register 0x0C8 R/W INTMTX_CORE0_TWAI0_TIMER_INTR_MAP_REG TWAI0_TIMER_INTR mapping register 0x0CC R/W INTMTX_CORE0_TWAI1_INTR_MAP_REG TWAI1_INTR mapping register 0x0D0 R/W INTMTX_CORE0_TWAI1_TIMER_INTR_MAP_REG TWAI1_TIMER_INTR mapping register 0x0D4 R/W INTMTX_CORE0_USB_SERIAL_JTAG_INTR_MAP_REG USB_SERIAL_JTAG_INTR mapping register 0x0D8 R/W INTMTX_CORE0_RMT_INTR_MAP_REG RMT_INTR mapping register 0x0DC R/W INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG I2C_EXT0_INTR mapping register 0x0E0 R/W INTMTX_CORE0_TG0_T0_INTR_MAP_REG TG0_T0_INTR mapping register 0x0E4 R/W INTMTX_CORE0_TG0_WDT_INTR_MAP_REG TG0_WDT_INTR mapping register 0x0E8 R/W INTMTX_CORE0_TG1_T0_INTR_MAP_REG TG1_T0_INTR mapping register 0x0EC R/W INTMTX_CORE0_TG1_WDT_INTR_MAP_REG TG1_WDT_INTR mapping register 0x0F0 R/W INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG SYSTIMER_TARGET0_INTR mapping register 0x0F4 R/W INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG SYSTIMER_TARGET1_INTR mapping register 0x0F8 R/W INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG SYSTIMER_TARGET2_INTR mapping register 0x0FC R/W INTMTX_CORE0_APB_ADC_INTR_MAP_REG APB_ADC_INTR mapping register 0x100 R/W INTMTX_CORE0_PWM_INTR_MAP_REG PWM_INTR mapping register 0x104 R/W Espressif Systems 383 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 9 Interrupt Matrix Name Description Address Access INTMTX_CORE0_PCNT_INTR_MAP_REG PCNT_INTR mapping register 0x108 R/W INTMTX_CORE0_PARL_IO_TX_INTR_MAP_REG PARL_IO_TX_INTR mapping register 0x10C R/W INTMTX_CORE0_PARL_IO_RX_INTR_MAP_REG PARL_IO_RX_INTR mapping register 0x110 R/W INTMTX_CORE0_SLC0_INTR_MAP_REG SLC0_INTR mapping register 0x114 R/W INTMTX_CORE0_SLC1_INTR_MAP_REG SLC1_INTR mapping register 0x118 R/W INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG DMA_IN_CH0_INTR mapping register 0x11C R/W INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG DMA_IN_CH1_INTR mapping register 0x120 R/W INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG DMA_IN_CH2_INTR mapping register 0x124 R/W INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG DMA_OUT_CH0_INTR mapping register 0x128 R/W INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG DMA_OUT_CH1_INTR mapping register 0x12C R/W INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG DMA_OUT_CH2_INTR mapping register 0x130 R/W INTMTX_CORE0_GPSPI2_INTR_MAP_REG GPSPI2_INTR mapping register 0x134 R/W INTMTX_CORE0_AES_INTR_MAP_REG AES_INTR mapping register 0x138 R/W INTMTX_CORE0_SHA_INTR_MAP_REG SHA_INTR mapping register 0x13C R/W INTMTX_CORE0_RSA_INTR_MAP_REG RSA_INTR mapping register 0x140 R/W INTMTX_CORE0_ECC_INTR_MAP_REG ECC_INTR mapping register 0x144 R/W INTMTX_CORE0_ECDSA_INTR_MAP_REG ECDSA_INTR mapping register 0x148 R/W INTMTX_CORE0_INT_STATUS_0_REG Status register for INTMTX sources 0 31 0x0150 RO INTMTX_CORE0_INT_STATUS_1_REG Status register for INTMTX sources 32 63 0x0154 RO INTMTX_CORE0_INT_STATUS_2_REG Status register for INTMTX sources 64 83 0x0158 RO INTMTX_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0_REG Delegation Status Register for INTMTX sources 0 31 0x015C RO INTMTX_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1_REG Delegation Status Register for INTMTX sources 32 63 0x0160 RO INTMTX_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2_REG Delegation Status Register for INTMTX sources 64 83 0x0164 RO INTMTX_CORE0_INT_SIG_IDX_ASSERT_IN_SEC_REG Configuration register for interrupt delegation 0x0168 R/W INTMTX_CORE0_SECURE_STATUS_REG Status register for interrupt delegation 0x016C RO INTMTX_CORE0_CLOCK_GATE_REG INTMTX clock gating configure register 0x0170 R/W Version Register INTMTX_CORE0_INTMTX_DATE_REG Version control register 0x07FC R/W Espressif Systems 384 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 9 Interrupt Matrix 9.6.2 Software Interrupt Register Summary The addresses in this section are relative to the software interrupt base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Interrupt Registers INTPRI_CPU_INTR_FROM_CPU_0_REG CPU_INTR_FROM_CPU_0 mapping register 0x0090 R/W INTPRI_CPU_INTR_FROM_CPU_1_REG CPU_INTR_FROM_CPU_1 mapping register 0x0094 R/W INTPRI_CPU_INTR_FROM_CPU_2_REG CPU_INTR_FROM_CPU_2 mapping register 0x0098 R/W INTPRI_CPU_INTR_FROM_CPU_3_REG CPU_INTR_FROM_CPU_3 mapping register 0x009C R/W Version Registers INTPRI_DATE_REG Version control register 0x00A0 R/W Espressif Systems 385 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 9 Interrupt Matrix 9.7 Registers 9.7.1 Interrupt Matrix Registers The addresses in this section are relative to the interrupt matrix base address provided in Table 4.3-2 in Chapter 4 System and Memory. Register 9.1. INTMTX_CORE0_PMU_INTR_MAP_REG (0x034) Register 9.2. INTMTX_CORE0_EFUSE_INTR_MAP_REG (0x038) Register 9.3. INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG (0x03C) Register 9.4. INTMTX_CORE0_LP_UART_INTR_MAP_REG (0x040) Register 9.5. INTMTX_CORE0_LP_I2C_INTR_MAP_REG (0x044) Register 9.6. INTMTX_CORE0_LP_WDT_INTR_MAP_REG (0x048) Register 9.7. INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG (0x04C) Register 9.8. INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG (0x050) Register 9.9. INTMTX_CORE0_LP_APM_M1_INTR_MAP_REG (0x054) Register 9.10. INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (0x05C) Register 9.11. INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (0x060) Register 9.12. INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (0x064) Register 9.13. INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (0x068) Register 9.14. INTMTX_CORE0_BUS_MONITOR_INTR_MAP_REG (0x06C) Register 9.15. INTMTX_CORE0_TRACE_INTR_MAP_REG (0x070) Register 9.16. INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG (0x078) Register 9.17. INTMTX_CORE0_GPIO_INTR_PRO_MAP_REG (0x07C) Register 9.18. INTMTX_CORE0_GPIO_INTR_EXT_MAP_REG (0x080) Register 9.19. INTMTX_CORE0_PAU_INTR_MAP_REG (0x084) Register 9.20. INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (0x088) Register 9.21. INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG (0x090) Register 9.22. INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG (0x094) Register 9.23. INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG (0x098) Register 9.24. INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG (0x09C) Register 9.25. INTMTX_CORE0_HP_APM_M4_INTR_MAP_REG (0x0A0) Register 9.26. INTMTX_CORE0_LP_APM0_INTR_MAP_REG (0x0A4) Register 9.27. INTMTX_CORE0_CPU_APM_M0_INTR_MAP_REG (0x0A8) Register 9.28. INTMTX_CORE0_CPU_APM_M1_INTR_MAP_REG (0x0AC) Register 9.29. INTMTX_CORE0_MSPI_INTR_MAP_REG (0x0B0) Register 9.30. INTMTX_CORE0_I2S_INTR_MAP_REG (0x0B4) Espressif Systems 386 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 9 Interrupt Matrix Register 9.31. INTMTX_CORE0_UHCI0_INTR_MAP_REG (0x0B8) Register 9.32. INTMTX_CORE0_UART0_INTR_MAP_REG (0x0BC) Register 9.33. INTMTX_CORE0_UART1_INTR_MAP_REG (0x0C0) Register 9.34. INTMTX_CORE0_LEDC_INTR_MAP_REG (0x0C4) Register 9.35. INTMTX_CORE0_TWAI0_INTR_MAP_REG (0x0C8) Register 9.36. INTMTX_CORE0_TWAI0_TIMER_INTR_MAP_REG (0x0CC) Register 9.37. INTMTX_CORE0_TWAI1_INTR_MAP_REG (0x0D0) Register 9.38. INTMTX_CORE0_TWAI1_TIMER_INTR_MAP_REG (0x0D4) Register 9.39. INTMTX_CORE0_USB_SERIAL_JTAG_INTR_MAP_REG (0x0D8) Register 9.40. INTMTX_CORE0_RMT_INTR_MAP_REG (0x0DC) Register 9.41. INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG (0x0E0) Register 9.42. INTMTX_CORE0_TG0_T0_INTR_MAP_REG (0x0E4) Register 9.43. INTMTX_CORE0_TG0_WDT_INTR_MAP_REG (0x0E8) Register 9.44. INTMTX_CORE0_TG1_T0_INTR_MAP_REG (0x0EC) Register 9.45. INTMTX_CORE0_TG1_WDT_INTR_MAP_REG (0x0F0) Register 9.46. INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (0x0F4) Register 9.47. INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (0x0F8) Register 9.48. INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (0x0FC) Register 9.49. INTMTX_CORE0_APB_ADC_INTR_MAP_REG (0x100) Register 9.50. INTMTX_CORE0_PWM_INTR_MAP_REG (0x104) Register 9.51. INTMTX_CORE0_PCNT_INTR_MAP_REG (0x108) Register 9.52. INTMTX_CORE0_PARL_IO_TX_INTR_MAP_REG (0x10C) Register 9.53. INTMTX_CORE0_PARL_IO_RX_INTR_MAP_REG (0x110) Register 9.54. INTMTX_CORE0_SLC0_INTR_MAP_REG (0x114) Register 9.55. INTMTX_CORE0_SLC1_INTR_MAP_REG (0x118) Register 9.56. INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG (0x11C) Register 9.57. INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG (0x120) Register 9.58. INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG (0x124) Register 9.59. INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG (0x128) Register 9.60. INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG (0x12C) Register 9.61. INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG (0x130) Register 9.62. INTMTX_CORE0_GPSPI2_INTR_MAP_REG (0x134) Register 9.63. INTMTX_CORE0_AES_INTR_MAP_REG (0x138) Register 9.64. INTMTX_CORE0_SHA_INTR_MAP_REG (0x13C) Register 9.65. INTMTX_CORE0_RSA_INTR_MAP_REG (0x140) Espressif Systems 387 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 9 Interrupt Matrix Register 9.66. INTMTX_CORE0_ECC_INTR_MAP_REG (0x144) Register 9.67. INTMTX_CORE0_ECDSA_INTR_MAP_REG (0x148) Register 9.68. INTMTX_CORE0_SOURCE_INTR_MAP_REG (0x0000 - 0x0100) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 9 (INTMTX_CORE0_SOURCE_INTR_PASS_IN_SEC_REG) 0 8 (reserved) 0 0 7 6 INTMTX_CORE0_SOURCE_INTR_MAP_REG 0 5 0 Reset INTMTX_CORE0_SOURCE_INTR_MAP Map the INTMTX source (SOURCE) into one CPU INTMTX. For the information of SOURCE, see Table 9.5-1. (R/W) INTMTX_CORE0_SOURCE_INTR_PASS_IN_SEC Delegate the interrupt signal of the INTMTX source (SOURCE) to a CPU Machine Mode interrupt.(R/W) Register 9.69. INTMTX_CORE0_INT_STATUS_0_REG (0x0150) INTMTX_CORE0_INT_STATUS_0 0x000000 31 0 Reset INTMTX_CORE0_INT_STATUS_0 Represents the status of the INTMTX sources numbered from 0 31. Each bit corresponds to one INTMTX source. 0: No interrupt triggered from the corresponding INTMTX source 1: The corresponding INTMTX source triggered an interrupt (RO) Espressif Systems 388 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 9 Interrupt Matrix Register 9.70. INTMTX_CORE0_INT_STATUS_1_REG (0x0154) INTMTX_CORE0_INT_STATUS_1 0x000000 31 0 Reset INTMTX_CORE0_INT_STATUS_1 Represents the status of the INTMTX sources numbered from 32 63. Each bit corresponds to one INTMTX source. 0: No interrupt triggered from the corresponding INTMTX source 1: The corresponding INTMTX source triggered an interrupt (RO) Register 9.71. INTMTX_CORE0_INT_STATUS_2_REG (0x0158) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 31 20 INTMTX_CORE0_INT_STATUS_2 0x000000 19 0 Reset INTMTX_CORE0_INT_STATUS_2 Represents the status of the INTMTX sources numbered from 64 95. Each bit corresponds to one INTMTX source. 0: No interrupt triggered from the corresponding INTMTX source 1: The corresponding INTMTX source triggered an interrupt (RO) Espressif Systems 389 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 9 Interrupt Matrix Register 9.72. INTMTX_CORE0_SRC_PASS_IN_SEC_STATUS_0_REG (0x015C) INTMTX_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0 0x000000 31 0 Reset INTMTX_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0 Represents whether the INTMTX sources numbered from 0 31 are configured for delegated interrupts. Each bit represents the configuration status of one INTMTX source. 0: The corresponding INTMTX source is not configured for delegation. 1: The corresponding INTMTX source is configured for delegation. (RO) Register 9.73. INTMTX_CORE0_SRC_PASS_IN_SEC_STATUS_1_REG (0x0160) INTMTX_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1 0x000000 31 0 Reset INTMTX_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1 Represents whether the INTMTX sources numbered from 31 63 are configured for delegated interrupts. Each bit represents the configuration status of one INTMTX source. 0: The corresponding INTMTX source is not configured for delegation. 1: The corresponding INTMTX source is configured for delegation. (RO) Espressif Systems 390 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 9 Interrupt Matrix Register 9.74. INTMTX_CORE0_SRC_PASS_IN_SEC_STATUS_2_REG (0x0164) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 31 20 INTMTX_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2 0x000 19 0 Reset INTMTX_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2 Represents whether the INTMTX sources numbered from 64 83 are configured for delegated interrupts. Each bit represents the configuration status of one INTMTX source. 0: The corresponding INTMTX source is not configured for delegation. 1: The corresponding INTMTX source is configured for delegation. (RO) Register 9.75. INTMTX_CORE0_INT_SIG_IDX_ASSERT_IN_SEC_REG (0x0168) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 6 IINTMTX_CORE0_INT_SIG_IDX_ASSERT_IN_SEC 0x0 5 0 Reset INTMTX_CORE0_INT_SIG_IDX_ASSERT_IN_SEC Configure which CPU Machine Mode INTMTX source the interrupt should be delegated to. (R/W) Espressif Systems 391 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 9 Interrupt Matrix Register 9.76. INTMTX_CORE0_SECURE_STATUS_REG (0x016C) INTMTX_CORE0_INT_SECURE_STATUS 0x000000 31 0 Reset INTMTX_CORE0_INT_SECURE_STATUS Represents which CPU User Mode interrupt the dele- gated Machine Mode interrupt was originally mapped to. (RO) Register 9.77. INTMTX_CORE0_CLOCK_GATE_REG (0x0170) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 INTMTX_CORE0_REG_CLK_EN 0 0 Reset INTMTX_CORE0_REG_CLK_EN INTMTX clock gating configure register. (R/W) Register 9.78. INTMTX_CORE0_INTMTX_DATE_REG (0x07FC) (reserved) 0 0 0 0 31 28 INTMTX_CORE0_INTMTX_DATE 0x241024A 27 0 Reset INTMTX_CORE0_INTMTX_DATE Version control register. (R/W) 9.7.2 Software Interrupt Registers The addresses in this section are relative to the software interrupt base address provided in Table 4.3-2 in Chapter 4 System and Memory. Espressif Systems 392 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 9 Interrupt Matrix Register 9.79. INTPRI_CPU_INTR_FROM_CPU_n_REG (n: 0-3) (0x0090+0x4*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 INTPRI_CPU_INTR_FROM_CPU_0 0 0 Reset INTPRI_CPU_INTR_FROM_CPU_n CPU_INTR_FROM_CPU_n mapping register. Configures whether to generate interrupts by configuring the register through software. 0: Stop generating interrupts 1: Generate interrupts (R/W) Register 9.80. INTPRI_DATE_REG (0x00A0) (reserved) 0 0 0 0 31 28 INTPRI_DATE 0x2303150 27 0 Reset INTPRI_DATE Version control register. (R/W) Espressif Systems 393 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Chapter 10 Event Task Matrix (ETM) 10.1 Overview The Event Task Matrix (ETM) peripheral contains 50 configurable channels. Each channel can map an event of any specified peripheral to a task of any specified peripheral. In this way, peripherals can be triggered to execute specified tasks without CPU intervention. 10.2 Features The Event Task Matrix has the following features: • Receive various events from multiple peripherals • Generate various tasks for multiple peripherals • 50 independently configurable ETM channels • An ETM channel can be set up to receive any event, and map it to any task • Each ETM channel can be enabled or disabled independently. If disabled, the channel will not respond to the configured event and generate the task mapped to that event • Support for checking event and task status • Peripherals supporting ETM include GPIO, LED PWM, general-purpose timers, RTC Timer, system timer, MCPWM, temperature sensor, ADC, I2S, LP CPU, GDMA, and PMU Note that the 50 ETM channels are identical regarding their features and operations. Thus, in the following sections, ETM channels are collectively referred to as channeln (where n ranges from 0 to 49). 10.3 Functional Description 10.3.1 Architecture The Event Task Matrix has 50 independent channels. Each channel can select any event as input, and map the event to any task as output (see Section 10.3.2 and Section 10.3.3 respectively). Each channel has an individual enable bit (see Section 10.3.6). Espressif Systems 394 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) ETM channel Channel n Events Tasks MUX DEMUX SOC_ETM_CHn_EVT_ID SOC_ETM_CHn_TASK_ID SOC_ETM_CH_ENABLEn SOC_ETM_CH_DISABLEn SOC_ETM_CH_ENABLEDn Figure 10.3-1. ETM Channeln Architecture Figure 10.3-1 illustrates the structure of an ETM channel. The SOC_ETM_CHn_EVT_ID field configures the MUX (multiplexer) to select one of the events as the input of channeln. The SOC_ETM_CHn_TASK_ID field configures the DEMUX (demultiplexer) to map the event selected by channeln to one of the tasks. SOC_ETM_CH_ENABLEn and SOC_ETM_CH_DISABLEn are used to enable or disable channeln. SOC_ETM_CH_ENABLEDn is used to indicate the status of the channeln. 10.3.2 Events An ETM channel can be set up to select one event to receive by configuring the SOC_ETM_CHn_EVT_ID field. Table 10.3-1 shows the configuration values of SOC_ETM_CHn_EVT_ID and their corresponding events. Table 10.3-1. Selectable Events for ETM Channeln SOC_ETM_CHn_EVT_ID Selected Event Peripheral Generating This Event 1 GPIO_EVT_CH0_RISE_EDGE GPIO 2 GPIO_EVT_CH1_RISE_EDGE 3 GPIO_EVT_CH2_RISE_EDGE 4 GPIO_EVT_CH3_RISE_EDGE 5 GPIO_EVT_CH4_RISE_EDGE 6 GPIO_EVT_CH5_RISE_EDGE 7 GPIO_EVT_CH6_RISE_EDGE 8 GPIO_EVT_CH7_RISE_EDGE 9 GPIO_EVT_CH0_FALL_EDGE 10 GPIO_EVT_CH1_FALL_EDGE 11 GPIO_EVT_CH2_FALL_EDGE Espressif Systems 395 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) SOC_ETM_CHn_EVT_ID Selected Event Peripheral Generating This Event 12 GPIO_EVT_CH3_FALL_EDGE 13 GPIO_EVT_CH4_FALL_EDGE 14 GPIO_EVT_CH5_FALL_EDGE 15 GPIO_EVT_CH6_FALL_EDGE 16 GPIO_EVT_CH7_FALL_EDGE 17 GPIO_EVT_CH0_ANY_EDGE 18 GPIO_EVT_CH1_ANY_EDGE 19 GPIO_EVT_CH2_ANY_EDGE 20 GPIO_EVT_CH3_ANY_EDGE 21 GPIO_EVT_CH4_ANY_EDGE 22 GPIO_EVT_CH5_ANY_EDGE 23 GPIO_EVT_CH6_ANY_EDGE 24 GPIO_EVT_CH7_ANY_EDGE 25 GPIO_EVT_ZERO_DET_POS0 26 GPIO_EVT_ZERO_DET_NEG0 27 LEDC_EVT_DUTY_CHNG_END_CH0 LED PWM Controller (LEDC) 28 LEDC_EVT_DUTY_CHNG_END_CH1 29 LEDC_EVT_DUTY_CHNG_END_CH2 30 LEDC_EVT_DUTY_CHNG_END_CH3 31 LEDC_EVT_DUTY_CHNG_END_CH4 32 LEDC_EVT_DUTY_CHNG_END_CH5 33 LEDC_EVT_OVF_CNT_PLS_CH0 34 LEDC_EVT_OVF_CNT_PLS_CH1 35 LEDC_EVT_OVF_CNT_PLS_CH2 36 LEDC_EVT_OVF_CNT_PLS_CH3 37 LEDC_EVT_OVF_CNT_PLS_CH4 38 LEDC_EVT_OVF_CNT_PLS_CH5 39 LEDC_EVT_TIME_OVF_TIMER0 40 LEDC_EVT_TIME_OVF_TIMER1 41 LEDC_EVT_TIME_OVF_TIMER2 42 LEDC_EVT_TIME_OVF_TIMER3 43 LEDC_EVT_TIMER0_CMP 44 LEDC_EVT_TIMER1_CMP 45 LEDC_EVT_TIMER2_CMP 46 LEDC_EVT_TIMER3_CMP 47 TG0_EVT_CNT_CMP_TIMER0 General-purpose timer group 0 49 TG1_EVT_CNT_CMP_TIMER0 General-purpose timer group 1 51 SYSTIMER_EVT_CNT_CMP0 System Timer 52 SYSTIMER_EVT_CNT_CMP1 53 SYSTIMER_EVT_CNT_CMP2 54 MCPWM0_EVT_TIMER0_STOP MCPWM0 55 MCPWM0_EVT_TIMER1_STOP 56 MCPWM0_EVT_TIMER2_STOP 57 MCPWM0_EVT_TIMER0_TEZ 58 MCPWM0_EVT_TIMER1_TEZ Espressif Systems 396 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) SOC_ETM_CHn_EVT_ID Selected Event Peripheral Generating This Event 59 MCPWM0_EVT_TIMER2_TEZ 60 MCPWM0_EVT_TIMER0_TEP 61 MCPWM0_EVT_TIMER1_TEP 62 MCPWM0_EVT_TIMER2_TEP 63 MCPWM0_EVT_OP0_TEA 64 MCPWM0_EVT_OP1_TEA 65 MCPWM0_EVT_OP2_TEA 66 MCPWM0_EVT_OP0_TEB 67 MCPWM0_EVT_OP1_TEB 68 MCPWM0_EVT_OP2_TEB 69 MCPWM0_EVT_F0 70 MCPWM0_EVT_F1 71 MCPWM0_EVT_F2 72 MCPWM0_EVT_F0_CLR 73 MCPWM0_EVT_F1_CLR 74 MCPWM0_EVT_F2_CLR 75 MCPWM0_EVT_TZ0_CBC 76 MCPWM0_EVT_TZ1_CBC 77 MCPWM0_EVT_TZ2_CBC 78 MCPWM0_EVT_TZ0_OST 79 MCPWM0_EVT_TZ1_OST 80 MCPWM0_EVT_TZ2_OST 81 MCPWM0_EVT_CAP0 82 MCPWM0_EVT_CAP1 83 MCPWM0_EVT_CAP2 84 MCPWM0_EVT_OP0_TEE1 85 MCPWM0_EVT_OP1_TEE1 86 MCPWM0_EVT_OP2_TEE1 87 MCPWM0_EVT_OP0_TEE2 88 MCPWM0_EVT_OP1_TEE2 89 MCPWM0_EVT_OP2_TEE2 90 ADC_EVT_CONV_CMPLT0 ADC Controller 91 ADC_EVT_EQ_ABOVE_THRESH0 92 ADC_EVT_EQ_ABOVE_THRESH1 93 ADC_EVT_EQ_BELOW_THRESH0 94 ADC_EVT_EQ_BELOW_THRESH1 96 ADC_EVT_STOPPED0 97 ADC_EVT_STARTED0 106 TMPSNSR_EVT_OVER_LIMIT Temperature Sensor 107 I2S0_EVT_RX_DONE I2S 108 I2S0_EVT_TX_DONE 109 I2S0_EVT_X_WORDS_RECEIVED 110 I2S0_EVT_X_WORDS_SENT 111 ULP_EVT_ERR_INTR Low-Power CPU Espressif Systems 397 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) SOC_ETM_CHn_EVT_ID Selected Event Peripheral Generating This Event 113 ULP_EVT_START_INTR 114 RTC_EVT_TICK RTC Timer 115 RTC_EVT_OVF 116 RTC_EVT_CMP 117 GDMA_EVT_IN_DONE_CH0 GDMA Controller (GDMA) 118 GDMA_EVT_IN_DONE_CH1 119 GDMA_EVT_IN_DONE_CH2 120 GDMA_EVT_IN_SUC_EOF_CH0 121 GDMA_EVT_IN_SUC_EOF_CH1 122 GDMA_EVT_IN_SUC_EOF_CH2 123 GDMA_EVT_IN_FIFO_EMPTY_CH0 124 GDMA_EVT_IN_FIFO_EMPTY_CH1 125 GDMA_EVT_IN_FIFO_EMPTY_CH2 126 GDMA_EVT_IN_FIFO_FULL_CH0 127 GDMA_EVT_IN_FIFO_FULL_CH1 128 GDMA_EVT_IN_FIFO_FULL_CH2 129 GDMA_EVT_OUT_DONE_CH0 130 GDMA_EVT_OUT_DONE_CH1 131 GDMA_EVT_OUT_DONE_CH2 132 GDMA_EVT_OUT_EOF_CH0 133 GDMA_EVT_OUT_EOF_CH1 134 GDMA_EVT_OUT_EOF_CH2 135 GDMA_EVT_OUT_TOTAL_EOF_CH0 136 GDMA_EVT_OUT_TOTAL_EOF_CH1 137 GDMA_EVT_OUT_TOTAL_EOF_CH2 138 GDMA_EVT_OUT_FIFO_EMPTY_CH0 139 GDMA_EVT_OUT_FIFO_EMPTY_CH1 140 GDMA_EVT_OUT_FIFO_EMPTY_CH2 141 GDMA_EVT_OUT_FIFO_FULL_CH0 142 GDMA_EVT_OUT_FIFO_FULL_CH1 143 GDMA_EVT_OUT_FIFO_FULL_CH2 144 PMU_EVT_SLEEP_WEEKUP PMU Whenever any of these events occurs, the corresponding peripheral generates a pulse signal. As soon as the pulse signal is high, the event is considered as being received. For more detailed descriptions of an event, please refer to the chapter for the peripheral generating this event. 10.3.3 Tasks An ETM channel can be set up to map its event to one of the tasks by configuring the SOC_ETM_CHn_TASK_ID field. Table 10.3-2 shows the configuration values of SOC_ETM_CHn_TASK_ID and their corresponding tasks. Espressif Systems 398 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Table 10.3-2. Mappable Tasks for ETM Channeln SOC_ETM_CHn_TASK_ID Mapped Task Peripheral Receiving This Task 1 GPIO_TASK_CH0_SET GPIO 2 GPIO_TASK_CH1_SET 3 GPIO_TASK_CH2_SET 4 GPIO_TASK_CH3_SET 5 GPIO_TASK_CH4_SET 6 GPIO_TASK_CH5_SET 7 GPIO_TASK_CH6_SET 8 GPIO_TASK_CH7_SET 9 GPIO_TASK_CH0_CLEAR 10 GPIO_TASK_CH1_CLEAR 11 GPIO_TASK_CH2_CLEAR 12 GPIO_TASK_CH3_CLEAR 13 GPIO_TASK_CH4_CLEAR 14 GPIO_TASK_CH5_CLEAR 15 GPIO_TASK_CH6_CLEAR 16 GPIO_TASK_CH7_CLEAR 17 GPIO_TASK_CH0_TOGGLE 18 GPIO_TASK_CH1_TOGGLE 19 GPIO_TASK_CH2_TOGGLE 20 GPIO_TASK_CH3_TOGGLE 21 GPIO_TASK_CH4_TOGGLE 22 GPIO_TASK_CH5_TOGGLE 23 GPIO_TASK_CH6_TOGGLE 24 GPIO_TASK_CH7_TOGGLE 25 LEDC_TASK_TIMER0_RES_UPDATE LED PWM Controller (LEDC) 26 LEDC_TASK_TIMER1_RES_UPDATE 27 LEDC_TASK_TIMER2_RES_UPDATE 28 LEDC_TASK_TIMER3_RES_UPDATE 29 LEDC_TASK_DUTY_SCALE_UPDATE_CH0 30 LEDC_TASK_DUTY_SCALE_UPDATE_CH1 31 LEDC_TASK_DUTY_SCALE_UPDATE_CH2 32 LEDC_TASK_DUTY_SCALE_UPDATE_CH3 33 LEDC_TASK_DUTY_SCALE_UPDATE_CH4 34 LEDC_TASK_DUTY_SCALE_UPDATE_CH5 35 LEDC_TASK_TIMER0_CAP 36 LEDC_TASK_TIMER1_CAP 37 LEDC_TASK_TIMER2_CAP 38 LEDC_TASK_TIMER3_CAP 39 LEDC_TASK_SIG_OUT_DIS_CH0 40 LEDC_TASK_SIG_OUT_DIS_CH1 41 LEDC_TASK_SIG_OUT_DIS_CH2 42 LEDC_TASK_SIG_OUT_DIS_CH3 43 LEDC_TASK_SIG_OUT_DIS_CH4 Espressif Systems 399 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) SOC_ETM_CHn_TASK_ID Mapped Task Peripheral Receiving This Task 44 LEDC_TASK_SIG_OUT_DIS_CH5 45 LEDC_TASK_OVF_CNT_RST_CH0 46 LEDC_TASK_OVF_CNT_RST_CH1 47 LEDC_TASK_OVF_CNT_RST_CH2 48 LEDC_TASK_OVF_CNT_RST_CH3 49 LEDC_TASK_OVF_CNT_RST_CH4 50 LEDC_TASK_OVF_CNT_RST_CH5 51 LEDC_TASK_TIMER0_RST 52 LEDC_TASK_TIMER1_RST 53 LEDC_TASK_TIMER2_RST 54 LEDC_TASK_TIMER3_RST 55 LEDC_TASK_TIMER0_RESUME 56 LEDC_TASK_TIMER1_RESUME 57 LEDC_TASK_TIMER2_RESUME 58 LEDC_TASK_TIMER3_RESUME 59 LEDC_TASK_TIMER0_PAUSE 60 LEDC_TASK_TIMER1_PAUSE 61 LEDC_TASK_TIMER2_PAUSE 62 LEDC_TASK_TIMER3_PAUSE 63 LEDC_TASK_GAMMA_RESTART_CH0 64 LEDC_TASK_GAMMA_RESTART_CH1 65 LEDC_TASK_GAMMA_RESTART_CH2 66 LEDC_TASK_GAMMA_RESTART_CH3 67 LEDC_TASK_GAMMA_RESTART_CH4 68 LEDC_TASK_GAMMA_RESTART_CH5 69 LEDC_TASK_GAMMA_PAUSE_CH0 70 LEDC_TASK_GAMMA_PAUSE_CH1 71 LEDC_TASK_GAMMA_PAUSE_CH2 72 LEDC_TASK_GAMMA_PAUSE_CH3 73 LEDC_TASK_GAMMA_PAUSE_CH4 74 LEDC_TASK_GAMMA_PAUSE_CH5 75 LEDC_TASK_GAMMA_RESUME_CH0 76 LEDC_TASK_GAMMA_RESUME_CH1 77 LEDC_TASK_GAMMA_RESUME_CH2 78 LEDC_TASK_GAMMA_RESUME_CH3 79 LEDC_TASK_GAMMA_RESUME_CH4 80 LEDC_TASK_GAMMA_RESUME_CH5 81 TG0_TASK_CNT_START_TIMER0 General-purpose timer group 0 82 TG0_TASK_ALARM_START_TIMER0 83 TG0_TASK_CNT_STOP_TIMER0 84 TG0_TASK_CNT_RELOAD_TIMER0 85 TG0_TASK_CNT_CAP_TIMER0 91 TG1_TASK_CNT_START_TIMER0 General-purpose timer group 1 92 TG1_TASK_ALARM_START_TIMER0 93 TG1_TASK_CNT_STOP_TIMER0 Espressif Systems 400 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) SOC_ETM_CHn_TASK_ID Mapped Task Peripheral Receiving This Task 94 TG1_TASK_CNT_RELOAD_TIMER0 95 TG1_TASK_CNT_CAP_TIMER0 101 MCPWM0_TASK_CMPR0_A_UP MCPWM0 102 MCPWM0_TASK_CMPR1_A_UP 103 MCPWM0_TASK_CMPR2_A_UP 104 MCPWM0_TASK_CMPR0_B_UP 105 MCPWM0_TASK_CMPR1_B_UP 106 MCPWM0_TASK_CMPR2_B_UP 107 MCPWM0_TASK_GEN_STOP 108 MCPWM0_TASK_TIMER0_SYN 109 MCPWM0_TASK_TIMER1_SYN 110 MCPWM0_TASK_TIMER2_SYN 111 MCPWM0_TASK_TIMER0_PERIOD_UP 112 MCPWM0_TASK_TIMER1_PERIOD_UP 113 MCPWM0_TASK_TIMER2_PERIOD_UP 114 MCPWM0_TASK_TZ0_OST 115 MCPWM0_TASK_TZ1_OST 116 MCPWM0_TASK_TZ2_OST 117 MCPWM0_TASK_CLR0_OST 118 MCPWM0_TASK_CLR1_OST 119 MCPWM0_TASK_CLR2_OST 120 MCPWM0_TASK_CAP0 121 MCPWM0_TASK_CAP1 122 MCPWM0_TASK_CAP2 123 ADC_TASK_SAMPLE0 ADC Controller 125 ADC_TASK_START0 126 ADC_TASK_STOP0 131 TMPSNSR_TASK_START_SAMPLE Temperature Sensor 132 TMPSNSR_TASK_STOP_SAMPLE 133 I2S0_TASK_START_RX I2S 134 I2S0_TASK_START_TX 135 I2S0_TASK_STOP_RX 136 I2S0_TASK_STOP_TX 137 ULP_TASK_WEAKUP_CPU Low-Power CPU 143 GDMA_TASK_IN_START_CH0 GDMA Controller (GDMA) 144 GDMA_TASK_IN_START_CH1 145 GDMA_TASK_IN_START_CH2 146 GDMA_TASK_OUT_START_CH0 147 GDMA_TASK_OUT_START_CH1 148 GDMA_TASK_OUT_START_CH2 149 PMU_TASK_SLEEP_REQ PMU When a channel receives a valid event pulse signal, it generates the mapped task pulse signal. For more detailed descriptions of a task, please refer to the chapter for the peripheral receiving this task. Espressif Systems 401 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Events from different channels can be optionally mapped to the same task. For example, field SOC_ETM_CHn_TASK_ID of multiple channels can be configured with the same value, and field SOC_ETM_CHn_EVT_ID can be configured with the same or different values. In this case, when the event received by any of the channels is valid, the task will be generated. If events received by multiple channels are valid at the same time, the task will be generated only once. 10.3.4 Event and Task Status The ETM module supports checking the status of events and tasks by reading registers as follows: • Event status can be checked by reading the SOC_ETM_EVT_STn_REG register. If the field corresponding to an event is 1, it indicates that the event has been received by ETM. Otherwise, it indicates that the event has not been received by ETM. The fields in the SOC_ETM_EVT_STn_REG register can be cleared by writing 1 to the corresponding fields in the SOC_ETM_EVT_STn_CLR_REG register. • Task status can be checked by reading the SOC_ETM_TASK_STn_REG register. If the field corresponding to a task is 1, it indicates that the task has been generated by ETM. Otherwise, it indicates that the task has not been generated by ETM. The fields in the SOC_ETM_TASK_STn_REG register can be cleared by writing 1 to the corresponding fields in the SOC_ETM_TASK_STn_CLR_REG register. 10.3.5 Timing Considerations Figure 10.3-2 shows the structure of clocks that drive received events, sent tasks, and ETM channels. ETM channel Channel n Events Tasks MUX DEMUX peripheralx clock domain peripheraly clock domain peripheralz clock domain clock domain crossing clock domain crossing peripheralx clock domain peripheraly clock domain peripheralz clock domain ETM clock domain Figure 10.3-2. Event Task Matrix Clock Architecture ETM is running at the SYS_CLK domain (see Chapter 7 Reset and Clock). Each event corresponds to a pulse signal generated by the corresponding peripheral in its clock domain, while each task is mapped by the ETM to a pulse signal under its corresponding peripheral clock domain. The peripherals generating events, the Event Task Matrix, and peripherals receiving tasks are not necessarily running off the same clock and as such need to be synchronized. Therefore, to avoid event loss, there should be a delay between two consecutive event pulses which is dependent on the clock of the peripheral generating the event, on the ETM’s clock, and on the clock of the peripheral executing the task. To make sure the Event Task Matrix receives every event successfully, for peripherals generating event pulses, the interval between two consecutive pulses must be greater than one ETM clock cycle, namely Espressif Systems 402 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) ceil( peripheral_clock_frequency ET M _clock_frequency ) in the unit of peripheral clock cycles. For example, assuming that peripheral A is in the 80 MHz clock domain (PLL_F80M_CLK), and the ETM runs in the 40 MHz clock domain (SYS_CLK). Peripheral A generates event 1, which should be received by ETM. To receive each event 1 successfully, the interval between two consecutive event 1 must be greater than two peripheral A clock cycles (i.e., one ETM clock cycle). Likewise, to make sure the Event Task Matrix maps the received event (i.e., event synchronized to the ETM’s clock domain) successfully to a task, the interval between two consecutive event pulses in the ETM clock domain must be greater than one peripheral clock cycle, namely ceil( ET M _clock_frequency peripheral_clock_frequency ) in the unit of ETM clock cycles. For example, assuming that peripheral B is in the 20 MHz clock domain (RC_FAST_CLK), and the ETM runs in the 40 MHz clock domain (SYS_CLK). ETM maps an event to task 1, which should be received by peripheral B. To map each received event successfully to task 1, the interval between two consecutive events must be greater than two ETM clock cycles (i.e., one peripheral B clock cycle). As a result, to map two consecutive events generated by peripheral A to peripheral B, the interval between these two events must be ceil( peripheral_A_clock_frequency ET M _clock_frequency ) ∗ ceil( ET M _clock_frequency peripheral_B_clock_frequency ) in the unit of peripheral A clock cycles. For example, assuming that peripheral A is in the 80 MHz clock domain (PLL_F80M_CLK), peripheral B is in the 20 MHz clock domain (RC_FAST_CLK), and the ETM runs in the 40 MHz clock domain (SYS_CLK). ETM maps event 1 generated by peripheral A to task 1 received by peripheral B. To successfully map each event 1 to task 1, the interval between two consecutive event 1 must be greater than 2 ∗ 2 = 4 peripheral A clock cycles. 10.3.6 Channel Control Each ETM channel can be independently configured to be enabled or disabled. When channeln is enabled and receives the event configured via SOC_ETM_CHn_EVT_ID, it maps the event to the task configured via SOC_ETM_CHn_TASK_ID. When channeln is disabled, even if it receives the event configured via SOC_ETM_CHn_EVT_ID, no task will be generated. To enable ETM channeln, write 1 to SOC_ETM_CH_ENABLEn. To disable ETM channeln, Write 1 to SOC_ETM_CH_DISABLEn. The status of ETM channeln can be obtained by reading SOC_ETM_CH_ENABLEDn. 1 indicates that channeln has been enabled, and 0 indicates disabled. If SOC_ETM_CHn_EVT_ID or SOC_ETM_CHn_TASK_ID is configured to 0, ETM channeln will also be disabled. The complete procedure to configure ETM channeln is as follows: 1. Enable the ETM’s clock by writing 1 to PCR_ETM_CLK_EN 2. Select the event to be received by channeln via SOC_ETM_CHn_EVT_ID 3. Select the task mapped to the received event via SOC_ETM_CHn_TASK_ID 4. Enable channeln by setting SOC_ETM_CH_ENABLEn 5. When channeln no longer needs to map the selected event to the selected task, disable channeln by setting SOC_ETM_CH_DISABLEn. To configure a new event and task mapping, repeat Steps 2 to 4. If no further configurations, channeln will remain disabled Espressif Systems 403 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) 6. The whole ETM module (i.e., all ETM channels) can be reset by writing 1 and then 0 to the PCR_ETM_RST_EN field Espressif Systems 404 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) 10.4 Register Summary The addresses in this section are relative to Event Task Matrix base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Status register SOC_ETM_CH_ENA_AD0_REG Channel enable status register 0x0000 R/WTC/WTS SOC_ETM_CH_ENA_AD1_REG Channel enable status register 0x000C R/WTC/WTS SOC_ETM_EVT_ST0_REG Event trigger status register 0x01A8 R/WTC/SS SOC_ETM_EVT_ST1_REG Event trigger status register 0x01B0 R/WTC/SS SOC_ETM_EVT_ST2_REG Event trigger status register 0x01B8 R/WTC/SS SOC_ETM_EVT_ST3_REG Event trigger status register 0x01C0 R/WTC/SS SOC_ETM_EVT_ST4_REG Event trigger status register 0x01C8 R/WTC/SS SOC_ETM_TASK_ST0_REG Task trigger status register 0x01D0 R/WTC/SS SOC_ETM_TASK_ST1_REG Task trigger status register 0x01D8 R/WTC/SS SOC_ETM_TASK_ST2_REG Task trigger status register 0x01E0 R/WTC/SS SOC_ETM_TASK_ST3_REG Task trigger status register 0x01E8 R/WTC/SS SOC_ETM_TASK_ST4_REG Task trigger status register 0x01F0 R/WTC/SS Configuration Register SOC_ETM_CH_ENA_AD0_SET_REG Channel enable register 0x0004 WT SOC_ETM_CH_ENA_AD0_CLR_REG Channel disable register 0x0008 WT SOC_ETM_CH_ENA_AD1_SET_REG Channel enable register 0x0010 WT SOC_ETM_CH_ENA_AD1_CLR_REG Channel disable register 0x0014 WT SOC_ETM_CH0_EVT_ID_REG Channel 0 event ID register 0x0018 R/W SOC_ETM_CH0_TASK_ID_REG Channel 0 task ID register 0x001C R/W SOC_ETM_CH1_EVT_ID_REG Channel 1 event ID register 0x0020 R/W SOC_ETM_CH1_TASK_ID_REG Channel 1 task ID register 0x0024 R/W SOC_ETM_CH2_EVT_ID_REG Channel 2 event ID register 0x0028 R/W SOC_ETM_CH2_TASK_ID_REG Channel 2 task ID register 0x002C R/W SOC_ETM_CH3_EVT_ID_REG Channel 3 event ID register 0x0030 R/W SOC_ETM_CH3_TASK_ID_REG Channel 3 task ID register 0x0034 R/W SOC_ETM_CH4_EVT_ID_REG Channel 4 event ID register 0x0038 R/W SOC_ETM_CH4_TASK_ID_REG Channel 4 task ID register 0x003C R/W SOC_ETM_CH5_EVT_ID_REG Channel 5 event ID register 0x0040 R/W SOC_ETM_CH5_TASK_ID_REG Channel 5 task ID register 0x0044 R/W SOC_ETM_CH6_EVT_ID_REG Channel 6 event ID register 0x0048 R/W SOC_ETM_CH6_TASK_ID_REG Channel 6 task ID register 0x004C R/W SOC_ETM_CH7_EVT_ID_REG Channel 7 event ID register 0x0050 R/W SOC_ETM_CH7_TASK_ID_REG Channel 7 task ID register 0x0054 R/W SOC_ETM_CH8_EVT_ID_REG Channel 8 event ID register 0x0058 R/W SOC_ETM_CH8_TASK_ID_REG Channel 8 task ID register 0x005C R/W SOC_ETM_CH9_EVT_ID_REG Channel 9 event ID register 0x0060 R/W Espressif Systems 405 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Name Description Address Access SOC_ETM_CH9_TASK_ID_REG Channel 9 task ID register 0x0064 R/W SOC_ETM_CH10_EVT_ID_REG Channel 10 event ID register 0x0068 R/W SOC_ETM_CH10_TASK_ID_REG Channel 10 task ID register 0x006C R/W SOC_ETM_CH11_EVT_ID_REG Channel 11 event ID register 0x0070 R/W SOC_ETM_CH11_TASK_ID_REG Channel 11 task ID register 0x0074 R/W SOC_ETM_CH12_EVT_ID_REG Channel 12 event ID register 0x0078 R/W SOC_ETM_CH12_TASK_ID_REG Channel 12 task ID register 0x007C R/W SOC_ETM_CH13_EVT_ID_REG Channel 13 event ID register 0x0080 R/W SOC_ETM_CH13_TASK_ID_REG Channel 13 task ID register 0x0084 R/W SOC_ETM_CH14_EVT_ID_REG Channel 14 event ID register 0x0088 R/W SOC_ETM_CH14_TASK_ID_REG Channel 14 task ID register 0x008C R/W SOC_ETM_CH15_EVT_ID_REG Channel 15 event ID register 0x0090 R/W SOC_ETM_CH15_TASK_ID_REG Channel 15 task ID register 0x0094 R/W SOC_ETM_CH16_EVT_ID_REG Channel 16 event ID register 0x0098 R/W SOC_ETM_CH16_TASK_ID_REG Channel 16 task ID register 0x009C R/W SOC_ETM_CH17_EVT_ID_REG Channel 17 event ID register 0x00A0 R/W SOC_ETM_CH17_TASK_ID_REG Channel 17 task ID register 0x00A4 R/W SOC_ETM_CH18_EVT_ID_REG Channel 18 event ID register 0x00A8 R/W SOC_ETM_CH18_TASK_ID_REG Channel 18 task ID register 0x00AC R/W SOC_ETM_CH19_EVT_ID_REG Channel 19 event ID register 0x00B0 R/W SOC_ETM_CH19_TASK_ID_REG Channel 19 task ID register 0x00B4 R/W SOC_ETM_CH20_EVT_ID_REG Channel 20 event ID register 0x00B8 R/W SOC_ETM_CH20_TASK_ID_REG Channel 20 task ID register 0x00BC R/W SOC_ETM_CH21_EVT_ID_REG Channel 21 event ID register 0x00C0 R/W SOC_ETM_CH21_TASK_ID_REG Channel 21 task ID register 0x00C4 R/W SOC_ETM_CH22_EVT_ID_REG Channel 22 event ID register 0x00C8 R/W SOC_ETM_CH22_TASK_ID_REG Channel 22 task ID register 0x00CC R/W SOC_ETM_CH23_EVT_ID_REG Channel 23 event ID register 0x00D0 R/W SOC_ETM_CH23_TASK_ID_REG Channel 23 task ID register 0x00D4 R/W SOC_ETM_CH24_EVT_ID_REG Channel 24 event ID register 0x00D8 R/W SOC_ETM_CH24_TASK_ID_REG Channel 24 task ID register 0x00DC R/W SOC_ETM_CH25_EVT_ID_REG Channel 25 event ID register 0x00E0 R/W SOC_ETM_CH25_TASK_ID_REG Channel 25 task ID register 0x00E4 R/W SOC_ETM_CH26_EVT_ID_REG Channel 26 event ID register 0x00E8 R/W SOC_ETM_CH26_TASK_ID_REG Channel 26 task ID register 0x00EC R/W SOC_ETM_CH27_EVT_ID_REG Channel 27 event ID register 0x00F0 R/W SOC_ETM_CH27_TASK_ID_REG Channel 27 task ID register 0x00F4 R/W SOC_ETM_CH28_EVT_ID_REG Channel 28 event ID register 0x00F8 R/W SOC_ETM_CH28_TASK_ID_REG Channel 28 task ID register 0x00FC R/W SOC_ETM_CH29_EVT_ID_REG Channel 29 event ID register 0x0100 R/W SOC_ETM_CH29_TASK_ID_REG Channel 29 task ID register 0x0104 R/W SOC_ETM_CH30_EVT_ID_REG Channel 30 event ID register 0x0108 R/W SOC_ETM_CH30_TASK_ID_REG Channel 30 task ID register 0x010C R/W Espressif Systems 406 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Name Description Address Access SOC_ETM_CH31_EVT_ID_REG Channel 31 event ID register 0x0110 R/W SOC_ETM_CH31_TASK_ID_REG Channel 31 task ID register 0x0114 R/W SOC_ETM_CH32_EVT_ID_REG Channel 32 event ID register 0x0118 R/W SOC_ETM_CH32_TASK_ID_REG Channel 32 task ID register 0x011C R/W SOC_ETM_CH33_EVT_ID_REG Channel 33 event ID register 0x0120 R/W SOC_ETM_CH33_TASK_ID_REG Channel 33 task ID register 0x0124 R/W SOC_ETM_CH34_EVT_ID_REG Channel 34 event ID register 0x0128 R/W SOC_ETM_CH34_TASK_ID_REG Channel 34 task ID register 0x012C R/W SOC_ETM_CH35_EVT_ID_REG Channel 35 event ID register 0x0130 R/W SOC_ETM_CH35_TASK_ID_REG Channel 35 task ID register 0x0134 R/W SOC_ETM_CH36_EVT_ID_REG Channel 36 event ID register 0x0138 R/W SOC_ETM_CH36_TASK_ID_REG Channel 36 task ID register 0x013C R/W SOC_ETM_CH37_EVT_ID_REG Channel 37 event ID register 0x0140 R/W SOC_ETM_CH37_TASK_ID_REG Channel 37 task ID register 0x0144 R/W SOC_ETM_CH38_EVT_ID_REG Channel 38 event ID register 0x0148 R/W SOC_ETM_CH38_TASK_ID_REG Channel 38 task ID register 0x014C R/W SOC_ETM_CH39_EVT_ID_REG Channel 39 event ID register 0x0150 R/W SOC_ETM_CH39_TASK_ID_REG Channel 39 task ID register 0x0154 R/W SOC_ETM_CH40_EVT_ID_REG Channel 40 event ID register 0x0158 R/W SOC_ETM_CH40_TASK_ID_REG Channel 40 task ID register 0x015C R/W SOC_ETM_CH41_EVT_ID_REG Channel 41 event ID register 0x0160 R/W SOC_ETM_CH41_TASK_ID_REG Channel 41 task ID register 0x0164 R/W SOC_ETM_CH42_EVT_ID_REG Channel 42 event ID register 0x0168 R/W SOC_ETM_CH42_TASK_ID_REG Channel 42 task ID register 0x016C R/W SOC_ETM_CH43_EVT_ID_REG Channel 43 event ID register 0x0170 R/W SOC_ETM_CH43_TASK_ID_REG Channel 43 task ID register 0x0174 R/W SOC_ETM_CH44_EVT_ID_REG Channel 44 event ID register 0x0178 R/W SOC_ETM_CH44_TASK_ID_REG Channel 44 task ID register 0x017C R/W SOC_ETM_CH45_EVT_ID_REG Channel 45 event ID register 0x0180 R/W SOC_ETM_CH45_TASK_ID_REG Channel 45 task ID register 0x0184 R/W SOC_ETM_CH46_EVT_ID_REG Channel 46 event ID register 0x0188 R/W SOC_ETM_CH46_TASK_ID_REG Channel 46 task ID register 0x018C R/W SOC_ETM_CH47_EVT_ID_REG Channel 47 event ID register 0x0190 R/W SOC_ETM_CH47_TASK_ID_REG Channel 47 task ID register 0x0194 R/W SOC_ETM_CH48_EVT_ID_REG Channel 48 event ID register 0x0198 R/W SOC_ETM_CH48_TASK_ID_REG Channel 48 task ID register 0x019C R/W SOC_ETM_CH49_EVT_ID_REG Channel 49 event ID register 0x01A0 R/W SOC_ETM_CH49_TASK_ID_REG Channel 49 task ID register 0x01A4 R/W SOC_ETM_EVT_ST0_CLR_REG Event trigger status clear register 0x01AC WT SOC_ETM_EVT_ST1_CLR_REG Event trigger status clear register 0x01B4 WT SOC_ETM_EVT_ST2_CLR_REG Event trigger status clear register 0x01BC WT SOC_ETM_EVT_ST3_CLR_REG Event trigger status clear register 0x01C4 WT SOC_ETM_EVT_ST4_CLR_REG Event trigger status clear register 0x01CC WT Espressif Systems 407 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Name Description Address Access SOC_ETM_TASK_ST0_CLR_REG Task trigger status clear register 0x01D4 WT SOC_ETM_TASK_ST1_CLR_REG Task trigger status clear register 0x01DC WT SOC_ETM_TASK_ST2_CLR_REG Task trigger status clear register 0x01E4 WT SOC_ETM_TASK_ST3_CLR_REG Task trigger status clear register 0x01EC WT SOC_ETM_TASK_ST4_CLR_REG Task trigger status clear register 0x01F4 WT SOC_ETM_CLK_EN_REG ETM clock enable register 0x01F8 R/W Version Register SOC_ETM_DATE_REG Version control register 0x01FC R/W Espressif Systems 408 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) 10.5 Registers The addresses in this section are relative to Event Task Matrix base address provided in Table 4.3-2 in Chapter 4 System and Memory. For how to program reserved fields, please refer to Section Programming Reserved Register Field. Register 10.1. SOC_ETM_CH_ENA_AD0_REG (0x0000) SOC_ETM_CH_ENABLED31 0 31 SOC_ETM_CH_ENABLED30 0 30 SOC_ETM_CH_ENABLED29 0 29 SOC_ETM_CH_ENABLED28 0 28 SOC_ETM_CH_ENABLED27 0 27 SOC_ETM_CH_ENABLED26 0 26 SOC_ETM_CH_ENABLED25 0 25 SOC_ETM_CH_ENABLED24 0 24 SOC_ETM_CH_ENABLED23 0 23 SOC_ETM_CH_ENABLED22 0 22 SOC_ETM_CH_ENABLED21 0 21 SOC_ETM_CH_ENABLED20 0 20 SOC_ETM_CH_ENABLED19 0 19 SOC_ETM_CH_ENABLED18 0 18 SOC_ETM_CH_ENABLED17 0 17 SOC_ETM_CH_ENABLED16 0 16 SOC_ETM_CH_ENABLED15 0 15 SOC_ETM_CH_ENABLED14 0 14 SOC_ETM_CH_ENABLED13 0 13 SOC_ETM_CH_ENABLED12 0 12 SOC_ETM_CH_ENABLED11 0 11 SOC_ETM_CH_ENABLED10 0 10 SOC_ETM_CH_ENABLED9 0 9 SOC_ETM_CH_ENABLED8 0 8 SOC_ETM_CH_ENABLED7 0 7 SOC_ETM_CH_ENABLED6 0 6 SOC_ETM_CH_ENABLED5 0 5 SOC_ETM_CH_ENABLED4 0 4 SOC_ETM_CH_ENABLED3 0 3 SOC_ETM_CH_ENABLED2 0 2 SOC_ETM_CH_ENABLED1 0 1 SOC_ETM_CH_ENABLED0 0 0 Reset SOC_ETM_CH_ENABLEDn (n: 0-31) Represents channel n enable status. 0: Disable 1: Enable (R/WTC/WTS) Register 10.2. SOC_ETM_CH_ENA_AD1_REG (0x000C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 18 SOC_ETM_CH_ENABLED49 0 17 SOC_ETM_CH_ENABLED48 0 16 SOC_ETM_CH_ENABLED47 0 15 SOC_ETM_CH_ENABLED46 0 14 SOC_ETM_CH_ENABLED45 0 13 SOC_ETM_CH_ENABLED44 0 12 SOC_ETM_CH_ENABLED43 0 11 SOC_ETM_CH_ENABLED42 0 10 SOC_ETM_CH_ENABLED41 0 9 SOC_ETM_CH_ENABLED40 0 8 SOC_ETM_CH_ENABLED39 0 7 SOC_ETM_CH_ENABLED38 0 6 SOC_ETM_CH_ENABLED37 0 5 SOC_ETM_CH_ENABLED36 0 4 SOC_ETM_CH_ENABLED35 0 3 SOC_ETM_CH_ENABLED34 0 2 SOC_ETM_CH_ENABLED33 0 1 SOC_ETM_CH_ENABLED32 0 0 Reset SOC_ETM_CH_ENABLEDn (n: 32-49) Represents channel n enable status. 0: Disable 1: Enable (R/WTC/WTS) Espressif Systems 409 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.3. SOC_ETM_EVT_ST0_REG (0x01A8) SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST 0 31 SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST 0 30 SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST 0 29 SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST 0 28 SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST 0 27 SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST 0 26 SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST 0 25 SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST 0 24 SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST 0 23 SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST 0 22 SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST 0 21 SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST 0 20 SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST 0 19 SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST 0 18 SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST 0 17 SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST 0 16 SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST 0 15 SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST 0 14 SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST 0 13 SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST 0 12 SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST 0 11 SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST 0 10 SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST 0 9 SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST 0 8 SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST 0 7 SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST 0 6 SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST 0 5 SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST 0 4 SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST 0 3 SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST 0 2 SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST 0 1 SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST 0 0 Reset SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST Represents GPIO_EVT_CH0_RISE_EDGE trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST Represents GPIO_EVT_CH1_RISE_EDGE trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST Represents GPIO_EVT_CH2_RISE_EDGE trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST Represents GPIO_EVT_CH3_RISE_EDGE trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST Represents GPIO_EVT_CH4_RISE_EDGE trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) Continued on the next page... Espressif Systems 410 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.3. SOC_ETM_EVT_ST0_REG (0x01A8) Continued from the previous page... SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST Represents GPIO_EVT_CH5_RISE_EDGE trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST Represents GPIO_EVT_CH6_RISE_EDGE trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST Represents GPIO_EVT_CH7_RISE_EDGE trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST Represents GPIO_EVT_CH0_FALL_EDGE trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST Represents GPIO_EVT_CH1_FALL_EDGE trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST Represents GPIO_EVT_CH2_FALL_EDGE trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST Represents GPIO_EVT_CH3_FALL_EDGE trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) Continued on the next page... Espressif Systems 411 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.3. SOC_ETM_EVT_ST0_REG (0x01A8) Continued from the previous page... SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST Represents GPIO_EVT_CH4_FALL_EDGE trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST Represents GPIO_EVT_CH5_FALL_EDGE trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST Represents GPIO_EVT_CH6_FALL_EDGE trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST Represents GPIO_EVT_CH7_FALL_EDGE trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST Represents GPIO_EVT_CH0_ANY_EDGE trigger sta- tus. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST Represents GPIO_EVT_CH1_ANY_EDGE trigger sta- tus. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST Represents GPIO_EVT_CH2_ANY_EDGE trigger sta- tus. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST Represents GPIO_EVT_CH3_ANY_EDGE trigger sta- tus. 0: Not triggered 1: Triggered (R/WTC/SS) Continued on the next page... Espressif Systems 412 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.3. SOC_ETM_EVT_ST0_REG (0x01A8) Continued from the previous page... SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST Represents GPIO_EVT_CH4_ANY_EDGE trigger sta- tus. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST Represents GPIO_EVT_CH5_ANY_EDGE trigger sta- tus. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST Represents GPIO_EVT_CH6_ANY_EDGE trigger sta- tus. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST Represents GPIO_EVT_CH7_ANY_EDGE trigger sta- tus. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST Represents GPIO_EVT_ZERO_DET_POS0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST Represents GPIO_EVT_ZERO_DET_NEG0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST Represents LEDC_EVT_DUTY_CHNG_END_CH0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) Continued on the next page... Espressif Systems 413 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.3. SOC_ETM_EVT_ST0_REG (0x01A8) Continued from the previous page... SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST Represents LEDC_EVT_DUTY_CHNG_END_CH1 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST Represents LEDC_EVT_DUTY_CHNG_END_CH2 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST Represents LEDC_EVT_DUTY_CHNG_END_CH3 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST Represents LEDC_EVT_DUTY_CHNG_END_CH4 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST Represents LEDC_EVT_DUTY_CHNG_END_CH5 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) Espressif Systems 414 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.4. SOC_ETM_EVT_ST1_REG (0x01B0) SOC_ETM_MCPWM0_EVT_OP1_TEA_ST 0 31 SOC_ETM_MCPWM0_EVT_OP0_TEA_ST 0 30 SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST 0 29 SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST 0 28 SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST 0 27 SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST 0 26 SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST 0 25 SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST 0 24 SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST 0 23 SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST 0 22 SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST 0 21 SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST 0 20 SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST 0 19 SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST 0 18 SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST 0 17 SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST 0 16 SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST 0 15 SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST 0 14 SOC_ETM_LEDC_EVT_TIMER3_CMP_ST 0 13 SOC_ETM_LEDC_EVT_TIMER2_CMP_ST 0 12 SOC_ETM_LEDC_EVT_TIMER1_CMP_ST 0 11 SOC_ETM_LEDC_EVT_TIMER0_CMP_ST 0 10 SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST 0 9 SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST 0 8 SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST 0 7 SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST 0 6 SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST 0 5 SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST 0 4 SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST 0 3 SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST 0 2 SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST 0 1 SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST 0 0 Reset SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST Represents LEDC_EVT_OVF_CNT_PLS_CH0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST Represents LEDC_EVT_OVF_CNT_PLS_CH1 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST Represents LEDC_EVT_OVF_CNT_PLS_CH2 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST Represents LEDC_EVT_OVF_CNT_PLS_CH3 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST Represents LEDC_EVT_OVF_CNT_PLS_CH4 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST Represents LEDC_EVT_OVF_CNT_PLS_CH5 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) Continued on the next page... Espressif Systems 415 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.4. SOC_ETM_EVT_ST1_REG (0x01B0) Continued from the previous page... SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST Represents LEDC_EVT_TIME_OVF_TIMER0 trig- ger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST Represents LEDC_EVT_TIME_OVF_TIMER1 trig- ger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST Represents LEDC_EVT_TIME_OVF_TIMER2 trig- ger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST Represents LEDC_EVT_TIME_OVF_TIMER3 trig- ger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_EVT_TIMER0_CMP_ST Represents LEDC_EVT_TIMER0_CMP trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_EVT_TIMER1_CMP_ST Represents LEDC_EVT_TIMER1_CMP trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_EVT_TIMER2_CMP_ST Represents LEDC_EVT_TIMER2_CMP trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_EVT_TIMER3_CMP_ST Represents LEDC_EVT_TIMER3_CMP trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) Continued on the next page... Espressif Systems 416 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.4. SOC_ETM_EVT_ST1_REG (0x01B0) Continued from the previous page... SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST Represents TG0_EVT_CNT_CMP_TIMER0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST Represents TG0_EVT_CNT_CMP_TIMER1 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST Represents TG1_EVT_CNT_CMP_TIMER0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST Represents TG1_EVT_CNT_CMP_TIMER1 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST Represents SYSTIMER_EVT_CNT_CMP0 trigger sta- tus. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST Represents SYSTIMER_EVT_CNT_CMP1 trigger sta- tus. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST Represents SYSTIMER_EVT_CNT_CMP2 trigger sta- tus. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST Represents MCPWM0_EVT_TIMER0_STOP trig- ger status. 0: Not triggered 1: Triggered (R/WTC/SS) Continued on the next page... Espressif Systems 417 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.4. SOC_ETM_EVT_ST1_REG (0x01B0) Continued from the previous page... SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST Represents MCPWM0_EVT_TIMER1_STOP trig- ger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST Represents MCPWM0_EVT_TIMER2_STOP trig- ger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST Represents MCPWM0_EVT_TIMER0_TEZ trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST Represents MCPWM0_EVT_TIMER1_TEZ trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST Represents MCPWM0_EVT_TIMER2_TEZ trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST Represents MCPWM0_EVT_TIMER0_TEP trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST Represents MCPWM0_EVT_TIMER1_TEP trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) Continued on the next page... Espressif Systems 418 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.4. SOC_ETM_EVT_ST1_REG (0x01B0) Continued from the previous page... SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST Represents MCPWM0_EVT_TIMER2_TEP trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_EVT_OP0_TEA_ST Represents MCPWM0_EVT_OP0_TEA trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_EVT_OP1_TEA_ST Represents MCPWM0_EVT_OP1_TEA trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) Espressif Systems 419 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.5. SOC_ETM_EVT_ST2_REG (0x01B8) SOC_ETM_ADC_EVT_STOPPED0_ST 0 31 SOC_ETM_ADC_EVT_RESULT_DONE0_ST 0 30 SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST 0 29 SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST 0 28 SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST 0 27 SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST 0 26 SOC_ETM_ADC_EVT_CONV_CMPLT0_ST 0 25 SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST 0 24 SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST 0 23 SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST 0 22 SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST 0 21 SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST 0 20 SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST 0 19 SOC_ETM_MCPWM0_EVT_CAP2_ST 0 18 SOC_ETM_MCPWM0_EVT_CAP1_ST 0 17 SOC_ETM_MCPWM0_EVT_CAP0_ST 0 16 SOC_ETM_MCPWM0_EVT_TZ2_OST_ST 0 15 SOC_ETM_MCPWM0_EVT_TZ1_OST_ST 0 14 SOC_ETM_MCPWM0_EVT_TZ0_OST_ST 0 13 SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST 0 12 SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST 0 11 SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST 0 10 SOC_ETM_MCPWM0_EVT_F2_CLR_ST 0 9 SOC_ETM_MCPWM0_EVT_F1_CLR_ST 0 8 SOC_ETM_MCPWM0_EVT_F0_CLR_ST 0 7 SOC_ETM_MCPWM0_EVT_F2_ST 0 6 SOC_ETM_MCPWM0_EVT_F1_ST 0 5 SOC_ETM_MCPWM0_EVT_F0_ST 0 4 SOC_ETM_MCPWM0_EVT_OP2_TEB_ST 0 3 SOC_ETM_MCPWM0_EVT_OP1_TEB_ST 0 2 SOC_ETM_MCPWM0_EVT_OP0_TEB_ST 0 1 SOC_ETM_MCPWM0_EVT_OP2_TEA_ST 0 0 Reset SOC_ETM_MCPWM0_EVT_OP2_TEA_ST Represents MCPWM0_EVT_OP2_TEA trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_EVT_OP0_TEB_ST Represents MCPWM0_EVT_OP0_TEB trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_EVT_OP1_TEB_ST Represents MCPWM0_EVT_OP1_TEB trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_EVT_OP2_TEB_ST Represents MCPWM0_EVT_OP2_TEB trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_EVT_F0_ST Represents MCPWM0_EVT_F0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_EVT_F1_ST Represents MCPWM0_EVT_F1 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) Continued on the next page... Espressif Systems 420 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.5. SOC_ETM_EVT_ST2_REG (0x01B8) Continued from the previous page... SOC_ETM_MCPWM0_EVT_F2_ST Represents MCPWM0_EVT_F2 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_EVT_F0_CLR_ST Represents MCPWM0_EVT_F0_CLR trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_EVT_F1_CLR_ST Represents MCPWM0_EVT_F1_CLR trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_EVT_F2_CLR_ST Represents MCPWM0_EVT_F2_CLR trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST Represents MCPWM0_EVT_TZ0_CBC trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST Represents MCPWM0_EVT_TZ1_CBC trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST Represents MCPWM0_EVT_TZ2_CBC trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_EVT_TZ0_OST_ST Represents MCPWM0_EVT_TZ0_OST trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) Continued on the next page... Espressif Systems 421 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.5. SOC_ETM_EVT_ST2_REG (0x01B8) Continued from the previous page... SOC_ETM_MCPWM0_EVT_TZ1_OST_ST Represents MCPWM0_EVT_TZ1_OST trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_EVT_TZ2_OST_ST Represents MCPWM0_EVT_TZ2_OST trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_EVT_CAP0_ST Represents MCPWM0_EVT_CAP0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_EVT_CAP1_ST Represents MCPWM0_EVT_CAP1 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_EVT_CAP2_ST Represents MCPWM0_EVT_CAP2 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST Represents MCPWM0_EVT_OP0_TEE1 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST Represents MCPWM0_EVT_OP1_TEE1 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST Represents MCPWM0_EVT_OP2_TEE1 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) Continued on the next page... Espressif Systems 422 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.5. SOC_ETM_EVT_ST2_REG (0x01B8) Continued from the previous page... SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST Represents MCPWM0_EVT_OP0_TEE2 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST Represents MCPWM0_EVT_OP1_TEE2 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST Represents MCPWM0_EVT_OP2_TEE2 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_ADC_EVT_CONV_CMPLT0_ST Represents ADC_EVT_CONV_CMPLT0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST Represents ADC_EVT_EQ_ABOVE_THRESH0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST Represents ADC_EVT_EQ_ABOVE_THRESH1 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST Represents ADC_EVT_EQ_BELOW_THRESH0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) Continued on the next page... Espressif Systems 423 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.5. SOC_ETM_EVT_ST2_REG (0x01B8) Continued from the previous page... SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST Represents ADC_EVT_EQ_BELOW_THRESH1 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_ADC_EVT_RESULT_DONE0_ST Represents ADC_EVT_RESULT_DONE0 trigger sta- tus. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_ADC_EVT_STOPPED0_ST Represents ADC_EVT_STOPPED0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) Espressif Systems 424 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.6. SOC_ETM_EVT_ST3_REG (0x01C0) SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST 0 31 SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST 0 30 SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST 0 29 SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST 0 28 SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST 0 27 SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST 0 26 SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST 0 25 SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST 0 24 SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST 0 23 SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST 0 22 SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST 0 21 SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST 0 20 SOC_ETM_RTC_EVT_CMP_ST 0 19 SOC_ETM_RTC_EVT_OVF_ST 0 18 SOC_ETM_RTC_EVT_TICK_ST 0 17 SOC_ETM_ULP_EVT_START_INTR_ST 0 16 SOC_ETM_ULP_EVT_HALT_ST 0 15 SOC_ETM_ULP_EVT_ERR_INTR_ST 0 14 SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST 0 13 SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST 0 12 SOC_ETM_I2S0_EVT_TX_DONE_ST 0 11 SOC_ETM_I2S0_EVT_RX_DONE_ST 0 10 SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST 0 9 (reserved) 0 0 0 0 0 0 0 0 8 1 SOC_ETM_ADC_EVT_STARTED0_ST 0 0 Reset SOC_ETM_ADC_EVT_STARTED0_ST Represents ADC_EVT_STARTED0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST Represents TMPSNSR_EVT_OVER_LIMIT trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_I2S0_EVT_RX_DONE_ST Represents I2S0_EVT_RX_DONE trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_I2S0_EVT_TX_DONE_ST Represents I2S0_EVT_TX_DONE trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST Represents I2S0_EVT_X_WORDS_RECEIVED trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST Represents I2S0_EVT_X_WORDS_SENT trigger sta- tus. 0: Not triggered 1: Triggered (R/WTC/SS) Continued on the next page... Espressif Systems 425 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.6. SOC_ETM_EVT_ST3_REG (0x01C0) Continued from the previous page... SOC_ETM_ULP_EVT_ERR_INTR_ST Represents ULP_EVT_ERR_INTR trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_ULP_EVT_HALT_ST Represents ULP_EVT_HALT trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_ULP_EVT_START_INTR_ST Represents ULP_EVT_START_INTR trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_RTC_EVT_TICK_ST Represents RTC_EVT_TICK trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_RTC_EVT_OVF_ST Represents RTC_EVT_OVF trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_RTC_EVT_CMP_ST Represents RTC_EVT_CMP trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST Represents GDMA_EVT_IN_DONE_CH0 trigger sta- tus. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST Represents GDMA_EVT_IN_DONE_CH1 trigger sta- tus. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST Represents GDMA_EVT_IN_DONE_CH2 trigger sta- tus. 0: Not triggered 1: Triggered (R/WTC/SS) Continued on the next page... Espressif Systems 426 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.6. SOC_ETM_EVT_ST3_REG (0x01C0) Continued from the previous page... SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST Represents GDMA_EVT_IN_SUC_EOF_CH0 trig- ger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST Represents GDMA_EVT_IN_SUC_EOF_CH1 trig- ger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST Represents GDMA_EVT_IN_SUC_EOF_CH2 trig- ger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST Represents GDMA_EVT_IN_FIFO_EMPTY_CH0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST Represents GDMA_EVT_IN_FIFO_EMPTY_CH1 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST Represents GDMA_EVT_IN_FIFO_EMPTY_CH2 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST Represents GDMA_EVT_IN_FIFO_FULL_CH0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) Continued on the next page... Espressif Systems 427 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.6. SOC_ETM_EVT_ST3_REG (0x01C0) Continued from the previous page... SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST Represents GDMA_EVT_IN_FIFO_FULL_CH1 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST Represents GDMA_EVT_IN_FIFO_FULL_CH2 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) Espressif Systems 428 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.7. SOC_ETM_EVT_ST4_REG (0x01C8) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST 0 15 SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST 0 14 SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST 0 13 SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST 0 12 SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST 0 11 SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST 0 10 SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST 0 9 SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST 0 8 SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST 0 7 SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST 0 6 SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST 0 5 SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST 0 4 SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST 0 3 SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST 0 2 SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST 0 1 SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST 0 0 Reset SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST Represents GDMA_EVT_OUT_DONE_CH0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST Represents GDMA_EVT_OUT_DONE_CH1 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST Represents GDMA_EVT_OUT_DONE_CH2 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST Represents GDMA_EVT_OUT_EOF_CH0 trigger sta- tus. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST Represents GDMA_EVT_OUT_EOF_CH1 trigger sta- tus. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST Represents GDMA_EVT_OUT_EOF_CH2 trigger sta- tus. 0: Not triggered 1: Triggered (R/WTC/SS) Continued on the next page... Espressif Systems 429 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.7. SOC_ETM_EVT_ST4_REG (0x01C8) Continued from the previous page... SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST Represents GDMA_EVT_OUT_TOTAL_EOF_CH0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST Represents GDMA_EVT_OUT_TOTAL_EOF_CH1 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST Represents GDMA_EVT_OUT_TOTAL_EOF_CH2 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST Represents GDMA_EVT_OUT_FIFO_EMPTY_CH0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST Represents GDMA_EVT_OUT_FIFO_EMPTY_CH1 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST Represents GDMA_EVT_OUT_FIFO_EMPTY_CH2 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST Represents GDMA_EVT_OUT_FIFO_FULL_CH0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) Continued on the next page... Espressif Systems 430 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.7. SOC_ETM_EVT_ST4_REG (0x01C8) Continued from the previous page... SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST Represents GDMA_EVT_OUT_FIFO_FULL_CH1 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST Represents GDMA_EVT_OUT_FIFO_FULL_CH2 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST Represents PMU_EVT_SLEEP_WEEKUP trigger sta- tus. 0: Not triggered 1: Triggered (R/WTC/SS) Espressif Systems 431 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.8. SOC_ETM_TASK_ST0_REG (0x01D0) SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST 0 31 SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST 0 30 SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST 0 29 SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST 0 28 SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST 0 27 SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST 0 26 SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST 0 25 SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST 0 24 SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST 0 23 SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST 0 22 SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST 0 21 SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST 0 20 SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST 0 19 SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST 0 18 SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST 0 17 SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST 0 16 SOC_ETM_GPIO_TASK_CH7_CLEAR_ST 0 15 SOC_ETM_GPIO_TASK_CH6_CLEAR_ST 0 14 SOC_ETM_GPIO_TASK_CH5_CLEAR_ST 0 13 SOC_ETM_GPIO_TASK_CH4_CLEAR_ST 0 12 SOC_ETM_GPIO_TASK_CH3_CLEAR_ST 0 11 SOC_ETM_GPIO_TASK_CH2_CLEAR_ST 0 10 SOC_ETM_GPIO_TASK_CH1_CLEAR_ST 0 9 SOC_ETM_GPIO_TASK_CH0_CLEAR_ST 0 8 SOC_ETM_GPIO_TASK_CH7_SET_ST 0 7 SOC_ETM_GPIO_TASK_CH6_SET_ST 0 6 SOC_ETM_GPIO_TASK_CH5_SET_ST 0 5 SOC_ETM_GPIO_TASK_CH4_SET_ST 0 4 SOC_ETM_GPIO_TASK_CH3_SET_ST 0 3 SOC_ETM_GPIO_TASK_CH2_SET_ST 0 2 SOC_ETM_GPIO_TASK_CH1_SET_ST 0 1 SOC_ETM_GPIO_TASK_CH0_SET_ST 0 0 Reset SOC_ETM_GPIO_TASK_CH0_SET_ST Represents GPIO_TASK_CH0_SET trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_TASK_CH1_SET_ST Represents GPIO_TASK_CH1_SET trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_TASK_CH2_SET_ST Represents GPIO_TASK_CH2_SET trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_TASK_CH3_SET_ST Represents GPIO_TASK_CH3_SET trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_TASK_CH4_SET_ST Represents GPIO_TASK_CH4_SET trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_TASK_CH5_SET_ST Represents GPIO_TASK_CH5_SET trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) Continued on the next page... Espressif Systems 432 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.8. SOC_ETM_TASK_ST0_REG (0x01D0) Continued from the previous page... SOC_ETM_GPIO_TASK_CH6_SET_ST Represents GPIO_TASK_CH6_SET trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_TASK_CH7_SET_ST Represents GPIO_TASK_CH7_SET trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_TASK_CH0_CLEAR_ST Represents GPIO_TASK_CH0_CLEAR trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_TASK_CH1_CLEAR_ST Represents GPIO_TASK_CH1_CLEAR trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_TASK_CH2_CLEAR_ST Represents GPIO_TASK_CH2_CLEAR trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_TASK_CH3_CLEAR_ST Represents GPIO_TASK_CH3_CLEAR trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_TASK_CH4_CLEAR_ST Represents GPIO_TASK_CH4_CLEAR trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_TASK_CH5_CLEAR_ST Represents GPIO_TASK_CH5_CLEAR trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) Continued on the next page... Espressif Systems 433 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.8. SOC_ETM_TASK_ST0_REG (0x01D0) Continued from the previous page... SOC_ETM_GPIO_TASK_CH6_CLEAR_ST Represents GPIO_TASK_CH6_CLEAR trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_TASK_CH7_CLEAR_ST Represents GPIO_TASK_CH7_CLEAR trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST Represents GPIO_TASK_CH0_TOGGLE trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST Represents GPIO_TASK_CH1_TOGGLE trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST Represents GPIO_TASK_CH2_TOGGLE trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST Represents GPIO_TASK_CH3_TOGGLE trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST Represents GPIO_TASK_CH4_TOGGLE trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST Represents GPIO_TASK_CH5_TOGGLE trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) Continued on the next page... Espressif Systems 434 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.8. SOC_ETM_TASK_ST0_REG (0x01D0) Continued from the previous page... SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST Represents GPIO_TASK_CH6_TOGGLE trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST Represents GPIO_TASK_CH7_TOGGLE trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST Represents LEDC_TASK_TIMER0_RES_UPDATE trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST Represents LEDC_TASK_TIMER1_RES_UPDATE trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST Represents LEDC_TASK_TIMER2_RES_UPDATE trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST Represents LEDC_TASK_TIMER3_RES_UPDATE trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST Represents LEDC_TASK_DUTY_SCALE_UPDATE_CH0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) Continued on the next page... Espressif Systems 435 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.8. SOC_ETM_TASK_ST0_REG (0x01D0) Continued from the previous page... SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST Represents LEDC_TASK_DUTY_SCALE_UPDATE_CH1 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST Represents LEDC_TASK_DUTY_SCALE_UPDATE_CH2 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST Represents LEDC_TASK_DUTY_SCALE_UPDATE_CH3 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) Espressif Systems 436 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.9. SOC_ETM_TASK_ST1_REG (0x01D8) SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST 0 31 SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST 0 30 SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST 0 29 SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST 0 28 SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST 0 27 SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST 0 26 SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST 0 25 SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST 0 24 SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST 0 23 SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST 0 22 SOC_ETM_LEDC_TASK_TIMER3_RST_ST 0 21 SOC_ETM_LEDC_TASK_TIMER2_RST_ST 0 20 SOC_ETM_LEDC_TASK_TIMER1_RST_ST 0 19 SOC_ETM_LEDC_TASK_TIMER0_RST_ST 0 18 SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST 0 17 SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST 0 16 SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST 0 15 SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST 0 14 SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST 0 13 SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST 0 12 SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST 0 11 SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST 0 10 SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST 0 9 SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST 0 8 SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST 0 7 SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST 0 6 SOC_ETM_LEDC_TASK_TIMER3_CAP_ST 0 5 SOC_ETM_LEDC_TASK_TIMER2_CAP_ST 0 4 SOC_ETM_LEDC_TASK_TIMER1_CAP_ST 0 3 SOC_ETM_LEDC_TASK_TIMER0_CAP_ST 0 2 SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST 0 1 SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST 0 0 Reset SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST Represents LEDC_TASK_DUTY_SCALE_UPDATE_CH4 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST Represents LEDC_TASK_DUTY_SCALE_UPDATE_CH5 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_TIMER0_CAP_ST Represents LEDC_TASK_TIMER0_CAP trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_TIMER1_CAP_ST Represents LEDC_TASK_TIMER1_CAP trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_TIMER2_CAP_ST Represents LEDC_TASK_TIMER2_CAP trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_TIMER3_CAP_ST Represents LEDC_TASK_TIMER3_CAP trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) Continued on the next page... Espressif Systems 437 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.9. SOC_ETM_TASK_ST1_REG (0x01D8) Continued from the previous page... SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST Represents LEDC_TASK_SIG_OUT_DIS_CH0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST Represents LEDC_TASK_SIG_OUT_DIS_CH1 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST Represents LEDC_TASK_SIG_OUT_DIS_CH2 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST Represents LEDC_TASK_SIG_OUT_DIS_CH3 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST Represents LEDC_TASK_SIG_OUT_DIS_CH4 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST Represents LEDC_TASK_SIG_OUT_DIS_CH5 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST Represents LEDC_TASK_OVF_CNT_RST_CH0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) Continued on the next page... Espressif Systems 438 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.9. SOC_ETM_TASK_ST1_REG (0x01D8) Continued from the previous page... SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST Represents LEDC_TASK_OVF_CNT_RST_CH1 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST Represents LEDC_TASK_OVF_CNT_RST_CH2 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST Represents LEDC_TASK_OVF_CNT_RST_CH3 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST Represents LEDC_TASK_OVF_CNT_RST_CH4 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST Represents LEDC_TASK_OVF_CNT_RST_CH5 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_TIMER0_RST_ST Represents LEDC_TASK_TIMER0_RST trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_TIMER1_RST_ST Represents LEDC_TASK_TIMER1_RST trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) Continued on the next page... Espressif Systems 439 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.9. SOC_ETM_TASK_ST1_REG (0x01D8) Continued from the previous page... SOC_ETM_LEDC_TASK_TIMER2_RST_ST Represents LEDC_TASK_TIMER2_RST trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_TIMER3_RST_ST Represents LEDC_TASK_TIMER3_RST trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST Represents LEDC_TASK_TIMER0_RESUME trig- ger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST Represents LEDC_TASK_TIMER1_RESUME trig- ger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST Represents LEDC_TASK_TIMER2_RESUME trig- ger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST Represents LEDC_TASK_TIMER3_RESUME trig- ger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST Represents LEDC_TASK_TIMER0_PAUSE trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) Continued on the next page... Espressif Systems 440 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.9. SOC_ETM_TASK_ST1_REG (0x01D8) Continued from the previous page... SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST Represents LEDC_TASK_TIMER1_PAUSE trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST Represents LEDC_TASK_TIMER2_PAUSE trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST Represents LEDC_TASK_TIMER3_PAUSE trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST Represents LEDC_TASK_GAMMA_RESTART_CH0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST Represents LEDC_TASK_GAMMA_RESTART_CH1 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) Espressif Systems 441 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.10. SOC_ETM_TASK_ST2_REG (0x01E0) SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST 0 31 SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST 0 30 SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST 0 29 SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST 0 28 SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST 0 27 SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST 0 26 SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST 0 25 SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST 0 24 SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST 0 23 SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST 0 22 SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST 0 21 SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST 0 20 SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST 0 19 SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST 0 18 SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST 0 17 SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST 0 16 SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST 0 15 SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST 0 14 SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST 0 13 SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST 0 12 SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST 0 11 SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST 0 10 SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST 0 9 SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST 0 8 SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST 0 7 SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST 0 6 SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST 0 5 SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST 0 4 SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST 0 3 SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST 0 2 SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST 0 1 SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST 0 0 Reset SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST Represents LEDC_TASK_GAMMA_RESTART_CH2 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST Represents LEDC_TASK_GAMMA_RESTART_CH3 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST Represents LEDC_TASK_GAMMA_RESTART_CH4 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST Represents LEDC_TASK_GAMMA_RESTART_CH5 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST Represents LEDC_TASK_GAMMA_PAUSE_CH0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) Continued on the next page... Espressif Systems 442 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.10. SOC_ETM_TASK_ST2_REG (0x01E0) Continued from the previous page... SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST Represents LEDC_TASK_GAMMA_PAUSE_CH1 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST Represents LEDC_TASK_GAMMA_PAUSE_CH2 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST Represents LEDC_TASK_GAMMA_PAUSE_CH3 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST Represents LEDC_TASK_GAMMA_PAUSE_CH4 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST Represents LEDC_TASK_GAMMA_PAUSE_CH5 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST Represents LEDC_TASK_GAMMA_RESUME_CH0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST Represents LEDC_TASK_GAMMA_RESUME_CH1 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) Continued on the next page... Espressif Systems 443 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.10. SOC_ETM_TASK_ST2_REG (0x01E0) Continued from the previous page... SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST Represents LEDC_TASK_GAMMA_RESUME_CH2 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST Represents LEDC_TASK_GAMMA_RESUME_CH3 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST Represents LEDC_TASK_GAMMA_RESUME_CH4 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST Represents LEDC_TASK_GAMMA_RESUME_CH5 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST Represents TG0_TASK_CNT_START_TIMER0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST Represents TG0_TASK_ALARM_START_TIMER0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST Represents TG0_TASK_CNT_STOP_TIMER0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) Continued on the next page... Espressif Systems 444 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.10. SOC_ETM_TASK_ST2_REG (0x01E0) Continued from the previous page... SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST Represents TG0_TASK_CNT_RELOAD_TIMER0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST Represents TG0_TASK_CNT_CAP_TIMER0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST Represents TG0_TASK_CNT_START_TIMER1 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST Represents TG0_TASK_ALARM_START_TIMER1 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST Represents TG0_TASK_CNT_STOP_TIMER1 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST Represents TG0_TASK_CNT_RELOAD_TIMER1 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST Represents TG0_TASK_CNT_CAP_TIMER1 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) Continued on the next page... Espressif Systems 445 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.10. SOC_ETM_TASK_ST2_REG (0x01E0) Continued from the previous page... SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST Represents TG1_TASK_CNT_START_TIMER0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST Represents TG1_TASK_ALARM_START_TIMER0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST Represents TG1_TASK_CNT_STOP_TIMER0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST Represents TG1_TASK_CNT_RELOAD_TIMER0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST Represents TG1_TASK_CNT_CAP_TIMER0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST Represents TG1_TASK_CNT_START_TIMER1 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) Espressif Systems 446 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.11. SOC_ETM_TASK_ST3_REG (0x01E8) (reserved) 0 0 31 30 SOC_ETM_ADC_TASK_STOP0_ST 0 29 SOC_ETM_ADC_TASK_START0_ST 0 28 (reserved) 0 27 SOC_ETM_ADC_TASK_SAMPLE0_ST 0 26 SOC_ETM_MCPWM0_TASK_CAP2_ST 0 25 SOC_ETM_MCPWM0_TASK_CAP1_ST 0 24 SOC_ETM_MCPWM0_TASK_CAP0_ST 0 23 SOC_ETM_MCPWM0_TASK_CLR2_OST_ST 0 22 SOC_ETM_MCPWM0_TASK_CLR1_OST_ST 0 21 SOC_ETM_MCPWM0_TASK_CLR0_OST_ST 0 20 SOC_ETM_MCPWM0_TASK_TZ2_OST_ST 0 19 SOC_ETM_MCPWM0_TASK_TZ1_OST_ST 0 18 SOC_ETM_MCPWM0_TASK_TZ0_OST_ST 0 17 SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST 0 16 SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST 0 15 SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST 0 14 SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST 0 13 SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST 0 12 SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST 0 11 SOC_ETM_MCPWM0_TASK_GEN_STOP_ST 0 10 SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST 0 9 SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST 0 8 SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST 0 7 SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST 0 6 SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST 0 5 SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST 0 4 SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST 0 3 SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST 0 2 SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST 0 1 SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST 0 0 Reset SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST Represents TG1_TASK_ALARM_START_TIMER1 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST Represents TG1_TASK_CNT_STOP_TIMER1 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST Represents TG1_TASK_CNT_RELOAD_TIMER1 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST Represents TG1_TASK_CNT_CAP_TIMER1 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST Represents MCPWM0_TASK_CMPR0_A_UP trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) Continued on the next page... Espressif Systems 447 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.11. SOC_ETM_TASK_ST3_REG (0x01E8) Continued from the previous page... SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST Represents MCPWM0_TASK_CMPR1_A_UP trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST Represents MCPWM0_TASK_CMPR2_A_UP trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST Represents MCPWM0_TASK_CMPR0_B_UP trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST Represents MCPWM0_TASK_CMPR1_B_UP trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST Represents MCPWM0_TASK_CMPR2_B_UP trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_TASK_GEN_STOP_ST Represents MCPWM0_TASK_GEN_STOP trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST Represents MCPWM0_TASK_TIMER0_SYN trig- ger status. 0: Not triggered 1: Triggered (R/WTC/SS) Continued on the next page... Espressif Systems 448 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.11. SOC_ETM_TASK_ST3_REG (0x01E8) Continued from the previous page... SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST Represents MCPWM0_TASK_TIMER1_SYN trig- ger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST Represents MCPWM0_TASK_TIMER2_SYN trig- ger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST Represents MCPWM0_TASK_TIMER0_PERIOD_UP trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST Represents MCPWM0_TASK_TIMER1_PERIOD_UP trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST Represents MCPWM0_TASK_TIMER2_PERIOD_UP trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_TASK_TZ0_OST_ST Represents MCPWM0_TASK_TZ0_OST trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_TASK_TZ1_OST_ST Represents MCPWM0_TASK_TZ1_OST trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_TASK_TZ2_OST_ST Represents MCPWM0_TASK_TZ2_OST trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) Continued on the next page... Espressif Systems 449 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.11. SOC_ETM_TASK_ST3_REG (0x01E8) Continued from the previous page... SOC_ETM_MCPWM0_TASK_CLR0_OST_ST Represents MCPWM0_TASK_CLR0_OST trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_TASK_CLR1_OST_ST Represents MCPWM0_TASK_CLR1_OST trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_TASK_CLR2_OST_ST Represents MCPWM0_TASK_CLR2_OST trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_TASK_CAP0_ST Represents MCPWM0_TASK_CAP0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_TASK_CAP1_ST Represents MCPWM0_TASK_CAP1 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_MCPWM0_TASK_CAP2_ST Represents MCPWM0_TASK_CAP2 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_ADC_TASK_SAMPLE0_ST Represents ADC_TASK_SAMPLE0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) Continued on the next page... Espressif Systems 450 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.11. SOC_ETM_TASK_ST3_REG (0x01E8) Continued from the previous page... SOC_ETM_ADC_TASK_START0_ST Represents ADC_TASK_START0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_ADC_TASK_STOP0_ST Represents ADC_TASK_STOP0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) Espressif Systems 451 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.12. SOC_ETM_TASK_ST4_REG (0x01F0) (reserved) 0 0 0 0 0 0 0 0 0 0 0 31 21 SOC_ETM_PMU_TASK_SLEEP_REQ_ST 0 20 SOC_ETM_GDMA_TASK_OUT_START_CH2_ST 0 19 SOC_ETM_GDMA_TASK_OUT_START_CH1_ST 0 18 SOC_ETM_GDMA_TASK_OUT_START_CH0_ST 0 17 SOC_ETM_GDMA_TASK_IN_START_CH2_ST 0 16 SOC_ETM_GDMA_TASK_IN_START_CH1_ST 0 15 SOC_ETM_GDMA_TASK_IN_START_CH0_ST 0 14 SOC_ETM_RTC_TASK_TRIGGERFLW_ST 0 13 SOC_ETM_RTC_TASK_CLR_ST 0 12 SOC_ETM_RTC_TASK_STOP_ST 0 11 SOC_ETM_RTC_TASK_START_ST 0 10 (reserved) 0 9 SOC_ETM_ULP_TASK_WAKEUP_CPU_ST 0 8 SOC_ETM_I2S0_TASK_STOP_TX_ST 0 7 SOC_ETM_I2S0_TASK_STOP_RX_ST 0 6 SOC_ETM_I2S0_TASK_START_TX_ST 0 5 SOC_ETM_I2S0_TASK_START_RX_ST 0 4 SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST 0 3 SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST 0 2 (reserved) 0 0 1 0 Reset SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST Represents TMP- SNSR_TASK_START_SAMPLE trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST Represents TMPSNSR_TASK_STOP_SAMPLE trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_I2S0_TASK_START_RX_ST Represents I2S0_TASK_START_RX trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_I2S0_TASK_START_TX_ST Represents I2S0_TASK_START_TX trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) Continued on the next page... Espressif Systems 452 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.12. SOC_ETM_TASK_ST4_REG (0x01F0) Continued from the previous page... SOC_ETM_I2S0_TASK_STOP_RX_ST Represents I2S0_TASK_STOP_RX trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_I2S0_TASK_STOP_TX_ST Represents I2S0_TASK_STOP_TX trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_ULP_TASK_WAKEUP_CPU_ST Represents ULP_TASK_WAKEUP_CPU trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_RTC_TASK_START_ST Represents RTC_TASK_START trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_RTC_TASK_STOP_ST Represents RTC_TASK_STOP trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_RTC_TASK_CLR_ST Represents RTC_TASK_CLR trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_RTC_TASK_TRIGGERFLW_ST Represents RTC_TASK_TRIGGERFLW trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) Continued on the next page... Espressif Systems 453 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.12. SOC_ETM_TASK_ST4_REG (0x01F0) Continued from the previous page... SOC_ETM_GDMA_TASK_IN_START_CH0_ST Represents GDMA_TASK_IN_START_CH0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GDMA_TASK_IN_START_CH1_ST Represents GDMA_TASK_IN_START_CH1 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GDMA_TASK_IN_START_CH2_ST Represents GDMA_TASK_IN_START_CH2 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GDMA_TASK_OUT_START_CH0_ST Represents GDMA_TASK_OUT_START_CH0 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GDMA_TASK_OUT_START_CH1_ST Represents GDMA_TASK_OUT_START_CH1 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_GDMA_TASK_OUT_START_CH2_ST Represents GDMA_TASK_OUT_START_CH2 trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) SOC_ETM_PMU_TASK_SLEEP_REQ_ST Represents PMU_TASK_SLEEP_REQ trigger status. 0: Not triggered 1: Triggered (R/WTC/SS) Espressif Systems 454 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.13. SOC_ETM_CH_ENA_AD0_SET_REG (0x0004) SOC_ETM_CH_ENABLE31 0 31 SOC_ETM_CH_ENABLE30 0 30 SOC_ETM_CH_ENABLE29 0 29 SOC_ETM_CH_ENABLE28 0 28 SOC_ETM_CH_ENABLE27 0 27 SOC_ETM_CH_ENABLE26 0 26 SOC_ETM_CH_ENABLE25 0 25 SOC_ETM_CH_ENABLE24 0 24 SOC_ETM_CH_ENABLE23 0 23 SOC_ETM_CH_ENABLE22 0 22 SOC_ETM_CH_ENABLE21 0 21 SOC_ETM_CH_ENABLE20 0 20 SOC_ETM_CH_ENABLE19 0 19 SOC_ETM_CH_ENABLE18 0 18 SOC_ETM_CH_ENABLE17 0 17 SOC_ETM_CH_ENABLE16 0 16 SOC_ETM_CH_ENABLE15 0 15 SOC_ETM_CH_ENABLE14 0 14 SOC_ETM_CH_ENABLE13 0 13 SOC_ETM_CH_ENABLE12 0 12 SOC_ETM_CH_ENABLE11 0 11 SOC_ETM_CH_ENABLE10 0 10 SOC_ETM_CH_ENABLE9 0 9 SOC_ETM_CH_ENABLE8 0 8 SOC_ETM_CH_ENABLE7 0 7 SOC_ETM_CH_ENABLE6 0 6 SOC_ETM_CH_ENABLE5 0 5 SOC_ETM_CH_ENABLE4 0 4 SOC_ETM_CH_ENABLE3 0 3 SOC_ETM_CH_ENABLE2 0 2 SOC_ETM_CH_ENABLE1 0 1 SOC_ETM_CH_ENABLE0 0 0 Reset SOC_ETM_CH_ENABLEn (n: 0-31) Configures whether or not to enable channel n. 0: Invalid. No effect 1: Enable (WT) Register 10.14. SOC_ETM_CH_ENA_AD0_CLR_REG (0x0008) SOC_ETM_CH_DISABLE31 0 31 SOC_ETM_CH_DISABLE30 0 30 SOC_ETM_CH_DISABLE29 0 29 SOC_ETM_CH_DISABLE28 0 28 SOC_ETM_CH_DISABLE27 0 27 SOC_ETM_CH_DISABLE26 0 26 SOC_ETM_CH_DISABLE25 0 25 SOC_ETM_CH_DISABLE24 0 24 SOC_ETM_CH_DISABLE23 0 23 SOC_ETM_CH_DISABLE22 0 22 SOC_ETM_CH_DISABLE21 0 21 SOC_ETM_CH_DISABLE20 0 20 SOC_ETM_CH_DISABLE19 0 19 SOC_ETM_CH_DISABLE18 0 18 SOC_ETM_CH_DISABLE17 0 17 SOC_ETM_CH_DISABLE16 0 16 SOC_ETM_CH_DISABLE15 0 15 SOC_ETM_CH_DISABLE14 0 14 SOC_ETM_CH_DISABLE13 0 13 SOC_ETM_CH_DISABLE12 0 12 SOC_ETM_CH_DISABLE11 0 11 SOC_ETM_CH_DISABLE10 0 10 SOC_ETM_CH_DISABLE9 0 9 SOC_ETM_CH_DISABLE8 0 8 SOC_ETM_CH_DISABLE7 0 7 SOC_ETM_CH_DISABLE6 0 6 SOC_ETM_CH_DISABLE5 0 5 SOC_ETM_CH_DISABLE4 0 4 SOC_ETM_CH_DISABLE3 0 3 SOC_ETM_CH_DISABLE2 0 2 SOC_ETM_CH_DISABLE1 0 1 SOC_ETM_CH_DISABLE0 0 0 Reset SOC_ETM_CH_DISABLEn (n: 0-31) Configures whether or not to disable channel n. 0: Invalid. No effect 1: Clear (WT) Espressif Systems 455 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.15. SOC_ETM_CH_ENA_AD1_SET_REG (0x0010) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 18 SOC_ETM_CH_ENABLE49 0 17 SOC_ETM_CH_ENABLE48 0 16 SOC_ETM_CH_ENABLE47 0 15 SOC_ETM_CH_ENABLE46 0 14 SOC_ETM_CH_ENABLE45 0 13 SOC_ETM_CH_ENABLE44 0 12 SOC_ETM_CH_ENABLE43 0 11 SOC_ETM_CH_ENABLE42 0 10 SOC_ETM_CH_ENABLE41 0 9 SOC_ETM_CH_ENABLE40 0 8 SOC_ETM_CH_ENABLE39 0 7 SOC_ETM_CH_ENABLE38 0 6 SOC_ETM_CH_ENABLE37 0 5 SOC_ETM_CH_ENABLE36 0 4 SOC_ETM_CH_ENABLE35 0 3 SOC_ETM_CH_ENABLE34 0 2 SOC_ETM_CH_ENABLE33 0 1 SOC_ETM_CH_ENABLE32 0 0 Reset SOC_ETM_CH_ENABLEn (n: 32-49) Configures whether or not to enable channel n. 0: Invalid. No effect 1: Enable (WT) Register 10.16. SOC_ETM_CH_ENA_AD1_CLR_REG (0x0014) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 18 SOC_ETM_CH_DISABLE49 0 17 SOC_ETM_CH_DISABLE48 0 16 SOC_ETM_CH_DISABLE47 0 15 SOC_ETM_CH_DISABLE46 0 14 SOC_ETM_CH_DISABLE45 0 13 SOC_ETM_CH_DISABLE44 0 12 SOC_ETM_CH_DISABLE43 0 11 SOC_ETM_CH_DISABLE42 0 10 SOC_ETM_CH_DISABLE41 0 9 SOC_ETM_CH_DISABLE40 0 8 SOC_ETM_CH_DISABLE39 0 7 SOC_ETM_CH_DISABLE38 0 6 SOC_ETM_CH_DISABLE37 0 5 SOC_ETM_CH_DISABLE36 0 4 SOC_ETM_CH_DISABLE35 0 3 SOC_ETM_CH_DISABLE34 0 2 SOC_ETM_CH_DISABLE33 0 1 SOC_ETM_CH_DISABLE32 0 0 Reset SOC_ETM_CH_DISABLEn (n: 32-49) Configures whether or not to disable channel n. 0: Invalid. No effect 1: Clear (WT) Register 10.17. SOC_ETM_CHn_EVT_ID_REG (n: 0-49) (0x0018+0x8*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 SOC_ETM_CH0_EVT_ID 0 7 0 Reset SOC_ETM_CHn_EVT_ID Configures channel n event ID. (R/W) Espressif Systems 456 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.18. SOC_ETM_CHn_TASK_ID_REG (n: 0-49) (0x001C+0x8*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 SOC_ETM_CH0_TASK_ID 0 7 0 Reset SOC_ETM_CHn_TASK_ID Configures channel n task ID. (R/W) Espressif Systems 457 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.19. SOC_ETM_EVT_ST0_CLR_REG (0x01AC) SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR 0 31 SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR 0 30 SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR 0 29 SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR 0 28 SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR 0 27 SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR 0 26 SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_CLR 0 25 SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_CLR 0 24 SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR 0 23 SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR 0 22 SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR 0 21 SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR 0 20 SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR 0 19 SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR 0 18 SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR 0 17 SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR 0 16 SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR 0 15 SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR 0 14 SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR 0 13 SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR 0 12 SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR 0 11 SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR 0 10 SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR 0 9 SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR 0 8 SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR 0 7 SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR 0 6 SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR 0 5 SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR 0 4 SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR 0 3 SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR 0 2 SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR 0 1 SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR 0 0 Reset SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR Configures whether or not to clear GPIO_EVT_CH0_RISE_EDGE trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR Configures whether or not to clear GPIO_EVT_CH1_RISE_EDGE trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR Configures whether or not to clear GPIO_EVT_CH2_RISE_EDGE trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR Configures whether or not to clear GPIO_EVT_CH3_RISE_EDGE trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR Configures whether or not to clear GPIO_EVT_CH4_RISE_EDGE trigger status. 0: Invalid. No effect 1: Clear (WT) Continued on the next page... Espressif Systems 458 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.19. SOC_ETM_EVT_ST0_CLR_REG (0x01AC) Continued from the previous page... SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR Configures whether or not to clear GPIO_EVT_CH5_RISE_EDGE trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR Configures whether or not to clear GPIO_EVT_CH6_RISE_EDGE trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR Configures whether or not to clear GPIO_EVT_CH7_RISE_EDGE trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR Configures whether or not to clear GPIO_EVT_CH0_FALL_EDGE trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR Configures whether or not to clear GPIO_EVT_CH1_FALL_EDGE trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR Configures whether or not to clear GPIO_EVT_CH2_FALL_EDGE trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR Configures whether or not to clear GPIO_EVT_CH3_FALL_EDGE trigger status. 0: Invalid. No effect 1: Clear (WT) Continued on the next page... Espressif Systems 459 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.19. SOC_ETM_EVT_ST0_CLR_REG (0x01AC) Continued from the previous page... SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR Configures whether or not to clear GPIO_EVT_CH4_FALL_EDGE trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR Configures whether or not to clear GPIO_EVT_CH5_FALL_EDGE trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR Configures whether or not to clear GPIO_EVT_CH6_FALL_EDGE trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR Configures whether or not to clear GPIO_EVT_CH7_FALL_EDGE trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR Configures whether or not to clear GPIO_EVT_CH0_ANY_EDGE trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR Configures whether or not to clear GPIO_EVT_CH1_ANY_EDGE trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR Configures whether or not to clear GPIO_EVT_CH2_ANY_EDGE trigger status. 0: Invalid. No effect 1: Clear (WT) Continued on the next page... Espressif Systems 460 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.19. SOC_ETM_EVT_ST0_CLR_REG (0x01AC) Continued from the previous page... SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR Configures whether or not to clear GPIO_EVT_CH3_ANY_EDGE trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR Configures whether or not to clear GPIO_EVT_CH4_ANY_EDGE trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR Configures whether or not to clear GPIO_EVT_CH5_ANY_EDGE trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR Configures whether or not to clear GPIO_EVT_CH6_ANY_EDGE trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR Configures whether or not to clear GPIO_EVT_CH7_ANY_EDGE trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_CLR Configures whether or not to clear GPIO_EVT_ZERO_DET_POS0 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_CLR Configures whether or not to clear GPIO_EVT_ZERO_DET_NEG0 trigger status. 0: Invalid. No effect 1: Clear (WT) Continued on the next page... Espressif Systems 461 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.19. SOC_ETM_EVT_ST0_CLR_REG (0x01AC) Continued from the previous page... SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR Configures whether or not to clear LEDC_EVT_DUTY_CHNG_END_CH0 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR Configures whether or not to clear LEDC_EVT_DUTY_CHNG_END_CH1 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR Configures whether or not to clear LEDC_EVT_DUTY_CHNG_END_CH2 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR Configures whether or not to clear LEDC_EVT_DUTY_CHNG_END_CH3 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR Configures whether or not to clear LEDC_EVT_DUTY_CHNG_END_CH4 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR Configures whether or not to clear LEDC_EVT_DUTY_CHNG_END_CH5 trigger status. 0: Invalid. No effect 1: Clear (WT) Espressif Systems 462 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.20. SOC_ETM_EVT_ST1_CLR_REG (0x01B4) SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_CLR 0 31 SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_CLR 0 30 SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_CLR 0 29 SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_CLR 0 28 SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_CLR 0 27 SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_CLR 0 26 SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_CLR 0 25 SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_CLR 0 24 SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_CLR 0 23 SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_CLR 0 22 SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_CLR 0 21 SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR 0 20 SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR 0 19 SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR 0 18 SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR 0 17 SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR 0 16 SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR 0 15 SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR 0 14 SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR 0 13 SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR 0 12 SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR 0 11 SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR 0 10 SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR 0 9 SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR 0 8 SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR 0 7 SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR 0 6 SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR 0 5 SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR 0 4 SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR 0 3 SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR 0 2 SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR 0 1 SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR 0 0 Reset SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR Configures whether or not to clear LEDC_EVT_OVF_CNT_PLS_CH0 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR Configures whether or not to clear LEDC_EVT_OVF_CNT_PLS_CH1 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR Configures whether or not to clear LEDC_EVT_OVF_CNT_PLS_CH2 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR Configures whether or not to clear LEDC_EVT_OVF_CNT_PLS_CH3 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR Configures whether or not to clear LEDC_EVT_OVF_CNT_PLS_CH4 trigger status. 0: Invalid. No effect 1: Clear (WT) Continued on the next page... Espressif Systems 463 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.20. SOC_ETM_EVT_ST1_CLR_REG (0x01B4) Continued from the previous page... SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR Configures whether or not to clear LEDC_EVT_OVF_CNT_PLS_CH5 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR Configures whether or not to clear LEDC_EVT_TIME_OVF_TIMER0 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR Configures whether or not to clear LEDC_EVT_TIME_OVF_TIMER1 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR Configures whether or not to clear LEDC_EVT_TIME_OVF_TIMER2 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR Configures whether or not to clear LEDC_EVT_TIME_OVF_TIMER3 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR Configures whether or not to clear LEDC_EVT_TIMER0_CMP trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR Configures whether or not to clear LEDC_EVT_TIMER1_CMP trigger status. 0: Invalid. No effect 1: Clear (WT) Continued on the next page... Espressif Systems 464 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.20. SOC_ETM_EVT_ST1_CLR_REG (0x01B4) Continued from the previous page... SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR Configures whether or not to clear LEDC_EVT_TIMER2_CMP trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR Configures whether or not to clear LEDC_EVT_TIMER3_CMP trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR Configures whether or not to clear TG0_EVT_CNT_CMP_TIMER0 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR Configures whether or not to clear TG0_EVT_CNT_CMP_TIMER1 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR Configures whether or not to clear TG1_EVT_CNT_CMP_TIMER0 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR Configures whether or not to clear TG1_EVT_CNT_CMP_TIMER1 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR Configures whether or not to clear SYS- TIMER_EVT_CNT_CMP0 trigger status. 0: Invalid. No effect 1: Clear (WT) Continued on the next page... Espressif Systems 465 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.20. SOC_ETM_EVT_ST1_CLR_REG (0x01B4) Continued from the previous page... SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR Configures whether or not to clear SYS- TIMER_EVT_CNT_CMP1 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR Configures whether or not to clear SYS- TIMER_EVT_CNT_CMP2 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_CLR Configures whether or not to clear MCPWM0_EVT_TIMER0_STOP trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_CLR Configures whether or not to clear MCPWM0_EVT_TIMER1_STOP trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_CLR Configures whether or not to clear MCPWM0_EVT_TIMER2_STOP trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_CLR Configures whether or not to clear MCPWM0_EVT_TIMER0_TEZ trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_CLR Configures whether or not to clear MCPWM0_EVT_TIMER1_TEZ trigger status. 0: Invalid. No effect 1: Clear (WT) Continued on the next page... Espressif Systems 466 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.20. SOC_ETM_EVT_ST1_CLR_REG (0x01B4) Continued from the previous page... SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_CLR Configures whether or not to clear MCPWM0_EVT_TIMER2_TEZ trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_CLR Configures whether or not to clear MCPWM0_EVT_TIMER0_TEP trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_CLR Configures whether or not to clear MCPWM0_EVT_TIMER1_TEP trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_CLR Configures whether or not to clear MCPWM0_EVT_TIMER2_TEP trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_CLR Configures whether or not to clear MCPWM0_EVT_OP0_TEA trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_CLR Configures whether or not to clear MCPWM0_EVT_OP1_TEA trigger status. 0: Invalid. No effect 1: Clear (WT) Espressif Systems 467 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.21. SOC_ETM_EVT_ST2_CLR_REG (0x01BC) SOC_ETM_ADC_EVT_STOPPED0_ST_CLR 0 31 SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR 0 30 SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR 0 29 SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR 0 28 SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR 0 27 SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR 0 26 SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR 0 25 SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_CLR 0 24 SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_CLR 0 23 SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_CLR 0 22 SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_CLR 0 21 SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_CLR 0 20 SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_CLR 0 19 SOC_ETM_MCPWM0_EVT_CAP2_ST_CLR 0 18 SOC_ETM_MCPWM0_EVT_CAP1_ST_CLR 0 17 SOC_ETM_MCPWM0_EVT_CAP0_ST_CLR 0 16 SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_CLR 0 15 SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_CLR 0 14 SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_CLR 0 13 SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_CLR 0 12 SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_CLR 0 11 SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_CLR 0 10 SOC_ETM_MCPWM0_EVT_F2_CLR_ST_CLR 0 9 SOC_ETM_MCPWM0_EVT_F1_CLR_ST_CLR 0 8 SOC_ETM_MCPWM0_EVT_F0_CLR_ST_CLR 0 7 SOC_ETM_MCPWM0_EVT_F2_ST_CLR 0 6 SOC_ETM_MCPWM0_EVT_F1_ST_CLR 0 5 SOC_ETM_MCPWM0_EVT_F0_ST_CLR 0 4 SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_CLR 0 3 SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_CLR 0 2 SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_CLR 0 1 SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_CLR 0 0 Reset SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_CLR Configures whether or not to clear MCPWM0_EVT_OP2_TEA trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_CLR Configures whether or not to clear MCPWM0_EVT_OP0_TEB trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_CLR Configures whether or not to clear MCPWM0_EVT_OP1_TEB trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_CLR Configures whether or not to clear MCPWM0_EVT_OP2_TEB trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_EVT_F0_ST_CLR Configures whether or not to clear MCPWM0_EVT_F0 trig- ger status. 0: Invalid. No effect 1: Clear (WT) Continued on the next page... Espressif Systems 468 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.21. SOC_ETM_EVT_ST2_CLR_REG (0x01BC) Continued from the previous page... SOC_ETM_MCPWM0_EVT_F1_ST_CLR Configures whether or not to clear MCPWM0_EVT_F1 trig- ger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_EVT_F2_ST_CLR Configures whether or not to clear MCPWM0_EVT_F2 trig- ger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_EVT_F0_CLR_ST_CLR Configures whether or not to clear MCPWM0_EVT_F0_CLR trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_EVT_F1_CLR_ST_CLR Configures whether or not to clear MCPWM0_EVT_F1_CLR trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_EVT_F2_CLR_ST_CLR Configures whether or not to clear MCPWM0_EVT_F2_CLR trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_CLR Configures whether or not to clear MCPWM0_EVT_TZ0_CBC trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_CLR Configures whether or not to clear MCPWM0_EVT_TZ1_CBC trigger status. 0: Invalid. No effect 1: Clear (WT) Continued on the next page... Espressif Systems 469 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.21. SOC_ETM_EVT_ST2_CLR_REG (0x01BC) Continued from the previous page... SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_CLR Configures whether or not to clear MCPWM0_EVT_TZ2_CBC trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_CLR Configures whether or not to clear MCPWM0_EVT_TZ0_OST trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_CLR Configures whether or not to clear MCPWM0_EVT_TZ1_OST trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_CLR Configures whether or not to clear MCPWM0_EVT_TZ2_OST trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_EVT_CAP0_ST_CLR Configures whether or not to clear MCPWM0_EVT_CAP0 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_EVT_CAP1_ST_CLR Configures whether or not to clear MCPWM0_EVT_CAP1 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_EVT_CAP2_ST_CLR Configures whether or not to clear MCPWM0_EVT_CAP2 trigger status. 0: Invalid. No effect 1: Clear (WT) Continued on the next page... Espressif Systems 470 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.21. SOC_ETM_EVT_ST2_CLR_REG (0x01BC) Continued from the previous page... SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_CLR Configures whether or not to clear MCPWM0_EVT_OP0_TEE1 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_CLR Configures whether or not to clear MCPWM0_EVT_OP1_TEE1 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_CLR Configures whether or not to clear MCPWM0_EVT_OP2_TEE1 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_CLR Configures whether or not to clear MCPWM0_EVT_OP0_TEE2 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_CLR Configures whether or not to clear MCPWM0_EVT_OP1_TEE2 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_CLR Configures whether or not to clear MCPWM0_EVT_OP2_TEE2 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR Configures whether or not to clear ADC_EVT_CONV_CMPLT0 trigger status. 0: Invalid. No effect 1: Clear (WT) Continued on the next page... Espressif Systems 471 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.21. SOC_ETM_EVT_ST2_CLR_REG (0x01BC) Continued from the previous page... SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR Configures whether or not to clear ADC_EVT_EQ_ABOVE_THRESH0 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR Configures whether or not to clear ADC_EVT_EQ_ABOVE_THRESH1 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR Configures whether or not to clear ADC_EVT_EQ_BELOW_THRESH0 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR Configures whether or not to clear ADC_EVT_EQ_BELOW_THRESH1 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR Configures whether or not to clear ADC_EVT_RESULT_DONE0 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_ADC_EVT_STOPPED0_ST_CLR Configures whether or not to clear ADC_EVT_STOPPED0 trigger status. 0: Invalid. No effect 1: Clear (WT) Espressif Systems 472 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.22. SOC_ETM_EVT_ST3_CLR_REG (0x01C4) SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST_CLR 0 31 SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST_CLR 0 30 SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST_CLR 0 29 SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST_CLR 0 28 SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST_CLR 0 27 SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST_CLR 0 26 SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST_CLR 0 25 SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_CLR 0 24 SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST_CLR 0 23 SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST_CLR 0 22 SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST_CLR 0 21 SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST_CLR 0 20 SOC_ETM_RTC_EVT_CMP_ST_CLR 0 19 SOC_ETM_RTC_EVT_OVF_ST_CLR 0 18 SOC_ETM_RTC_EVT_TICK_ST_CLR 0 17 SOC_ETM_ULP_EVT_START_INTR_ST_CLR 0 16 SOC_ETM_ULP_EVT_HALT_ST_CLR 0 15 SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR 0 14 SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR 0 13 SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR 0 12 SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR 0 11 SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR 0 10 SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR 0 9 (reserved) 0 0 0 0 0 0 0 0 8 1 SOC_ETM_ADC_EVT_STARTED0_ST_CLR 0 0 Reset SOC_ETM_ADC_EVT_STARTED0_ST_CLR Configures whether or not to clear ADC_EVT_STARTED0 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR Configures whether or not to clear TMP- SNSR_EVT_OVER_LIMIT trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR Configures whether or not to clear I2S0_EVT_RX_DONE trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR Configures whether or not to clear I2S0_EVT_TX_DONE trigger status. 0: Invalid. No effect 1: Clear (WT) Continued on the next page... Espressif Systems 473 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.22. SOC_ETM_EVT_ST3_CLR_REG (0x01C4) Continued from the previous page... SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR Configures whether or not to clear I2S0_EVT_X_WORDS_RECEIVED trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR Configures whether or not to clear I2S0_EVT_X_WORDS_SENT trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR Configures whether or not to clear ULP_EVT_ERR_INTR trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_ULP_EVT_HALT_ST_CLR Configures whether or not to clear ULP_EVT_HALT trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_ULP_EVT_START_INTR_ST_CLR Configures whether or not to clear ULP_EVT_START_INTR trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_RTC_EVT_TICK_ST_CLR Configures whether or not to clear RTC_EVT_TICK trigger sta- tus. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_RTC_EVT_OVF_ST_CLR Configures whether or not to clear RTC_EVT_OVF trigger sta- tus. 0: Invalid. No effect 1: Clear (WT) Continued on the next page... Espressif Systems 474 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.22. SOC_ETM_EVT_ST3_CLR_REG (0x01C4) Continued from the previous page... SOC_ETM_RTC_EVT_CMP_ST_CLR Configures whether or not to clear RTC_EVT_CMP trigger sta- tus. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST_CLR Configures whether or not to clear GDMA_EVT_IN_DONE_CH0 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST_CLR Configures whether or not to clear GDMA_EVT_IN_DONE_CH1 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST_CLR Configures whether or not to clear GDMA_EVT_IN_DONE_CH2 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST_CLR Configures whether or not to clear GDMA_EVT_IN_SUC_EOF_CH0 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_CLR Configures whether or not to clear GDMA_EVT_IN_SUC_EOF_CH1 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST_CLR Configures whether or not to clear GDMA_EVT_IN_SUC_EOF_CH2 trigger status. 0: Invalid. No effect 1: Clear (WT) Continued on the next page... Espressif Systems 475 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.22. SOC_ETM_EVT_ST3_CLR_REG (0x01C4) Continued from the previous page... SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST_CLR Configures whether or not to clear GDMA_EVT_IN_FIFO_EMPTY_CH0 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST_CLR Configures whether or not to clear GDMA_EVT_IN_FIFO_EMPTY_CH1 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST_CLR Configures whether or not to clear GDMA_EVT_IN_FIFO_EMPTY_CH2 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST_CLR Configures whether or not to clear GDMA_EVT_IN_FIFO_FULL_CH0 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST_CLR Configures whether or not to clear GDMA_EVT_IN_FIFO_FULL_CH1 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST_CLR Configures whether or not to clear GDMA_EVT_IN_FIFO_FULL_CH2 trigger status. 0: Invalid. No effect 1: Clear (WT) Espressif Systems 476 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.23. SOC_ETM_EVT_ST4_CLR_REG (0x01CC) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR 0 15 SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST_CLR 0 14 SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST_CLR 0 13 SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST_CLR 0 12 SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR 0 11 SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR 0 10 SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR 0 9 SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_CLR 0 8 SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_CLR 0 7 SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_CLR 0 6 SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST_CLR 0 5 SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST_CLR 0 4 SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST_CLR 0 3 SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST_CLR 0 2 SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST_CLR 0 1 SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST_CLR 0 0 Reset SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST_CLR Configures whether or not to clear GDMA_EVT_OUT_DONE_CH0 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST_CLR Configures whether or not to clear GDMA_EVT_OUT_DONE_CH1 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST_CLR Configures whether or not to clear GDMA_EVT_OUT_DONE_CH2 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST_CLR Configures whether or not to clear GDMA_EVT_OUT_EOF_CH0 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST_CLR Configures whether or not to clear GDMA_EVT_OUT_EOF_CH1 trigger status. 0: Invalid. No effect 1: Clear (WT) Continued on the next page... Espressif Systems 477 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.23. SOC_ETM_EVT_ST4_CLR_REG (0x01CC) Continued from the previous page... SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST_CLR Configures whether or not to clear GDMA_EVT_OUT_EOF_CH2 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_CLR Configures whether or not to clear GDMA_EVT_OUT_TOTAL_EOF_CH0 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_CLR Configures whether or not to clear GDMA_EVT_OUT_TOTAL_EOF_CH1 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_CLR Configures whether or not to clear GDMA_EVT_OUT_TOTAL_EOF_CH2 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR Configures whether or not to clear GDMA_EVT_OUT_FIFO_EMPTY_CH0 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR Configures whether or not to clear GDMA_EVT_OUT_FIFO_EMPTY_CH1 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR Configures whether or not to clear GDMA_EVT_OUT_FIFO_EMPTY_CH2 trigger status. 0: Invalid. No effect 1: Clear (WT) Continued on the next page... Espressif Systems 478 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.23. SOC_ETM_EVT_ST4_CLR_REG (0x01CC) Continued from the previous page... SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST_CLR Configures whether or not to clear GDMA_EVT_OUT_FIFO_FULL_CH0 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST_CLR Configures whether or not to clear GDMA_EVT_OUT_FIFO_FULL_CH1 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST_CLR Configures whether or not to clear GDMA_EVT_OUT_FIFO_FULL_CH2 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR Configures whether or not to clear PMU_EVT_SLEEP_WEEKUP trigger status. 0: Invalid. No effect 1: Clear (WT) Espressif Systems 479 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.24. SOC_ETM_TASK_ST0_CLR_REG (0x01D4) SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR 0 31 SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR 0 30 SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR 0 29 SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR 0 28 SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR 0 27 SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR 0 26 SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR 0 25 SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR 0 24 SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR 0 23 SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR 0 22 SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR 0 21 SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR 0 20 SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR 0 19 SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR 0 18 SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR 0 17 SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR 0 16 SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR 0 15 SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR 0 14 SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR 0 13 SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR 0 12 SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR 0 11 SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR 0 10 SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR 0 9 SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR 0 8 SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR 0 7 SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR 0 6 SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR 0 5 SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR 0 4 SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR 0 3 SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR 0 2 SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR 0 1 SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR 0 0 Reset SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR Configures whether or not to clear GPIO_TASK_CH0_SET trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR Configures whether or not to clear GPIO_TASK_CH1_SET trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR Configures whether or not to clear GPIO_TASK_CH2_SET trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR Configures whether or not to clear GPIO_TASK_CH3_SET trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR Configures whether or not to clear GPIO_TASK_CH4_SET trigger status. 0: Invalid. No effect 1: Clear (WT) Continued on the next page... Espressif Systems 480 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.24. SOC_ETM_TASK_ST0_CLR_REG (0x01D4) Continued from the previous page... SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR Configures whether or not to clear GPIO_TASK_CH5_SET trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR Configures whether or not to clear GPIO_TASK_CH6_SET trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR Configures whether or not to clear GPIO_TASK_CH7_SET trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR Configures whether or not to clear GPIO_TASK_CH0_CLEAR trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR Configures whether or not to clear GPIO_TASK_CH1_CLEAR trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR Configures whether or not to clear GPIO_TASK_CH2_CLEAR trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR Configures whether or not to clear GPIO_TASK_CH3_CLEAR trigger status. 0: Invalid. No effect 1: Clear (WT) Continued on the next page... Espressif Systems 481 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.24. SOC_ETM_TASK_ST0_CLR_REG (0x01D4) Continued from the previous page... SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR Configures whether or not to clear GPIO_TASK_CH4_CLEAR trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR Configures whether or not to clear GPIO_TASK_CH5_CLEAR trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR Configures whether or not to clear GPIO_TASK_CH6_CLEAR trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR Configures whether or not to clear GPIO_TASK_CH7_CLEAR trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR Configures whether or not to clear GPIO_TASK_CH0_TOGGLE trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR Configures whether or not to clear GPIO_TASK_CH1_TOGGLE trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR Configures whether or not to clear GPIO_TASK_CH2_TOGGLE trigger status. 0: Invalid. No effect 1: Clear (WT) Continued on the next page... Espressif Systems 482 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.24. SOC_ETM_TASK_ST0_CLR_REG (0x01D4) Continued from the previous page... SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR Configures whether or not to clear GPIO_TASK_CH3_TOGGLE trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR Configures whether or not to clear GPIO_TASK_CH4_TOGGLE trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR Configures whether or not to clear GPIO_TASK_CH5_TOGGLE trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR Configures whether or not to clear GPIO_TASK_CH6_TOGGLE trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR Configures whether or not to clear GPIO_TASK_CH7_TOGGLE trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR Configures whether or not to clear LEDC_TASK_TIMER0_RES_UPDATE trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR Configures whether or not to clear LEDC_TASK_TIMER1_RES_UPDATE trigger status. 0: Invalid. No effect 1: Clear (WT) Continued on the next page... Espressif Systems 483 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.24. SOC_ETM_TASK_ST0_CLR_REG (0x01D4) Continued from the previous page... SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR Configures whether or not to clear LEDC_TASK_TIMER2_RES_UPDATE trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR Configures whether or not to clear LEDC_TASK_TIMER3_RES_UPDATE trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR Configures whether or not to clear LEDC_TASK_DUTY_SCALE_UPDATE_CH0 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR Configures whether or not to clear LEDC_TASK_DUTY_SCALE_UPDATE_CH1 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR Configures whether or not to clear LEDC_TASK_DUTY_SCALE_UPDATE_CH2 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR Configures whether or not to clear LEDC_TASK_DUTY_SCALE_UPDATE_CH3 trigger status. 0: Invalid. No effect 1: Clear (WT) Espressif Systems 484 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.25. SOC_ETM_TASK_ST1_CLR_REG (0x01DC) SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR 0 31 SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR 0 30 SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR 0 29 SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR 0 28 SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR 0 27 SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR 0 26 SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR 0 25 SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR 0 24 SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR 0 23 SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR 0 22 SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR 0 21 SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR 0 20 SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR 0 19 SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR 0 18 SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR 0 17 SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR 0 16 SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR 0 15 SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR 0 14 SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR 0 13 SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR 0 12 SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR 0 11 SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR 0 10 SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR 0 9 SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR 0 8 SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR 0 7 SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR 0 6 SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR 0 5 SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR 0 4 SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR 0 3 SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR 0 2 SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR 0 1 SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR 0 0 Reset SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR Configures whether or not to clear LEDC_TASK_DUTY_SCALE_UPDATE_CH4 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR Configures whether or not to clear LEDC_TASK_DUTY_SCALE_UPDATE_CH5 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR Configures whether or not to clear LEDC_TASK_TIMER0_CAP trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR Configures whether or not to clear LEDC_TASK_TIMER1_CAP trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR Configures whether or not to clear LEDC_TASK_TIMER2_CAP trigger status. 0: Invalid. No effect 1: Clear (WT) Continued on the next page... Espressif Systems 485 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.25. SOC_ETM_TASK_ST1_CLR_REG (0x01DC) Continued from the previous page... SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR Configures whether or not to clear LEDC_TASK_TIMER3_CAP trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR Configures whether or not to clear LEDC_TASK_SIG_OUT_DIS_CH0 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR Configures whether or not to clear LEDC_TASK_SIG_OUT_DIS_CH1 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR Configures whether or not to clear LEDC_TASK_SIG_OUT_DIS_CH2 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR Configures whether or not to clear LEDC_TASK_SIG_OUT_DIS_CH3 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR Configures whether or not to clear LEDC_TASK_SIG_OUT_DIS_CH4 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR Configures whether or not to clear LEDC_TASK_SIG_OUT_DIS_CH5 trigger status. 0: Invalid. No effect 1: Clear (WT) Continued on the next page... Espressif Systems 486 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.25. SOC_ETM_TASK_ST1_CLR_REG (0x01DC) Continued from the previous page... SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR Configures whether or not to clear LEDC_TASK_OVF_CNT_RST_CH0 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR Configures whether or not to clear LEDC_TASK_OVF_CNT_RST_CH1 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR Configures whether or not to clear LEDC_TASK_OVF_CNT_RST_CH2 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR Configures whether or not to clear LEDC_TASK_OVF_CNT_RST_CH3 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR Configures whether or not to clear LEDC_TASK_OVF_CNT_RST_CH4 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR Configures whether or not to clear LEDC_TASK_OVF_CNT_RST_CH5 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR Configures whether or not to clear LEDC_TASK_TIMER0_RST trigger status. 0: Invalid. No effect 1: Clear (WT) Continued on the next page... Espressif Systems 487 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.25. SOC_ETM_TASK_ST1_CLR_REG (0x01DC) Continued from the previous page... SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR Configures whether or not to clear LEDC_TASK_TIMER1_RST trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR Configures whether or not to clear LEDC_TASK_TIMER2_RST trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR Configures whether or not to clear LEDC_TASK_TIMER3_RST trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR Configures whether or not to clear LEDC_TASK_TIMER0_RESUME trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR Configures whether or not to clear LEDC_TASK_TIMER1_RESUME trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR Configures whether or not to clear LEDC_TASK_TIMER2_RESUME trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR Configures whether or not to clear LEDC_TASK_TIMER3_RESUME trigger status. 0: Invalid. No effect 1: Clear (WT) Continued on the next page... Espressif Systems 488 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.25. SOC_ETM_TASK_ST1_CLR_REG (0x01DC) Continued from the previous page... SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR Configures whether or not to clear LEDC_TASK_TIMER0_PAUSE trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR Configures whether or not to clear LEDC_TASK_TIMER1_PAUSE trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR Configures whether or not to clear LEDC_TASK_TIMER2_PAUSE trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR Configures whether or not to clear LEDC_TASK_TIMER3_PAUSE trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR Configures whether or not to clear LEDC_TASK_GAMMA_RESTART_CH0 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR Configures whether or not to clear LEDC_TASK_GAMMA_RESTART_CH1 trigger status. 0: Invalid. No effect 1: Clear (WT) Espressif Systems 489 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.26. SOC_ETM_TASK_ST2_CLR_REG (0x01E4) SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR 0 31 SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR 0 30 SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR 0 29 SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR 0 28 SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR 0 27 SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR 0 26 SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR 0 25 SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR 0 24 SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR 0 23 SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR 0 22 SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR 0 21 SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR 0 20 SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR 0 19 SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR 0 18 SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR 0 17 SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR 0 16 SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR 0 15 SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR 0 14 SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR 0 13 SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR 0 12 SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR 0 11 SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR 0 10 SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR 0 9 SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR 0 8 SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR 0 7 SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR 0 6 SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR 0 5 SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR 0 4 SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR 0 3 SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR 0 2 SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR 0 1 SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR 0 0 Reset SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR Configures whether or not to clear LEDC_TASK_GAMMA_RESTART_CH2 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR Configures whether or not to clear LEDC_TASK_GAMMA_RESTART_CH3 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR Configures whether or not to clear LEDC_TASK_GAMMA_RESTART_CH4 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR Configures whether or not to clear LEDC_TASK_GAMMA_RESTART_CH5 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR Configures whether or not to clear LEDC_TASK_GAMMA_PAUSE_CH0 trigger status. 0: Invalid. No effect 1: Clear (WT) Continued on the next page... Espressif Systems 490 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.26. SOC_ETM_TASK_ST2_CLR_REG (0x01E4) Continued from the previous page... SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR Configures whether or not to clear LEDC_TASK_GAMMA_PAUSE_CH1 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR Configures whether or not to clear LEDC_TASK_GAMMA_PAUSE_CH2 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR Configures whether or not to clear LEDC_TASK_GAMMA_PAUSE_CH3 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR Configures whether or not to clear LEDC_TASK_GAMMA_PAUSE_CH4 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR Configures whether or not to clear LEDC_TASK_GAMMA_PAUSE_CH5 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR Configures whether or not to clear LEDC_TASK_GAMMA_RESUME_CH0 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR Configures whether or not to clear LEDC_TASK_GAMMA_RESUME_CH1 trigger status. 0: Invalid. No effect 1: Clear (WT) Continued on the next page... Espressif Systems 491 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.26. SOC_ETM_TASK_ST2_CLR_REG (0x01E4) Continued from the previous page... SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR Configures whether or not to clear LEDC_TASK_GAMMA_RESUME_CH2 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR Configures whether or not to clear LEDC_TASK_GAMMA_RESUME_CH3 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR Configures whether or not to clear LEDC_TASK_GAMMA_RESUME_CH4 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR Configures whether or not to clear LEDC_TASK_GAMMA_RESUME_CH5 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR Configures whether or not to clear TG0_TASK_CNT_START_TIMER0 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR Configures whether or not to clear TG0_TASK_ALARM_START_TIMER0 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR Configures whether or not to clear TG0_TASK_CNT_STOP_TIMER0 trigger status. 0: Invalid. No effect 1: Clear (WT) Continued on the next page... Espressif Systems 492 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.26. SOC_ETM_TASK_ST2_CLR_REG (0x01E4) Continued from the previous page... SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR Configures whether or not to clear TG0_TASK_CNT_RELOAD_TIMER0 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR Configures whether or not to clear TG0_TASK_CNT_CAP_TIMER0 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR Configures whether or not to clear TG0_TASK_CNT_START_TIMER1 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR Configures whether or not to clear TG0_TASK_ALARM_START_TIMER1 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR Configures whether or not to clear TG0_TASK_CNT_STOP_TIMER1 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR Configures whether or not to clear TG0_TASK_CNT_RELOAD_TIMER1 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR Configures whether or not to clear TG0_TASK_CNT_CAP_TIMER1 trigger status. 0: Invalid. No effect 1: Clear (WT) Continued on the next page... Espressif Systems 493 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.26. SOC_ETM_TASK_ST2_CLR_REG (0x01E4) Continued from the previous page... SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR Configures whether or not to clear TG1_TASK_CNT_START_TIMER0 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR Configures whether or not to clear TG1_TASK_ALARM_START_TIMER0 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR Configures whether or not to clear TG1_TASK_CNT_STOP_TIMER0 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR Configures whether or not to clear TG1_TASK_CNT_RELOAD_TIMER0 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR Configures whether or not to clear TG1_TASK_CNT_CAP_TIMER0 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR Configures whether or not to clear TG1_TASK_CNT_START_TIMER1 trigger status. 0: Invalid. No effect 1: Clear (WT) Espressif Systems 494 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.27. SOC_ETM_TASK_ST3_CLR_REG (0x01EC) (reserved) 0 0 31 30 SOC_ETM_ADC_TASK_STOP0_ST_CLR 0 29 SOC_ETM_ADC_TASK_START0_ST_CLR 0 28 (reserved) 0 27 SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR 0 26 SOC_ETM_MCPWM0_TASK_CAP2_ST_CLR 0 25 SOC_ETM_MCPWM0_TASK_CAP1_ST_CLR 0 24 SOC_ETM_MCPWM0_TASK_CAP0_ST_CLR 0 23 SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_CLR 0 22 SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_CLR 0 21 SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_CLR 0 20 SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_CLR 0 19 SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_CLR 0 18 SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_CLR 0 17 SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR 0 16 SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR 0 15 SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR 0 14 SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_CLR 0 13 SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_CLR 0 12 SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_CLR 0 11 SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_CLR 0 10 SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_CLR 0 9 SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_CLR 0 8 SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_CLR 0 7 SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_CLR 0 6 SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_CLR 0 5 SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_CLR 0 4 SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR 0 3 SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR 0 2 SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR 0 1 SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR 0 0 Reset SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR Configures whether or not to clear TG1_TASK_ALARM_START_TIMER1 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR Configures whether or not to clear TG1_TASK_CNT_STOP_TIMER1 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR Configures whether or not to clear TG1_TASK_CNT_RELOAD_TIMER1 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR Configures whether or not to clear TG1_TASK_CNT_CAP_TIMER1 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_CLR Configures whether or not to clear MCPWM0_TASK_CMPR0_A_UP trigger status. 0: Invalid. No effect 1: Clear (WT) Continued on the next page... Espressif Systems 495 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.27. SOC_ETM_TASK_ST3_CLR_REG (0x01EC) Continued from the previous page... SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_CLR Configures whether or not to clear MCPWM0_TASK_CMPR1_A_UP trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_CLR Configures whether or not to clear MCPWM0_TASK_CMPR2_A_UP trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_CLR Configures whether or not to clear MCPWM0_TASK_CMPR0_B_UP trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_CLR Configures whether or not to clear MCPWM0_TASK_CMPR1_B_UP trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_CLR Configures whether or not to clear MCPWM0_TASK_CMPR2_B_UP trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_CLR Configures whether or not to clear MCPWM0_TASK_GEN_STOP trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_CLR Configures whether or not to clear MCPWM0_TASK_TIMER0_SYN trigger status. 0: Invalid. No effect 1: Clear (WT) Continued on the next page... Espressif Systems 496 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.27. SOC_ETM_TASK_ST3_CLR_REG (0x01EC) Continued from the previous page... SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_CLR Configures whether or not to clear MCPWM0_TASK_TIMER1_SYN trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_CLR Configures whether or not to clear MCPWM0_TASK_TIMER2_SYN trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR Configures whether or not to clear MCPWM0_TASK_TIMER0_PERIOD_UP trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR Configures whether or not to clear MCPWM0_TASK_TIMER1_PERIOD_UP trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR Configures whether or not to clear MCPWM0_TASK_TIMER2_PERIOD_UP trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_CLR Configures whether or not to clear MCPWM0_TASK_TZ0_OST trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_CLR Configures whether or not to clear MCPWM0_TASK_TZ1_OST trigger status. 0: Invalid. No effect 1: Clear (WT) Continued on the next page... Espressif Systems 497 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.27. SOC_ETM_TASK_ST3_CLR_REG (0x01EC) Continued from the previous page... SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_CLR Configures whether or not to clear MCPWM0_TASK_TZ2_OST trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_CLR Configures whether or not to clear MCPWM0_TASK_CLR0_OST trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_CLR Configures whether or not to clear MCPWM0_TASK_CLR1_OST trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_CLR Configures whether or not to clear MCPWM0_TASK_CLR2_OST trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_TASK_CAP0_ST_CLR Configures whether or not to clear MCPWM0_TASK_CAP0 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_TASK_CAP1_ST_CLR Configures whether or not to clear MCPWM0_TASK_CAP1 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_MCPWM0_TASK_CAP2_ST_CLR Configures whether or not to clear MCPWM0_TASK_CAP2 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR Configures whether or not to clear ADC_TASK_SAMPLE0 trigger status. 0: Invalid. No effect 1: Clear (WT) Continued on the next page... Espressif Systems 498 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.27. SOC_ETM_TASK_ST3_CLR_REG (0x01EC) Continued from the previous page... SOC_ETM_ADC_TASK_START0_ST_CLR Configures whether or not to clear ADC_TASK_START0 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_ADC_TASK_STOP0_ST_CLR Configures whether or not to clear ADC_TASK_STOP0 trigger status. 0: Invalid. No effect 1: Clear (WT) Espressif Systems 499 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.28. SOC_ETM_TASK_ST4_CLR_REG (0x01F4) (reserved) 0 0 0 0 0 0 0 0 0 0 0 31 21 SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR 0 20 SOC_ETM_GDMA_TASK_OUT_START_CH2_ST_CLR 0 19 SOC_ETM_GDMA_TASK_OUT_START_CH1_ST_CLR 0 18 SOC_ETM_GDMA_TASK_OUT_START_CH0_ST_CLR 0 17 SOC_ETM_GDMA_TASK_IN_START_CH2_ST_CLR 0 16 SOC_ETM_GDMA_TASK_IN_START_CH1_ST_CLR 0 15 SOC_ETM_GDMA_TASK_IN_START_CH0_ST_CLR 0 14 SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR 0 13 SOC_ETM_RTC_TASK_CLR_ST_CLR 0 12 SOC_ETM_RTC_TASK_STOP_ST_CLR 0 11 SOC_ETM_RTC_TASK_START_ST_CLR 0 10 (reserved) 0 9 SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR 0 8 SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR 0 7 SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR 0 6 SOC_ETM_I2S0_TASK_START_TX_ST_CLR 0 5 SOC_ETM_I2S0_TASK_START_RX_ST_CLR 0 4 SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR 0 3 SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR 0 2 (reserved) 0 0 1 0 Reset SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR Configures whether or not to clear TMP- SNSR_TASK_START_SAMPLE trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR Configures whether or not to clear TMP- SNSR_TASK_STOP_SAMPLE trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_I2S0_TASK_START_RX_ST_CLR Configures whether or not to clear I2S0_TASK_START_RX trigger status. 0: Invalid. No effect 1: Clear (WT) Continued on the next page... Espressif Systems 500 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.28. SOC_ETM_TASK_ST4_CLR_REG (0x01F4) Continued from the previous page... SOC_ETM_I2S0_TASK_START_TX_ST_CLR Configures whether or not to clear I2S0_TASK_START_TX trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR Configures whether or not to clear I2S0_TASK_STOP_RX trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR Configures whether or not to clear I2S0_TASK_STOP_TX trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR Configures whether or not to clear ULP_TASK_WAKEUP_CPU trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_RTC_TASK_START_ST_CLR Configures whether or not to clear RTC_TASK_START trig- ger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_RTC_TASK_STOP_ST_CLR Configures whether or not to clear RTC_TASK_STOP trig- ger status. 0: Invalid. No effect 1: Clear (WT) Continued on the next page... Espressif Systems 501 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.28. SOC_ETM_TASK_ST4_CLR_REG (0x01F4) Continued from the previous page... SOC_ETM_RTC_TASK_CLR_ST_CLR Configures whether or not to clear RTC_TASK_CLR trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR Configures whether or not to clear RTC_TASK_TRIGGERFLW trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GDMA_TASK_IN_START_CH0_ST_CLR Configures whether or not to clear GDMA_TASK_IN_START_CH0 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GDMA_TASK_IN_START_CH1_ST_CLR Configures whether or not to clear GDMA_TASK_IN_START_CH1 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GDMA_TASK_IN_START_CH2_ST_CLR Configures whether or not to clear GDMA_TASK_IN_START_CH2 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GDMA_TASK_OUT_START_CH0_ST_CLR Configures whether or not to clear GDMA_TASK_OUT_START_CH0 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_GDMA_TASK_OUT_START_CH1_ST_CLR Configures whether or not to clear GDMA_TASK_OUT_START_CH1 trigger status. 0: Invalid. No effect 1: Clear (WT) Continued on the next page... Espressif Systems 502 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 10 Event Task Matrix (ETM) Register 10.28. SOC_ETM_TASK_ST4_CLR_REG (0x01F4) Continued from the previous page... SOC_ETM_GDMA_TASK_OUT_START_CH2_ST_CLR Configures whether or not to clear GDMA_TASK_OUT_START_CH2 trigger status. 0: Invalid. No effect 1: Clear (WT) SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR Configures whether or not to clear PMU_TASK_SLEEP_REQ trigger status. 0: Invalid. No effect 1: Clear (WT) Register 10.29. SOC_ETM_CLK_EN_REG (0x01F8) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 SOC_ETM_CLK_EN 0 0 Reset SOC_ETM_CLK_EN Configures whether or not to open register clock gate. 0: Open the clock gate only when application writes registers 1: Force open the clock gate for register (R/W) Register 10.30. SOC_ETM_DATE_REG (0x01FC) (reserved) 0 0 0 0 31 28 SOC_ETM_DATE 0x2311281 27 0 Reset SOC_ETM_DATE Version control register. (R/W) Espressif Systems 503 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 11 System Timer Chapter 11 System Timer 11.1 Overview ESP32-C5 provides a 52-bit system timer, which can be used to generate tick interrupts for the operating system, or be used as a general timer to generate periodic interrupts or one-time interrupts. 11.2 Features The system timer has the following features: • Two 52-bit counters and three 52-bit comparators • Software accessing registers clocked by APB_CLK • CNT_CLK used for counting, with an average frequency of 16 MHz in two counting cycles • 40 MHz/48 MHz XTAL_CLK as the clock source of CNT_CLK • 52-bit alarm values (t) and 26-bit alarm periods (δt) • Two modes to generate alarms: – Target mode: only a one-time alarm is generated based on the alarm value (t) – Period mode: periodic alarms are generated based on the alarm period (δt) • Three comparators generating three independent interrupts based on configured alarm value (t) or alarm period (δt) • Software configuring the reference count value. For example, the system timer is able to load back the sleep time recorded by RTC timer via software after Light-sleep • Able to stall or continue running when CPU stalls or enters the on-chip-debugging mode • Alarm for Event Task Matrix (ETM) event Espressif Systems 504 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 11 System Timer 11.3 System Timer Structure The timer consists of two counters: UNIT0 and UNIT1. The count values can be monitored by three comparators, COMP0, COMP1, and COMP2. See the timer block diagram in Figure 11.3-1. Figure 11.3-1. System Timer Structure 11.4 Clock Source Selection The counters and comparators use XTAL_CLK or RC_FAST_CLK as the clock sources. The clock source can be selected by configuring field PCR_SYSTIMER_FUNC_CLK_SEL in register PCR_SYSTIMER_FUNC_CLK_CONF_REG. After XTAL_CLK is scaled, a counter clock signal CNT_CLK clock is generated. The average clock frequency of CNT_CLK is 16 MHz, as shown in Figure 11.5-1. The timer counter is incremented by 1/16 µs on each CNT_CLK cycle. Software operation such as configuring registers is clocked by APB_CLK. For more information about APB_CLK, see Chapter 7 Reset and Clock. The following two bits of system registers are also used to control the system timer: • Set PCR_SYSTIMER_CLK_EN in register PCR_SYSTIMER_CONF_REG to enable APB_CLK signal to the system timer. • Set PCR_SYSTIMER_RST_EN in register PCR_SYSTIMER_CONF_REG to reset the system timer. Note that if the timer is reset, its registers will be restored to their default values. For more information, please refer to Chapter 7 Reset and Clock. Espressif Systems 505 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 11 System Timer 11.5 Functional Description Figure 11.5-1. System Timer Alarm Generation Figure 11.5-1 shows the procedure to generate alarm in system timer. In this process, one timer counter and one timer comparator are used. An alarm interrupt will be generated accordingly based on the comparison result in the comparator. 11.5.1 Counter The system timer has two 52-bit timer counters, shown as UNITn (n = 0 or 1). Their counting clock source is a 16 MHz clock, i.e. CNT_CLK. Whether UNITn works or not is controlled by three bits in register SYSTIMER_CONF_REG: • SYSTIMER_TIMER_UNITn_WORK_EN: set this bit to enable the counter UNITn in the system timer. • SYSTIMER_TIMER_UNITn_CORE0_STALL_EN: if this bit is set, the counter UNITn stops when CPU0 is stalled. The counter continues its counting after the CPU resumes. • SYSTIMER_TIMER_UNITn_CORE1_STALL_EN: if this bit is set, the counter UNITn stops when CPU1 is stalled. The counter continues its counting after the CPU resumes. The configuration of the bits to control the counter UNITn is shown below, assuming that CPU is stalled. Table 11.5-1. UNITn Configuration Bits SYSTIMER_TIMER_ SYSTIMER_TIMER_ SYSTIMER_TIMER_ Counter UNITn_WORK_EN UNITn_CORE0_STALL_EN UNITn_CORE1_STALL_EN UNITn 0 x * x * Not at work 1 x 1 Stop counting, but will con- tinue its counting after the CPU1 resumes 1 1 x Stop counting, but will con- tinue its counting after the CPU0 resumes 1 0 0 Keep counting * x: Don’t-care. Espressif Systems 506 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 11 System Timer When the counter UNITn is at work, the count value is incremented on each counting cycle. When the counter UNITn is stopped, the count value stops increasing and keeps unchanged. The lower 32 and higher 20 bits of the initial count value are loaded from the registers SYSTIMER_TIMER_UNITn_LOAD_LO and SYSTIMER_TIMER_UNITn_LOAD_HI. Writing 1 to the bit SYSTIMER_TIMER_UNITn_LOAD will trigger a reload event, and the current count value will be changed immediately. If UNITn is at work, the counter will continue to count up from the new reloaded value. Writing 1 to SYSTIMER_TIMER_UNITn_UPDATE will trigger an update event. The lower 32 and higher 20 bits of the current count value will be locked into the registers SYSTIMER_TIMER_UNITn_VALUE_LO and SYSTIMER_TIMER_UNITn_VALUE_HI, and then SYSTIMER_TIMER_UNITn_VALUE_VALID is asserted. Before the next update event, the values of SYSTIMER_TIMER_UNITn_VALUE_LO and SYSTIMER_TIMER_UNITn_VALUE_HI remain unchanged. 11.5.2 Comparator and Alarm The system timer has three 52-bit comparators, shown as COMPx (x = 0, 1, or 2). The comparators can generate independent interrupts based on different alarm values (t) or alarm periods (δt). Configure SYSTIMER_TARGETx_PERIOD_MODE to choose from the two alarm modes for each COMPx: • 1: period mode • 0: target mode In period mode, the alarm period (δt) is provided by the register SYSTIMER_TARGETx_PERIOD. Assuming that current count value is t1, when it reaches (t1 + δt), an alarm interrupt will be generated. When the count value reaches (t1 + 2×δt), another alarm interrupt also will be generated. By such way, periodic alarms are generated. In target mode, the lower 32 bits and higher 20 bits of the alarm value (t) are provided by SYSTIMER_TIMER_TARGETx_LO and SYSTIMER_TIMER_TARGETx_HI. Assuming that current count value is t2 (t2 <= t), an alarm interrupt will be generated when the count value reaches the alarm value (t). Unlike in period mode, only one alarm interrupt is generated in target mode. SYSTIMER_TARGETx_TIMER_UNIT_SEL is used to choose the count value from which timer counter to be compared to generate alarms: • 1: Use the count value from UNIT1 • 0: Use the count value from UNIT0 Finally, set SYSTIMER_TARGETx_WORK_EN and COMPx starts to compare the count value: • In target mode, COMPx compares it with the alarm value (t). • In period mode, COMPx compares it with the alarm period (t1 + n×δt). An alarm is generated when the count value equals to the alarm value (t) in target mode or to the start value + n×δt (n = 1, 2, 3...) in period mode. But if the alarm value (t) set in registers is less than the current count value, i.e., the target has already passed, when the current count value is larger than the alarm value (t) within a range (0 2 51 – 1), an alarm interrupt will also be generated immediately. No matter in target mode or period mode, the low 32 bits and high 20 bits of the real alarm value can always be read from SYSTIMER_TARGETx_LO_RO and SYSTIMER_TARGETx_HI_RO. The alarm trigger point and the relationship between current count value t c and the alarm value t t are shown below. Espressif Systems 507 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 11 System Timer Table 11.5-2. Trigger Point Relationship Between t c and t t Trigger Point t c - t t <= 0 t c = t t , an alarm is triggered. 0 <= t c - t t < 2 51 - 1 ( t c < 2 51 and t t < 2 51 , or t c >= 2 51 and t t >= 2 51 ) An alarm is triggered immediately. t c - t t >= 2 51 - 1 t c overflows after counting to its maximum value 52’hfffffffffffff, and then starts counting up from 0. When its value reaches t t , an alarm is triggered. 11.5.3 Event Task Matrix The system timer on ESP32-C5 supports the Event Task Matrix (ETM) function, which allows the system timer’s ETM tasks to be triggered by any peripherals’ ETM events, or system timer’s ETM events to trigger any peripherals’ ETM tasks. This section introduces the ETM tasks and events related to the system timer. For more information, please refer to Chapter 10 Event Task Matrix (ETM). The system timer can generate the following ETM event: • SYSTIMER_EVT_CNT_CMPx: Indicates the alarm events generated by COMPx. When SYSTIMER_ETM_EN is set to 1, the alarm events can trigger the ETM event. 11.5.4 Synchronization Operation The frequency of the clock used for software configuration is different from that of the clock driving the timer counters and comparators. Therefore, synchronization is required for configuring some registers. The steps are as follows: 1. Software writes specific values to configuration fields. See the first column in Table 11.5-3. 2. Software writes 1 to corresponding bits to start synchronization. See the second column in Table 11.5-3. Table 11.5-3. Synchronization Operation for Configuration Registers Configuration Fields Synchronization Enable Bit SYSTIMER_TIMER_UNITn_LOAD_LO SYSTIMER_TIMER_UNITn_LOAD_HI SYSTIMER_TIMER_UNITn_LOAD SYSTIMER_TARGETx_PERIOD SYSTIMER_TIMER_TARGETx_HI SYSTIMER_TIMER_TARGETx_LO SYSTIMER_TIMER_COMPx_LOAD The frequency of the clock used for software reading is different from that of the clock driving the timer counters and comparators. Therefore, synchronization is also needed for reading some registers. The steps are as follows: 1. Software writes specific values to the updating register SYSTIMER_TIMER_UNITn_UPDATE. Espressif Systems 508 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 11 System Timer 2. Software reads the corresponding bit SYSTIMER_TIMER_UNITn_VALUE_VALID to be valid to confirm synchronization is done. 3. Software reads the corresponding status registers SYSTIMER_TIMER_UNITn_VALUE_HI and SYSTIMER_TIMER_UNITn_VALUE_LO. 11.6 Interrupts ESP32-C5’s system timer can generate the following interrupt signals that will be sent to the Interrupt Matrix. • SYSTIMER_TARGET0_INT • SYSTIMER_TARGET1_INT • SYSTIMER_TARGET2_INT There are several internal interrupt sources from the system timer that can generate the above interrupt signals. The interrupt sources from the system timer are listed with their trigger conditions and the resulted interrupt signals in Table 11.6-1. Table 11.6-1. System Timer’s Internal Interrupt Sources Internal Interrupt Source Trigger Condition Interrupt Signal SYSTIMER_INT0 When COMP0 alarms SYSTIMER_TARGET0_INT SYSTIMER_INT1 When COMP1 alarms SYSTIMER_TARGET1_INT SYSTIMER_INT2 When COMP2 alarms SYSTIMER_TARGET2_INT The above interrupts are level-type alarm interrupts. The interrupt signal is asserted high when the comparator starts to alarm. Until the software clears the interrupt, it remains high. To enable interrupts, set the bit SYSTIMER_TARGETx_INT_ENA. Note: For definitions of interrupt, interrupt signal, interrupt source, and their correlations, please refer to Chapter 9 Interrupt Matrix > Section 9.2 Terminology. Each interrupt source can be configured by a common set of registers that are described in Section Interrupt Configuration Registers. The specific registers can be found in Section 11.8 Register Summary. 11.7 Programming Procedure When configuring COMPx and UNITn, please ensure the corresponding COMP and UNIT are at work. 11.7.1 Read Current Count Value 1. Set SYSTIMER_TIMER_UNITn_UPDATE to fill the current count value of COMPx into SYSTIMER_TIMER_UNITn_VALUE_HI and SYSTIMER_TIMER_UNITn_VALUE_LO. Espressif Systems 509 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 11 System Timer 2. Poll the reading of SYSTIMER_TIMER_UNITn_VALUE_VALID till it is 1. Then, user can read the count value from SYSTIMER_TIMER_UNITn_VALUE_HI and SYSTIMER_TIMER_UNITn_VALUE_LO. 3. Read the lower 32 bits and higher 20 bits from SYSTIMER_TIMER_UNITn_VALUE_LO and SYSTIMER_TIMER_UNITn_VALUE_HI respectively. 11.7.2 Configure a One-Time Alarm in Target Mode 1. Set SYSTIMER_TARGETx_TIMER_UNIT_SEL to select the counter (UNIT0 or UNIT1) used for comparison with COMPx. 2. Read the current count value with reference to Section 11.7.1. This value will be used to calculate the alarm value (t) in Step 4. 3. Clear SYSTIMER_TARGETx_PERIOD_MODE to enable target mode. 4. Set an alarm value (t), and fill its lower 32 bits into SYSTIMER_TIMER_TARGETx_LO, and the higher 20 bits into SYSTIMER_TIMER_TARGETx_HI. 5. Set SYSTIMER_TIMER_COMPx_LOAD to synchronize the alarm value (t) to COMPx, i.e., load the alarm value (t) to the COMPx. 6. Set SYSTIMER_TARGETx_WORK_EN to enable the selected COMPx. COMPx starts comparing the count value with the alarm value (t). 7. Set SYSTIMER_TARGETx_INT_ENA to enable the timer interrupt. When UNITn reaches the alarm value (t), a SYSTIMER_TARGETx_INT interrupt is triggered. 11.7.3 Configure Periodic Alarms in Period Mode 1. Set SYSTIMER_TARGETx_TIMER_UNIT_SEL to select the counter (UNIT0 or UNIT1) used for comparison with COMPx. 2. Set an alarm period (δt), and fill it into SYSTIMER_TARGETx_PERIOD. 3. Set SYSTIMER_TIMER_COMPx_LOAD to synchronize the alarm period (δt) to COMPx, i.e., load the alarm period (δt) to COMPx. 4. Clear and then set SYSTIMER_TARGETx_PERIOD_MODE to configure COMPx into period mode. 5. Set SYSTIMER_TARGETx_WORK_EN to enable the selected COMPx. COMPx starts comparing the count value with the sum of (start value + n×δt) (n = 1, 2, 3...). 6. Set SYSTIMER_TARGETx_INT_ENA to enable the timer interrupt. A SYSTIMER_TARGETx_INT interrupt is triggered when UNITn reaches start value + n×δt (n = 1, 2, 3...) set in Step 2. 11.7.4 Update After Light-sleep 1. Configure RTC timer before the chip goes to Light-sleep mode, to record the exact sleep time. For more information, see Chapter 2 Low-power Management [to be added later]. 2. Read the sleep time from the RTC timer when the chip wakes up from Light-sleep mode. 3. Read the current count value of system timer, see Section 11.7.1. Espressif Systems 510 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 11 System Timer 4. Convert the time value recorded by RTC timer from the clock cycles based on RTC_SLOW_CLK to that based on 16 MHz CNT_CLK. For example, if the frequency of RTC_SLOW_CLK is 32 kHz, the recorded RTC timer value should be converted by multiplying by 500. 5. Add the converted RTC value to the current count value of system timer: • Fill the new value into SYSTIMER_TIMER_UNITn_LOAD_LO (low 32 bits) and SYSTIMER_TIMER_UNITn_LOAD_HI (high 20 bits). • Set SYSTIMER_TIMER_UNITn_LOAD to load the new timer value into the system timer. By such way, the system timer is updated. Espressif Systems 511 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 11 System Timer 11.8 Register Summary The addresses in this section are relative to system timer base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Clock Control Register SYSTIMER_CONF_REG Configure system timer clock 0x0000 R/W UNIT0 Control and Configuration Registers SYSTIMER_UNIT0_OP_REG Read UNIT0 value to registers 0x0004 varies SYSTIMER_UNIT0_LOAD_HI_REG High 20 bits to be loaded to UNIT0 0x000C R/W SYSTIMER_UNIT0_LOAD_LO_REG Low 32 bits to be loaded to UNIT0 0x0010 R/W SYSTIMER_UNIT0_VALUE_HI_REG UNIT0 value, high 20 bits 0x0040 RO SYSTIMER_UNIT0_VALUE_LO_REG UNIT0 value, low 32 bits 0x0044 RO SYSTIMER_UNIT0_LOAD_REG UNIT0 synchronization register 0x005C WT UNIT1 Control and Configuration Registers SYSTIMER_UNIT1_OP_REG Read UNIT1 value to registers 0x0008 varies SYSTIMER_UNIT1_LOAD_HI_REG High 20 bits to be loaded to UNIT1 0x0014 R/W SYSTIMER_UNIT1_LOAD_LO_REG Low 32 bits to be loaded to UNIT1 0x0018 R/W SYSTIMER_UNIT1_VALUE_HI_REG UNIT1 value, high 20 bits 0x0048 RO SYSTIMER_UNIT1_VALUE_LO_REG UNIT1 value, low 32 bits 0x004C RO SYSTIMER_UNIT1_LOAD_REG UNIT1 synchronization register 0x0060 WT Comparator0 Control and Configuration Registers SYSTIMER_TARGET0_HI_REG Alarm value to be loaded to COMP0, high 20 bits 0x001C R/W SYSTIMER_TARGET0_LO_REG Alarm value to be loaded to COMP0, low 32 bits 0x0020 R/W SYSTIMER_TARGET0_CONF_REG Configure COMP0 alarm mode 0x0034 R/W SYSTIMER_COMP0_LOAD_REG COMP0 synchronization register 0x0050 WT Comparator1 Control and Configuration Registers SYSTIMER_TARGET1_HI_REG Alarm value to be loaded to COMP1, high 20 bits 0x0024 R/W SYSTIMER_TARGET1_LO_REG Alarm value to be loaded to COMP1, low 32 bits 0x0028 R/W SYSTIMER_TARGET1_CONF_REG Configure COMP1 alarm mode 0x0038 R/W SYSTIMER_COMP1_LOAD_REG COMP1 synchronization register 0x0054 WT Comparator2 Control and Configuration Registers SYSTIMER_TARGET2_HI_REG Alarm value to be loaded to COMP2, high 20 bits 0x002C R/W SYSTIMER_TARGET2_LO_REG Alarm value to be loaded to COMP2, low 32 bits 0x0030 R/W SYSTIMER_TARGET2_CONF_REG Configure COMP2 alarm mode 0x003C R/W SYSTIMER_COMP2_LOAD_REG COMP2 synchronization register 0x0058 WT Interrupt Registers SYSTIMER_INT_ENA_REG Interrupt enable register of system timer 0x0064 R/W SYSTIMER_INT_RAW_REG Interrupt raw register of system timer 0x0068 R/WTC/SS SYSTIMER_INT_CLR_REG Interrupt clear register of system timer 0x006C WT SYSTIMER_INT_ST_REG Interrupt status register of system timer 0x0070 RO COMP0 Status Registers Espressif Systems 512 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 11 System Timer Name Description Address Access SYSTIMER_REAL_TARGET0_LO_REG Actual target value of COMP0, low 32 bits 0x0074 RO SYSTIMER_REAL_TARGET0_HI_REG Actual target value of COMP0, high 20 bits 0x0078 RO COMP1 Status Registers SYSTIMER_REAL_TARGET1_LO_REG Actual target value of COMP1, low 32 bits 0x007C RO SYSTIMER_REAL_TARGET1_HI_REG Actual target value of COMP1, high 20 bits 0x0080 RO COMP2 Status Registers SYSTIMER_REAL_TARGET2_LO_REG Actual target value of COMP2, low 32 bits 0x0084 RO SYSTIMER_REAL_TARGET2_HI_REG Actual target value of COMP2, high 20 bits 0x0088 RO Version Register SYSTIMER_DATE_REG Version control register 0x00FC R/W Espressif Systems 513 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 11 System Timer 11.9 Registers The addresses in this section are relative to system timer base address provided in Table 4.3-2 in Chapter 4 System and Memory. Register 11.1. SYSTIMER_CONF_REG (0x0000) SYSTIMER_CLK_EN 0 31 SYSTIMER_TIMER_UNIT0_WORK_EN 1 30 SYSTIMER_TIMER_UNIT1_WORK_EN 0 29 SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN 0 28 SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN 0 27 SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN 1 26 SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN 1 25 SYSTIMER_TARGET0_WORK_EN 0 24 SYSTIMER_TARGET1_WORK_EN 0 23 SYSTIMER_TARGET2_WORK_EN 0 22 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21 2 SYSTIMER_ETM_EN 0 1 (reserved) 0 0 Reset SYSTIMER_ETM_EN Configures whether to enable generation of ETM events. 0: Disable 1: Enable (R/W) SYSTIMER_TARGET2_WORK_EN Configures whether to enable COMP2. 0: Disable 1: Enable (R/W) SYSTIMER_TARGET1_WORK_EN Configures whether to enable COMP1. See details in SYS- TIMER_TARGET2_WORK_EN. (R/W) SYSTIMER_TARGET0_WORK_EN Configures whether to enable COMP0. See details in SYS- TIMER_TARGET2_WORK_EN. (R/W) SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN Configures whether UNIT1 is stalled when CORE1 is stalled. 0: UNIT1 is not stalled. 1: UNIT1 is stalled. (R/W) SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN Configures whether UNIT1 is stalled when CORE0 is stalled. See details in SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN. (R/W) SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN Configures whether UNIT0 is stalled when CORE1 is stalled. See details in SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN. (R/W) SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN Configures whether UNIT0 is stalled when CORE0 is stalled. See details in SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN. (R/W) Continued on the next page... Espressif Systems 514 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 11 System Timer Register 11.1. SYSTIMER_CONF_REG (0x0000) Continued from the previous page... SYSTIMER_TIMER_UNIT1_WORK_EN Configures whether to enable UNIT1. 0: Disable 1: Enable (R/W) SYSTIMER_TIMER_UNIT0_WORK_EN Configures whether to enable UNIT0. 0: Disable 1: Enable (R/W) SYSTIMER_CLK_EN Configures register clock gating. 0: Only enable needed clock for register read or write operations. 1: Register clock is always enabled for read and write operations. (R/W) Register 11.2. SYSTIMER_UNIT0_OP_REG (0x0004) (reserved) 0 31 SYSTIMER_TIMER_UNIT0_UPDATE 0 30 SYSTIMER_TIMER_UNIT0_VALUE_VALID 0 29 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28 0 Reset SYSTIMER_TIMER_UNIT0_VALUE_VALID Represents whether UNIT0 value is synchronized and valid. 0: UNIT0 value is neither synchronized nor valid 1: UNIT0 value is synchronized and valid (R/SS/WTC) SYSTIMER_TIMER_UNIT0_UPDATE Configures whether to update timer UNIT0, i.e., reads the UNIT0 count value to SYSTIMER_TIMER_UNIT0_VALUE_HI and SYS- TIMER_TIMER_UNIT0_VALUE_LO. 0: No effect 1: Update timer UNIT0 (WT) Espressif Systems 515 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 11 System Timer Register 11.3. SYSTIMER_UNIT0_LOAD_HI_REG (0x000C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 31 20 SYSTIMER_TIMER_UNIT0_LOAD_HI 0 19 0 Reset SYSTIMER_TIMER_UNIT0_LOAD_HI Configures the value to be loaded to UNIT0, high 20 bits. (R/W) Register 11.4. SYSTIMER_UNIT0_LOAD_LO_REG (0x0010) SYSTIMER_TIMER_UNIT0_LOAD_LO 0 31 0 Reset SYSTIMER_TIMER_UNIT0_LOAD_LO Configures the value to be loaded to UNIT0, low 32 bits. (R/W) Register 11.5. SYSTIMER_UNIT0_VALUE_HI_REG (0x0040) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 31 20 SYSTIMER_TIMER_UNIT0_VALUE_HI 0 19 0 Reset SYSTIMER_TIMER_UNIT0_VALUE_HI Represents UNIT0 read value, high 20 bits. (RO) Espressif Systems 516 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 11 System Timer Register 11.6. SYSTIMER_UNIT0_VALUE_LO_REG (0x0044) SYSTIMER_TIMER_UNIT0_VALUE_LO 0 31 0 Reset SYSTIMER_TIMER_UNIT0_VALUE_LO Represents UNIT0 read value, low 32 bits. (RO) Register 11.7. SYSTIMER_UNIT0_LOAD_REG (0x005C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 SYSTIMER_TIMER_UNIT0_LOAD 0 0 Reset SYSTIMER_TIMER_UNIT0_LOAD Configures whether to reload the value of UNIT0, i.e., reloads the values of SYSTIMER_TIMER_UNIT0_VALUE_HI and SYSTIMER_TIMER_UNIT0_VALUE_LO to UNIT0. 0: No effect 1: Reload the value of UNIT0 (WT) Espressif Systems 517 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 11 System Timer Register 11.8. SYSTIMER_UNIT1_OP_REG (0x0008) (reserved) 0 31 SYSTIMER_TIMER_UNIT1_UPDATE 0 30 SYSTIMER_TIMER_UNIT1_VALUE_VALID 0 29 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28 0 Reset SYSTIMER_TIMER_UNIT1_VALUE_VALID Represents UNIT1 value is synchronized and valid. (R/SS/WTC) SYSTIMER_TIMER_UNIT1_UPDATE Configures whether to update timer UNIT1, i.e., reads the UNIT1 count value to SYSTIMER_TIMER_UNIT1_VALUE_HI and SYS- TIMER_TIMER_UNIT1_VALUE_LO. 0: No effect 1: Update timer UNIT1 (WT) Register 11.9. SYSTIMER_UNIT1_LOAD_HI_REG (0x0014) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 31 20 SYSTIMER_TIMER_UNIT1_LOAD_HI 0 19 0 Reset SYSTIMER_TIMER_UNIT1_LOAD_HI Configures the value to be loaded to UNIT1, high 20 bits. (R/W) Espressif Systems 518 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 11 System Timer Register 11.10. SYSTIMER_UNIT1_LOAD_LO_REG (0x0018) SYSTIMER_TIMER_UNIT1_LOAD_LO 0 31 0 Reset SYSTIMER_TIMER_UNIT1_LOAD_LO Configures the value to be loaded to UNIT1, low 32 bits. (R/W) Register 11.11. SYSTIMER_UNIT1_VALUE_HI_REG (0x0048) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 31 20 SYSTIMER_TIMER_UNIT1_VALUE_HI 0 19 0 Reset SYSTIMER_TIMER_UNIT1_VALUE_HI Represents UNIT1 read value, high 20 bits. (RO) Register 11.12. SYSTIMER_UNIT1_VALUE_LO_REG (0x004C) SYSTIMER_TIMER_UNIT1_VALUE_LO 0 31 0 Reset SYSTIMER_TIMER_UNIT1_VALUE_LO Represents UNIT1 read value, low 32 bits. (RO) Espressif Systems 519 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 11 System Timer Register 11.13. SYSTIMER_UNIT1_LOAD_REG (0x0060) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 SYSTIMER_TIMER_UNIT1_LOAD 0 0 Reset SYSTIMER_TIMER_UNIT1_LOAD Configures whether to reload the value of UNIT1, i.e., reload the values of SYSTIMER_TIMER_UNIT1_VALUE_HI and SYSTIMER_TIMER_UNIT1_VALUE_LO to UNIT1. 0: No effect 1: Reload the value of UNIT1 (WT) Register 11.14. SYSTIMER_TARGET0_HI_REG (0x001C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 31 20 SYSTIMER_TIMER_TARGET0_HI 0 19 0 Reset SYSTIMER_TIMER_TARGET0_HI Configures the alarm value to be loaded to COMP0, high 20 bits. (R/W) Register 11.15. SYSTIMER_TARGET0_LO_REG (0x0020) SYSTIMER_TIMER_TARGET0_LO 0 31 0 Reset SYSTIMER_TIMER_TARGET0_LO Configures the alarm value to be loaded to COMP0, low 32 bits. (R/W) Espressif Systems 520 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 11 System Timer Register 11.16. SYSTIMER_TARGET0_CONF_REG (0x0034) SYSTIMER_TARGET0_TIMER_UNIT_SEL 0 31 SYSTIMER_TARGET0_PERIOD_MODE 0 30 (reserved) 0 0 0 0 29 26 SYSTIMER_TARGET0_PERIOD 0x00000 25 0 Reset SYSTIMER_TARGET0_PERIOD Configures COMP0 alarm period. (R/W) SYSTIMER_TARGET0_PERIOD_MODE Selects the two alarm modes for COMP0. 0: Target mode 1: Period mode (R/W) SYSTIMER_TARGET0_TIMER_UNIT_SEL Chooses the count value for comparison with COMP0. 0: Use the count value from UNIT0 1: Use the count value from UNIT1 (R/W) Register 11.17. SYSTIMER_COMP0_LOAD_REG (0x0050) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 SYSTIMER_TIMER_COMP0_LOAD 0 0 Reset SYSTIMER_TIMER_COMP0_LOAD Configures whether to enable COMP0 synchronization, i.e., reload the alarm value/period to COMP0. 0: No effect 1: Enable COMP0 synchronization (WT) Espressif Systems 521 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 11 System Timer Register 11.18. SYSTIMER_TARGET1_HI_REG (0x0024) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 31 20 SYSTIMER_TIMER_TARGET1_HI 0 19 0 Reset SYSTIMER_TIMER_TARGET1_HI Configures the alarm value to be loaded to COMP1, high 20 bits. (R/W) Register 11.19. SYSTIMER_TARGET1_LO_REG (0x0028) SYSTIMER_TIMER_TARGET1_LO 0 31 0 Reset SYSTIMER_TIMER_TARGET1_LO Configures the alarm value to be loaded to COMP1, low 32 bits. (R/W) Espressif Systems 522 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 11 System Timer Register 11.20. SYSTIMER_TARGET1_CONF_REG (0x0038) SYSTIMER_TARGET1_TIMER_UNIT_SEL 0 31 SYSTIMER_TARGET1_PERIOD_MODE 0 30 (reserved) 0 0 0 0 29 26 SYSTIMER_TARGET1_PERIOD 0x00000 25 0 Reset SYSTIMER_TARGET1_PERIOD Configures COMP1 alarm period. (R/W) SYSTIMER_TARGET1_PERIOD_MODE Selects the two alarm modes for COMP1. See details in SYSTIMER_TARGET0_PERIOD_MODE. (R/W) SYSTIMER_TARGET1_TIMER_UNIT_SEL Chooses the count value for comparison with COMP1. See details in SYSTIMER_TARGET0_TIMER_UNIT_SEL. (R/W) Register 11.21. SYSTIMER_COMP1_LOAD_REG (0x0054) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 SYSTIMER_TIMER_COMP1_LOAD 0 0 Reset SYSTIMER_TIMER_COMP1_LOAD Configures whether to enable COMP1 synchronization, i.e., reload the alarm value/period to COMP1. 0: No effect 1: Enable COMP1 synchronization (WT) Espressif Systems 523 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 11 System Timer Register 11.22. SYSTIMER_TARGET2_HI_REG (0x002C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 31 20 SYSTIMER_TIMER_TARGET2_HI 0 19 0 Reset SYSTIMER_TIMER_TARGET2_HI Configures the alarm value to be loaded to COMP2, high 20 bits. (R/W) Register 11.23. SYSTIMER_TARGET2_LO_REG (0x0030) SYSTIMER_TIMER_TARGET2_LO 0 31 0 Reset SYSTIMER_TIMER_TARGET2_LO Configures the alarm value to be loaded to COMP2, low 32 bits. (R/W) Espressif Systems 524 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 11 System Timer Register 11.24. SYSTIMER_TARGET2_CONF_REG (0x003C) SYSTIMER_TARGET2_TIMER_UNIT_SEL 0 31 SYSTIMER_TARGET2_PERIOD_MODE 0 30 (reserved) 0 0 0 0 29 26 SYSTIMER_TARGET2_PERIOD 0x00000 25 0 Reset SYSTIMER_TARGET2_PERIOD Configures COMP2 alarm period. (R/W) SYSTIMER_TARGET2_PERIOD_MODE Configures Configures the two alarm modes for COMP2. See details in SYSTIMER_TARGET0_PERIOD_MODE. (R/W) SYSTIMER_TARGET2_TIMER_UNIT_SEL Chooses the count value for comparison with COMP2. See details in SYSTIMER_TARGET0_TIMER_UNIT_SEL. (R/W) Register 11.25. SYSTIMER_COMP2_LOAD_REG (0x0058) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 SYSTIMER_TIMER_COMP2_LOAD 0 0 Reset SYSTIMER_TIMER_COMP2_LOAD Configures whether to enable COMP2 synchronization, i.e., reload the alarm value/period to COMP2. 0: No effect 1: Enable COMP2 synchronization (WT) Espressif Systems 525 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 11 System Timer Register 11.26. SYSTIMER_INT_ENA_REG (0x0064) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 SYSTIMER_TARGET2_INT_ENA 0 2 SYSTIMER_TARGET1_INT_ENA 0 1 SYSTIMER_TARGET0_INT_ENA 0 0 Reset SYSTIMER_TARGET0_INT_ENA Write 1 to enable SYSTIMER_TARGET0_INT. (R/W) SYSTIMER_TARGET1_INT_ENA Write 1 to enable SYSTIMER_TARGET1_INT. (R/W) SYSTIMER_TARGET2_INT_ENA Write 1 to enable SYSTIMER_TARGET2_INT. (R/W) Register 11.27. SYSTIMER_INT_RAW_REG (0x0068) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 SYSTIMER_TARGET2_INT_RAW 0 2 SYSTIMER_TARGET1_INT_RAW 0 1 SYSTIMER_TARGET0_INT_RAW 0 0 Reset SYSTIMER_TARGET0_INT_RAW The raw interrupt status of SYSTIMER_TARGET0_INT. (R/WTC/SS) SYSTIMER_TARGET1_INT_RAW The raw interrupt status of SYSTIMER_TARGET1_INT. (R/WTC/SS) SYSTIMER_TARGET2_INT_RAW The raw interrupt status of SYSTIMER_TARGET2_INT. (R/WTC/SS) Espressif Systems 526 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 11 System Timer Register 11.28. SYSTIMER_INT_CLR_REG (0x006C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 SYSTIMER_TARGET2_INT_CLR 0 2 SYSTIMER_TARGET1_INT_CLR 0 1 SYSTIMER_TARGET0_INT_CLR 0 0 Reset SYSTIMER_TARGET0_INT_CLR Write 1 to clear SYSTIMER_TARGET0_INT. (WT) SYSTIMER_TARGET1_INT_CLR Write 1 to clear SYSTIMER_TARGET1_INT. (WT) SYSTIMER_TARGET2_INT_CLR Write 1 to clear SYSTIMER_TARGET2_INT. (WT) Register 11.29. SYSTIMER_INT_ST_REG (0x0070) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 SYSTIMER_TARGET2_INT_ST 0 2 SYSTIMER_TARGET1_INT_ST 0 1 SYSTIMER_TARGET0_INT_ST 0 0 Reset SYSTIMER_TARGET0_INT_ST The masked interrupt status of SYSTIMER_TARGET0_INT. (RO) SYSTIMER_TARGET1_INT_ST The masked interrupt status of SYSTIMER_TARGET1_INT. (RO) SYSTIMER_TARGET2_INT_ST The masked interrupt status of SYSTIMER_TARGET2_INT. (RO) Register 11.30. SYSTIMER_REAL_TARGET0_LO_REG (0x0074) SYSTIMER_TARGET0_LO_RO 0 31 0 Reset SYSTIMER_TARGET0_LO_RO Represents the actual target value of COMP0, low 32 bits. (RO) Espressif Systems 527 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 11 System Timer Register 11.31. SYSTIMER_REAL_TARGET0_HI_REG (0x0078) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 31 20 SYSTIMER_TARGET0_HI_RO 0 19 0 Reset SYSTIMER_TARGET0_HI_RO Represents the actual target value of COMP0, high 20 bits. (RO) Register 11.32. SYSTIMER_REAL_TARGET1_LO_REG (0x007C) SYSTIMER_TARGET1_LO_RO 0 31 0 Reset SYSTIMER_TARGET1_LO_RO Represents the actual target value of COMP1, low 32 bits. (RO) Register 11.33. SYSTIMER_REAL_TARGET1_HI_REG (0x0080) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 31 20 SYSTIMER_TARGET1_HI_RO 0 19 0 Reset SYSTIMER_TARGET1_HI_RO Represents the actual target value of COMP1, high 20 bits. (RO) Espressif Systems 528 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 11 System Timer Register 11.34. SYSTIMER_REAL_TARGET2_LO_REG (0x0084) SYSTIMER_TARGET2_LO_RO 0 31 0 Reset SYSTIMER_TARGET2_LO_RO Represents the actual target value of COMP2, low 32 bits. (RO) Register 11.35. SYSTIMER_REAL_TARGET2_HI_REG (0x0088) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 31 20 SYSTIMER_TARGET2_HI_RO 0 19 0 Reset SYSTIMER_TARGET2_HI_RO Represents the actual target value of COMP2, high 20 bits. (RO) Register 11.36. SYSTIMER_DATE_REG (0x00FC) SYSTIMER_DATE 0x2201073 31 0 Reset SYSTIMER_DATE Version control register. (R/W) Espressif Systems 529 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 12 Timer Group (TIMG) Chapter 12 Timer Group (TIMG) 12.1 Overview General-purpose timers can be used to precisely time an interval, trigger an interrupt after a particular interval (periodically and aperiodically), or act as a hardware clock. As shown in Figure 12.1-1, the ESP32-C5 chip contains two timer groups, namely timer group 0 and timer group 1. Each timer group consists of one general-purpose timer referred to as T0 and one Main System Watchdog Timer. The general-purpose timer is based on a 16-bit prescaler and a 54-bit auto-reload-capable up-down counter. Figure 12.1-1. Timer Group Overview Note that while the Main System Watchdog Timer registers are described in this chapter, their functional description is included in Chapter 13 Watchdog Timers (WDT). Therefore, the term ”timer” within this chapter refers to the general-purpose timer. 12.2 Feature List The timer’s features are summarized as follows: • A 54-bit time-base counter programmable to incrementing or decrementing • Three clock sources: PLL_F80M_CLK or XTAL_CLK or RC_FAST_CLK • A 16-bit clock prescaler, from 2 to 65536 • Able to read real-time value of the time-base counter • Able to halt and resume the time-base counter • Programmable alarm generation Espressif Systems 530 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 12 Timer Group (TIMG) • Timer value reload — Auto-reload at alarm or software-controlled instant reload • Frequency calculation of slow clock for timer group 0 • Level interrupt generation • Support several ETM tasks and events 12.3 Architectural Overview Figure 12.3-1. Timer Group Architecture Figure 12.3-1 is a diagram of timer T0 in a timer group. T0 contains a 16-bit integer divider as a prescaler, a timer-based counter, and a comparator for alarm generation. 12.4 Functional Description 12.4.1 16-bit Prescaler and Clock Selection Take the T0 in timer group 0 as an example: • The timer can select its clock source by setting the PCR_TG0_TIMER_CLK_SEL field of the PCR_TIMERGROUP0_TIMER_CLK_CONF_REG register. When the field is 0, CLK0 is selected, which indicates XTAL_CLK; when the field is 1, CLK1 is selected, which indicates RC_FAST_CLK; when the field is 2, CLK2 is selected, which indicates PLL_F80M_CLK. • The selected clock can be switched on by setting PCR_TG0_TIMER_CLK_EN field of the PCR_TIMERGROUP0_TIMER_CLK_CONF_REG register to 1 and switched off by setting it to 0. This field is indicated as TIMER_CLK_EN in Figure 12.3-1. The clock is then divided by a 16-bit prescaler to generate the time-base counter clock (TB_CLK) used by the time-base counter. The divisor of the prescaler can be configured through the TIMG_T0_DIVIDER field. TIMG_T0_DIVIDER field can be configured as 0 65535 for a divisor range of 2 65536. To be more specific, when TIMG_T0_DIVIDER is configured as: • 0: the divisor is 65536 • 1: the divisor is 2 • 2: the divisor is also 2 • 3 65525: the divisor is 3 65535 Espressif Systems 531 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 12 Timer Group (TIMG) To modify the 16-bit prescaler, please first configure the TIMG_T0_DIVIDER field, and then set TIMG_T0_DIVCNT_RST to 1. Meanwhile, the timer must be disabled (i.e., TIMG_T0_EN should be cleared). Otherwise, the result can be unpredictable. 12.4.2 54-bit Time-base Counter The 54-bit time-base counter is based on TB_CLK and can be configured to increment or decrement via the TIMG_T0_INCREASE field. The time-base counter can be enabled or disabled by setting or clearing the TIMG_T0_EN field, respectively. When enabled, the time-base counter increments or decrements on each cycle of TB_CLK. When disabled, the time-base counter is essentially frozen. Note that the TIMG_T0_INCREASE field can be changed no matter whether TIMG_T0_EN is set or not, and this will cause the time-base counter to change direction instantly. To read the 54-bit value of the time-base counter, the timer value must be latched to two registers before being read by the CPU (due to the CPU being 32-bit). By writing any value to the TIMG_T0UPDATE_REG, the current value of the 54-bit timer starts to be latched into the TIMG_T0LO_REG and TIMG_T0HI_REG registers containing the lower 32-bits and higher 22-bits, respectively. When TIMG_T0UPDATE_REG is cleared by hardware, it indicates the latch operation has been completed and current timer value can be read from the TIMG_T0LO_REG and TIMG_T0HI_REG registers. TIMG_T0LO_REG and TIMG_T0HI_REG registers will remain unchanged for the CPU to read in its own time until TIMG_T0UPDATE_REG is written to again. 12.4.3 Alarm Generation A timer can be configured to trigger an alarm when the timer’s current value matches the alarm value. An alarm will cause an interrupt to occur and (optionally) an automatic reload of the timer’s current value (see Section 12.4.4). The 54-bit alarm value is configured using TIMG_T0ALARMLO_REG and TIMG_T0ALARMHI_REG, which represent the lower 32-bits and higher 22-bits of the alarm value, respectively. However, the configured alarm value is ineffective until the alarm is enabled by setting the TIMG_T0_ALARM_EN field. To avoid alarm being enabled ”too late” (i.e., the timer value has already passed the alarm value when the alarm is enabled), the hardware will trigger the alarm immediately if the current timer value is: • higher than the alarm value (within a defined range) when the up-down counter increments • lower than the alarm value (within a defined range) when the up-down counter decrements Table 12.4-1 and Table 12.4-2 show the relationship between the current value of the timer, the alarm value, and when an alarm is triggered. The current time value and the alarm value are defined as follows: • TIMG_VALUE = {TIMG_T0HI_REG, TIMG_T0LO_REG} • ALARM_VALUE = {TIMG_T0ALARMHI_REG, TIMG_T0ALARMLO_REG} Espressif Systems 532 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 12 Timer Group (TIMG) Table 12.4-1. Alarm Generation When Up-Down Counter Increments Scenario Range Alarm 1 ALARM_VALUE − TIMG_VALUE > 2 53 Triggered 2 0 < ALARM_VALUE − TIMG_VALUE ≤ 2 53 Triggered when the up-down counter counts TIMG_VALUE up to ALARM_VALUE 3 0 ≤ TIMG_VALUE − ALARM_VALUE < 2 53 Triggered 4 TIMG_VALUE − ALARM_VALUE ≥ 2 53 Triggered when the up-down counter restarts counting up from 0 after reaching the timer’s maximum value and counts TIMG_VALUE up to ALARM_VALUE Table 12.4-2. Alarm Generation When Up-Down Counter Decrements Scenario Range Alarm 5 TIMG_VALUE − ALARM_VALUE > 2 53 Triggered 6 0 < TIMG_VALUE − ALARM_VALUE ≤ 2 53 Triggered when the up-down counter counts TIMG_VALUE down to ALARM_VALUE 7 0 ≤ ALARM_VALUE − TIMG_VALUE < 2 53 Triggered 8 ALARM_VALUE − TIMG_VALUE ≥ 2 53 Triggered when the up-down counter restarts counting down from the timer’s maximum value after reaching the minimum value and counts TIMG_VALUE down to ALARM_VALUE When an alarm occurs, the TIMG_T0_ALARM_EN field is automatically cleared and no alarm will occur again until the TIMG_T0_ALARM_EN is set next time. 12.4.4 Timer Reload A timer is reloaded when a timer’s current value is overwritten with a reload value stored in the TIMG_T0_LOAD_LO and TIMG_T0_LOAD_HI fields that correspond to the lower 32-bits and higher 22-bits of the timer’s new value, respectively. However, writing a reload value to TIMG_T0_LOAD_LO and TIMG_T0_LOAD_HI will not cause the timer’s current value to change. Instead, the reload value is ignored by the timer until a reload event occurs. A reload event can be triggered either by a software instant reload or an auto-reload at alarm. A software instant reload is triggered by the CPU writing any value to TIMG_T0LOAD_REG, which causes the timer’s current value to be instantly reloaded. If TIMG_T0_EN is set, the timer will continue incrementing or decrementing from the new value. In this case, if TIMG_T0_ALARM_EN is set, the timer will still trigger alarms in scenarios listed in Table 12.4-1 and 12.4-2. If TIMG_T0_EN is cleared, the timer will remain frozen at the new value until counting is re-enabled. An auto-reload at alarm will cause a timer reload when an alarm occurs, thus allowing the timer to continue incrementing or decrementing from the reload value. This is generally useful for resetting the timer’s value when using periodic alarms. To enable auto-reload at alarm, the TIMG_T0_AUTORELOAD field should be set. If not enabled, the timer’s value will continue to increment or decrement past the alarm value after an alarm. Espressif Systems 533 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 12 Timer Group (TIMG) 12.4.5 Frequency Calculation of Slow Clock for Timer Group 0 Using XTAL_CLK as a reference, it is possible to calculate the frequency of slow clock sources provided by ESP32-C5. For the slow clock inputted to the timer group, please refer to 9 Interrupt Matrix > 9.2 Terminology. The calculation method is as follows: 1. Start periodic or one-shot frequency calculation (see Section 12.7.5 for details); 2. Once receiving the signal to start calculation, the counter of XTAL_CLK and the counter of slow clock begin to work at the same time. When the counter of slow clock counts to C0, the two counters stop counting simultaneously; 3. Assume the value of XTAL_CLK’s counter is C1, and the frequency of slow clock would be calculated as: f_rtc = C0×f _XT AL_CLK C1 Please note that the input frequency should not be larger than f_XT AL_CLK 2 when calculating the frequency of slow clock. 12.5 Event Task Matrix Feature The timer groups on ESP32-C5 support the Event Task Matrix (ETM) function, which allows timer groups’ ETM tasks to be triggered by any peripherals’ ETM events, or timer groups’ ETM events to trigger any peripherals’ ETM tasks. This section introduces the ETM tasks and events related to timer groups. For more information, please refer to Chapter 10 Event Task Matrix (ETM). The timer groups can receive the following ETM tasks: • TG0_TASK_CNT_START_TIMER0: When triggered, it will enable the time-base counter. • TG1_TASK_CNT_START_TIMER0: When triggered, it will enable the time-base counter. • TG0_TASK_CNT_STOP_TIMER0: When triggered, it will disable the time-base counter. • TG1_TASK_CNT_STOP_TIMER0: When triggered, it will disable the time-base counter. Note: The above two ETM tasks have the same function as the APB configuration TIMG_T0_EN. When these operations occur at the same time, the priority of each operation from high to low is as follows: 1. TG0_TASK_CNT_START_TIMER0 and TG1_TASK_CNT_START_TIMER0: When triggered, it will enable the time-base counter; 2. TG0_TASK_CNT_STOP_TIMER0 and TG1_TASK_CNT_STOP_TIMER0: When triggered, it will disable the time-base counter; 3. APB configuration TIMG_T0_EN: When triggered, it will enable or disable the time-base counter. • TG0_TASK_ALARM_START_TIMER0: When triggered, it will enable the alarm generation. • TG1_TASK_ALARM_START_TIMER0: When triggered, it will enable the alarm generation. Note: Alarm generation can also be configured through APB method and hardware events. When these operations occur Espressif Systems 534 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 12 Timer Group (TIMG) at the same time, the priority of each operation from high to low is as follows: 1. TG0_TASK_ALARM_START_TIMER0 and TG1_TASK_ALARM_START_TIMER0: When triggered, it will en- able the alarm generation; 2. Alarm events: When triggered, it will disable the alarm generation; 3. APB configuration TIMG_ALARM_EN: When triggered, it will enable or disable the alarm generation. • TG0_TASK_CNT_CAP_TIMER0: When triggered, it will update the current counter value to the TIMG_T0LO_REG and TIMG_T0HI_REG registers. • TG1_TASK_CNT_CAP_TIMER0: When triggered, it will update the current counter value to the TIMG_T0LO_REG and TIMG_T0HI_REG registers. • TG0_TASK_CNT_RELOAD_TIMER0: When triggered, it will overwrite the current counter value with the reload value stored in TIMG_T0_LOAD_LO and TIMG_T0_LOAD_HI. • TG1_TASK_CNT_RELOAD_TIMER0: When triggered, it will overwrite the current counter value with the reload value stored in TIMG_T0_LOAD_LO and TIMG_T0_LOAD_HI. The timer groups can generate the following ETM events: • TG0_EVT_CNT_CMP_TIMER0: Indicates the interrupt event of T0 in TIMG0. • TG1_EVT_CNT_CMP_TIMER0: Indicates the interrupt event of T0 in TIMG1. All the ETM tasks and events will not take effect until the TIMG_ETM_EN is set to 1. In practical applications, timer groups’ ETM events can trigger their own ETM tasks. For example, TG0_TASK_ALARM_START_TIMER0 and TG1_TASK_ALARM_START_TIMER0 can be triggered respectively by TG0_EVT_CNT_CMP_TIMER0 and TG1_EVT_CNT_CMP_TIMER0 to realize periodic alarm. For configuration steps, please refer to 12.7.4 Timer as Periodic Alarm by ETM. 12.6 Interrupts ESP32-C5’s TIMGn can generate the following interrupt signal(s) that will be sent to the Interrupt Matrix. • TGn_T0_INTR • TGn_WDT_INTR There are several internal interrupt sources from TIMGn that can generate the above interrupt signals. The interrupt sources from TIMGn are listed with their trigger conditions and the resulted interrupt signals in Table 12.6-1. Table 12.6-1. TIMGn’s Internal Interrupt Sources Internal Interrupt Source Trigger Condition Interrupt Signal TIMG_T0_INT T0 generates an alarm TGn_T0_INTR TIMG_WDT_INT The watchdog timer generates an alarm TGn_WDT_INTR Note: For definitions of interrupt, interrupt signal, interrupt source, and their correlations, please refer to Chapter 9 Interrupt Matrix Espressif Systems 535 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 12 Timer Group (TIMG) > Section 9.2 Terminology. Each interrupt source can be configured by a common set of registers that are described in Section Interrupt Configuration Registers. The specific registers can be found in Section 12.8 Register Summary. 12.7 Programming Procedures 12.7.1 Timer as a Simple Clock 1. Configure the time-base counter • Select clock source by setting or clearing PCR_TG0_TIMER_CLK_SEL field. • Configure the 16-bit prescaler by setting TIMG_T0_DIVIDER. • Configure the timer direction by setting or clearing TIMG_T0_INCREASE. • Set the timer’s starting value by writing the starting value to TIMG_T0_LOAD_LO and TIMG_T0_LOAD_HI, then reloading it into the timer by writing any value to TIMG_T0LOAD_REG. 2. Start the timer by setting TIMG_T0_EN. 3. Get the timer’s current value. • Write any value to TIMG_T0UPDATE_REG to latch the timer’s current value. • Wait until TIMG_T0UPDATE_REG is cleared by hardware. • Read the latched timer value from TIMG_T0LO_REG and TIMG_T0HI_REG. 12.7.2 Timer as One-shot Alarm 1. Configure the time-base counter following step 1 of Section 12.7.1. 2. Configure the alarm. • Configure the alarm value by setting TIMG_T0ALARMLO_REG and TIMG_T0ALARMHI_REG. • Enable interrupt by setting TIMG_T0_INT_ENA. 3. Disable auto reload by clearing TIMG_T0_AUTORELOAD. 4. Start the alarm by setting TIMG_T0_ALARM_EN. 5. Handle the alarm interrupt. • Clear the interrupt by setting the timer’s corresponding bit in TIMG_T0_INT_CLR. • Disable the timer by clearing TIMG_T0_EN. 12.7.3 Timer as Periodic Alarm by APB 1. Configure the time-base counter following step 1 in Section 12.7.1. 2. Configure the alarm following step 2 in Section 12.7.2. Espressif Systems 536 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 12 Timer Group (TIMG) 3. Enable auto reload by setting TIMG_T0_AUTORELOAD and configure the reload value via TIMG_T0_LOAD_LO and TIMG_T0_LOAD_HI. 4. Start the alarm by setting TIMG_T0_ALARM_EN. 5. Handle the alarm interrupt (repeat on each alarm iteration). • Clear the interrupt by setting the timer’s corresponding bit in TIMG_T0_INT_CLR. • If the next alarm requires a new alarm value and reload value (i.e., different alarm interval per iteration), then TIMG_T0ALARMLO_REG, TIMG_T0ALARMHI_REG, TIMG_T0_LOAD_LO, and TIMG_T0_LOAD_HI should be reconfigured as needed. Otherwise, the aforementioned registers should remain unchanged. • Re-enable the alarm by setting TIMG_T0_ALARM_EN. 6. Stop the timer (on final alarm iteration). • Clear the interrupt by setting the timer’s corresponding bit in TIMG_T0_INT_CLR. • Disable the timer by clearing TIMG_T0_EN. 12.7.4 Timer as Periodic Alarm by ETM 1. Enable the ETM module’s clock 2. Map ETM event to ETM task (which means using the event to trigger the task) • If TIMG_T0_AUTORELOAD is set to 1, map TG0_EVT_CNT_CMP_TIMER0 and TG1_EVT_CNT_CMP_TIMER0 to the TG0_TASK_ALARM_START_TIMER0 and TG1_TASK_ALARM_START_TIMER0 respectively by one ETM channel. • If TIMG_T0_AUTORELOAD is set to 0, in addition to mapping TG0_EVT_CNT_CMP_TIMER0 and TG1_EVT_CNT_CMP_TIMER0 to the TG0_TASK_ALARM_START_TIMER0 and TG1_TASK_ALARM_START_TIMER0, the TG0_EVT_CNT_CMP_TIMER0 and TG1_EVT_CNT_CMP_TIMER0 should also be mapped to TG0_TASK_CNT_RELOAD_TIMER0 and TG1_TASK_CNT_RELOAD_TIMER0 by another ETM channel. 3. Choose to enable the one or two ETM channels. 4. Set TIMER_ETM_EN to 1 to enable timer group’s ETM events and tasks. 5. Configure the time-base counter following step 1 in Section 12.7.1. 6. Configure the alarm following step 2 in Section 12.7.2. 7. Configure the reload value via TIMG_T0_LOAD_LO and TIMG_T0_LOAD_HI. 8. Handle the TG0_EVT_CNT_CMP_TIMER0 and TG1_EVT_CNT_CMP_TIMER0. • When alarm generates, the TG0_EVT_CNT_CMP_TIMER0 and TG1_EVT_CNT_CMP_TIMER0 also generate, and the alarm generation will be disabled by the alarm. • If TIMG_T0_AUTORELOAD is 1, the current counter value is overwritten by the reloaded value. The alarm generation will be reopened by TG0_TASK_ALARM_START_TIMER0 and TG1_TASK_ALARM_START_TIMER0. Espressif Systems 537 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 12 Timer Group (TIMG) • If TIMG_T0_AUTORELOAD is 0, the current counter value is overwritten by the reloaded value because of the TG0_TASK_CNT_RELOAD_TIMER0 and TG1_TASK_CNT_RELOAD_TIMER0. The alarm generation will be reopened by TG0_TASK_ALARM_START_TIMER0 and TG1_TASK_ALARM_START_TIMER0. 9. Stop the timer (on final alarm iteration). • Disable the ETM channels used to map timer group’s event and task • Set TIMER_ETM_EN to 0. • Clear the interrupt by setting the timer’s corresponding bit in TIMG_T0_INT_CLR. • Disable the timer by clearing TIMG_T0_EN. 12.7.5 Frequency Calculation of Slow Clock 1. One-shot frequency calculation • Select the clock whose frequency is to be calculated via PCR_32_SEL. For the relationship between the value of this register and the clock source, please refer to Chapter 14 RTC Timer. • To meet the prerequisites for calculating the slow clock frequency, prescale RC_FAST_CLK via PCR_FOSC_TICK_NUM. • Configure the time of calculation via TIMG_RTC_CALI_MAX. • Select one-shot frequency calculation by clearing TIMG_RTC_CALI_START_CYCLING, and enable the two counters via TIMG_RTC_CALI_START. • Once TIMG_RTC_CALI_RDY becomes 1, read TIMG_RTC_CALI_VALUE to get the value of XTAL_CLK’s counter, and calculate the frequency of slow clock according to the formula in Section 12.4.5. 2. Periodic frequency calculation • Select the clock whose frequency is to be calculated via PCR_32_SEL. • To meet the prerequisites for calculating the slow clock frequency, prescale RC_FAST_CLK via PCR_FOSC_TICK_NUM. • Configure the time of calculation via TIMG_RTC_CALI_MAX. • Select periodic frequency calculation by enabling TIMG_RTC_CALI_START_CYCLING. • When TIMG_RTC_CALI_CYCLING_DATA_VLD is 1, TIMG_RTC_CALI_VALUE is valid. 3. Timeout If the counter of slow clock cannot finish counting in TIMG_RTC_CALI_TIMEOUT_RST_CNT cycles, TIMG_RTC_CALI_TIMEOUT will be set to indicate a timeout. Espressif Systems 538 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 12 Timer Group (TIMG) 12.8 Register Summary The addresses in this section are relative to Timer Group base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access T0 Control and configuration registers TIMG_T0CONFIG_REG Timer 0 configuration register 0x0000 varies TIMG_T0LO_REG Timer 0 current value, low 32 bits 0x0004 RO TIMG_T0HI_REG Timer 0 current value, high 22 bits 0x0008 RO TIMG_T0UPDATE_REG Write to copy current timer value to TIMG_T0LO_REG or TIMG_T0HI_REG 0x000C R/W/SC TIMG_T0ALARMLO_REG Timer 0 alarm value, low 32 bits 0x0010 R/W TIMG_T0ALARMHI_REG Timer 0 alarm value, high 22 bits 0x0014 R/W TIMG_T0LOADLO_REG Timer 0 reload value, low 32 bits 0x0018 R/W TIMG_T0LOADHI_REG Timer 0 reload value, high 22 bits 0x001C R/W TIMG_T0LOAD_REG Write to reload timer from TIMG_T0LOADLO_REG or TIMG_T0LOADHI_REG 0x0020 WT WDT Control and configuration registers TIMG_WDTCONFIG0_REG Watchdog timer configuration register 0x0048 varies TIMG_WDTCONFIG1_REG Watchdog timer prescaler register 0x004C varies TIMG_WDTCONFIG2_REG Watchdog timer stage 0 timeout value 0x0050 R/W TIMG_WDTCONFIG3_REG Watchdog timer stage 1 timeout value 0x0054 R/W TIMG_WDTCONFIG4_REG Watchdog timer stage 2 timeout value 0x0058 R/W TIMG_WDTCONFIG5_REG Watchdog timer stage 3 timeout value 0x005C R/W TIMG_WDTFEED_REG Write to feed the watchdog timer 0x0060 WT TIMG_WDTWPROTECT_REG Watchdog write protect register 0x0064 R/W RTC CALI Control and configuration registers TIMG_RTCCALICFG_REG RTC calibration configure register 0x0068 varies TIMG_RTCCALICFG1_REG RTC calibration configure register 1 0x006C RO TIMG_RTCCALICFG2_REG RTC calibration configure register 2 0x0080 varies Interrupt registers TIMG_INT_ENA_TIMERS_REG Interrupt enable bits 0x0070 R/W TIMG_INT_RAW_TIMERS_REG Raw interrupt status 0x0074 R/SS/WTC TIMG_INT_ST_TIMERS_REG Masked interrupt status 0x0078 RO TIMG_INT_CLR_TIMERS_REG Interrupt clear bits 0x007C WT Version register TIMG_NTIMERS_DATE_REG Timer version control register 0x00F8 R/W Clock configuration registers TIMG_REGCLK_REG Timer group clock gate register 0x00FC R/W Espressif Systems 539 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 12 Timer Group (TIMG) 12.9 Registers The addresses in this section are relative to Timer Group base address provided in Table 4.3-2 in Chapter 4 System and Memory. Register 12.1. TIMG_T0CONFIG_REG (0x0000) TIMG_T0_EN 0 31 TIMG_T0_INCREASE 1 30 TIMG_T0_AUTORELOAD 1 29 TIMG_T0_DIVIDER 0x01 28 13 TIMG_T0_DIVCNT_RST 0 12 (reserved) 0 11 TIMG_T0_ALARM_EN 0 10 (reserved) 0 0 0 0 0 0 0 0 0 0 9 0 Reset TIMG_T0_ALARM_EN Configures whether or not to enable the timer 0 alarm function. This bit will be automatically cleared once an alarm occurs. 0: Disable 1: Enable (R/W/SC) TIMG_T0_DIVCNT_RST Configures whether or not to reset the timer 0 ’s clock divider counter. 0: No effect 1: Reset (WT) TIMG_T0_DIVIDER Represents the timer 0 clock (T0_clk) prescaler value. (R/W) TIMG_T0_AUTORELOAD Configures whether or not to enable the timer 0 auto-reload function at the time of alarm. 0: No effect 1: Enable (R/W) TIMG_T0_INCREASE Configures the counting direction of the timer 0 time-base counter. 0: Decrement 1: Increment (R/W) TIMG_T0_EN Configures whether or not to enable the timer 0 time-base counter. 0: Disable 1: Enable (R/W/SS/SC) Espressif Systems 540 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 12 Timer Group (TIMG) Register 12.2. TIMG_T0LO_REG (0x0004) TIMG_T0_LO 0x000000 31 0 Reset TIMG_T0_LO Represents the low 32 bits of the time-base counter of timer 0. Valid only after writing to TIMG_T0UPDATE_REG. Measurement unit: T0_clk (RO) Register 12.3. TIMG_T0HI_REG (0x0008) (reserved) 0 0 0 0 0 0 0 0 0 0 31 22 TIMG_T0_HI 0x0000 21 0 Reset TIMG_T0_HI Represents the high 22 bits of the time-base counter of timer 0. Valid only after writing to TIMG_T0UPDATE_REG. Measurement unit: T0_clk (RO) Register 12.4. TIMG_T0UPDATE_REG (0x000C) TIMG_T0_UPDATE 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 0 Reset TIMG_T0_UPDATE Configures to latch the counter value. 0: Latch 1: Latch Note that writing either 0 or 1 to this bit will trigger latching of the counter value. (R/W/SC) Espressif Systems 541 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 12 Timer Group (TIMG) Register 12.5. TIMG_T0ALARMLO_REG (0x0010) TIMG_T0_ALARM_LO 0x000000 31 0 Reset TIMG_T0_ALARM_LO Configures the low 32 bits of timer 0 alarm trigger time-base counter value. Valid only when TIMG_T0_ALARM_EN is 1. Measurement unit: T0_clk (R/W) Register 12.6. TIMG_T0ALARMHI_REG (0x0014) (reserved) 0 0 0 0 0 0 0 0 0 0 31 22 TIMG_T0_ALARM_HI 0x0000 21 0 Reset TIMG_T0_ALARM_HI Configures the high 22 bits of timer 0 alarm trigger time-base counter value. Valid only when TIMG_T0_ALARM_EN is 1. Measurement unit: T0_clk (R/W) Register 12.7. TIMG_T0LOADLO_REG (0x0018) TIMG_T0_LOAD_LO 0x000000 31 0 Reset TIMG_T0_LOAD_LO Configures low 32 bits of the value that a reload will load onto timer 0 time-base counter. Measurement unit: T0_clk (R/W) Espressif Systems 542 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 12 Timer Group (TIMG) Register 12.8. TIMG_T0LOADHI_REG (0x001C) (reserved) 0 0 0 0 0 0 0 0 0 0 31 22 TIMG_T0_LOAD_HI 0x0000 21 0 Reset TIMG_T0_LOAD_HI Configures high 22 bits of the value that a reload will load onto timer 0 time-base counter. Measurement unit: T0_clk (R/W) Register 12.9. TIMG_T0LOAD_REG (0x0020) TIMG_T0_LOAD 0x000000 31 0 Reset TIMG_T0_LOAD Write any value to trigger a timer 0 time-base counter reload. (WT) Espressif Systems 543 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 12 Timer Group (TIMG) Register 12.10. TIMG_WDTCONFIG0_REG (0x0048) TIMG_WDT_EN 0 31 TIMG_WDT_STG0 0 30 29 TIMG_WDT_STG1 0 28 27 TIMG_WDT_STG2 0 26 25 TIMG_WDT_STG3 0 24 23 TIMG_WDT_CONF_UPDATE_EN 0 22 (reserved) 0 21 TIMG_WDT_CPU_RESET_LENGTH 0x1 20 18 TIMG_WDT_SYS_RESET_LENGTH 0x1 17 15 TIMG_WDT_FLASHBOOT_MOD_EN 1 14 TIMG_WDT_PROCPU_RESET_EN 0 13 reserved 0 12 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 11 0 Reset TIMG_WDT_PROCPU_RESET_EN Configures whether to mask the CPU reset generated by MWDT. Valid only when write protection is disabled. 0: Mask 1: Unmask (R/W) TIMG_WDT_FLASHBOOT_MOD_EN Configures whether to enable flash boot protection. 0: Disable 1: Enable (R/W) TIMG_WDT_SYS_RESET_LENGTH Configures the system reset signal length. Valid only when write protection is disabled. Measurement unit: mwdt_clk 0: 8 1: 16 2: 24 3: 32 4: 40 5: 64 6: 128 7: 256 (R/W) TIMG_WDT_CPU_RESET_LENGTH Configures the CPU reset signal length. Valid only when write protection is disabled. Measurement unit: mwdt_clk 0: 8 1: 16 2: 24 3: 32 4: 40 5: 64 6: 128 7: 256 (R/W) Continued on the next page... Espressif Systems 544 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 12 Timer Group (TIMG) Register 12.10. USB_SERIAL_JTAG_CONF0_REG (0x0018) Continued from the previous page... TIMG_WDT_CONF_UPDATE_EN Configures to update the WDT configuration registers. 0: No effect 1: Update (WT) TIMG_WDT_STG3 Configures the timeout action of stage 3. See details in TIMG_WDT_STG0. Valid only when write protection is disabled. (R/W) TIMG_WDT_STG2 Configures the timeout action of stage 2. See details in TIMG_WDT_STG0. Valid only when write protection is disabled. (R/W) TIMG_WDT_STG1 Configures the timeout action of stage 1. See details in TIMG_WDT_STG0. Valid only when write protection is disabled. (R/W) TIMG_WDT_STG0 Configures the timeout action of stage 0. Valid only when write protection is dis- abled. 0: No effect 1: Interrupt 2: Reset CPU 3: Reset system (R/W) TIMG_WDT_EN Configures whether or not to enable the MWDT. Valid only when write protection is disabled. 0: Disable 1: Enable (R/W) Espressif Systems 545 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 12 Timer Group (TIMG) Register 12.11. TIMG_WDTCONFIG1_REG (0x004C) TIMG_WDT_CLK_PRESCALE 0x01 31 16 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 1 TIMG_WDT_DIVCNT_RST 0 0 Reset TIMG_WDT_DIVCNT_RST Configures whether to reset WDT ’s clock divider counter. 0: No effect 1: Reset (WT) TIMG_WDT_CLK_PRESCALE Configures MWDT clock prescaler value. Valid only when write pro- tection is disabled. MWDT clock period = MWDT’s clock source period * TIMG_WDT_CLK_PRESCALE. (R/W) Register 12.12. TIMG_WDTCONFIG2_REG (0x0050) TIMG_WDT_STG0_HOLD 26000000 31 0 Reset TIMG_WDT_STG0_HOLD Configures the stage 0 timeout value. Valid only when write protection is disabled. Measurement unit: mwdt_clk (R/W) Espressif Systems 546 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 12 Timer Group (TIMG) Register 12.13. TIMG_WDTCONFIG3_REG (0x0054) TIMG_WDT_STG1_HOLD 0x7ffffff 31 0 Reset TIMG_WDT_STG1_HOLD Configures the stage 1 timeout value. Valid only when write protection is disabled. Measurement unit: mwdt_clk (R/W) Register 12.14. TIMG_WDTCONFIG4_REG (0x0058) TIMG_WDT_STG2_HOLD 0x0fffff 31 0 Reset TIMG_WDT_STG2_HOLD Configures the stage 2 timeout value. Valid only when write protection is disabled. Measurement unit: mwdt_clk (R/W) Register 12.15. TIMG_WDTCONFIG5_REG (0x005C) TIMG_WDT_STG3_HOLD 0x0fffff 31 0 Reset TIMG_WDT_STG3_HOLD Configures the stage 3 timeout value. Valid only when write protection is disabled. Measurement unit: mwdt_clk (R/W) Espressif Systems 547 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 12 Timer Group (TIMG) Register 12.16. TIMG_WDTFEED_REG (0x0060) TIMG_WDT_FEED 0x000000 31 0 Reset TIMG_WDT_FEED Write any value to feed the MWDT. Valid only when write protection is disabled. (WT) Register 12.17. TIMG_WDTWPROTECT_REG (0x0064) TIMG_WDT_WKEY 0x50d83aa1 31 0 Reset TIMG_WDT_WKEY Configures a different value than its reset value to enable write protection. (R/W) Espressif Systems 548 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 12 Timer Group (TIMG) Register 12.18. TIMG_RTCCALICFG_REG (0x0068) TIMG_RTC_CALI_START 0 31 TIMG_RTC_CALI_MAX 0x01 30 16 TIMG_RTC_CALI_RDY 0 15 (reserved) 0 0 14 13 TIMG_RTC_CALI_START_CYCLING 1 12 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 11 0 Reset TIMG_RTC_CALI_START_CYCLING Configures the frequency calculation mode. 0: one-shot frequency calculation 1: periodic frequency calculation (R/W) TIMG_RTC_CALI_RDY Represents whether one-shot frequency calculation is done. 0: Not done 1: Done (RO) TIMG_RTC_CALI_MAX Configures the time to calculate RTC slow clock’s frequency. Measurement unit: XTAL_CLK (R/W) TIMG_RTC_CALI_START Configures whether to enable one-shot frequency calculation. 0: Disable 1: Enable (R/W) Espressif Systems 549 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 12 Timer Group (TIMG) Register 12.19. TIMG_RTCCALICFG1_REG (0x006C) TIMG_RTC_CALI_VALUE 0x00000 31 7 (reserved) 0 0 0 0 0 0 6 1 TIMG_RTC_CALI_CYCLING_DATA_VLD 0 0 Reset TIMG_RTC_CALI_CYCLING_DATA_VLD Represents whether periodic frequency calculation is done. 0: Not done 1: Done (RO) TIMG_RTC_CALI_VALUE Represents the value countered by XTAL_CLK when one-shot or periodic frequency calculation is done. It is used to calculate RTC slow clock’s frequency. (RO) Register 12.20. TIMG_RTCCALICFG2_REG (0x0080) TIMG_RTC_CALI_TIMEOUT_THRES 0x1ffffff 31 7 TIMG_RTC_CALI_TIMEOUT_RST_CNT 3 6 3 (reserved) 0 0 2 1 TIMG_RTC_CALI_TIMEOUT 0 0 Reset TIMG_RTC_CALI_TIMEOUT Represents whether RTC frequency calculation is timeout. 0: No timeout 1: Timeout (RO) TIMG_RTC_CALI_TIMEOUT_RST_CNT Configures the cycles that reset frequency calculation time- out. Measurement unit: XTAL_CLK (R/W) TIMG_RTC_CALI_TIMEOUT_THRES Configures the threshold value for the RTC frequency calcula- tion timer. If the timer’s value exceeds this threshold, a timeout is triggered. Measurement unit: XTAL_CLK (R/W) Espressif Systems 550 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 12 Timer Group (TIMG) Register 12.21. TIMG_INT_ENA_TIMERS_REG (0x0070) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 TIMG_WDT_INT_ENA 0 2 (reserved) 0 1 TIMG_T0_INT_ENA 0 0 Reset TIMG_T0_INT_ENA Write 1 to enable the TIMG_T0_INT interrupt. (R/W) TIMG_WDT_INT_ENA Write 1 to enable the TIMG_WDT_INT interrupt. (R/W) Register 12.22. TIMG_INT_RAW_TIMERS_REG (0x0074) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 TIMG_WDT_INT_RAW 0 2 (reserved) 0 1 TIMG_T0_INT_RAW 0 0 Reset TIMG_T0_INT_RAW The raw interrupt status bit of the TIMG_T0_INT interrupt. (R/SS/WTC) TIMG_WDT_INT_RAW The raw interrupt status bit of the TIMG_WDT_INT interrupt. (R/SS/WTC) Register 12.23. TIMG_INT_ST_TIMERS_REG (0x0078) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 TIMG_WDT_INT_ST 0 2 (reserved) 0 1 TIMG_T0_INT_ST 0 0 Reset TIMG_T0_INT_ST The masked interrupt status bit of the TIMG_T0_INT interrupt. (RO) TIMG_WDT_INT_ST The masked interrupt status bit of the TIMG_WDT_INT interrupt. (RO) Espressif Systems 551 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 12 Timer Group (TIMG) Register 12.24. TIMG_INT_CLR_TIMERS_REG (0x007C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 TIMG_WDT_INT_CLR 0 2 (reserved) 0 1 TIMG_T0_INT_CLR 0 0 Reset TIMG_T0_INT_CLR Write 1 to clear the TIMG_T0_INT interrupt. (WT) TIMG_WDT_INT_CLR Write 1 to clear the TIMG_WDT_INT interrupt. (WT) Register 12.25. TIMG_NTIMERS_DATE_REG (0x00F8) (reserved) 0 0 0 0 31 28 TIMG_NTIMGS_DATE 0x2209142 27 0 Reset TIMG_NTIMGS_DATE Version control register (R/W) Register 12.26. TIMG_REGCLK_REG (0x00FC) TIMG_CLK_EN 0 31 (reserved) 0 0 30 29 TIMG_ETM_EN 1 28 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27 0 Reset TIMG_ETM_EN Configures whether to enable timer’s ETM task and event. 0: Disable 1: Enable (R/W) TIMG_CLK_EN Configures whether to enable gate clock signal for registers. 0: Force clock on for registers 1: Support clock only when registers are read or written to by software. (R/W) Espressif Systems 552 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 13 Watchdog Timers (WDT) Chapter 13 Watchdog Timers (WDT) 13.1 Overview Watchdog timers are hardware timers used to detect and recover from malfunctions. They must be periodically fed (reset) to prevent a timeout. A system/software that is behaving unexpectedly (e.g. is stuck in a software loop or in overdue events) will fail to feed the watchdog and thus trigger a watchdog timeout. Therefore, watchdog timers are useful for detecting and handling erroneous system/software behaviors. As shown in Figure 13.1-1, ESP32-C5 contains three digital watchdog timers: one in each of the two timer groups in Chapter 12 Timer Group (TIMG) (called Main System Watchdog Timers, or MWDT) and one in the RTC Module (called the RTC Watchdog Timer, or RWDT). Each digital watchdog timer allows for four separately configurable stages and each stage can be programmed to take one action upon timeout, unless the watchdog is fed or disabled. MWDT supports three timeout actions: interrupt, CPU reset, and core reset, while RWDT supports four timeout actions: interrupt, CPU reset, core reset, and system reset (see details in Section 13.2.2.2 Stages and Timeout Actions). A timeout value can be set for each stage individually. During the flash boot process, RWDT and the MWDT in timer group 0 are enabled automatically in order to detect and recover from booting errors. ESP32-C5 also has one analog watchdog timer: Super watchdog (SWD). It is an ultra-low-power circuit in analog domain that helps to prevent the system from operating in a sub-optimal state and resets the system if required. Main System Watchdog Timer 0 MWDT0 Main System Watchdog Timer 1 MWDT1 RTC Watchdog Timer RWDT Super Watchdog SWD Digital Domain Analog Domain Figure 13.1-1. Watchdog Timers Overview Espressif Systems 553 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 13 Watchdog Timers (WDT) Note that while this chapter provides the functional descriptions of the watchdog timers, MWDT register descriptions are detailed in Chapter 12 Timer Group (TIMG), and the RWDT and SWD register descriptions are detailed in Section 13.5 Register Summary. 13.2 Digital Watchdog Timers 13.2.1 Features Watchdog timers have the following features: • Four stages, each with a separately programmable timeout value and timeout action • Timeout actions: – MWDT: interrupt, CPU reset, core reset – RWDT: interrupt, CPU reset, core reset, system reset • Flash boot protection at stage 0: – MWDT0: core reset upon timeout – RWDT: system reset upon timeout • Write protection that makes WDT register read only unless unlocked • 32-bit timeout counter • Clock source: – MWDT: PLL_F80M_CLK, RC_FAST_CLK, or XTAL_CLK – RWDT: RTC_SLOW_CLK Espressif Systems 554 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 13 Watchdog Timers (WDT) 13.2.2 Functional Description Figure 13.2-1. Digital Watchdog Timers in ESP32-C5 Figure 13.2-1 shows the three watchdog timers in ESP32-C5 digital systems. 13.2.2.1 Clock Source and 32-Bit Counter At the core of each watchdog timer is a 32-bit counter. Take MWDT0 as an example: • MWDT0 can select between the PLL_F80M_CLK, RC_FAST_CLK, or XTAL_CLK (external) clock as its clock source by setting the PCR_TG0_WDT_CLK_SEL field of the PCR_TIMERGROUP0_WDT_CLK_CONF_REG register. • The selected clock is switched on by setting PCR_TG0_WDT_CLK_EN field of the PCR_TIMERGROUP0_WDT_CLK_CONF_REG register to 1 and switched off by setting it to 0. Then the selected clock is divided by a 16-bit configurable prescaler. See more details in Table 7.2-2 of Chapter 7 Reset and Clock. The 16-bit prescaler value for MWDT is configured via the TIMG_WDT_CLK_PRESCALE field of TIMG_WDTCONFIG1_REG. When TIMG_WDT_DIVCNT_RST field is set, the prescaler is reset and it can be re-configured at once. Espressif Systems 555 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 13 Watchdog Timers (WDT) In contrast, the clock source of RWDT is derived directly from RTC_SLOW_CLK (see details in Chapter 7 Reset and Clock). MWDT and RWDT are enabled by setting the TIMG_WDT_EN and RTC_WDT_EN fields respectively. When enabled, the 32-bit counters of the watchdog will increment on each source clock cycle until the timeout value of the current stage is reached (i.e. timeout of the current stage). When this occurs, the current counter value is reset to zero and the next stage will become active. If a watchdog timer is fed by software, the timer will return to stage 0 and reset its counter value to zero. Software can feed a watchdog timer by writing any value to TIMG_WDTFEED_REG for MDWT and by writing 1 to RTC_WDT_FEED for RWDT. 13.2.2.2 Stages and Timeout Actions Timer stages allow for a timer to have a series of different timeout values and corresponding timeout action. When one stage times out, the timeout action is triggered, the counter value is reset to zero, and the next stage becomes active. MWDT/RWDT provide four stages (called stages 0 to 3). The watchdog timers will progress through each stage in a loop (i.e. from stage 0 to 3, then back to stage 0). Timeout values of each stage for MWDT are configured in TIMG_WDTCONFIGi_REG (where i ranges from 2 to 5), whilst timeout values for RWDT are configured using RTC_WDT_STGj_HOLD field (where j ranges from 0 to 3). Please note that the timeout value of stage 0 for RWDT (T hold0 ) is determined by the combination of the EFUSE_WDT_DELAY_SEL field of the eFuse register EFUSE_RD_REPEAT_DATA0_REG and the RTC_WDT_STG0_HOLD field. The relationship is as follows: T hold0 = RT C_W DT _ST G0_HOLD << (EF U SE_W DT _DELAY _SEL + 1) where << is a left-shift operator. For example, if RTC_WDT_STG0_HOLD is configured as 100 and EFUSE_WDT_DELAY_SEL is 1, the T hold0 will be 400 cycles. Upon the timeout of each stage, one of the following timeout actions will be executed: Table 13.2-1. Timeout Actions Timeout Action Description Interrupt Trigger an interrupt CPU reset See Chapter 7 Reset and Clock > Section 7.1.3 FeaturesCore reset System reset Disabled No effect on the system For MWDT, the timeout action of all stages is configured in TIMG_WDTCONFIG0_REG. Likewise for RWDT, the timeout action is configured in RTC_WDT_CONFIG0_REG. 13.2.2.3 Write Protection Watchdog timers are critical to detecting and handling erroneous system/software behavior, and thus should not be disabled easily (e.g. due to a misplaced register write). Therefore, MWDT and RWDT incorporate a write Espressif Systems 556 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 13 Watchdog Timers (WDT) protection mechanism that prevents the watchdogs from being disabled or tampered with due to an accidental write. The write protection mechanism is implemented using a write-key field for each timer (TIMG_WDT_WKEY for MWDT, RTC_WDT_WKEY for RWDT). The value 0x50D83AA1 must be written to the watchdog timer’s write-key field before any other register of the same watchdog timer can be changed. Any attempts to write to a watchdog timer’s registers (other than the write-key field itself) whilst the write-key field’s value is not 0x50D83AA1 will be ignored. The recommended procedure for accessing a watchdog timer is as follows: 1. Disable the write protection by writing the value 0x50D83AA1 to the timer’s write-key field. 2. Make the required modification of the watchdog such as feeding or changing its configuration. 3. Re-enable write protection by writing any value other than 0x50D83AA1 to the timer’s write-key field. 13.2.2.4 Flash Boot Protection During flash booting process, MWDT0 as well as RWDT, are automatically enabled. Stage 0 for the enabled MWDT0 is automatically configured as core reset action upon timeout, known as core reset. Likewise, stage 0 for RWDT is configured to system reset, which resets the main system and RTC when it times out. After booting, TIMG_WDT_FLASHBOOT_MOD_EN and RTC_WDT_FLASHBOOT_MOD_EN should be cleared to stop the flash boot protection procedure for both MWDT0 and RWDT respectively. After this, MWDT0 and RWDT can be configured by software. 13.3 Super Watchdog Super watchdog (SWD) is an ultra-low-power circuit in analog domain that helps to prevent the system from operating in a sub-optimal state and resets the system (system reset) if required. SWD contains a watchdog circuit that needs to be fed for at least once during its timeout period, which is slightly less than one second. About 100 ms before watchdog timeout, it will also send out a WD_INTR signal as a request to remind the system to feed the watchdog. If the system doesn’t respond to SWD feed request and watchdog finally times out, SWD will generate a system level signal SWD_RSTB to reset whole digital circuits on the chip (system reset) . The source of the clock for SWD is constant and can not be selected. 13.3.1 Features SWD has the following features: • An analog watchdog that operates independently of the digital circuit and can function in environments where the digital circuit’s clock and voltage are abnormal • Interrupt to indicate that the SWD is about to time out • Various dedicated methods for software to feed SWD, which enables SWD to monitor the working state of the whole operating system 13.3.2 Super Watchdog Controller Espressif Systems 557 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 13 Watchdog Timers (WDT) 13.3.2.1 Structure Figure 13.3-1. Super Watchdog Controller Structure 13.3.2.2 Workflow In normal state: • SWD controller receives feed request from SWD. • SWD controller sends an interrupt to HP CPU. • HP CPU feeds SWD directly by setting RTC_WDT_SWD_FEED. • When trying to feed SWD, CPU needs to disable SWD controller’s write protection by writing 0x50D83AA1 to RTC_WDT_SWD_WKEY. This prevents SWD from being fed by mistake when the system is operating in sub-optimal state. • If setting RTC_WDT_SWD_AUTO_FEED_EN to 1, SWD controller can also receive interrupts from the SWD for feeding the watchdog itself without any interaction with CPU. After reset: • Check LP_CLKRST_RESET_CAUSE[4:0] for the cause of CPU reset. If LP_CLKRST_RESET_CAUSE[4:0] == 0x12, it indicates that the cause is SWD reset. • Set RTC_WDT_SWD_RST_FLAG_CLR to clear the SWD reset flag. 13.4 Interrupts For watchdog timer interrupts, please refer to Section 12.6 Interrupts in Chapter 12 Timer Group (TIMG). Espressif Systems 558 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 13 Watchdog Timers (WDT) 13.5 Register Summary The addresses in this section are relative to RTC_WDT base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access configuration register RTC_WDT_CONFIG0_REG Configure the RWDT operation 0x0000 R/W RTC_WDT_CONFIG1_REG Configure the RWDT timeout time of stage0 0x0004 R/W RTC_WDT_CONFIG2_REG Configure the RWDT timeout time of stage1 0x0008 R/W RTC_WDT_CONFIG3_REG Configure the RWDT timeout time of stage2 0x000C R/W RTC_WDT_CONFIG4_REG Configure the RWDT timeout time of stage3 0x0010 R/W RTC_WDT_FEED_REG Configure the feed function of RWDT 0x0014 WT RTC_WDT_WPROTECT_REG Configure the lock function of RWDT 0x0018 R/W RTC_WDT_SWD_CONFIG_REG Configure the SWD operation 0x001C varies RTC_WDT_SWD_WPROTECT_REG Configure the lock function of SWD 0x0020 R/W RTC_WDT_INT_RAW_REG The interrupt raw register of WDT 0x0024 R/WTC/SS RTC_WDT_INT_ST_REG The interrupt status register of WDT 0x0028 RO RTC_WDT_INT_ENA_REG The interrupt enable register of WDT 0x002C R/W RTC_WDT_INT_CLR_REG The interrupt clear register of WDT 0x0030 WT RTC_WDT_DATE_REG Version control register 0x03FC R/W 13.6 Registers MWDT registers are part of the timer submodule and are described in Section 12.8 Register Summary in Chapter 12 Timer Group (TIMG). The addresses of RWDT and SWD registers in this section are relative to RTC_WDT base address provided in Table 4.3-2 in Chapter 4 System and Memory. Espressif Systems 559 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 13 Watchdog Timers (WDT) Register 13.1. RTC_WDT_CONFIG0_REG (0x0000) RTC_WDT_EN 0 31 RTC_WDT_STG0 0x0 30 28 RTC_WDT_STG1 0x0 27 25 RTC_WDT_STG2 0x0 24 22 RTC_WDT_STG3 0x0 21 19 RTC_WDT_CPU_RESET_LENGTH 0x1 18 16 RTC_WDT_SYS_RESET_LENGTH 0x1 15 13 RTC_WDT_FLASHBOOT_MOD_EN 1 12 RTC_WDT_PROCPU_RESET_EN 0 11 (reserved) 0 10 RTC_WDT_PAUSE_IN_SLP 1 9 (reserved) 0 0 0 0 0 0 0 0 0 8 0 Reset RTC_WDT_PAUSE_IN_SLP Configures whether or not to pause RWDT when chip is in Light-sleep or Deep-sleep mode. 0: Enable 1: Disable (R/W) RTC_WDT_PROCPU_RESET_EN Configures whether or not to enable RWDT to reset CPU. 0: Disable 1: Enable (R/W) RTC_WDT_FLASHBOOT_MOD_EN Configures whether or not to enable RWDT when chip is in SPI boot mode. 0: Disable 1: Enable (R/W) RTC_WDT_SYS_RESET_LENGTH Configures the core reset time. Measurement unit: LP_DYN_FAST_CLK cycles (R/W) RTC_WDT_CPU_RESET_LENGTH Configures the CPU reset time. Measurement unit: LP_DYN_FAST_CLK cycles (R/W) RTC_WDT_STG3 Configures the timeout action of stage3. 0: No operation 1: Generate interrupt 2: Generate CPU reset 3: Generate core reset 4: Generate system reset (R/W) Continued on the next page... Espressif Systems 560 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 13 Watchdog Timers (WDT) Register 13.1. RTC_WDT_CONFIG0_REG (0x0000) Continued from the previous page... RTC_WDT_STG2 Configures the timeout action of stage2. 0: No operation 1: Generate interrupt 2: Generate CPU reset 3: Generate core reset 4: Generate system reset (R/W) RTC_WDT_STG1 Configures the timeout action of stage1. 0: No operation 1: Generate interrupt 2: Generate CPU reset 3: Generate core reset 4: Generate system reset (R/W) RTC_WDT_STG0 Configures the timeout action of stage0. 0: No operation 1: Generate interrupt 2: Generate CPU reset 3: Generate core reset 4: Generate system reset (R/W) RTC_WDT_EN Configures whether or not enable RWDT. 0: Disable RWDT 1: Enable RWDT (R/W) Register 13.2. RTC_WDT_CONFIG1_REG (0x0004) RTC_WDT_STG0_HOLD 200000 31 0 Reset RTC_WDT_STG0_HOLD Configures the timeout time for stage0. Measurement unit: LP_DYN_SLOW_CLK cycles (R/W) Espressif Systems 561 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 13 Watchdog Timers (WDT) Register 13.3. RTC_WDT_CONFIG2_REG (0x0008) RTC_WDT_STG1_HOLD 80000 31 0 Reset RTC_WDT_STG1_HOLD Configures the timeout time for stage1. Measurement unit: LP_DYN_SLOW_CLK cycles (R/W) Register 13.4. RTC_WDT_CONFIG3_REG (0x000C) RTC_WDT_STG2_HOLD 0x000fff 31 0 Reset RTC_WDT_STG2_HOLD Configures the timeout time for stage2. Measurement unit: LP_DYN_SLOW_CLK cycles (R/W) Register 13.5. RTC_WDT_CONFIG4_REG (0x0010) RTC_WDT_STG3_HOLD 0x000fff 31 0 Reset RTC_WDT_STG3_HOLD Configures the timeout time for stage3. Measurement unit: LP_DYN_SLOW_CLK cycles (R/W) Espressif Systems 562 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 13 Watchdog Timers (WDT) Register 13.6. RTC_WDT_FEED_REG (0x0014) RTC_WDT_FEED 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 0 Reset RTC_WDT_FEED Configures this bit to feed the RWDT. 0: Invalid 1: Feed RWDT (WT) Register 13.7. RTC_WDT_WPROTECT_REG (0x0018) RTC_WDT_WKEY 0x000000 31 0 Reset RTC_WDT_WKEY Configures this field to lock or unlock RWDT’s configuration registers. 0x50D83AA1: unlock the RWDT configuration register Other values: lock the RWDT configuration register which can’t be modified by software. (R/W) Espressif Systems 563 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 13 Watchdog Timers (WDT) Register 13.8. RTC_WDT_SWD_CONFIG_REG (0x001C) RTC_WDT_SWD_FEED 0 31 RTC_WDT_SWD_DISABLE 0 30 RTC_WDT_SWD_SIGNAL_WIDTH 300 29 20 RTC_WDT_SWD_RST_FLAG_CLR 0 19 RTC_WDT_SWD_AUTO_FEED_EN 0 18 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 1 RTC_WDT_SWD_RESET_FLAG 0 0 Reset RTC_WDT_SWD_RESET_FLAG Represents whether the SWD generates a reset signal or not. 0: No 1: Yes (RO) RTC_WDT_SWD_AUTO_FEED_EN Configures this bit to enable to feed SWD automatically by hard- ware. 0: Disable 1: Enable (R/W) RTC_WDT_SWD_RST_FLAG_CLR Configures this bit to clear SWD reset flag. 0: Invalid 1: Clear the reset flag (WT) RTC_WDT_SWD_SIGNAL_WIDTH Confgure the SWD signal length that output to analog circuit. Measurement unit: LP_DYN_FAST_CLK (R/W) RTC_WDT_SWD_DISABLE Configures this bit to disable the SWD. 0: Enable the SWD 1: Disable the SWD (R/W) RTC_WDT_SWD_FEED Configures this bit to feed the SWD. 0: Invalid 1: Feed SWD (WT) Espressif Systems 564 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 13 Watchdog Timers (WDT) Register 13.9. RTC_WDT_SWD_WPROTECT_REG (0x0020) RTC_WDT_SWD_WKEY 0x000000 31 0 Reset RTC_WDT_SWD_WKEY Configures this field to lock or unlock SWD’s configuration registers. 0x50D83AA1: unlock the SWD configuration register. Other values: lock the SWD configuration register which can’t be modified by the software. (R/W) Register 13.10. RTC_WDT_INT_RAW_REG (0x0024) RTC_WDT_INT_RAW 0 31 RTC_WDT_SWD_INT_RAW 0 30 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29 0 Reset RTC_WDT_SWD_INT_RAW The raw interrupt status of RTC_WDT_SWD_INT interrupt.(R/WTC/SS) RTC_WDT_INT_RAW The raw interrupt status of RTC_WDT_INT interrupt. (R/WTC/SS) Register 13.11. RTC_WDT_INT_ST_REG (0x0028) RTC_WDT_INT_ST 0 31 RTC_WDT_SWD_INT_ST 0 30 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29 0 Reset RTC_WDT_SWD_INT_ST The masked interrupt status of RTC_WDT_SWD_INT interrupt.(RO) RTC_WDT_INT_ST The masked interrupt status of RTC_WDT_INT interrupt.(RO) Espressif Systems 565 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 13 Watchdog Timers (WDT) Register 13.12. RTC_WDT_INT_ENA_REG (0x002C) RTC_WDT_INT_ENA 0 31 RTC_WDT_SWD_INT_ENA 0 30 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29 0 Reset RTC_WDT_SWD_INT_ENA Write 1 to enable RTC_WDT_SWD_INT. (R/W) RTC_WDT_INT_ENA Write 1 to enable RTC_WDT_INT. (R/W) Register 13.13. RTC_WDT_INT_CLR_REG (0x0030) RTC_WDT_INT_CLR 0 31 RTC_WDT_SWD_INT_CLR 0 30 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29 0 Reset RTC_WDT_SWD_INT_CLR Write 1 to clear RTC_WDT_SWD_INT. (WT) RTC_WDT_INT_CLR Write 1 to clear RTC_WDT_INT. (WT) Register 13.14. RTC_WDT_DATE_REG (0x03FC) RTC_WDT_CLK_EN 0 31 RTC_WDT_DATE 0x2112080 30 0 Reset RTC_WDT_DATE Version control register. (R/W) RTC_WDT_CLK_EN Reserved. (R/W) Espressif Systems 566 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 14 RTC Timer Chapter 14 RTC Timer 14.1 Introduction The RTC Timer is a 48-bit readable counter that can operate in any power mode. It is used as a system timer when the timers in the HP system is unavailable. It also allows for configuring timer interrupts and logging the time when specific events happen in the system. 14.2 Feature List • 48-bit counter • Time logging when one of the following events happens: – HP system reset – CPU enters stall state – CPU exits stall state – Crystal powers up – Crystal powers down • Time logging through register configuration • Occurrence time cached of the most recent two specific events • Generation of interrupts at target times, which are configurable. It is also possible to configure two target times simultaneously • Uninterrupted operation during any reset or sleep mode, except for power-on reset of LP system • Can work as the wake-up source (see Chapter 2 Low-power Management [to be added later]) 14.3 Functional Description • 48-bit counter – The implementation of the RTC Timer is based on a 48-bit counter, driven by the RC_SLOW_CLK in the Always-On power domain (for details about power domains, see Chapter 2 Low-power Management [to be added later]). It uses continuous loop counting (except during LP system reset), and an overflow interrupt is generated when the 48-bit counter overflows. • Log the occurrence time of specific events – The RTC Timer supports logging the occurrence time of three types of events: Espressif Systems 567 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 14 RTC Timer * HP system reset * CPU enters or exits stall state * Crystal powers up or down – The above three types of events have their own independent configuration registers. When the configuration registers are enabled, if the corresponding events occur, the hardware pulse generated will trigger the RTC Timer to log the current time. The corresponding configuration registers are shown in the table below. Table 14.3-1. Configure RTC Timer to Log the Occurrence Time of Specific Events Configuration Register Description RTC_TIMER_MAIN_TIMER_SYS_RST Enable the RTC Timer to log the time of system reset. RTC_TIMER_MAIN_TIMER_SYS_STALL Enable the RTC Timer to log the time when the CPU enters or exits the stall state. RTC_TIMER_MAIN_TIMER_XTAL_OFF Enable the RTC Timer to log the time when the crystal pow- ers up or down. • Log the current time through software configuration. – In addition to the above three specific events that can trigger the RTC Timer to log the time, the RTC Timer can also log the current time through the configuration register RTC_TIMER_MAIN_TIMER_UPDATE. – A pulse signal will be generated by configuring the RTC_TIMER_MAIN_TIMER_UPDATE, which will trigger the RTC Timer to log the current time. • Generate counting interrupts at target times – The RTC Timer supports configuring two target times simultaneously, referred to as target time 0 and target time 1. When the timer reaches target time 0, it will trigger the RTC_TIMER_CMP0_INT interrupt. Similarly, when the timer reaches Target Moment 1, it will trigger the RTC_TIMER_CMP1_INT interrupt. – Configure the target times through the registers below: Table 14.3-2. Target Time Configuration Configuration Register Description RTC_TIMER_MAIN_TIMER_TAR_ENn n = 0 or 1, enable target time configuration. RTC_TIMER_MAIN_TIMER_TAR_LOWn n = 0 or 1, configure the lower 32 bits of the target time. RTC_TIMER_MAIN_TIMER_TAR_HIGHn n = 0 or 1, configure the higher 16 bits of the target time. • Read the time cached in the RTC Timer – There are two sets of registers used to cache the occurrence time of specific events, namely register group 0 and register group 1. – Register group 0 includes register RTC_TIMER_MAIN_BUF0_LOW_REG and RTC_TIMER_MAIN_BUF1_HIGH_REG which are used to cache the count value of the RTC Timer under the current trigger. Espressif Systems 568 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 14 RTC Timer – Register group 1 includes register RTC_TIMER_MAIN_BUF1_LOW_REG and RTC_TIMER_MAIN_BUF1_HIGH_REG, which are used to cache the count value of the RTC Timer from the last trigger. – On a new trigger, the record from the previous trigger will be moved from register group 0 to register group 1 (and the previous record in register group 1 will be overwritten), and the record of this trigger will be stored in register group 0. Therefore, only the last two triggers can be logged at any time. 14.4 Event Task Matrix Feature The RTC Timer on ESP32-C5 supports the Event Task Matrix (ETM) function, which allows RTC Timer’s ETM events to trigger any peripherals’ ETM tasks. The ETM tasks of RTC timer are not supported. This section introduces the ETM events related to RTC Timer. For more information, please refer to Chapter 10 Event Task Matrix (ETM). The RTC Timer can generate the following ETM events: • RTC_EVT_CMP: Indicates that the RTC Timer reaches the target time 0 configured by RTC_TIMER_MAIN_TIMER_TAR_LOW0 and RTC_TIMER_MAIN_TIMER_TAR_HIGH0. • RTC_EVT_OVF: Indicates that the 48-bit counter overflows. • RTC_EVT_TICK: Indicates the event that occurs when the RTC timer increments by 1. 14.5 Interrupts ESP32-C5’s RTC Timer can generate the following interrupt signal(s) that will be sent to the Interrupt Matrix. • LP_TIMER_REG_0_INTR (only for HP CPU) • LP_TIMER_REG_1_INTR (only for LP CPU) There are several internal interrupt sources from the RTC Timer that can generate the above interrupt signal(s). The interrupt sources from the RTC Timer are listed with their trigger conditions and the resulted interrupt signal(s) in Table 14.5-1. Table 14.5-1. RTC Timer’s Internal Interrupt Sources Internal Interrupt Source Trigger Condition Interrupt Signal RTC_TIMER_CMP0_INT RTC Timer reaches the target time 0 LP_TIMER_REG_0_INTR RTC_TIMER_CMP1_INT RTC Timer reaches the target time 1 LP_TIMER_REG_1_INTR RTC_TIMER_OVERFLOW_INT 48-bit counter overflows LP_TIMER_REG_0_INTR LP_TIMER_REG_1_INTR Note: For definitions of interrupt, interrupt signal, interrupt source, and their correlations, please refer to Chapter 9 Interrupt Matrix > Section 9.2 Terminology. Espressif Systems 569 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 14 RTC Timer Each interrupt source can be configured by a common set of registers that are described in Section Interrupt Configuration Registers. The specific registers can be found in Section 14.6 Register Summary. Espressif Systems 570 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 14 RTC Timer 14.6 Register Summary The addresses in this section are relative to RTC Timer base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Configuration Registers RTC_TIMER_TAR0_LOW_REG Configures the low 32 bits of the target time 0 0x0000 R/W RTC_TIMER_TAR0_HIGH_REG Configures the high 16 bits of the target time 0 0x0004 varies RTC_TIMER_TAR1_LOW_REG Configures the low 32 bits of the target time 1 0x0008 R/W RTC_TIMER_TAR1_HIGH_REG Configures the high 16 bits of the target time 1 0x000C varies RTC_TIMER_UPDATE_REG Configures to enable the RTC Timer to latch current value 0x0010 varies RTC_TIMER_MAIN_BUF0_LOW_REG The low 32 bits of the cached value 0 in RTC Timer 0x0014 RO RTC_TIMER_MAIN_BUF0_HIGH_REG The high 16 bits of the cached value 0 in RTC Timer 0x0018 RO RTC_TIMER_MAIN_BUF1_LOW_REG The low 32 bits of the cached value 1 in RTC Timer 0x001C RO RTC_TIMER_MAIN_BUF1_HIGH_REG The high 16 bits of the cached value 1 in RTC Timer 0x0020 RO Interrupt Registers RTC_TIMER_INT_RAW_REG The interrupt raw status register for the RTC Timer reaching the target time 0 0x0028 R/WTC/SS RTC_TIMER_INT_ST_REG The interrupt status register for the RTC Timer reaching the target time 0 0x002C RO RTC_TIMER_INT_ENA_REG The interrupt enable register for the RTC Timer reaching the target time 0 0x0030 R/W RTC_TIMER_INT_CLR_REG The interrupt clear register for the RTC Timer reaching the target time 0 0x0034 WT RTC_TIMER_LP_INT_RAW_REG The interrupt raw status register for RTC Timer reaching the target time 1 0x0038 R/WTC/SS RTC_TIMER_LP_INT_ST_REG The interrupt status register for the RTC Timer reaching the target time 1 0x003C RO RTC_TIMER_LP_INT_ENA_REG The interrupt enable register for the RTC Timer reaching the target time 1 0x0040 R/W RTC_TIMER_LP_INT_CLR_REG The interrupt clear register for the RTC Timer reaching the target time 1 0x0044 WT Version Register RTC_TIMER_DATE_REG Version control register 0x03FC R/W Espressif Systems 571 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 14 RTC Timer 14.7 Registers The addresses in this section are relative to RTC Timer base address provided in Table 4.3-2 in Chapter 4 System and Memory. For how to program reserved fields, please refer to Section Programming Reserved Register Field. Register 14.1. RTC_TIMER_TAR0_LOW_REG (0x0000) RTC_TIMER_MAIN_TIMER_TAR_LOW0 0 31 0 Reset RTC_TIMER_MAIN_TIMER_TAR_LOW0 Configures the low 32 bits of the target time 0 of the RTC Timer. (R/W) Register 14.2. RTC_TIMER_TAR0_HIGH_REG (0x0004) RTC_TIMER_MAIN_TIMER_TAR_EN0 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 16 RTC_TIMER_MAIN_TIMER_TAR_HIGH0 0 15 0 Reset RTC_TIMER_MAIN_TIMER_TAR_HIGH0 Configures the high 16 bits of the target time 0. (R/W) RTC_TIMER_MAIN_TIMER_TAR_EN0 Configures to enable the target time 0 of the RTC Timer. 0: Disable 1: Enable (WT) Espressif Systems 572 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 14 RTC Timer Register 14.3. RTC_TIMER_TAR1_LOW_REG (0x0008) RTC_TIMER_MAIN_TIMER_TAR_LOW1 0 31 0 Reset RTC_TIMER_MAIN_TIMER_TAR_LOW1 Configures the low 32 bits of the target time 1. (R/W) Register 14.4. RTC_TIMER_TAR1_HIGH_REG (0x000C) RTC_TIMER_MAIN_TIMER_TAR_EN1 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 16 RTC_TIMER_MAIN_TIMER_TAR_HIGH1 0 15 0 Reset RTC_TIMER_MAIN_TIMER_TAR_HIGH1 Configures the high 16 bits of the target time 1. (R/W) RTC_TIMER_MAIN_TIMER_TAR_EN1 Configures to enable the target time 1 of the RTC Timer. 0: Disable 1: Enable (WT) Espressif Systems 573 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 14 RTC Timer Register 14.5. RTC_TIMER_UPDATE_REG (0x0010) RTC_TIMER_MAIN_TIMER_SYS_RST 0 31 RTC_TIMER_MAIN_TIMER_SYS_STALL 0 30 RTC_TIMER_MAIN_TIMER_XTAL_OFF 0 29 (reserved)) 0 28 RTC_TIMER_MAIN_TIMER_UPDATE 0 27 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 26 0 Reset RTC_TIMER_MAIN_TIMER_UPDATE Configures whether to log the current time through software configuration. 0: Not log 1: Log (WT) RTC_TIMER_MAIN_TIMER_XTAL_OFF Configures whether to enable RTC Timer to log the time when the crystal powers up or down. 0: Disable 1: Enable (R/W) RTC_TIMER_MAIN_TIMER_SYS_STALL Configures whether to enable the RTC Timer to log the time when the CPU enters or exits the stall state. 0: Disable 1: Enable (R/W) RTC_TIMER_MAIN_TIMER_SYS_RST Configures whether to enable RTC Timer to log the time of system reset. 0: Disable 1: Enable (R/W) Espressif Systems 574 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 14 RTC Timer Register 14.6. RTC_TIMER_MAIN_BUF0_LOW_REG (0x0014) RTC_TIMER_MAIN_TIMER_BUF0_LOW 0 31 0 Reset RTC_TIMER_MAIN_TIMER_BUF0_LOW Represents the low 32 bits of the cached value 0 in RTC Timer. (RO) Register 14.7. RTC_TIMER_MAIN_BUF0_HIGH_REG (0x0018) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 RTC_TIMER_MAIN_TIMER_BUF0_HIGH 0 15 0 Reset RTC_TIMER_MAIN_TIMER_BUF0_HIGH Represents the high 16 bits of the cached value 0 in RTC Timer. (RO) Register 14.8. RTC_TIMER_MAIN_BUF1_LOW_REG (0x001C) RTC_TIMER_MAIN_TIMER_BUF1_LOW 0 31 0 Reset RTC_TIMER_MAIN_TIMER_BUF1_LOW Represents the low 32 bits of the cached value 1 in RTC Timer. (RO) Espressif Systems 575 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 14 RTC Timer Register 14.9. RTC_TIMER_MAIN_BUF1_HIGH_REG (0x0020) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 RTC_TIMER_MAIN_TIMER_BUF1_HIGH 0 15 0 Reset RTC_TIMER_MAIN_TIMER_BUF1_HIGH Represents the high 16 bits of the cached value 1 in RTC Timer. (RO) Register 14.10. RTC_TIMER_INT_RAW_REG (0x0028) RTC_TIMER_SOC_WAKEUP_INT_RAW 0 31 RTC_TIMER_OVERFLOW_RAW 0 30 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29 0 Reset RTC_TIMER_OVERFLOW_RAW The raw interrupt status of RTC_TIMER_OVERFLOW_INT (HP CPU). (R/WTC/SS) RTC_TIMER_SOC_WAKEUP_INT_RAW The raw interrupt status of RTC_TIMER_CMP0_INT. (R/WTC/SS) Espressif Systems 576 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 14 RTC Timer Register 14.11. RTC_TIMER_INT_ST_REG (0x002C) RTC_TIMER_SOC_WAKEUP_INT_ST 0 31 RTC_TIMER_OVERFLOW_ST 0 30 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29 0 Reset RTC_TIMER_OVERFLOW_ST The masked interrupt status of RTC_TIMER_OVERFLOW_INT (HP CPU). (RO) RTC_TIMER_SOC_WAKEUP_INT_ST The masked interrupt status of RTC_TIMER_CMP0_INT. (RO) Register 14.12. RTC_TIMER_INT_ENA_REG (0x0030) RTC_TIMER_SOC_WAKEUP_INT_ENA 0 31 RTC_TIMER_OVERFLOW_ENA 0 30 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29 0 Reset RTC_TIMER_OVERFLOW_ENA Write 1 to enable RTC_TIMER_OVERFLOW_INT (HP CPU). (R/W) RTC_TIMER_SOC_WAKEUP_INT_ENA Write 1 to enable RTC_TIMER_CMP0_INT. (R/W) Register 14.13. RTC_TIMER_INT_CLR_REG (0x0034) RTC_TIMER_SOC_WAKEUP_INT_CLR 0 31 RTC_TIMER_OVERFLOW_CLR 0 30 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29 0 Reset RTC_TIMER_OVERFLOW_CLR Write 1 to clear RTC_TIMER_OVERFLOW_INT (HP CPU). (WT) RTC_TIMER_SOC_WAKEUP_INT_CLR Write 1 to clear RTC_TIMER_CMP0_INT. (WT) Espressif Systems 577 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 14 RTC Timer Register 14.14. RTC_TIMER_LP_INT_RAW_REG (0x0038) RTC_TIMER_MAIN_TIMER_LP_INT_RAW 0 31 RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW 0 30 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29 0 Reset RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW The raw interrupt status of RTC_TIMER_OVERFLOW_INT (LP CPU). (R/WTC/SS) RTC_TIMER_MAIN_TIMER_LP_INT_RAW The raw interrupt status of RTC_TIMER_CMP1_INT. (R/WTC/SS) Register 14.15. RTC_TIMER_LP_INT_ST_REG (0x003C) RTC_TIMER_MAIN_TIMER_LP_INT_ST 0 31 RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST 0 30 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29 0 Reset RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST The masked interrupt status of RTC_TIMER_OVERFLOW_INT (LP CPU). (RO) RTC_TIMER_MAIN_TIMER_LP_INT_ST The masked interrupt status of RTC_TIMER_CMP1_INT. (RO) Espressif Systems 578 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 14 RTC Timer Register 14.16. RTC_TIMER_LP_INT_ENA_REG (0x0040) RTC_TIMER_MAIN_TIMER_LP_INT_ENA 0 31 RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA 0 30 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29 0 Reset RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA Write 1 to enable RTC_TIMER_OVERFLOW_INT (LP CPU). (R/W) RTC_TIMER_MAIN_TIMER_LP_INT_ENA Write 1 to enable RTC_TIMER_CMP1_INT. (R/W) Register 14.17. RTC_TIMER_LP_INT_CLR_REG (0x0044) RTC_TIMER_MAIN_TIMER_LP_INT_CLR 0 31 RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR 0 30 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29 0 Reset RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR Write 1 to clear RTC_TIMER_OVERFLOW_INT (LP CPU). (WT) RTC_TIMER_MAIN_TIMER_LP_INT_CLR Write 1 to clear RTC_TIMER_CMP1_INT. (WT) Espressif Systems 579 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 14 RTC Timer Register 14.18. RTC_TIMER_DATE_REG (0x03FC) RTC_TIMER_CLK_EN 0 31 RTC_TIMER_DATE 0x2311090 30 0 Reset RTC_TIMER_DATE Version control register. (R/W) RTC_TIMER_CLK_EN Configures RTC timer clock gating. 0: Support clock only when the application writes registers. 1: Always force the clock on for registers. (R/W) Espressif Systems 580 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Chapter 15 Permission Control (PMS) 15.1 Overview The permission control of ESP32-C5 can be divided into two parts: PMP (Physical Memory Protection) and APM (Access Permission Management). PMP is located inside the HP CPU and can control the HP CPU’s access to all address spaces. APM is an access permission management module located at the bus port. APM, together with PMP, manages permissions for the HP CPU to access parts of the memory and the peripheral registers. APM can manage the LP CPU independently to access parts of the internal and external memory. Additionally, APM manages DMA masters such as GDMA and TCM_MEM_MONITOR to access parts of internal and external memory. The distribution of management areas by PMP and APM is shown in Table 15.1-1. For the HP CPU, the control relationship between PMP and APM is shown in Figure 15.1-1. Table 15.1-1. Management Areas by PMP and AMP Masters Slaves ROM HP SRAM LP SRAM HP CPU_PERI 1 HP_PERI 2 LP_PERI 3 EXT MEM 4 HP CPU PMP PMP+ CPU_APM PMP + LP_APM/ LP_APM0 PMP + HP_APM + PERI_APM PMP + HP_APM + PERI_APM PMP + LP_APM + PERI_APM PMP LP CPU N/A HP_APM LP_APM/ LP_APM0 N/A HP_APM + PERI_APM LP_APM + PERI_APM N/A GDMA N/A HP_APM LP_APM/ LP_APM0 N/A N/A N/A HP_APM Other masters 5 N/A HP_APM LP_APM/ LP_APM0 N/A N/A N/A N/A 1 Peripheral registers in the HP CPU, address range: 0x600C_0000 – 0x600C_FFFF 2 Peripheral registers in the high-performance system, address range: 0x6000_0000 – 0x600A_FFFF 3 Peripheral registers in the low-power system, address range: 0x600B_0000 – 0x600B_FFFF 4 External memory, e.g., flash, PSRAM. 5 Masters that can request access to the bus, such as TCM_MEM_MONITOR, PSRAM_MEM_MONITOR. For a complete list of masters, please refer to Table 15.5-1. 6 For more information on CPU_APM, HP_APM, LP_APM, LP_APM0, and PERI_APM, please refer to Section 15.5.2. Espressif Systems 581 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Figure 15.1-1. PMP-APM Management Relation The diagram illustrates that when the HP CPU accesses ROM and EXT_MEM, the access paths are solely managed by PMP. On the other hand, when the HP CPU accesses the other address spaces, the access paths are controlled by both PMP and APM. If the PMP check fails, the APM permission control will not be triggered. For peripheral registers, there are two levels of APM permission control: the first level manages access permissions of address regions, and the second level manages access permissions of peripherals. PMP-related registers are located inside the HP CPU and can be read or configured with special instructions. For how to configure PMP, please refer to Chapter 1 High-Performance CPU [to be added later] > Memory Protection [to be added later]. The following sections will provide a detailed introduction to the APM module including its features, functions, and configurations. 15.2 Introduction to APM The APM module contains two parts: the TEE (Trusted Execution Environment) controller and the APM controller. Each module contains its own registers: TEE registers and APM registers. • The TEE controller configures the security mode of a particular master in ESP32-C5 (such as GDMA) to access memory or peripheral registers. It supports four security modes: TEE, REE0 (Rich Execution Environment), REE1, and REE2. • The APM controller has two types: SYS_APM controller and PERI_APM controller. The registers of SYS_APM controller are in the APM registers, and the registers of PERI_APM controller are in the TEE registers. – The SYS_APM controller manages a master’s access permissions when accessing memory and peripheral registers. By comparing the pre-configured address ranges and corresponding access permissions with the information carried on the bus, such as ID number (please refer to Table 15.5-1), security mode, access address, access permissions, etc, the SYS_APM controller determines whether the access is allowed. – The PERI_APM controller manages the master’s access permissions to peripheral registers. It Espressif Systems 582 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) compares the pre-configured read and write permission registers for each peripheral with the information carried on the bus, such as secure mode, the peripheral to which the access address belongs, and access permissions, to determine whether access is allowed. The TEE registers configure the security mode of each master. The APM registers specify the access permission and access address range of each master in the configured security mode. With the TEE controller and APM controller, ESP32-C5 can precisely control the access permission of all masters to the memory and peripheral registers. 15.3 Features ESP32-C5 has two TEE controllers: HP_TEE and LP_TEE. • HP_TEE has the following features: – Supports four security modes for the masters – Supports configurable security mode for 32 masters • LP_TEE has the following features: – Supports four security modes for the masters – Supports configurable security mode for one master (i.e., the LP CPU) ESP32-C5 has four SYS_APM controllers: HP_APM_CTRL, LP_APM_CTRL, LP_APM0_CTRL, and CPU_APM_CTRL. • HP_APM_CTRL has the following features: – Supports access permission configuration for up to 16 address ranges – Supports access management to HP SRAM, HP CPU peripheral registers, HP system peripheral registers, and external memory – Interrupt function on illegal access – Exception information record • LP_APM_CTRL has the following features: – Supports access permission configuration for up to eight address ranges – Supports access management to LP SRAM (in low-speed mode) and LP peripheral registers – Interrupt function on illegal access – Exception information record • LP_APM0_CTRL has the following features: – Supports access permission configuration for up to eight address ranges – Supports access management to LP SRAM (in high-speed mode) – Interrupt function on illegal access – Exception information record • CPU_APM_CTRL has the following features: Espressif Systems 583 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) – Supports access permission configuration for up to eight address ranges – Supports HP CPU’s access management to HP SRAM – Interrupt function on illegal access – Exception information record ESP32-C5 has two PERI_APM controllers: HP_PERI_APM_CTRL and LP_PERI_APM_CTRL. • HP_PERI_APM_CTRL and LP_PERI_APM_CTRL share the following features: – Support separate permission configuration for each peripheral register – Support returning error status to the master via the system bus – Exception information record 15.4 TEE and REE Terminology TEE Stands for Trusted Execution Environment, which is a secure area that is isolated from the main operating system and provides a secure environment for executing sensitive operations. REE Stands for Rich Execution Environment, which is the main operating system and envi- ronment in which most applications run. Table 15.4-2. Comparison Between TEE and REE Aspect TEE REE Security Enhanced security Normal security Access permission Masters in TEE mode always have read, write, and execute permissions in the address range. Different levels of access permissions of REE0/1/2 are configurable by software. 15.5 Functional Description 15.5.1 TEE Controller Functional Description ESP32-C5 supports four security modes: TEE, REE0, REE1, and REE2. For the HP CPU to access memory or peripheral registers, first select the machine mode or user mode for it, then configure its security mode with HP_TEE registers. For the configuration of machine mode and user mode, please refer to RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Version 1.10. • When the HP CPU is in machine mode, its security mode is TEE mode. • When the HP CPU is in user mode, its security mode is REE mode, defined by TEE_M0_MODE as follows: – If TEE_M0_MODE is 0, which is TEE mode, the valid mode that actually takes effect in the HP CPU user mode is REE0. – if TEE_M0_MODE is 1, 2, or 3, the security mode is REE0, REE1, and REE2 respectively. Espressif Systems 584 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) For the LP CPU to access memory or peripheral registers, set its secure mode with LP_TEE_M0_MODE. As for other masters, configure their security mode with TEE_Mn_MODE. n represents the ID number of master as listed in Table 15.5-1. Table 15.5-1. Master Access Source from HP System Value of n Source 0 HP CPU 1 Reserved 2 Reserved 3 Reserved 4 Reserved 5 TCM_MEM_MONITOR 6 TRACE 7 Reserved 8 PSRAM_MEM_MONITOR 9 15 Reserved 16 31 See the peripherals corresponding to the values 0 15 in Chapter 3 GDMA Controller (GDMA) > Table 3.4-1 GDMA Selecting Peripherals via Register Configuration. For example, 16 corre- sponds to the peripheral with value 0 in Table 3.4-1 GDMA Selecting Peripherals via Register Configuration, and 17 corresponds to the peripheral with value 1 in the table, and so on. You can configure TEE_Mn_LOCK and LP_TEE_M0_LOCK to lock the configuration of the master’s secure mode. Only chip reset, system reset, and core reset can unlock the configurations and restore all configurations in TEE registers to their default values. 15.5.2 APM Controller Functional Description 15.5.2.1 Architecture Figure 15.5-1 shows the architecture of the APM controller and the access paths managed by it. Espressif Systems 585 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Figure 15.5-1. APM Controller Architecture Note: For more information about the “Low-speed mode” and “High-speed mode” in the figure, please refer to 4 System and Memory. As shown in the figure, SYS_APM has four controllers: • HP_APM_CTRL, configured by the HP_APM_REG register module. • LP_APM0_CTRL, configured by the LP_APM0_REG register module. • LP_APM_CTRL, configured by the LP_APM_REG register module. • CPU_APM_CTRL, configured by the CPU_APM_REG register module. PERI_APM has two controllers: • HP_PERI_APM_CTRL, configured by the TEE_REG register module. • LP_PERI_APM_CTRL, configured by the LP_TEE_REG register module. The access paths and permission management configuration for each APM controller are as follows. • HP_APM_CTRL manages five access paths, namely M0 – M4 in the figure. Permission management of each path can be enabled by configuring HP_APM_FUNC_CTRL_REG (enabled by default). • LP_APM0_CTRL manages one access path, namely M0 in the figure. Permission management of this path can be enabled by configuring LP_APM0 _FUNC_CTRL_REG (enabled by default). • LP_APM_CTRL manages two access paths, namely M0 – M1 in the figure. Permission management of this path can be enabled by configuring LP_APM_FUNC_CTRL_REG (enabled by default). • CPU_APM_CTRL manages four access paths, namely M0 – M3 highlighted in red in the figure. Permission management of this path can be enabled by configuring CPU_APM _FUNC_CTRL_REG (enabled by default). Espressif Systems 586 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) • HP_PERI_APM_CTRL controls all peripheral register access paths in the high-performance system, and permission management of each path can be enabled by configuring TEE_PERI_CTRL_REG. • LP_PERI_APM_CTRL controls all peripheral register access paths in the low-power system, and permission management of each path can be enabled by configuring LP_TEE_PERI_CTRL_REG. Table 15.5-2 below provides detailed information about the APM controllers: Table 15.5-2. APM Controllers Configuration Registers APM Controllers Register Modules Number of Access Paths Enable Permission Management Number of Configurable Address Ranges Enable Address Ranges HP_APM_CTRL HP_APM_REG 5 HP_APM_ FUNC_CTRL_REG 16 HP_APM_REGION_FILTER_ EN_REG LP_APM0_CTRL LP_APM0_REG 1 LP_APM0_ FUNC_CTRL_REG 8 LP_APM0_REGION_FILTER_ EN_REG LP_APM_CTRL LP_APM_REG 2 LP_APM_ FUNC_CTRL_REG 8 LP_APM_REGION_FILTER_ EN_REG CPU_APM_CTRL CPU_APM_REG 4 CPU_APM _FUNC_CTRL_REG 8 CPU_APM_REGION_FILTER_ EN_REG HP_PERI_APM_CTRL TEE_REG Same as the number of HP system register modules N/A Same as the number of HP system register modules N/A LP_PERI_APM_CTRL LP_TEE_REG Same as the number of LP system register modules N/A Same as the number of LP system register modules N/A 15.5.2.2 SYS_APM Controller 15.5.2.2.1 Address Ranges • HP_APM_REG register module can configure up to 16 address ranges (i.e., region n, n=0-15) for HP_APM_CTRL. The start and end addresses of each region (address range) are configured by HP_APM_REGIONn_ADDR_START and HP_APM_REGIONn_ADDR_END, respectively. Configure the bit n of HP_APM_REGION_FILTER_EN_REG to enable region n. Region 0 (i.e., the first address range) is enabled by default. • LP_APM0_REG register module can configure up to eight address ranges (i.e., region n, n=0-7) for LP_APM0_CTRL. The start and end addresses of each region are configured by LP_APM0_REGIONn_ADDR_START and LP_APM0_REGIONn_ADDR_END. Configure the bit n of LP_APM0_REGION_FILTER_EN_REG to enable region n. Region 0 (i.e., the first address range) is enabled by default. • LP_APM_REG register module can configure up to eight address ranges (i.e., region n, n=0-7) for LP_APM_CTRL. The start and end addresses of each region are configured by LP_APM_REGIONn_ADDR_START and LP_APM_REGIONn_ADDR_END. Configure the bit n of LP_APM_REGION_FILTER_EN_REG to enable region n. Region 0 (i.e., the first address range) is enabled by default. Espressif Systems 587 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) • CPU_APM_REG register module can configure up to eight address ranges (i.e., region n, n=0-7) for CPU_APM_CTRL. The start and end addresses of each region are configured by CPU_APM_REGIONn_ADDR_START and CPU_APM_REGIONn_ADDR_END. Configure the bit n of CPU_APM_REGION_FILTER_EN_REG to enable region n. Region 0 (i.e., the first address range) is enabled by default. When configuring the address ranges, the address requires a 4-byte alignment (the lower two bits of the address are 0). For example, the address range could be set to 0x4080000C 0x40808774 or 0x600C0008 0X600CFF70. 15.5.2.2.2 Access Permissions of Address Ranges For each address range, the access permissions (read/write/execute) are configurable in different security modes: • Masters in TEE mode always have read, write, and execute permissions in the address range. • For masters in REE0, REE1 or REE2 mode, access permissions can be configured with HP_APM_REGIONn_ATTR_REG, LP_APM_REGIONn_ATTR_REG, or LP_APM0_REGIONn_ATTR_REG based on the access path. Different access paths managed by the same register module share the configuration of address ranges and access permissions. For example, the permission management of data paths HP_APM_CTRL M0-M4 shown in Figure 15.5-1 should follow the address ranges and access permissions of the 16 address ranges configured in the register module HP_APM_REG. Likewise, the permission management of data path LP_APM_CTRL M0-M1 shown in Figure 15.5-1 should follow the address ranges and access permissions of the four address ranges configured in the register module LP_APM_REG. Take HP SRAM as an example. All masters access it through HP_APM_CTRL M1, except that the HP CPU accesses it through PMP and CPU_APM_CTRL, and the LP CPU accesses it through HP_APM M2. Suppose that HP_APM_M1_FUNC_EN is enabled and a master in REE1 mode needs to access HP SRAM. The whole process is as follows: 1. HP_APM_CTRL M1 will first determine whether the address requested to access is within the 16 address ranges configured in the HP_APM_REG register module. 2. Assuming that the address requested to access is within the second address range, then HP_APM_CTRL M1 determines whether the address range is enabled, that is, whether bit 1 of HP_APM_REGION_FILTER_EN is 1. 3. If the address range is enabled, HP_APM_CTRL M1 checks whether the master has read permission for the second address range, that is, whether HP_APM_REGION1_R1_R in HP_APM_REGION1_ATTR_REG is 1. If valid, the read request will be allowed, otherwise, 0 will be returned. When the HP power domain (please refer to Chapter 2 Low-power Management [to be added later]) restarts after power-down, the LP CPU does not have access to HP SRAM by default. In TEE mode, you can configure LP_TEE_FORCE_ACC_HPMEM_EN to 1 for the LP CPU to access HP SRAM without requiring permission checks from the SYS_APM controller. Note: • When the chip is powered up, only the HP CPU is in TEE mode by default, and other masters are in REE2 mode. Espressif Systems 588 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) By default, the SYS_APM controller blocks access requests from all masters in REE0, REE1, and REE2 modes. • All registers listed in 15.8 Register Summary can only be configured by the masters that are in TEE security mode. • The address ranges configured may overlap. For example, if one region is set to be unreadable and another region is readable, then the overlapping area of the two regions is readable. The same rules apply for write and execute permissions. • You can configure HP_APM_REGIONn_LOCK, LP_APM_REGIONn_LOCK, and LP_APM0_REGIONn_LOCK to lock the configuration of the start and end address of REGIONn and its access permission. Only chip reset, system reset, and core reset can unlock the configurations and restore all configurations in APM registers to their default values. 15.5.2.3 PERI_APM Controller PERI_APM does not perform permission control by address ranges, but on a per-peripheral register basis. For each peripheral register PERI, there are the following eight configuration fields: • HP/LP_TEE_WRITE_TEE_PERI • HP/LP_TEE_WRITE_REE0_PERI • HP/LP_TEE_WRITE_REE1_PERI • HP/LP_TEE_WRITE_REE2_PERI • HP/LP_TEE_READ_TEE_PERI • HP/LP_TEE_READ_REE0_PERI • HP/LP_TEE_READ_REE1_PERI • HP/LP_TEE_READ_REE2_PERI Through the above eight fields, the read/write permissions of slave PERI in the four security modes TEE, REE0, REE1, and REE2 are respectively controlled. A value of 1 indicates having the corresponding read/write permission under that security mode. After reset, by default, for each peripheral register, only HP/LP_TEE_WRITE_TEE_PERI and HP/LP_TEE_READ_TEE_PERI are set to 1; other fields are all 0, indicating that only the master in TEE security mode can configure peripheral registers. The six register modules mentioned in this chapter are also peripherals whose access permissions are controlled by PERI_APM. The six register modules and their corresponding permission control registers in PERI_APM are as follows: • HP_APM_REG, with the permission control register TEE_HP_APM_CTRL_REG • LP_APM0_REG, with the permission control register TEE_HP_APM_CTRL_REG • LP_APM_REG, with the permission control register LP_TEE_LP_APM_CTRL_REG • CPU_APM_REG, with the permission control register TEE_CPU_APM_CTRL_REG • TEE_REG, with the permission control register TEE_TEE_CTRL_REG • LP_TEE_REG, with the permission control register LP_TEE_LP_TEE_CTRL_REG Espressif Systems 589 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) In these permission control registers, only the HP/LP_TEE_WRITE/READ_TEE_PERI fields are configurable; the HP/LP_TEE_WRITE/READ_REE0/1/2_PERI fields are not configurable and fixed to 0, indicating that only masters in TEE security mode can access these registers. 15.6 Illegal Access and Interrupts 15.6.1 SYS_APM Controller When the information carried on the bus does not match the configuration, ESP32-C5 treats it as an illegal access and handles it as follows: • Rejects the access request and returns a default value, specifically: – Returns 0 for read and execute operations – Ignores write operations • Triggers interrupt The SYS_APM controller will automatically record information related to the illegal access, including the master ID, security mode, access address, reasons for illegal access (address out of bounds or permission restrictions), and permission management result of each access path. All this information can be obtained from relevant registers listed in Section 15.8 Register Summary. Take the access path HP_APM_CTRL M0 as an example. When an illegal access occurs: • HP_APM_M0_EXCEPTION_ID records the master ID. • HP_APM_M0_EXCEPTION_MODE records the security mode. • HP_APM_M0_EXCEPTION_ADDR records the access address. • HP_APM_M0_EXCEPTION_STATUS records the reason for illegal access. – If the address requested to access is not within the enabled address ranges, bit 1 will be set to 1, indicating the address is out of bounds. – If the address requested to access is within the enabled address ranges, but the master does not have the read/write/execution permission within this region, then bit 0 will be set to 1, indicating permission restrictions. • HP_APM_M0_EXCEPTION_REGION records the permission management result of each address range. This register has a total of 16 bits, corresponding to 16 address ranges, and bit 0 corresponds to the first address range. When the address to access is within a particular enabled address range, but the master does not have the corresponding read/write/execute permission within this address range, the corresponding bit of this register will be set to 1. The SYS_APM controller can generate 12 interrupt signals, which will be sent to Interrupt Matrix: • HP_APM_M0_INTR • HP_APM_M1_INTR • HP_APM_M2_INTR • HP_APM_M3_INTR Espressif Systems 590 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) • HP_APM_M4_INTR • LP_APM_M0_INTR • LP_APM_M1_INTR • LP_APM0_M0_INTR • CPU_APM_M0_INTR • CPU_APM_M1_INTR • CPU_APM_M2_INTR • CPU_APM_M3_INTR These interrupt signals correspond to the controlled access paths shown in Figure 15.5-1. Each interrupt is configured with an interrupt enable register APM_INT_EN and an interrupt clear register EXCEPTION_STATUS_CLR. When the interrupt enable register is set to 1, if an illegal access occurs on a controlled access path, the corresponding interrupt will be generated. Configuring the interrupt clear register clears the interrupt signal until the next illegal access occurs. 15.6.2 PERI_APM Controller When the information carried on the bus does not match the configuration, ESP32-C5 treats it as an illegal access and handles it as follows: • Rejects the access request and returns a default value, specifically: – Returns 0 for read and execute operations – Ignores write operations • Returns an error message to the master via the bus, causing the master to enter an exception state Setting HP/LP_BUS_ERR_RESP_EN to 1 enables returning an error message on illegal access. The PERI_APM controller does not log information related to illegal access. 15.7 Programming Procedure For a master to access memory or peripheral registers, follow the programming procedures below: 1. Set the HP CPU to the machine mode (i.e., TEE mode). 2. Configure TEE_Mn_MODE or LP_TEE_Mn_MODE to choose the security mode for the master. The master ID n is defined in Table 15.5-1. 3. Configure HP_APM_REGIONn_ADDR_START and HP_APM_REGIONn_ADDR_END, or LP_APM_REGIONn_ADDR_START and LP_APM_REGIONn_ADDR_END, or LP_APM0_REGIONn_ADDR_START and LP_APM0_REGIONn_ADDR_END, or CPU_APM_REGIONn_ADDR_START and CPU_APM_REGIONn_ADDR_END to define the start and end address of the access address ranges. Espressif Systems 591 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) 4. Configure HP_APM_REGIONn_ATTR_REG, or LP_APM_REGIONn_ATTR_REG, or LP_APM0_REGIONn_ATTR_REG, or CPU_APM_REGIONn_ATTR_REG to set the access permissions of each region. 5. Configure HP_APM_REGION_FILTER_ EN_REG, or LP_APM_REGION_FILTER_ EN_REG, or LP_APM0_REGION_FILTER_ EN_REG, or CPU_APM_REGION_FILTER_ EN_REG to enable region n. 6. Configure HP_APM_ FUNC_CTRL_REG, or LP_APM _FUNC_CTRL_REG, or LP_APM0 _FUNC_CTRL_REG, or CPU_APM _FUNC_CTRL_REG to enable the permission management for different access paths (enabled by default). 7. (Required only when accessing peripheral registers) Configure TEE_PERI_CTRL_REG or LP_TEE_PERI_CTRL_REG to set the access permissions of the PERI register. Take I2S accessing HP SRAM via GDMA as an example, assuming that it is only allowed to read and write in the fourth address range 0x40805000 0x4080FFFF: 1. Configure the HP CPU to machine mode (i.e., TEE mode). 2. According to the master ID number in Table 15.5-1, set TEE_M19_MODE to 1, so that the security mode for I2S access via GDMA is REE0. 3. Configure HP_APM_REGION3_ADDR_START to 0x40805000 and HP_APM_REGION3_ADDR_END to 0x4080EFFC, respectively. 4. Set HP_APM_REGION3_R0_W and HP_APM_REGION3_R0_R to 1 to enable the access permissions to the address range. 5. Set bit 3 of HP_APM_REGION_FILTER_EN to 1 to enable region 3 (i.e., the fourth address range). 6. Set HP_APM_M1_FUNC_EN to 1 to enable the permission management for HP_APM_CTRL M1. Through this configuration, I2S can read and write in the address range of 0x40805000 to 0x4080FFFF in HP SRAM using GDMA. 15.8 Register Summary 15.8.1 HP_APM_REG The addresses in this section are relative to the HP_APM base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Configuration Registers HP_APM_REGION_FILTER_EN_REG Region enable register 0x0000 R/W HP_APM_REGION0_ADDR_START_REG Region address register 0x0004 R/W HP_APM_REGION0_ADDR_END_REG Region address register 0x0008 R/W HP_APM_REGION1_ADDR_START_REG Region address register 0x0010 R/W HP_APM_REGION1_ADDR_END_REG Region address register 0x0014 R/W HP_APM_REGION2_ADDR_START_REG Region address register 0x001C R/W HP_APM_REGION2_ADDR_END_REG Region address register 0x0020 R/W Espressif Systems 592 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Name Description Address Access HP_APM_REGION3_ADDR_START_REG Region address register 0x0028 R/W HP_APM_REGION3_ADDR_END_REG Region address register 0x002C R/W HP_APM_REGION4_ADDR_START_REG Region address register 0x0034 R/W HP_APM_REGION4_ADDR_END_REG Region address register 0x0038 R/W HP_APM_REGION5_ADDR_START_REG Region address register 0x0040 R/W HP_APM_REGION5_ADDR_END_REG Region address register 0x0044 R/W HP_APM_REGION6_ADDR_START_REG Region address register 0x004C R/W HP_APM_REGION6_ADDR_END_REG Region address register 0x0050 R/W HP_APM_REGION7_ADDR_START_REG Region address register 0x0058 R/W HP_APM_REGION7_ADDR_END_REG Region address register 0x005C R/W HP_APM_REGION8_ADDR_START_REG Region address register 0x0064 R/W HP_APM_REGION8_ADDR_END_REG Region address register 0x0068 R/W HP_APM_REGION9_ADDR_START_REG Region address register 0x0070 R/W HP_APM_REGION9_ADDR_END_REG Region address register 0x0074 R/W HP_APM_REGION10_ADDR_START_REG Region address register 0x007C R/W HP_APM_REGION10_ADDR_END_REG Region address register 0x0080 R/W HP_APM_REGION11_ADDR_START_REG Region address register 0x0088 R/W HP_APM_REGION11_ADDR_END_REG Region address register 0x008C R/W HP_APM_REGION12_ADDR_START_REG Region address register 0x0094 R/W HP_APM_REGION12_ADDR_END_REG Region address register 0x0098 R/W HP_APM_REGION13_ADDR_START_REG Region address register 0x00A0 R/W HP_APM_REGION13_ADDR_END_REG Region address register 0x00A4 R/W HP_APM_REGION14_ADDR_START_REG Region address register 0x00AC R/W HP_APM_REGION14_ADDR_END_REG Region address register 0x00B0 R/W HP_APM_REGION15_ADDR_START_REG Region address register 0x00B8 R/W HP_APM_REGION15_ADDR_END_REG Region address register 0x00BC R/W HP_APM_REGION0_ATTR_REG Region access permissions configuration register 0x000C R/W HP_APM_REGION1_ATTR_REG Region access permissions configuration register 0x0018 R/W HP_APM_REGION2_ATTR_REG Region access permissions configuration register 0x0024 R/W HP_APM_REGION3_ATTR_REG Region access permissions configuration register 0x0030 R/W HP_APM_REGION4_ATTR_REG Region access permissions configuration register 0x003C R/W HP_APM_REGION5_ATTR_REG Region access permissions configuration register 0x0048 R/W HP_APM_REGION6_ATTR_REG Region access permissions configuration register 0x0054 R/W HP_APM_REGION7_ATTR_REG Region access permissions configuration register 0x0060 R/W HP_APM_REGION8_ATTR_REG Region access permissions configuration register 0x006C R/W Espressif Systems 593 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Name Description Address Access HP_APM_REGION9_ATTR_REG Region access permissions configuration register 0x0078 R/W HP_APM_REGION10_ATTR_REG Region access permissions configuration register 0x0084 R/W HP_APM_REGION11_ATTR_REG Region access permissions configuration register 0x0090 R/W HP_APM_REGION12_ATTR_REG Region access permissions configuration register 0x009C R/W HP_APM_REGION13_ATTR_REG Region access permissions configuration register 0x00A8 R/W HP_APM_REGION14_ATTR_REG Region access permissions configuration register 0x00B4 R/W HP_APM_REGION15_ATTR_REG Region access permissions configuration register 0x00C0 R/W HP_APM_FUNC_CTRL_REG APM access path permission management register 0x00C4 R/W Status Registers HP_APM_M0_STATUS_REG HP_APM_CTRL M0 status register 0x00C8 RO HP_APM_M0_STATUS_CLR_REG HP_APM_CTRL M0 status clear register 0x00CC WT HP_APM_M0_EXCEPTION_INFO0_REG HP_APM_CTRL M0 exception information register 0x00D0 RO HP_APM_M0_EXCEPTION_INFO1_REG HP_APM_CTRL M0 exception information register 0x00D4 RO HP_APM_M1_STATUS_REG HP_APM_CTRL M1 status register 0x00D8 RO HP_APM_M1_STATUS_CLR_REG HP_APM_CTRL M1 status clear register 0x00DC WT HP_APM_M1_EXCEPTION_INFO0_REG HP_APM_CTRL M1 exception information register 0x00E0 RO HP_APM_M1_EXCEPTION_INFO1_REG HP_APM_CTRL M1 exception information register 0x00E4 RO HP_APM_M2_STATUS_REG HP_APM_CTRL M2 status register 0x00E8 RO HP_APM_M2_STATUS_CLR_REG HP_APM_CTRL M2 status clear register 0x00EC WT HP_APM_M2_EXCEPTION_INFO0_REG HP_APM_CTRL M2 exception information register 0x00F0 RO HP_APM_M2_EXCEPTION_INFO1_REG HP_APM_CTRL M2 exception information register 0x00F4 RO HP_APM_M3_STATUS_REG HP_APM_CTRL M3 status register 0x00F8 RO HP_APM_M3_STATUS_CLR_REG HP_APM_CTRL M3 status clear register 0x00FC WT HP_APM_M3_EXCEPTION_INFO0_REG HP_APM_CTRL M3 exception information register 0x0100 RO HP_APM_M3_EXCEPTION_INFO1_REG HP_APM_CTRL M3 exception information register 0x0104 RO HP_APM_M4_STATUS_REG HP_APM_CTRL M4 status register 0x0108 RO HP_APM_M4_STATUS_CLR_REG HP_APM_CTRL M4 status clear register 0x010C WT Espressif Systems 594 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Name Description Address Access HP_APM_M4_EXCEPTION_INFO0_REG HP_APM_CTRL M4 exception information register 0x0110 RO HP_APM_M4_EXCEPTION_INFO1_REG HP_APM_CTRL M4 exception information register 0x0114 RO Interrupt Registers HP_APM_INT_EN_REG HP_APM_CTRL M0/1/2/3/4 interrupt enable register 0x0118 R/W Clock Gating Registers HP_APM_CLOCK_GATE_REG Clock gating register 0x07F8 R/W Version Control Registers HP_APM_DATE_REG Version control register 0x07FC R/W 15.8.2 LP_APM_REG The addresses in this section are relative to the LP_APM base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Configuration Registers LP_APM_REGION_FILTER_EN_REG Region enable register 0x0000 R/W LP_APM_REGION0_ADDR_START_REG Region address register 0x0004 R/W LP_APM_REGION0_ADDR_END_REG Region address register 0x0008 R/W LP_APM_REGION1_ADDR_START_REG Region address register 0x0010 R/W LP_APM_REGION1_ADDR_END_REG Region address register 0x0014 R/W LP_APM_REGION2_ADDR_START_REG Region address register 0x001C R/W LP_APM_REGION2_ADDR_END_REG Region address register 0x0020 R/W LP_APM_REGION3_ADDR_START_REG Region address register 0x0028 R/W LP_APM_REGION3_ADDR_END_REG Region address register 0x002C R/W LP_APM_REGION4_ADDR_START_REG Region address register 0x0034 R/W LP_APM_REGION4_ADDR_END_REG Region address register 0x0038 R/W LP_APM_REGION5_ADDR_START_REG Region address register 0x0040 R/W LP_APM_REGION5_ADDR_END_REG Region address register 0x0044 R/W LP_APM_REGION6_ADDR_START_REG Region address register 0x004C R/W LP_APM_REGION6_ADDR_END_REG Region address register 0x0050 R/W LP_APM_REGION7_ADDR_START_REG Region address register 0x0058 R/W LP_APM_REGION7_ADDR_END_REG Region address register 0x005C R/W LP_APM_REGION0_ATTR_REG Region access permissions configuration register 0x000C R/W LP_APM_REGION1_ATTR_REG Region access permissions configuration register 0x0018 R/W LP_APM_REGION2_ATTR_REG Region access permissions configuration register 0x0024 R/W Espressif Systems 595 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Name Description Address Access LP_APM_REGION3_ATTR_REG Region access permissions configuration register 0x0030 R/W LP_APM_REGION4_ATTR_REG Region access permissions configuration register 0x003C R/W LP_APM_REGION5_ATTR_REG Region access permissions configuration register 0x0048 R/W LP_APM_REGION6_ATTR_REG Region access permissions configuration register 0x0054 R/W LP_APM_REGION7_ATTR_REG Region access permissions configuration register 0x0060 R/W LP_APM_FUNC_CTRL_REG APM access path permission management register 0x00C4 R/W Status Registers LP_APM_M0_STATUS_REG LP_APM_CTRL M0 status register 0x00C8 RO LP_APM_M0_STATUS_CLR_REG LP_APM_CTRL M0 status clear register 0x00CC WT LP_APM_M0_EXCEPTION_INFO0_REG LP_APM_CTRL M0 exception information register 0x00D0 RO LP_APM_M0_EXCEPTION_INFO1_REG LP_APM_CTRL M0 exception information register 0x00D4 RO LP_APM_M1_STATUS_REG LP_APM_CTRL M1 status register 0x00D8 RO LP_APM_M1_STATUS_CLR_REG LP_APM_CTRL M1 status clear register 0x00DC WT LP_APM_M1_EXCEPTION_INFO0_REG LP_APM_CTRL M1 exception information register 0x00E0 RO LP_APM_M1_EXCEPTION_INFO1_REG LP_APM_CTRL M1 exception information register 0x00E4 RO Interrupt Registers LP_APM_INT_EN_REG LP_APM_CTRL M0/1 interrupt enable register 0x00E8 R/W Clock Gating Registers LP_APM_CLOCK_GATE_REG Clock gating register 0x00EC R/W Version Control Registers LP_APM_DATE_REG Version control register 0x00FC R/W 15.8.3 LP_APM0_REG The addresses in this section are relative to the LP_APM0 base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Configuration Registers LP_APM0_REGION_FILTER_EN_REG Region enable register 0x0000 R/W LP_APM0_REGION0_ADDR_START_REG Region address register 0x0004 R/W Espressif Systems 596 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Name Description Address Access LP_APM0_REGION0_ADDR_END_REG Region address register 0x0008 R/W LP_APM0_REGION1_ADDR_START_REG Region address register 0x0010 R/W LP_APM0_REGION1_ADDR_END_REG Region address register 0x0014 R/W LP_APM0_REGION2_ADDR_START_REG Region address register 0x001C R/W LP_APM0_REGION2_ADDR_END_REG Region address register 0x0020 R/W LP_APM0_REGION3_ADDR_START_REG Region address register 0x0028 R/W LP_APM0_REGION3_ADDR_END_REG Region address register 0x002C R/W LP_APM0_REGION4_ADDR_START_REG Region address register 0x0034 R/W LP_APM0_REGION4_ADDR_END_REG Region address register 0x0038 R/W LP_APM0_REGION5_ADDR_START_REG Region address register 0x0040 R/W LP_APM0_REGION5_ADDR_END_REG Region address register 0x0044 R/W LP_APM0_REGION6_ADDR_START_REG Region address register 0x004C R/W LP_APM0_REGION6_ADDR_END_REG Region address register 0x0050 R/W LP_APM0_REGION7_ADDR_START_REG Region address register 0x0058 R/W LP_APM0_REGION7_ADDR_END_REG Region address register 0x005C R/W LP_APM0_REGION0_ATTR_REG Region access permissions configuration register 0x000C R/W LP_APM0_REGION1_ATTR_REG Region access permissions configuration register 0x0018 R/W LP_APM0_REGION2_ATTR_REG Region access permissions configuration register 0x0024 R/W LP_APM0_REGION3_ATTR_REG Region access permissions configuration register 0x0030 R/W LP_APM0_REGION4_ATTR_REG Region access permissions configuration register 0x003C R/W LP_APM0_REGION5_ATTR_REG Region access permissions configuration register 0x0048 R/W LP_APM0_REGION6_ATTR_REG Region access permissions configuration register 0x0054 R/W LP_APM0_REGION7_ATTR_REG Region access permissions configuration register 0x0060 R/W LP_APM0_FUNC_CTRL_REG APM access path permission management register 0x00C4 R/W Status Registers LP_APM0_M0_STATUS_REG LP_APM0_CTRL M0 status register 0x00C8 RO LP_APM0_M0_STATUS_CLR_REG LP_APM0_CTRL M0 status clear register 0x00CC WT LP_APM0_M0_EXCEPTION_INFO0_REG LP_APM0_CTRL M0 exception information register 0x00D0 RO LP_APM0_M0_EXCEPTION_INFO1_REG LP_APM0_CTRL M0 exception information register 0x00D4 RO Interrupt Registers LP_APM0_INT_EN_REG LP_APM0_CTRL interrupt enable register 0x00D8 R/W Espressif Systems 597 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Name Description Address Access Clock Gating Registers LP_APM0_CLOCK_GATE_REG Clock gating register 0x00DC R/W Version Control Registers LP_APM0_DATE_REG Version control register 0x07FC R/W 15.8.4 CPU_APM_REG The addresses in this section are relative to the CPU_APM base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Configuration Registers CPU_APM_REGION_FILTER_EN_REG Region enable register 0x0000 R/W Region Address Registers CPU_APM_REGION0_ADDR_START_REG Region address register 0x0004 varies CPU_APM_REGION0_ADDR_END_REG Region address register 0x0008 varies CPU_APM_REGION1_ADDR_START_REG Region address register 0x0010 varies CPU_APM_REGION1_ADDR_END_REG Region address register 0x0014 varies CPU_APM_REGION2_ADDR_START_REG Region address register 0x001C varies CPU_APM_REGION2_ADDR_END_REG Region address register 0x0020 varies CPU_APM_REGION3_ADDR_START_REG Region address register 0x0028 varies CPU_APM_REGION3_ADDR_END_REG Region address register 0x002C varies CPU_APM_REGION4_ADDR_START_REG Region address register 0x0034 varies CPU_APM_REGION4_ADDR_END_REG Region address register 0x0038 varies CPU_APM_REGION5_ADDR_START_REG Region address register 0x0040 varies CPU_APM_REGION5_ADDR_END_REG Region address register 0x0044 varies CPU_APM_REGION6_ADDR_START_REG Region address register 0x004C varies CPU_APM_REGION6_ADDR_END_REG Region address register 0x0050 varies CPU_APM_REGION7_ADDR_START_REG Region address register 0x0058 varies CPU_APM_REGION7_ADDR_END_REG Region address register 0x005C varies CPU_APM_REGION0_ATTR_REG Region access permissions configuration register 0x000C R/W CPU_APM_REGION1_ATTR_REG Region access permissions configuration register 0x0018 R/W CPU_APM_REGION2_ATTR_REG Region access permissions configuration register 0x0024 R/W CPU_APM_REGION3_ATTR_REG Region access permissions configuration register 0x0030 R/W CPU_APM_REGION4_ATTR_REG Region access permissions configuration register 0x003C R/W CPU_APM_REGION5_ATTR_REG Region access permissions configuration register 0x0048 R/W Espressif Systems 598 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Name Description Address Access CPU_APM_REGION6_ATTR_REG Region access permissions configuration register 0x0054 R/W CPU_APM_REGION7_ATTR_REG Region access permissions configuration register 0x0060 R/W CPU_APM_FUNC_CTRL_REG APM access path permission management register 0x00C4 R/W Status Registers CPU_APM_M0_STATUS_REG CPU_APM_CTRL M0 status register 0x00C8 RO CPU_APM_M0_STATUS_CLR_REG CPU_APM_CTRL M0 status clear register 0x00CC WT CPU_APM_M0_EXCEPTION_INFO0_REG CPU_APM_CTRL M0 exception information register 0x00D0 RO CPU_APM_M0_EXCEPTION_INFO1_REG CPU_APM_CTRL M0 exception information register 0x00D4 RO CPU_APM_M1_STATUS_REG CPU_APM_CTRL M1 status register 0x00D8 RO CPU_APM_M1_STATUS_CLR_REG CPU_APM_CTRL M1 status clear register 0x00DC WT CPU_APM_M1_EXCEPTION_INFO0_REG CPU_APM_CTRL M1 exception information register 0x00E0 RO CPU_APM_M1_EXCEPTION_INFO1_REG CPU_APM_CTRL M1 exception information register 0x00E4 RO Interrupt Registers CPU_APM_INT_EN_REG CPU_APM_CTRL M0/1 interrupt enable register 0x0118 R/W Clock Gating Registers CPU_APM_CLOCK_GATE_REG Clock gating register 0x07F8 R/W Version Control Registers CPU_APM_DATE_REG Version control register 0x07FC R/W 15.8.5 TEE_REG The addresses in this section are relative to the TEE base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Configuration Registers TEE_M0_MODE_CTRL_REG Security mode configuration register 0x0000 R/W TEE_M1_MODE_CTRL_REG Security mode configuration register 0x0004 R/W TEE_M2_MODE_CTRL_REG Security mode configuration register 0x0008 R/W TEE_M3_MODE_CTRL_REG Security mode configuration register 0x000C R/W TEE_M4_MODE_CTRL_REG Security mode configuration register 0x0010 R/W TEE_M5_MODE_CTRL_REG Security mode configuration register 0x0014 R/W TEE_M6_MODE_CTRL_REG Security mode configuration register 0x0018 R/W TEE_M7_MODE_CTRL_REG Security mode configuration register 0x001C R/W Espressif Systems 599 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Name Description Address Access TEE_M8_MODE_CTRL_REG Security mode configuration register 0x0020 R/W TEE_M9_MODE_CTRL_REG Security mode configuration register 0x0024 R/W TEE_M10_MODE_CTRL_REG Security mode configuration register 0x0028 R/W TEE_M11_MODE_CTRL_REG Security mode configuration register 0x002C R/W TEE_M12_MODE_CTRL_REG Security mode configuration register 0x0030 R/W TEE_M13_MODE_CTRL_REG Security mode configuration register 0x0034 R/W TEE_M14_MODE_CTRL_REG Security mode configuration register 0x0038 R/W TEE_M15_MODE_CTRL_REG Security mode configuration register 0x003C R/W TEE_M16_MODE_CTRL_REG Security mode configuration register 0x0040 R/W TEE_M17_MODE_CTRL_REG Security mode configuration register 0x0044 R/W TEE_M18_MODE_CTRL_REG Security mode configuration register 0x0048 R/W TEE_M19_MODE_CTRL_REG Security mode configuration register 0x004C R/W TEE_M20_MODE_CTRL_REG Security mode configuration register 0x0050 R/W TEE_M21_MODE_CTRL_REG Security mode configuration register 0x0054 R/W TEE_M22_MODE_CTRL_REG Security mode configuration register 0x0058 R/W TEE_M23_MODE_CTRL_REG Security mode configuration register 0x005C R/W TEE_M24_MODE_CTRL_REG Security mode configuration register 0x0060 R/W TEE_M25_MODE_CTRL_REG Security mode configuration register 0x0064 R/W TEE_M26_MODE_CTRL_REG Security mode configuration register 0x0068 R/W TEE_M27_MODE_CTRL_REG Security mode configuration register 0x006C R/W TEE_M28_MODE_CTRL_REG Security mode configuration register 0x0070 R/W TEE_M29_MODE_CTRL_REG Security mode configuration register 0x0074 R/W TEE_M30_MODE_CTRL_REG Security mode configuration register 0x0078 R/W TEE_M31_MODE_CTRL_REG Security mode configuration register 0x007C R/W Peripheral Read/Write Control Registers TEE_UART0_CTRL_REG UART0 read/write control register 0x0088 R/W TEE_UART1_CTRL_REG UART1 read/write control register 0x008C R/W TEE_UHCI0_CTRL_REG UHCI read/write control register 0x0090 R/W TEE_I2C_EXT0_CTRL_REG I2C read/write control register 0x0094 R/W TEE_I2S_CTRL_REG I2S read/write control register 0x009C R/W TEE_PARL_IO_CTRL_REG PARL_IO read/write control register 0x00A0 R/W TEE_PWM_CTRL_REG MCPWM read/write control register 0x00A4 R/W TEE_LEDC_CTRL_REG LEDC read/write control register 0x00AC R/W TEE_TWAI0_CTRL_REG TWAI0 read/write control register 0x00B0 R/W TEE_USB_SERIAL_JTAG_CTRL_REG USB_SERIAL_JTAG read/write control register 0x00B4 R/W TEE_RMT_CTRL_REG RMT read/write control register 0x00B8 R/W TEE_GDMA_CTRL_REG GDMA read/write control register 0x00BC R/W TEE_ETM_CTRL_REG SOC_ETM read/write control register 0x00C4 R/W TEE_INTMTX_CTRL_REG INTMTX read/write control register 0x00C8 R/W TEE_APB_ADC_CTRL_REG SAR ADC read/write control register 0x00D0 R/W TEE_TIMERGROUP0_CTRL_REG TIMG0 read/write control register 0x00D4 R/W TEE_TIMERGROUP1_CTRL_REG TIMG1 read/write control register 0x00D8 R/W Espressif Systems 600 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Name Description Address Access TEE_SYSTIMER_CTRL_REG SYSTIMER read/write control register 0x00DC R/W TEE_PCNT_CTRL_REG PCNT read/write control register 0x00F4 R/W TEE_IOMUX_CTRL_REG IO MUX read/write control register 0x00F8 R/W TEE_PSRAM_MEM_MONITOR_CTRL_REG PSRAM_MEM_MONITOR read/write control register 0x00FC R/W TEE_MEM_ACS_MONITOR_CTRL_REG TCM_MEM_MONITOR read/write control register 0x0100 R/W TEE_HP_SYSTEM_REG_CTRL_REG HP_SYSREG read/write control register 0x0104 R/W TEE_PCR_REG_CTRL_REG PCR read/write control register 0x0108 R/W TEE_MSPI_CTRL_REG SPI01 read/write control register 0x010C R/W TEE_HP_APM_CTRL_REG HP_APM and LP_APM0 read/write control register 0x0110 varies TEE_CPU_APM_CTRL_REG CPU_APM_REG read/write control register 0x0114 varies TEE_TEE_CTRL_REG TEE read/write control register 0x0118 varies TEE_CRYPT_CTRL_REG CRYPT read/write control register, including security peripherals from AES to ECDSA address range 0x011C R/W TEE_TRACE_CTRL_REG TRACE read/write control register 0x0120 R/W TEE_CPU_BUS_MONITOR_CTRL_REG BUS_MONITOR read/write control register 0x0128 R/W TEE_INTPRI_REG_CTRL_REG INTPRI_REG read/write control register 0x012C R/W TEE_TWAI1_CTRL_REG TWAI1 read/write control register 0x0138 R/W TEE_SPI2_CTRL_REG SPI2 read/write control register 0x013C R/W TEE_BS_CTRL_REG BITSCRAMBLER read/write control register 0x0140 R/W TEE_BUS_ERR_CONF_REG Error message return configuration register 0x0FF0 R/W clock gating register TEE_CLOCK_GATE_REG Clock gating register 0x0FF8 R/W Version Control Registers TEE_DATE_REG Version control register 0x0FFC R/W 15.8.6 LP_TEE_REG The addresses in this section are relative to the LP_TEE base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Configuration Registers LP_TEE_M0_MODE_CTRL_REG Security mode configuration register 0x0000 R/W Peripheral Read/Write Control Register Espressif Systems 601 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Name Description Address Access LP_TEE_EFUSE_CTRL_REG eFuse read/write control register 0x0004 R/W LP_TEE_PMU_CTRL_REG PMU read/write control register 0x0008 R/W LP_TEE_CLKRST_CTRL_REG LP_CLKRST read/write control register 0x000C R/W LP_TEE_LP_AON_CTRL_CTRL_REG LP_AON read/write control register 0x0010 R/W LP_TEE_LP_TIMER_CTRL_REG LP_TIMER read/write control register 0x0014 R/W LP_TEE_LP_WDT_CTRL_REG LP_WDT read/write control register 0x0018 R/W LP_TEE_LP_PERI_CTRL_REG LPPERI read/write control register 0x001C R/W LP_TEE_LP_ANA_PERI_CTRL_REG LP_ANA_PERI read/write control register 0x0020 R/W LP_TEE_LP_IO_CTRL_REG LP_GPIO and LP_IO_MUX read/write control register 0x002C R/W LP_TEE_LP_TEE_CTRL_REG LP_TEE read/write control register 0x0034 varies LP_TEE_UART_CTRL_REG LP_UART read/write control register 0x0038 R/W LP_TEE_I2C_EXT_CTRL_REG LP_I2C read/write control register 0x0040 R/W LP_TEE_I2C_ANA_MST_CTRL_REG I2C_ANA_MST read/write control register 0x0044 R/W LP_TEE_LP_APM_CTRL_REG LP_APM read/write control register 0x004C varies LP_TEE_FORCE_ACC_HP_REG Force access to HP SRAM configuration register 0x0090 R/W LP_TEE_BUS_ERR_CONF_REG Error message return configuration register 0x00F0 R/W Clock Gating Registers LP_TEE_CLOCK_GATE_REG Clock gating register 0x00F8 R/W Version Control Registers LP_TEE_DATE_REG Version control register 0x00FC R/W Espressif Systems 602 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) 15.9 Registers 15.9.1 HP_APM_REG The addresses in this section are relative to the HP_APM base address provided in Table 4.3-2 in Chapter 4 System and Memory. For how to program reserved fields, please refer to Section Programming Reserved Register Field. Register 15.1. HP_APM_REGION_FILTER_EN_REG (0x0000) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 HP_APM_REGION_FILTER_EN 0x01 15 0 Reset HP_APM_REGION_FILTER_EN Configure bit n (0-15) to enable permission checks for region n (0- 15). 0: Disable 1: Enable (R/W) Register 15.2. HP_APM_REGIONn_ADDR_START_REG (n: 0-15) (0x0004+0xC*n) HP_APM_REGIONn_ADDR_START 0 31 0 Reset HP_APM_REGIONn_ADDR_START Configures the start address of region n. (R/W) Espressif Systems 603 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Register 15.3. HP_APM_REGIONn_ADDR_END_REG (n: 0-15) (0x0008+0xC*n) HP_APM_REGIONn_ADDR_END 0xffffffff 31 0 Reset HP_APM_REGIONn_ADDR_END Configures the end address of region n. (R/W) Register 15.4. HP_APM_REGIONn_ATTR_REG (n: 0-15) (0x000C+0xC*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 12 HP_APM_REGIONn_LOCK 0 11 HP_APM_REGIONn_R2_R 0 10 HP_APM_REGIONn_R2_W 0 9 HP_APM_REGIONn_R2_X 0 8 (reserved) 0 7 HP_APM_REGIONn_R1_R 0 6 HP_APM_REGIONn_R1_W 0 5 HP_APM_REGIONn_R1_X 0 4 (reserved) 0 3 HP_APM_REGIONn_R0_R 0 2 HP_APM_REGIONn_R0_W 0 1 HP_APM_REGIONn_R0_X 0 0 Reset HP_APM_REGIONn_R0_X Configures the execution permission in region n in REE0 mode. (R/W) HP_APM_REGIONn_R0_W Configures the write permission in region n in REE0 mode. (R/W) HP_APM_REGIONn_R0_R Configures the read permission in region n in REE0 mode. (R/W) HP_APM_REGIONn_R1_X Configures the execution permission in region n in REE1 mode. (R/W) HP_APM_REGIONn_R1_W Configures the write permission in region n in REE1 mode. (R/W) HP_APM_REGIONn_R1_R Configures the read permission in region n in REE1 mode. (R/W) HP_APM_REGIONn_R2_X Configures the execution permission in region n in REE2 mode. (R/W) HP_APM_REGIONn_R2_W Configures the write permission in region n in REE2 mode. (R/W) HP_APM_REGIONn_R2_R Configures the read permission in region n in REE2 mode. (R/W) HP_APM_REGIONn_LOCK Configures to lock the value of region n configuration regis- ters (HP_APM_REGIONn_ADDR_START_REG, HP_APM_REGIONn_ADDR_END_REG and HP_APM_REGIONn_ATTR_REG). 0: Do not lock 1: Lock (R/W) Espressif Systems 604 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Register 15.5. HP_APM_FUNC_CTRL_REG (0x00C4) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 5 HP_APM_M4_FUNC_EN 1 4 HP_APM_M3_FUNC_EN 1 3 HP_APM_M2_FUNC_EN 1 2 HP_APM_M1_FUNC_EN 1 1 HP_APM_M0_FUNC_EN 1 0 Reset HP_APM_M0_FUNC_EN Configures to enable permission management for HP_APM_CTRL M0. (R/W) HP_APM_M1_FUNC_EN Configures to enable permission management for HP_APM_CTRL M1. (R/W) HP_APM_M2_FUNC_EN Configures to enable permission management for HP_APM_CTRL M2. (R/W) HP_APM_M3_FUNC_EN Configures to enable permission management for HP_APM_CTRL M3. (R/W) HP_APM_M4_FUNC_EN Configures to enable permission management for HP_APM_CTRL M4. (R/W) Register 15.6. HP_APM_M0_STATUS_REG (0x00C8) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 2 HP_APM_M0_EXCEPTION_STATUS 0 1 0 Reset HP_APM_M0_EXCEPTION_STATUS Represents exception status. bit0: 1 represents permission restrictions bit1: 1 represents address out of bounds (RO) Espressif Systems 605 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Register 15.7. HP_APM_M0_STATUS_CLR_REG (0x00CC) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 HP_APM_M0_EXCEPTION_STATUS_CLR 0 0 Reset HP_APM_M0_EXCEPTION_STATUS_CLR Configures to clear exception status. (WT) Register 15.8. HP_APM_M0_EXCEPTION_INFO0_REG (0x00D0) (reserved) 0 0 0 0 0 0 0 0 0 31 23 HP_APM_M0_EXCEPTION_ID 0 22 18 HP_APM_M0_EXCEPTION_MODE 0 17 16 HP_APM_M0_EXCEPTION_REGION 0 15 0 Reset HP_APM_M0_EXCEPTION_REGION Represents the region where an exception occurs. (RO) HP_APM_M0_EXCEPTION_MODE Represents the master’s security mode when an exception oc- curs. (RO) HP_APM_M0_EXCEPTION_ID Represents master ID when an exception occurs. (RO) Register 15.9. HP_APM_M0_EXCEPTION_INFO1_REG (0x00D4) HP_APM_M0_EXCEPTION_ADDR 0 31 0 Reset HP_APM_M0_EXCEPTION_ADDR Represents the access address when an exception occurs. (RO) Espressif Systems 606 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Register 15.10. HP_APM_M1_STATUS_REG (0x00D8) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 2 HP_APM_M1_EXCEPTION_STATUS 0 1 0 Reset HP_APM_M1_EXCEPTION_STATUS Represents exception status. bit0: 1 represents permission restrictions bit1: 1 represents address out of bounds (RO) Register 15.11. HP_APM_M1_STATUS_CLR_REG (0x00DC) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 HP_APM_M1_EXCEPTION_STATUS_CLR 0 0 Reset HP_APM_M1_EXCEPTION_STATUS_CLR Configures to clear exception status. (WT) Espressif Systems 607 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Register 15.12. HP_APM_M1_EXCEPTION_INFO0_REG (0x00E0) (reserved) 0 0 0 0 0 0 0 0 0 31 23 HP_APM_M1_EXCEPTION_ID 0 22 18 HP_APM_M1_EXCEPTION_MODE 0 17 16 HP_APM_M1_EXCEPTION_REGION 0 15 0 Reset HP_APM_M1_EXCEPTION_REGION Represents the region where an exception occurs. (RO) HP_APM_M1_EXCEPTION_MODE Represents the master’s security mode when an exception oc- curs. (RO) HP_APM_M1_EXCEPTION_ID Represents master ID when an exception occurs. (RO) Register 15.13. HP_APM_M1_EXCEPTION_INFO1_REG (0x00E4) HP_APM_M1_EXCEPTION_ADDR 0 31 0 Reset HP_APM_M1_EXCEPTION_ADDR Represents the access address when an exception occurs. (RO) Espressif Systems 608 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Register 15.14. HP_APM_M2_STATUS_REG (0x00E8) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 2 HP_APM_M2_EXCEPTION_STATUS 0 1 0 Reset HP_APM_M2_EXCEPTION_STATUS Represents exception status. bit0: 1 represents permission restrictions bit1: 1 represents address out of bounds (RO) Register 15.15. HP_APM_M2_STATUS_CLR_REG (0x00EC) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 HP_APM_M2_EXCEPTION_STATUS_CLR 0 0 Reset HP_APM_M2_EXCEPTION_STATUS_CLR Configures to clear exception status. (WT) Espressif Systems 609 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Register 15.16. HP_APM_M2_EXCEPTION_INFO0_REG (0x00F0) (reserved) 0 0 0 0 0 0 0 0 0 31 23 HP_APM_M2_EXCEPTION_ID 0 22 18 HP_APM_M2_EXCEPTION_MODE 0 17 16 HP_APM_M2_EXCEPTION_REGION 0 15 0 Reset HP_APM_M2_EXCEPTION_REGION Represents the region where an exception occurs. (RO) HP_APM_M2_EXCEPTION_MODE Represents the master’s security mode when an exception oc- curs. (RO) HP_APM_M2_EXCEPTION_ID Represents master ID when an exception occurs. (RO) Register 15.17. HP_APM_M2_EXCEPTION_INFO1_REG (0x00F4) HP_APM_M2_EXCEPTION_ADDR 0 31 0 Reset HP_APM_M2_EXCEPTION_ADDR Represents the access address when an exception occurs. (RO) Espressif Systems 610 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Register 15.18. HP_APM_M3_STATUS_REG (0x00F8) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 2 HP_APM_M3_EXCEPTION_STATUS 0 1 0 Reset HP_APM_M3_EXCEPTION_STATUS Represents exception status. bit0: 1 represents permission restrictions bit1: 1 represents address out of bounds (RO) Register 15.19. HP_APM_M3_STATUS_CLR_REG (0x00FC) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 HP_APM_M3_EXCEPTION_STATUS_CLR 0 0 Reset HP_APM_M3_EXCEPTION_STATUS_CLR Configures to clear exception status. (WT) Espressif Systems 611 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Register 15.20. HP_APM_M3_EXCEPTION_INFO0_REG (0x0100) (reserved) 0 0 0 0 0 0 0 0 0 31 23 HP_APM_M3_EXCEPTION_ID 0 22 18 HP_APM_M3_EXCEPTION_MODE 0 17 16 HP_APM_M3_EXCEPTION_REGION 0 15 0 Reset HP_APM_M3_EXCEPTION_REGION Represents the region where an exception occurs. (RO) HP_APM_M3_EXCEPTION_MODE Represents the master’s security mode when an exception oc- curs. (RO) HP_APM_M3_EXCEPTION_ID Represents master ID when an exception occurs. (RO) Register 15.21. HP_APM_M3_EXCEPTION_INFO1_REG (0x0104) HP_APM_M3_EXCEPTION_ADDR 0 31 0 Reset HP_APM_M3_EXCEPTION_ADDR Represents the access address when an exception occurs. (RO) Espressif Systems 612 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Register 15.22. HP_APM_M4_STATUS_REG (0x0108) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 2 HP_APM_M4_EXCEPTION_STATUS 0 1 0 Reset HP_APM_M4_EXCEPTION_STATUS Represents exception status. bit0: 1 represents permission restrictions bit1: 1 represents address out of bounds (RO) Register 15.23. HP_APM_M4_STATUS_CLR_REG (0x010C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 HP_APM_M4_EXCEPTION_STATUS_CLR 0 0 Reset HP_APM_M4_EXCEPTION_STATUS_CLR Configures to clear exception status. (WT) Espressif Systems 613 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Register 15.24. HP_APM_M4_EXCEPTION_INFO0_REG (0x0110) (reserved) 0 0 0 0 0 0 0 0 0 31 23 HP_APM_M4_EXCEPTION_ID 0 22 18 HP_APM_M4_EXCEPTION_MODE 0 17 16 HP_APM_M4_EXCEPTION_REGION 0 15 0 Reset HP_APM_M4_EXCEPTION_REGION Represents the region where an exception occurs. (RO) HP_APM_M4_EXCEPTION_MODE Represents the master’s security mode when an exception oc- curs. (RO) HP_APM_M4_EXCEPTION_ID Represents master ID when an exception occurs. (RO) Register 15.25. HP_APM_M4_EXCEPTION_INFO1_REG (0x0114) HP_APM_M4_EXCEPTION_ADDR 0 31 0 Reset HP_APM_M4_EXCEPTION_ADDR Represents the access address when an exception occurs. (RO) Espressif Systems 614 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Register 15.26. HP_APM_INT_EN_REG (0x0118) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 5 HP_APM_M4_APM_INT_EN 0 4 HP_APM_M3_APM_INT_EN 0 3 HP_APM_M2_APM_INT_EN 0 2 HP_APM_M1_APM_INT_EN 0 1 HP_APM_M0_APM_INT_EN 0 0 Reset HP_APM_M0_APM_INT_EN Configures to enable HP_APM_CTRL M0 interrupt. 0: Disable 1: Enable (R/W) HP_APM_M1_APM_INT_EN Configures to enable HP_APM_CTRL M1 interrupt. 0: Disable 1: Enable (R/W) HP_APM_M2_APM_INT_EN Configures to enable HP_APM_CTRL M2 interrupt. 0: Disable 1: Enable (R/W) HP_APM_M3_APM_INT_EN Configures to enable HP_APM_CTRL M3 interrupt. 0: Disable 1: Enable (R/W) HP_APM_M4_APM_INT_EN Configures to enable HP_APM_CTRL M4 interrupt. 0: Disable 1: Enable (R/W) Register 15.27. HP_APM_CLOCK_GATE_REG (0x07F8) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 HP_APM_CLK_EN 1 0 Reset HP_APM_CLK_EN Configures whether to keep the clock always on. 0: Enable automatic clock gating 1: Keep the clock always on (R/W) Espressif Systems 615 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Register 15.28. HP_APM_DATE_REG (0x07FC) (reserved) 0 0 0 0 31 28 HP_APM_DATE 0x2312010 27 0 Reset HP_APM_DATE Version control register. (R/W) 15.9.2 LP_APM_REG The addresses in this section are relative to the LP_APM base address provided in Table 4.3-2 in Chapter 4 System and Memory. For how to program reserved fields, please refer to Section Programming Reserved Register Field. Register 15.29. LP_APM_REGION_FILTER_EN_REG (0x0000) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 LP_APM_REGION_FILTER_EN 0x1 7 0 Reset LP_APM_REGION_FILTER_EN Configures bit n (0-7) to enable permission checks for region n (0-7). 0: Disable 1: Enable (R/W) Register 15.30. LP_APM_REGIONn_ADDR_START_REG (n: 0-7) (0x0004+0xC*n) LP_APM_REGIONn_ADDR_START 0 31 0 Reset LP_APM_REGIONn_ADDR_START Configures the start address of region n. (R/W) Espressif Systems 616 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Register 15.31. LP_APM_REGIONn_ADDR_END_REG (n: 0-7) (0x0008+0xC*n) LP_APM_REGIONn_ADDR_END 0xffffffff 31 0 Reset LP_APM_REGIONn_ADDR_END Configures the end address of region n. (R/W) Register 15.32. LP_APM_REGIONn_ATTR_REG (n: 0-7) (0x000C+0xC*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 12 LP_APM_REGIONn_LOCK 0 11 LP_APM_REGIONn_R2_R 0 10 LP_APM_REGIONn_R2_W 0 9 LP_APM_REGIONn_R2_X 0 8 (reserved) 0 7 LP_APM_REGIONn_R1_R 0 6 LP_APM_REGIONn_R1_W 0 5 LP_APM_REGIONn_R1_X 0 4 (reserved) 0 3 LP_APM_REGIONn_R0_R 0 2 LP_APM_REGIONn_R0_W 0 1 LP_APM_REGIONn_R0_X 0 0 Reset LP_APM_REGIONn_R0_X Configures the execution permission in region n in REE0 mode. (R/W) LP_APM_REGIONn_R0_W Configures the write permission in region n in REE0 mode. (R/W) LP_APM_REGIONn_R0_R Configures the read permission in region n in REE0 mode. (R/W) LP_APM_REGIONn_R1_X Configures the execution permission in region n in REE1 mode. (R/W) LP_APM_REGIONn_R1_W Configures the write permission in region n in REE1 mode. (R/W) LP_APM_REGIONn_R1_R Configures the read permission in region n in REE1 mode. (R/W) LP_APM_REGIONn_R2_X Configures the execution permission in region n in REE1 mode. (R/W) LP_APM_REGIONn_R2_W Configures the write permission in region n in REE2 mode. (R/W) LP_APM_REGIONn_R2_R Configures the read permission in region n in REE2 mode. (R/W) LP_APM_REGIONn_LOCK Configures to lock the value of region n configuration regis- ters (LP_APM_REGIONn_ADDR_START_REG, LP_APM_REGIONn_ADDR_END_REG and LP_APM_REGIONn_ATTR_REG). 0: Do not lock 1: Lock (R/W) Espressif Systems 617 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Register 15.33. LP_APM_FUNC_CTRL_REG (0x00C4) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 2 LP_APM_M1_FUNC_EN 1 1 LP_APM_M0_FUNC_EN 1 0 Reset LP_APM_M0_FUNC_EN Configures to enable permission management for LP_APM_CTRL M0. (R/W) LP_APM_M1_FUNC_EN Configures to enable permission management for LP_APM_CTRL M1. (R/W) Register 15.34. LP_APM_M0_STATUS_REG (0x00C8) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 2 LP_APM_M0_EXCEPTION_STATUS 0 1 0 Reset LP_APM_M0_EXCEPTION_STATUS Represents exception status. bit0: 1 represents permission restrictions bit1: 1 represents address out of bounds (RO) Register 15.35. LP_APM_M0_STATUS_CLR_REG (0x00CC) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 LP_APM_M0_EXCEPTION_STATUS_CLR 0 0 Reset LP_APM_M0_EXCEPTION_STATUS_CLR Configures to clear exception status. (WT) Espressif Systems 618 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Register 15.36. LP_APM_M0_EXCEPTION_INFO0_REG (0x00D0) (reserved) 0 0 0 0 0 0 0 0 0 31 23 LP_APM_M0_EXCEPTION_ID 0 22 18 LP_APM_M0_EXCEPTION_MODE 0 17 16 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 15 4 LP_APM_M0_EXCEPTION_REGION 0 3 0 Reset LP_APM_M0_EXCEPTION_REGION Represents the region where an exception occurs. (RO) LP_APM_M0_EXCEPTION_MODE Represents the master’s security mode when an exception oc- curs. (RO) LP_APM_M0_EXCEPTION_ID Represents master ID when an exception occurs. (RO) Register 15.37. LP_APM_M0_EXCEPTION_INFO1_REG (0x00D4) LP_APM_M0_EXCEPTION_ADDR 0 31 0 Reset LP_APM_M0_EXCEPTION_ADDR Represents the access address when an exception occurs. (RO) Register 15.38. LP_APM_M1_STATUS_REG (0x00D8) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 2 LP_APM_M1_EXCEPTION_STATUS 0 1 0 Reset LP_APM_M1_EXCEPTION_STATUS Represents exception status. bit0: 1 represents permission restrictions bit1: 1 represents address out of bounds (RO) Espressif Systems 619 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Register 15.39. LP_APM_M1_STATUS_CLR_REG (0x00DC) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 LP_APM_M1_EXCEPTION_STATUS_CLR 0 0 Reset LP_APM_M1_EXCEPTION_STATUS_CLR Configures to clear exception status. (WT) Register 15.40. LP_APM_M1_EXCEPTION_INFO0_REG (0x00E0) (reserved) 0 0 0 0 0 0 0 0 0 31 23 LP_APM_M1_EXCEPTION_ID 0 22 18 LP_APM_M1_EXCEPTION_MODE 0 17 16 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 15 4 LP_APM_M1_EXCEPTION_REGION 0 3 0 Reset LP_APM_M1_EXCEPTION_REGION Represents the region where an exception occurs. (RO) LP_APM_M1_EXCEPTION_MODE Represents the master’s security mode when an exception oc- curs. (RO) LP_APM_M1_EXCEPTION_ID Represents master ID when an exception occurs. (RO) Register 15.41. LP_APM_M1_EXCEPTION_INFO1_REG (0x00E4) LP_APM_M1_EXCEPTION_ADDR 0 31 0 Reset LP_APM_M1_EXCEPTION_ADDR Represents the access address when an exception occurs. (RO) Espressif Systems 620 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Register 15.42. LP_APM_INT_EN_REG (0x00E8) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 2 LP_APM_M1_APM_INT_EN 0 1 LP_APM_M0_APM_INT_EN 0 0 Reset LP_APM_M0_APM_INT_EN Configures to enable LP_APM_CTRL M0 interrupt. 0: Disable 1: Enable (R/W) LP_APM_M1_APM_INT_EN Configures to enable LP_APM_CTRL M1 interrupt. 0: Disable 1: Enable (R/W) Register 15.43. LP_APM_CLOCK_GATE_REG (0x00EC) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 LP_APM_CLK_EN 1 0 Reset LP_APM_CLK_EN Configures whether to keep the clock always on. 0: Enable automatic clock gating 1: Keep the clock always on (R/W) Register 15.44. LP_APM_DATE_REG (0x00FC) (reserved) 0 0 0 0 31 28 LP_APM_DATE 0x2212160 27 0 Reset LP_APM_DATE Version control register. (R/W) Espressif Systems 621 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) 15.9.3 LP_APM0_REG The addresses in this section are relative to the LP_APM0 base address provided in Table 4.3-2 in Chapter 4 System and Memory. For how to program reserved fields, please refer to Section Programming Reserved Register Field. Register 15.45. LP_APM0_REGION_FILTER_EN_REG (0x0000) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 LP_APM0_REGION_FILTER_EN 0x1 7 0 Reset LP_APM0_REGION_FILTER_EN Configures bit n (0-7) to enable permission checks for region n (0- 7). 0: Disable 1: Enable (R/W) Register 15.46. LP_APM0_REGIONn_ADDR_START_REG (n: 0-7) (0x0004+0xC*n) LP_APM0_REGIONn_ADDR_START 0 31 0 Reset LP_APM0_REGIONn_ADDR_START Configures the start address of region n. (R/W) Espressif Systems 622 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Register 15.47. LP_APM0_REGIONn_ADDR_END_REG (n: 0-7) (0x0008+0xC*n) LP_APM0_REGIONn_ADDR_END 0xffffffff 31 0 Reset LP_APM0_REGIONn_ADDR_END Configures the end address of region n. (R/W) Register 15.48. LP_APM0_REGIONn_ATTR_REG (n: 0-7) (0x000C+0xC*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 12 LP_APM0_REGIONn_LOCK 0 11 LP_APM0_REGIONn_R2_R 0 10 LP_APM0_REGIONn_R2_W 0 9 LP_APM0_REGIONn_R2_X 0 8 (reserved) 0 7 LP_APM0_REGIONn_R1_R 0 6 LP_APM0_REGIONn_R1_W 0 5 LP_APM0_REGIONn_R1_X 0 4 (reserved) 0 3 LP_APM0_REGIONn_R0_R 0 2 LP_APM0_REGIONn_R0_W 0 1 LP_APM0_REGIONn_R0_X 0 0 Reset LP_APM0_REGIONn_R0_X Configures the execution permission in region n in REE0 mode. (R/W) LP_APM0_REGIONn_R0_W Configures the write permission in region n in REE0 mode. (R/W) LP_APM0_REGIONn_R0_R Configures the read permission in region n in REE0 mode. (R/W) LP_APM0_REGIONn_R1_X Configures the execution permission in region n in REE1 mode. (R/W) LP_APM0_REGIONn_R1_W Configures the write permission in region n in REE1 mode. (R/W) LP_APM0_REGIONn_R1_R Configures the read permission in region n in REE1 mode. (R/W) LP_APM0_REGIONn_R2_X Configures the execution permission in region n in REE2 mode. (R/W) LP_APM0_REGIONn_R2_W Configures the write permission in region n in REE2 mode. (R/W) LP_APM0_REGIONn_R2_R Configures the read permission in region n in REE2 mode. (R/W) LP_APM0_REGIONn_LOCK Configures to lock the value of region n configuration regis- ters (LP_APM0_REGIONn_ADDR_START_REG, LP_APM0_REGIONn_ADDR_END_REG and LP_APM0_REGIONn_ATTR_REG). 0: Do not lock 1: Lock (R/W) Espressif Systems 623 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Register 15.49. LP_APM0_FUNC_CTRL_REG (0x00C4) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 LP_APM0_M0_FUNC_EN 1 0 Reset LP_APM0_M0_FUNC_EN Configures to enable permission management for LP_APM0_CTRL M0. (R/W) Register 15.50. LP_APM0_M0_STATUS_REG (0x00C8) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 2 LP_APM0_M0_EXCEPTION_STATUS 0 1 0 Reset LP_APM0_M0_EXCEPTION_STATUS Represents exception status. bit0: 1 represents permission restrictions bit1: 1 represents address out of bounds (RO) Register 15.51. LP_APM0_M0_STATUS_CLR_REG (0x00CC) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 LP_APM0_M0_EXCEPTION_STATUS_CLR 0 0 Reset LP_APM0_M0_EXCEPTION_STATUS_CLR Configures to clear exception status. (WT) Espressif Systems 624 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Register 15.52. LP_APM0_M0_EXCEPTION_INFO0_REG (0x00D0) (reserved) 0 0 0 0 0 0 0 0 0 31 23 LP_APM0_M0_EXCEPTION_ID 0 22 18 LP_APM0_M0_EXCEPTION_MODE 0 17 16 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 15 4 LP_APM0_M0_EXCEPTION_REGION 0 3 0 Reset LP_APM0_M0_EXCEPTION_REGION Represents the region where an exception occurs. (RO) LP_APM0_M0_EXCEPTION_MODE Represents the master’s security mode when an exception oc- curs. (RO) LP_APM0_M0_EXCEPTION_ID Represents master ID when an exception occurs. (RO) Register 15.53. LP_APM0_M0_EXCEPTION_INFO1_REG (0x00D4) LP_APM0_M0_EXCEPTION_ADDR 0 31 0 Reset LP_APM0_M0_EXCEPTION_ADDR Represents the access address when an exception occurs. (RO) Espressif Systems 625 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Register 15.54. LP_APM0_INT_EN_REG (0x00D8) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 LP_APM0_M0_APM_INT_EN 0 0 Reset LP_APM0_M0_APM_INT_EN Configures to enable LP_APM0_CTRL M0 interrupt. 0: Disable 1: Enable (R/W) Register 15.55. LP_APM0_CLOCK_GATE_REG (0x00DC) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 LP_APM0_CLK_EN 1 0 Reset LP_APM0_CLK_EN Configures whether to keep the clock always on. 0: Enable automatic clock gating 1: Keep the clock always on (R/W) Register 15.56. LP_APM0_DATE_REG (0x07FC) (reserved) 0 0 0 0 31 28 LP_APM0_DATE 0x2212160 27 0 Reset LP_APM0_DATE Version control register. (R/W) 15.9.4 CPU_APM_REG The addresses in this section are relative to the CPU_APM base address provided in Table 4.3-2 in Chapter 4 System and Memory. For how to program reserved fields, please refer to Section Programming Reserved Register Field. Espressif Systems 626 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Register 15.57. CPU_APM_REGION_FILTER_EN_REG (0x0000) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 CPU_APM_REGION_FILTER_EN 0x1 7 0 Reset CPU_APM_REGION_FILTER_EN Configures bit n (0-7) to enable permission checks for region n (0- 7). 0: Disable 1: Enable (R/W) Register 15.58. CPU_APM_REGIONn_ADDR_START_REG (n: 0-7) (0x0004+0xC*n) CPU_APM_REGIONn_ADDR_START_H 0x810 31 19 CPU_APM_REGIONn_ADDR_START 0x0 18 12 CPU_APM_REGIONn_ADDR_START_L 0x0 11 0 Reset CPU_APM_REGIONn_ADDR_START_L Indicates the lower 12 bits of the start address of region n. (HRO) CPU_APM_REGIONn_ADDR_START Configures the start address of region n. (R/W) CPU_APM_REGIONn_ADDR_START_H Indicates the higher 13 bits of the start address of region n. (HRO) Espressif Systems 627 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Register 15.59. CPU_APM_REGIONn_ADDR_END_REG (n: 0-7) (0x0008+0xC*n) CPU_APM_REGIONn_ADDR_END_H 0x810 31 19 CPU_APM_REGIONn_ADDR_END 0x7f 18 12 CPU_APM_REGIONn_ADDR_END_L 0xfff 11 0 Reset CPU_APM_REGIONn_ADDR_END_L Indicates the lower 12 bits of the end address of region n. (HRO) CPU_APM_REGIONn_ADDR_END Configures the end address of region n. (R/W) CPU_APM_REGIONn_ADDR_END_H Indicates the higher 13 bits of the end address of region n. (HRO) Espressif Systems 628 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Register 15.60. CPU_APM_REGIONn_ATTR_REG (n: 0-7) (0x000C+0xC*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 12 CPU_APM_REGIONn_LOCK 0 11 CPU_APM_REGIONn_R2_R 0 10 CPU_APM_REGIONn_R2_W 0 9 CPU_APM_REGIONn_R2_X 0 8 (reserved) 0 7 CPU_APM_REGIONn_R1_R 0 6 CPU_APM_REGIONn_R1_W 0 5 CPU_APM_REGIONn_R1_X 0 4 (reserved) 0 3 CPU_APM_REGIONn_R0_R 0 2 CPU_APM_REGIONn_R0_W 0 1 CPU_APM_REGIONn_R0_X 0 0 Reset CPU_APM_REGIONn_R0_X Configures the execution permission in region n in REE0 mode. (R/W) CPU_APM_REGIONn_R0_W Configures the write permission in region n in REE0 mode. (R/W) CPU_APM_REGIONn_R0_R Configures the read permission in region n in REE0 mode. (R/W) CPU_APM_REGIONn_R1_X Configures the execution permission in region n in REE1 mode. (R/W) CPU_APM_REGIONn_R1_W Configures the write permission in region n in REE1 mode. (R/W) CPU_APM_REGIONn_R1_R Configures the read permission in region n in REE1 mode. (R/W) CPU_APM_REGIONn_R2_X Configures the execution permission in region n in REE2 mode. (R/W) CPU_APM_REGIONn_R2_W Configures the write permission in region n in REE2 mode. (R/W) CPU_APM_REGIONn_R2_R Configures the read permission in region n in REE2 mode. (R/W) CPU_APM_REGIONn_LOCK Configures to lock the value of region n’s configuration regis- ters (CPU_APM_REGIONn_ADDR_START_REG, CPU_APM_REGIONn_ADDR_END_REG, and CPU_APM_REGIONn_ATTR_REG). 0: Do not lock 1: Lock (R/W) Espressif Systems 629 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Register 15.61. CPU_APM_FUNC_CTRL_REG (0x00C4) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 2 CPU_APM_M1_FUNC_EN 1 1 CPU_APM_M0_FUNC_EN 1 0 Reset CPU_APM_M0_FUNC_EN Configures whether to enable permission management for CPU_APM_CTRL M0. 0: Disable 1: Enable (R/W) CPU_APM_M1_FUNC_EN Configures whether to enable permission management for CPU_APM_CTRL M1. 0: Disable 1: Enable (R/W) Register 15.62. CPU_APM_M0_STATUS_REG (0x00C8) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 2 CPU_APM_M0_EXCEPTION_STATUS 0 1 0 Reset CPU_APM_M0_EXCEPTION_STATUS Represents exception status. bit0: 1 represents permission restrictions bit1: 1 represents address out of bounds (RO) Espressif Systems 630 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Register 15.63. CPU_APM_M0_STATUS_CLR_REG (0x00CC) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 CPU_APM_M0_EXCEPTION_STATUS_CLR 0 0 Reset CPU_APM_M0_EXCEPTION_STATUS_CLR Write 1 to clear exception status. (WT) Register 15.64. CPU_APM_M0_EXCEPTION_INFO0_REG (0x00D0) (reserved) 0 0 0 0 0 0 0 0 0 31 23 CPU_APM_M0_EXCEPTION_ID 0 22 18 CPU_APM_M0_EXCEPTION_MODE 0 17 16 CPU_APM_M0_EXCEPTION_REGION 0 15 0 Reset CPU_APM_M0_EXCEPTION_REGION Represents the region where an exception occurs. (RO) CPU_APM_M0_EXCEPTION_MODE Represents the master’s security mode when an exception oc- curs. (RO) CPU_APM_M0_EXCEPTION_ID Represents master ID when an exception occurs. (RO) Register 15.65. CPU_APM_M0_EXCEPTION_INFO1_REG (0x00D4) CPU_APM_M0_EXCEPTION_ADDR 0 31 0 Reset CPU_APM_M0_EXCEPTION_ADDR Represents the access address when an exception occurs. (RO) Espressif Systems 631 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Register 15.66. CPU_APM_M1_STATUS_REG (0x00D8) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 2 CPU_APM_M1_EXCEPTION_STATUS 0 1 0 Reset CPU_APM_M1_EXCEPTION_STATUS Represents exception status. bit0: 1 represents permission restrictions bit1: 1 represents address out of bounds (RO) Register 15.67. CPU_APM_M1_STATUS_CLR_REG (0x00DC) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 CPU_APM_M1_EXCEPTION_STATUS_CLR 0 0 Reset CPU_APM_M1_EXCEPTION_STATUS_CLR Write 1 to clear exception status. (WT) Espressif Systems 632 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Register 15.68. CPU_APM_M1_EXCEPTION_INFO0_REG (0x00E0) (reserved) 0 0 0 0 0 0 0 0 0 31 23 CPU_APM_M1_EXCEPTION_ID 0 22 18 CPU_APM_M1_EXCEPTION_MODE 0 17 16 CPU_APM_M1_EXCEPTION_REGION 0 15 0 Reset CPU_APM_M1_EXCEPTION_REGION Represents the region where an exception occurs. (RO) CPU_APM_M1_EXCEPTION_MODE Represents the master’s security mode when an exception oc- curs. (RO) CPU_APM_M1_EXCEPTION_ID Represents master ID when an exception occurs. (RO) Register 15.69. CPU_APM_M1_EXCEPTION_INFO1_REG (0x00E4) CPU_APM_M1_EXCEPTION_ADDR 0 31 0 Reset CPU_APM_M1_EXCEPTION_ADDR Represents the access address when an exception occurs. (RO) Espressif Systems 633 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Register 15.70. CPU_APM_INT_EN_REG (0x0118) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 2 CPU_APM_M1_APM_INT_EN 0 1 CPU_APM_M0_APM_INT_EN 0 0 Reset CPU_APM_M0_APM_INT_EN Configures whether to enable CPU_APM_CTRL M0 interrupt. 0: Disable 1: Enable (R/W) CPU_APM_M1_APM_INT_EN Configures whether to enable CPU_APM_CTRL M1 interrupt. 0: Disable 1: Enable (R/W) Register 15.71. CPU_APM_CLOCK_GATE_REG (0x07F8) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 CPU_APM_CLK_EN 1 0 Reset CPU_APM_CLK_EN Configures whether to keep the clock always on. 0: Enable automatic clock gating 1: Keep the clock always on (R/W) Register 15.72. CPU_APM_DATE_REG (0x07FC) (reserved) 0 0 0 0 31 28 CPU_APM_DATE 0x2405090 27 0 Reset CPU_APM_DATE Version control register. (R/W) Espressif Systems 634 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) 15.9.5 TEE_REG The addresses in this section are relative to the TEE base address provided in Table 4.3-2 in Chapter 4 System and Memory. For how to program reserved fields, please refer to Section Programming Reserved Register Field. Register 15.73. TEE_Mn_MODE_CTRL_REG (n: 0-31) (0x0000+0x4*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 TEE_Mn_LOCK 0 2 TEE_Mn_MODE 0 1 0 Reset TEE_Mn_MODE Configures the security mode for master n. 0: TEE 1: REE0 2: REE1 3: REE2 (R/W) TEE_Mn_LOCK Configures whether to lock the value of TEE_Mn_MODE. 0: Do not lock 1: Lock (R/W) Register 15.74. TEE_UART0_CTRL_REG (0x0088) Register 15.75. TEE_UART1_CTRL_REG (0x008C) Register 15.76. TEE_UHCI0_CTRL_REG (0x0090) Register 15.77. TEE_I2C_EXT0_CTRL_REG (0x0094) Register 15.78. TEE_I2S_CTRL_REG (0x009C) Register 15.79. TEE_PARL_IO_CTRL_REG (0x00A0) Register 15.80. TEE_PWM_CTRL_REG (0x00A4) Register 15.81. TEE_LEDC_CTRL_REG (0x00AC) Register 15.82. TEE_TWAI0_CTRL_REG (0x00B0) Register 15.83. TEE_USB_SERIAL_JTAG_CTRL_REG (0x00B4) Register 15.84. TEE_RMT_CTRL_REG (0x00B8) Register 15.85. TEE_GDMA_CTRL_REG (0x00BC) Register 15.86. TEE_ETM_CTRL_REG (0x00C4) Register 15.87. TEE_INTMTX_CTRL_REG (0x00C8) Register 15.88. TEE_APB_ADC_CTRL_REG (0x00D0) Espressif Systems 635 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Register 15.89. TEE_TIMERGROUP0_CTRL_REG (0x00D4) Register 15.90. TEE_TIMERGROUP1_CTRL_REG (0x00D8) Register 15.91. TEE_SYSTIMER_CTRL_REG (0x00DC) Register 15.92. TEE_PCNT_CTRL_REG (0x00F4) Register 15.93. TEE_IOMUX_CTRL_REG (0x00F8) Register 15.94. TEE_PSRAM_MEM_MONITOR_CTRL_REG (0x00FC) Register 15.95. TEE_MEM_ACS_MONITOR_CTRL_REG (0x0100) Register 15.96. TEE_HP_SYSTEM_REG_CTRL_REG (0x0104) Register 15.97. TEE_PCR_REG_CTRL_REG (0x0108) Register 15.98. TEE_MSPI_CTRL_REG (0x010C) Register 15.99. TEE_HP_APM_CTRL_REG (0x0110) Register 15.100. TEE_CPU_APM_CTRL_REG (0x0114) Register 15.101. TEE_TEE_CTRL_REG (0x0118) Register 15.102. TEE_CRYPT_CTRL_REG (0x011C) Register 15.103. TEE_TRACE_CTRL_REG (0x0120) Register 15.104. TEE_CPU_BUS_MONITOR_CTRL_REG (0x0128) Register 15.105. TEE_INTPRI_REG_CTRL_REG (0x012C) Register 15.106. TEE_TWAI1_CTRL_REG (0x0138) Register 15.107. TEE_SPI2_CTRL_REG (0x013C) Register 15.108. TEE_BS_CTRL_REG (0x0140) Register 15.109. TEE_PERI_CTRL_REG (0x0088-0x0158) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 TEE_WRITE_REE2_PERI 0 7 TEE_WRITE_REE1_PERI 0 6 TEE_WRITE_REE0_PERI 0 5 TEE_WRITE_TEE_PERI 1 4 TEE_READ_REE2_PERI 0 3 TEE_READ_REE1_PERI 0 2 TEE_READ_REE0_PERI 0 1 TEE_READ_TEE_PERI 1 0 Reset TEE_READ_TEE_PERI Configures the read permission of PERI in TEE mode. (R/W) TEE_READ_REE0_PERI Configures the read permission of PERI in REE0 mode. (R/W) TEE_READ_REE1_PERI Configures the read permission of PERI in REE1 mode. (R/W) TEE_READ_REE2_PERI Configures the read permission of PERI in REE2 mode. (R/W) TEE_WRITE_TEE_PERI Configures the write permission of PERI in TEE mode. (R/W) TEE_WRITE_REE0_PERI Configures the write permission of PERI in REE0 mode. (R/W) TEE_WRITE_REE1_PERI Configures the write permission of PERI in REE1 mode. (R/W) TEE_WRITE_REE2_PERI Configures the write permission of PERI in REE2 mode. (R/W) Espressif Systems 636 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Register 15.110. TEE_BUS_ERR_CONF_REG (0x0FF0) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 TEE_BUS_ERR_RESP_EN 0 0 Reset TEE_BUS_ERR_RESP_EN Configures whether to return error message to CPU when access is blocked. 0: Disable 1: Enable (R/W) Register 15.111. TEE_CLOCK_GATE_REG (0x0FF8) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 TEE_CLK_EN 1 0 Reset TEE_CLK_EN Configures whether to keep the clock always on. 0: Enable automatic clock gating 1: Keep the clock always on (R/W) Register 15.112. TEE_DATE_REG (0x0FFC) (reserved) 0 0 0 0 31 28 TEE_DATE 0x2406200 27 0 Reset TEE_DATE Version control register. (R/W) 15.9.6 LP_TEE_REG The addresses in this section are relative to the LP_TEE base address provided in Table 4.3-2 in Chapter 4 System and Memory. For how to program reserved fields, please refer to Section Programming Reserved Register Field. Espressif Systems 637 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Register 15.113. LP_TEE_M0_MODE_CTRL_REG (0x0000) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 LP_TEE_M0_LOCK 0 2 LP_TEE_M0_MODE 3 1 0 Reset LP_TEE_M0_MODE Configures the security mode for LP CPU. 0: TEE 1: REE0 2: REE1 3: REE2 (R/W) LP_TEE_M0_LOCK Configures to lock the value of LP_TEE_M0_MODE. 0: Do not lock 1: Lock (R/W) Register 15.114. LP_TEE_EFUSE_CTRL_REG (0x0004) Register 15.115. LP_TEE_PMU_CTRL_REG (0x0008) Register 15.116. LP_TEE_CLKRST_CTRL_REG (0x000C) Register 15.117. LP_TEE_LP_AON_CTRL_CTRL_REG (0x0010) Register 15.118. LP_TEE_LP_TIMER_CTRL_REG (0x0014) Register 15.119. LP_TEE_LP_WDT_CTRL_REG (0x0018) Register 15.120. LP_TEE_LP_PERI_CTRL_REG (0x001C) Register 15.121. LP_TEE_LP_ANA_PERI_CTRL_REG (0x0020) Register 15.122. LP_TEE_LP_IO_CTRL_REG (0x002C) Register 15.123. LP_TEE_LP_TEE_CTRL_REG (0x0034) Register 15.124. LP_TEE_UART_CTRL_REG (0x0038) Register 15.125. LP_TEE_I2C_EXT_CTRL_REG (0x0040) Register 15.126. LP_TEE_I2C_ANA_MST_CTRL_REG (0x0044) Register 15.127. LP_TEE_LP_APM_CTRL_REG (0x004C) Espressif Systems 638 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Register 15.128. LP_TEE_PERI_CTRL_REG (0x0004-0x004C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 LP_TEE_WRITE_REE2_PERI 0 7 LP_TEE_WRITE_REE1_PERI 0 6 LP_TEE_WRITE_REE0_PERI 0 5 LP_TEE_WRITE_TEE_PERI 1 4 LP_TEE_READ_REE2_PERI 0 3 LP_TEE_READ_REE1_PERI 0 2 LP_TEE_READ_REE0_PERI 0 1 LP_TEE_READ_TEE_PERI 1 0 Reset LP_TEE_READ_TEE_PERI Configures the read permission of PERI in TEE mode. (R/W) LP_TEE_READ_REE0_PERI Configures the read permission of PERI in REE0 mode. (R/W) LP_TEE_READ_REE1_PERI Configures the read permission of PERI in REE1 mode. (R/W) LP_TEE_READ_REE2_PERI Configures the read permission of PERI in REE2 mode. (R/W) LP_TEE_WRITE_TEE_PERI Configures the write permission of PERI in TEE mode. (R/W) LP_TEE_WRITE_REE0_PERI Configures the write permission of PERI in REE0 mode. (R/W) LP_TEE_WRITE_REE1_PERI Configures the write permission of PERI in REE1 mode. (R/W) LP_TEE_WRITE_REE2_PERI Configures the write permission of PERI in REE2 mode. (R/W) Register 15.129. LP_TEE_FORCE_ACC_HP_REG (0x0090) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 LP_TEE_FORCE_ACC_HPMEM_EN 0 0 Reset LP_TEE_FORCE_ACC_HPMEM_EN Configures whether to allow LP CPU to forcibly access HP SRAM regardless of permission management. 0: Disable force access to HP SRAM 1: Enable force access to HP SRAM (R/W) Espressif Systems 639 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 15 Permission Control (PMS) Register 15.130. LP_TEE_BUS_ERR_CONF_REG (0x00F0) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 LP_TEE_BUS_ERR_RESP_EN 0 0 Reset LP_TEE_BUS_ERR_RESP_EN Configures whether to return error message to CPU when access is blocked. 0: Disable 1: Enable (R/W) Register 15.131. LP_TEE_CLOCK_GATE_REG (0x00F8) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 LP_TEE_CLK_EN 1 0 Reset LP_TEE_CLK_EN Configures whether to keep the clock always on. 0: Enable automatic clock gating 1: Keep the clock always on (R/W) Register 15.132. LP_TEE_DATE_REG (0x00FC) (reserved) 0 0 0 0 31 28 LP_TEE_DATE 0x241018 27 0 Reset LP_TEE_DATE Version control register. (R/W) Espressif Systems 640 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 16 System Registers Chapter 16 System Registers 16.1 Overview ESP32-C5 supports a set of auxiliary chip features listed in subsection 16.2 Features below. This chapter describes the registers used to configure these features. 16.2 Features ESP32-C5 system registers control the following peripheral blocks and core modules: • External Memory Encryption/Decryption • Anti-DPA attack security • HP CPU/LP CPU debug • Bus timeout protection 16.3 Function Description 16.3.1 External Memory Encryption/Decryption Configuration Register HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG configures encryption and decryption options of the external memory. For details, please refer to Chapter 26 External Memory Encryption and Decryption (XTS_AES). 16.3.2 Anti-DPA Attack Security Control ESP32-C5 has a dual protection mechanism against Differential Power Analysis (DPA) attacks at the hardware level. • First, a mask mechanism is introduced in the symmetric encryption operation, which interferes with the power consumption trajectory by masking the real data in the operation process. This security mechanism cannot be turned off. • Second, the clock selected for the operation will change dynamically in real time, blurring the power consumption trajectory during the operation. For this security mechanism, ESP32-C5 provides 4 security levels for users to choose to adapt to different applications. Espressif Systems 641 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 16 System Registers Table 16.3-1. Security Level Security-Level Name Security-Level Value PLL_CLK (MHz) XTAL_CLK (MHz) SEC_DPA_OFF 0 160 48 B SEC_DPA_LOW 1 (120 ,160] A (24,48] A SEC_DPA_MIDDLE 2 (96,160] A (16,48] A SEC_DPA_HIGH 3 (80,160] A (9.6,48] A A (x,y] means the operating frequency is greater than x Hz, and equal to or less than y Hz. B This value corresponds to a 48 MHz external crystal. If a 40 MHz external crystal is used, the frequency here should be 40 MHz accordingly. By default, the field HP_SYSTEM_SEC_DPA_CFG_SEL in register HP_SYSTEM_SEC_DPA_CONF_REG is 0. In this case, the security-level is decided by the eFuse field EFUSE_SEC_DPA_LEVEL. If the field HP_SYSTEM_SEC_DPA_CFG_SEL is set to 1, the security-level is decided by HP_SYSTEM_SEC_DPA_CFG_LEVEL in register HP_SYSTEM_SEC_DPA_CONF_REG. 16.3.3 HP CPU/LP CPU Debug Control Register HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE controls the RunStall feature, which facilitates the debugging of HP CPU and LP CPU. If enabled, when any of the HP CPUs is in debug mode, the other one is stalled automatically. For details, please refer to the Subsection 3 Controller Area Network Flexible Data-Rate [to be added later] in Chapter 1 High-Performance CPU [to be added later]. 16.3.4 Bus Timeout Protection ESP32-C5 supports bus timeout protection and allows configurable timeout threshold. When a transfer is initiated, the internal counter of the timeout protection module increments by 1 on each clock cycle. • If the accumulated value remains below the timeout threshold and a response is received from the slave device, the counter is cleared. • If the accumulated value exceeds the threshold and no response has been received, the module forces the bus return signal high to terminate the transfer. At the same time, an interrupt is triggered, and the module logs the exception address and the master ID associated with the access. 16.3.4.1 CPU Peripheral Timeout Protection Register Register HP_SYSTEM_CPU_PERI_TIMEOUT_CONF_REG configures the timeout protection for accessing CPU peripherals, which refer to the peripherals or modules whose addresses are in the range of 0x600C_0000–0x600C_FFFF. For details, please refer to Subsection 4.3.5 Modules/Peripherals Address Mapping in Chapter 4 System and Memory. When a timeout occurs, the CPU_PERI_TIMEOUT_INTR interrupt will be triggered. • HP_SYSTEM_CPU_PERI_TIMEOUT_CONF_REG: Enables timeout protection and configures the timeout threshold. Espressif Systems 642 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 16 System Registers • HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_REG: When a timeout occurs, this register will record the address of the timeout. • HP_SYSTEM_CPU_PERI_TIMEOUT_UID_REG: When a timeout occurs, this register will record the master ID of the timeout. 16.3.4.2 HP Peripheral Timeout Protection Register HP_SYSTEM_HP_PERI_TIMEOUT_CONF_REG configures the timeout protection for accessing HP peripherals, which refer to the peripherals or modules whose addresses are in the range of 0x6000_0000–0x6009_FFFF. For details, please refer to Subsection 4.3.5 Modules/Peripherals Address Mapping in Chapter 4 System and Memory. When a timeout occurs, the HP_PERI_TIMEOUT_INTR interrupt will be triggered. • HP_SYSTEM_HP_PERI_TIMEOUT_CONF_REG: Enables timeout protection and configures the timeout threshold. • HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_REG: When a timeout occurs, this register will record the address of the timeout. • HP_SYSTEM_HP_PERI_TIMEOUT_UID_REG: When a timeout occurs, this register will record the master ID of the timeout. 16.3.4.3 LP Peripheral Timeout Protection Register Register LP_PERI_BUS_TIMEOUT_CONF_REG configures the timeout protection for accessing LP peripherals, which refer to the peripherals or modules whose addresses are in the range of 0x600B_0000–0x600B_FFFF. For details, please refer to Subsection 4.3.5 Modules/Peripherals Address Mapping in Chapter 4 System and Memory. When a timeout occurs, the LP_PERI_TIMEOUT_INTR interrupt will be triggered. • LP_PERI_BUS_TIMEOUT_CONF_REG: Enables timeout protection and configures the timeout threshold. • LP_PERI_BUS_TIMEOUT_ADDR_REG: When a timeout occurs, this register will record the address of the timeout. • LP_PERI_BUS_TIMEOUT_UID_REG: When a timeout occurs, this register will record the master ID of the timeout. Espressif Systems 643 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 16 System Registers 16.4 Register Summary In this section, addresses starting with HP_SYSTEM are relative to System Registers base address and addresses starting with LP_PERI are relative to LP Peripherals base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Configuration Register HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_- DECRYPT_CONTROL_REG External device encryption/decryption configuration register 0x0000 R/W HP_SYSTEM_SEC_DPA_CONF_REG HP anti-DPA security configuration register 0x0008 R/W HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_- REG Core Debug RunStall configuration register 0x0040 R/W HP_SYSTEM_BITSCRAMBLER_PERI_SEL_REG BitScrambler peripherals select 0x0080 R/W CPU Peripheral Timeout Register HP_SYSTEM_CPU_PERI_TIMEOUT_CONF_REG Timeout protection configuration register 0x000C varies HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_REG Abnormal access address register 0x0010 RO HP_SYSTEM_CPU_PERI_TIMEOUT_UID_REG Master ID and permission register 0x0014 WTC HP Peripheral Timeout Register HP_SYSTEM_HP_PERI_TIMEOUT_CONF_REG Timeout protection configuration register 0x0018 varies HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_REG Abnormal access address register 0x001C RO HP_SYSTEM_HP_PERI_TIMEOUT_UID_REG Master ID and permission register 0x0020 WTC LP Peripheral Timeout Register LP_PERI_BUS_TIMEOUT_CONF_REG LP Peripheral timeout configuration register 0x0010 varies LP_PERI_BUS_TIMEOUT_ADDR_REG LP Peripheral abnormal access address register 0x0014 RO LP_PERI_BUS_TIMEOUT_UID_REG LP Peripheral Master ID and permission register 0x0018 WTC Version Register HP_SYSTEM_DATE_REG Date control and version control register 0x03FC R/W Espressif Systems 644 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 16 System Registers 16.5 Registers In this section, addresses starting with HP_SYSTEM are relative to System Registers base address and addresses starting with LP_PERI are relative to LP Peripherals base address provided in Table 4.3-2 in Chapter 4 System and Memory. Register 16.1. HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (0x0000) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 4 HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT 0 3 HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT 0 2 (reserved) 0 1 HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT 0 0 Reset HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT Configures whether to enable MSPI XTS manual encryption in SPI boot mode. 0: Disable 1: Enable (R/W) HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT Configures whether to enable MSPI XTS auto decryption in download boot mode. 0: Disable 1: Enable (R/W) HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT Configures whether to enable MSPI XTS manual encryption in download boot mode. 0: Disable 1: Enable (R/W) Espressif Systems 645 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 16 System Registers Register 16.2. HP_SYSTEM_SEC_DPA_CONF_REG (0x0008) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 HP_SYSTEM_SEC_DPA_CFG_SEL 0 2 HP_SYSTEM_SEC_DPA_LEVEL 0x0 1 0 Reset HP_SYSTEM_SEC_DPA_LEVEL Configures whether to enable anti-DPA attack. Valid only when HP_SYSTEM_SEC_DPA_CFG_SEL is 0. 0: Disable 1-3: Enable. The larger the number, the higher the security level, which represents the ability to resist DPA attacks, with increased computational overhead of the hardware crypto-accelerators at the same time. (R/W) HP_SYSTEM_SEC_DPA_CFG_SEL Configures whether to select HP_SYSTEM_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL (from eFuse) to control DPA level. 0: Select EFUSE_SEC_DPA_LEVEL 1: Select HP_SYSTEM_SEC_DPA_LEVEL (R/W) Espressif Systems 646 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 16 System Registers Register 16.3. HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG (0x0040) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 2 HP_SYSTEM_CORE_RUNSTALLED 0 1 HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE 0 0 Reset HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE Configures whether to enable the RunStall feature for HP CPU and LP CPU, which means when any of the CPUs is in debug mode, the other one is stalled automatically. 0: Disable 1: Enable (R/W) HP_SYSTEM_CORE_RUNSTALLED Indicates the RunStall status of the HP CPU. 0: Not stalled 1: Stalled (RO) Espressif Systems 647 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 16 System Registers Register 16.4. HP_SYSTEM_BITSCRAMBLER_PERI_SEL_REG (0x0080) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 HP_SYSTEM_BITSCRAMBLER_TX_SEL 0x0 7 4 HP_SYSTEM_BITSCRAMBLER_RX_SEL 0x0 3 0 Reset HP_SYSTEM_BITSCRAMBLER_RX_SEL Configures to select the DMA-capable peripheral for BitScrambler’s RX channel. 1: GPSPI2 2: UHCI0 3: I2S0 4: AES 5: SHA 6: ADC 7: PARL_IO others: NONE (R/W) HP_SYSTEM_BITSCRAMBLER_TX_SEL Configures to select the DMA-capable peripheral for BitScrambler’s TX channel. 1: GPSPI2 2: UHCI0 3: I2S0 4: AES 5: SHA 6: ADC 7: PARL_IO others: Reserved (R/W) Espressif Systems 648 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 16 System Registers Register 16.5. HP_SYSTEM_CPU_PERI_TIMEOUT_CONF_REG (0x000C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 18 HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN 1 17 HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR 0 16 HP_SYSTEM_CPU_PERI_TIMEOUT_THRES 0xffff 15 0 Reset HP_SYSTEM_CPU_PERI_TIMEOUT_THRES Configures the timeout threshold for bus access for accessing CPU peripheral register in the number of clock cycles of the clock domain. (R/W) HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR Write 1 to clear timeout interrupt. (WT) HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN Configures whether to enable timeout protec- tion for accessing CPU peripheral registers. 0: Disable 1: Enable (R/W) Register 16.6. HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_REG (0x0010) HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR 0x000000 31 0 Reset HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR Represents the address information of abnormal ac- cess. (RO) Espressif Systems 649 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 16 System Registers Register 16.7. HP_SYSTEM_CPU_PERI_TIMEOUT_UID_REG (0x0014) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 7 HP_SYSTEM_CPU_PERI_TIMEOUT_UID 0x0 6 0 Reset HP_SYSTEM_CPU_PERI_TIMEOUT_UID Represents the master ID[4:0] and master permission[6:5] when trigger timeout. This register will be cleared after the interrupt is cleared. (WTC) Register 16.8. HP_SYSTEM_HP_PERI_TIMEOUT_CONF_REG (0x0018) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 18 HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN 1 17 HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR 0 16 HP_SYSTEM_HP_PERI_TIMEOUT_THRES 0xffff 15 0 Reset HP_SYSTEM_HP_PERI_TIMEOUT_THRES Configures the timeout threshold for bus access for ac- cessing HP peripheral registers, corresponding to the number of clock cycles of the clock domain. (R/W) HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR Write 1 to clear timeout interrupt. (WT) HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN Configures whether to enable timeout protec- tion for accessing HP peripheral registers. 0: Disable 1: Enable (R/W) Espressif Systems 650 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 16 System Registers Register 16.9. HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_REG (0x001C) HP_SYSTEM_HP_PERI_TIMEOUT_ADDR 0x000000 31 0 Reset HP_SYSTEM_HP_PERI_TIMEOUT_ADDR Represents the address information of abnormal access. (RO) Register 16.10. HP_SYSTEM_HP_PERI_TIMEOUT_UID_REG (0x0020) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 7 HP_SYSTEM_HP_PERI_TIMEOUT_UID 0x0 6 0 Reset HP_SYSTEM_HP_PERI_TIMEOUT_UID Represents the master ID[4:0] and master permission[6:5] when trigger timeout. This register will be cleared after the interrupt is cleared. (WTC) Espressif Systems 651 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 16 System Registers Register 16.11. LP_PERI_BUS_TIMEOUT_CONF_REG (0x0010) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 18 LP_PERI_BUS_TIMEOUT_PROTECT_EN 1 17 LP_PERI_BUS_TIMEOUT_INT_CLEAR 0 16 LP_PERI_BUS_TIMEOUT_THRES 0xffff 15 0 Reset LP_PERI_BUS_TIMEOUT_THRES Configures the timeout threshold for bus access for accessing LP peripheral registers, corresponding to the number of clock cycles of the clock domain. (R/W) LP_PERI_BUS_TIMEOUT_INT_CLEAR Write 1 to clear timeout interrupt.(WT) LP_PERI_BUS_TIMEOUT_PROTECT_EN Configures whether to enable timeout protection for ac- cessing LP peripheral registers. 0: Disable 1: Enable (R/W) Register 16.12. LP_PERI_BUS_TIMEOUT_ADDR_REG (0x0014) LP_PERI_BUS_TIMEOUT_ADDR 0x000000 31 0 Reset LP_PERI_BUS_TIMEOUT_ADDR Represents the address information of abnormal access. (RO) Espressif Systems 652 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 16 System Registers Register 16.13. LP_PERI_BUS_TIMEOUT_UID_REG (0x0018) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 7 LP_PERI_BUS_TIMEOUT_UID 0x0 6 0 Reset LP_PERI_BUS_TIMEOUT_UID Represents the master ID[4:0] and master permission[6:5] when trig- ger timeout. This register will be cleared after the interrupt is cleared. (WTC) Register 16.14. HP_SYSTEM_DATE_REG (0x03FC) (reserved) 0 0 0 0 31 28 HP_SYSTEM_DATE 0x2312080 27 0 Reset HP_SYSTEM_DATE Version control register. (R/W) Espressif Systems 653 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 17 Debug Assistant Chapter 17 Debug Assistant 17.1 Overview Debug Assistant is an auxiliary module that features a set of functions to help locate bugs and issues during software debugging. 17.2 Features The Debug Assistant module has the following features: • Region read/write monitoring: Monitors whether the High-Performance CPU (HP CPU) bus reads from or writes to a specified memory address space. A detected read or write in the monitored address space will trigger an interrupt. • Stack pointer (SP) monitoring: Monitors whether the SP exceeds the specified address space. A bounds violation will trigger an interrupt. • Program counter (PC) logging: Records the PC value. The last PC value at the most recent reset of HP CPU can be fetched. • Bus access logging: Records the information about bus access. When the HP CPU, Low-Power CPU (LP CPU), or the Direct Memory Access controller (DMA) writes a specified value, the Debug Assistant module will record the data type, address of this write operation, and additionally the PC value when the write is performed by HP CPU, and push such information to the HP SRAM. 17.3 Functional Description 17.3.1 Region Read/Write Monitoring The Debug Assistant module can monitor reads/writes performed by HP CPU bus in a certain address space, i.e., memory region. Whenever the bus reads or writes to the specified address space, an interrupt will be triggered. Please refer to Table 1 in Chapter 1 High-Performance CPU [to be added later]. In this chapter, when HP CPU bus accesses the data space, it is referred to as the Data bus, and when HP CPU bus accesses the AHB peripheral space, it is referred to as the Peripheral bus. The Debug Assistant module can simultaneously monitor two memory regions (assuming they are HP CPU region 0 and HP CPU region 1) on the Data bus, as well as on the Peripheral bus. The region 0 and 1 should be defined based on the developer’s needs. The supported region read/write monitoring modes are listed below. • Monitoring the read/write operations performed by the Data bus Espressif Systems 654 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 17 Debug Assistant – HP CPU Data bus reads from HP CPU region 0 – HP CPU Data bus writes to HP CPU region 0 – HP CPU Data bus reads from HP CPU region 1 – HP CPU Data bus writes to HP CPU region 1 • Monitoring the read/write operations performed by the Peripheral bus – HP CPU Peripheral bus reads from HP CPU region 0 – HP CPU Peripheral bus writes to HP CPU region 0 – HP CPU Peripheral bus reads from HP CPU region 1 – HP CPU Peripheral bus writes to HP CPU region 1 17.3.2 SP Monitoring The Debug Assistant module can monitor the SP to prevent stack overflow or erroneous push/pop in HP CPU. When the HP CPU SP exceeds the monitored region’s lower or upper bounds, the module will record the PC and generate an interrupt. The bound is configured by software. The supported SP monitoring modes are listed below. • HP CPU SP goes beyond the upper bound of the HP CPU SP monitored region • HP CPU SP goes below the lower bound of the HP CPU SP monitored region 17.3.3 PC Logging In some cases, software developers may need to identify the PC value at the last reset of HP CPU. For instance, when the program is stuck and requires a reset, the developer may want to know where the program got stuck in order to debug. The Debug Assistant module can record the PC at the last reset of HP CPU, which can be then read for software debugging. 17.3.4 CPU/DMA Bus Access Logging The Debug Assistant module can record the write operations of the HP CPU Data bus, LP CPU bus, and DMA bus in real time. When a write operation occurs in or a specific value is written to a specified address space, the module will record the bus type, the address, PC (only when the write is performed by the HP CPU), and other information. It will then store the data in the HP SRAM in a certain format. The specified address range must fall within the permitted memory regions of HP SRAM or external RAM. 17.4 Interrupts The Debug Assistant can generate the BUS_MONITOR_INT interrupt signal that will be sent to the Interrupt Matrix. The following interrupt sources can generate this interrupt signal. • BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INT: Triggered when the HP CPU Data bus reads from HP CPU region 0. Espressif Systems 655 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 17 Debug Assistant • BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INT: Triggered when the HP CPU Data bus writes to HP CPU region 0. • BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INT: Triggered when the HP CPU Data bus reads from HP CPU region 1. • BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INT: Triggered when the HP CPU Data bus writes to HP CPU region 1. • BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INT: Triggered when the HP CPU Peripheral bus reads from HP CPU region 0. • BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INT: Triggered when the HP CPU Peripheral bus writes to HP CPU region 0. • BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INT: Triggered when the HP CPU Peripheral bus reads from HP CPU region 1. • BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INT: Triggered when the HP CPU Peripheral bus writes to HP CPU region 1. • BUS_MONITOR_CORE_0_SP_SPILL_MIN_INT: Triggered when the HP CPU SP goes below the lower bound of the HP CPU SP monitored region. • BUS_MONITOR_CORE_0_SP_SPILL_MAX_INT: Triggered when the HP CPU SP goes beyond the upper bound of the HP CPU SP monitored region. Note: For definitions of interrupt, interrupt signal, interrupt source, and their correlations, please refer to Chapter 9 Interrupt Matrix > Section 9.2 Terminology. Each interrupt source can be configured by a common set of registers that are described in Section Interrupt Configuration Registers. The specific registers can be found in Section 17.6 Register Summary. 17.5 Programming Procedures 17.5.1 Region Monitoring and SP Monitoring Configuration The configuration process for region monitoring and SP monitoring is as follows: 1. Configure the monitored region and SP bounds. • Configure the HP CPU Data bus region 0 with BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN_REG and BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX_REG. • Configure the HP CPU Data bus region 1 with BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN_REG and BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX_REG. • Configure the HP CPU Peripheral bus region 0 with BUS_MONITOR_CORE_0_AREA_PIF_0_MIN_REG and BUS_MONITOR_CORE_0_AREA_PIF_0_MAX_REG. Espressif Systems 656 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 17 Debug Assistant • Configure the HP CPU Peripheral bus region 1 with BUS_MONITOR_CORE_0_AREA_PIF_1_MIN_REG and BUS_MONITOR_CORE_0_AREA_PIF_1_MAX_REG. • Configure the HP CPU SP bounds with BUS_MONITOR_CORE_0_SP_MIN_REG and BUS_MONITOR_CORE_0_SP_MAX_REG. 2. Configure BUS_MONITOR_CORE_0_INTR_ENA_REG to enable interrupts of a monitoring mode. 3. Configure BUS_MONITOR_CORE_0_MONTR_ENA_REG to enable the monitoring mode(s). Various monitoring modes can be enabled at the same time. 4. Read BUS_MONITOR_CORE_0_INTR_RAW_REG to get the raw interrupt status of a monitoring mode. 5. Configure BUS_MONITOR_CORE_0_INTR_CLR_REG to clear the interrupt of a monitoring mode. For example, if the Debug Assistant module needs to monitor whether the HP CPU Data bus has written to [A B] address space, the user can enable monitoring in either the HP CPU Data bus region 0 or region 1. The following configuration process is based on region 0: 1. Configure BUS_MONITOR_CORE_0_RCD_PDEBUGEN to 1 to enable HP CPU to update the PC signals to the Debug Assistant module. 2. Configure BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN_REG to Address A. 3. Configure BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX_REG to Address B. 4. Configure BUS_MONITOR_CORE_0_INTR_ENA_REG bit[1] to enable the interrupt for write operations by the HP CPU Data bus in region 0. 5. Configure BUS_MONITOR_CORE_0_MONTR_ENA_REG bit[1] to enable monitoring write operations by the HP CPU Data bus in region 0. 6. Configure interrupt matrix to map BUS_MONITOR_INTR into HP CPU interrupt (refer to Chapter 9 Interrupt Matrix). 7. After the interrupt is triggered: • Read BUS_MONITOR_CORE_0_INTR_RAW_REG to identify the interrupt source. • If the interrupt is triggered by HP CPU region monitoring, read BUS_MONITOR_CORE_0_AREA_PC for the HP CPU PC value, and BUS_MONITOR_CORE_0_AREA_SP for the HP CPU SP. • If the interrupt is triggered by SP monitoring, read BUS_MONITOR_CORE_0_SP_PC for the HP CPU PC value. • Write 1 to the corresponding bit of BUS_MONITOR_CORE_0_INTR_CLR_REG to clear the interrupt. 17.5.2 PC Logging Configuration Configure BUS_MONITOR_CORE_0_RCD_PDEBUGEN to 1 to enable HP CPU to update the PC signals to the Debug Assistant module. If BUS_MONITOR_CORE_0_RCD_RECORDEN is also configured to 1, BUS_MONITOR_CORE_0_RCD_PDEBUGPC_REG will record the HP CPU’s PC value and BUS_MONITOR_CORE_0_RCD_PDEBUGSP_REG will record the HP CPU SP value. Otherwise, these two registers will retain their original values. Espressif Systems 657 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 17 Debug Assistant When the HP CPU resets, BUS_MONITOR_CORE_0_RCD_EN_REG will reset, while BUS_MONITOR_CORE_0_RCD_PDEBUGPC_REG and BUS_MONITOR_CORE_0_RCD_PDEBUGSP_REG will not. Therefore, these two registers will retain the PC and SP values at the HP CPU reset. 17.5.3 CPU/DMA Bus Access Logging Configuration 17.5.3.1 Bus Access Logging 1 Configuration Bus access logging 1 includes HP CPU Bus access logging (HP SRAM and external RAM monitoring), LP CPU Bus access logging (HP SRAM monitoring), and DMA Bus access logging (HP SRAM monitoring). The configuration process is described below. 1. Configure monitored address space: set MEM_MONITOR_LOG_MIN_REG and MEM_MONITOR_LOG_MAX_REG to specify monitored address space. For HP CPU, the monitored address space should be in the address range of HP SRAM (0x4080_0000 0x4085_FFFF) or external RAM (0x4200_0000 0x43FF_FFFF). For LP CPU or DMA, the monitored address space should be in the address range of HP SRAM (0x4080_0000 0x4085_FFFF). 2. Configure the monitoring mode with MEM_MONITOR_LOG_MODE: • Write monitoring (detects bus write operations) • Word monitoring (detects writes of a specific word) • Halfword monitoring (detects writes of a specific halfword) • Byte monitoring (detects writes of a specific byte) 3. Configure the specific values to be monitored. • In word monitoring mode, MEM_MONITOR_LOG_CHECK_DATA_REG specifies the monitored word. • In halfword monitoring mode, MEM_MONITOR_LOG_CHECK_DATA_REG[15:0] specifies the monitored halfword. • In byte monitoring mode, MEM_MONITOR_LOG_CHECK_DATA_REG[7:0] specifies the monitored byte. • MEM_MONITOR_LOG_DATA_MASK_REG is used to mask the byte(s) specified in MEM_MONITOR_LOG_CHECK_DATA_REG. A masked byte can be any value. For example, in word monitoring, if MEM_MONITOR_LOG_CHECK_DATA_REG is configured to 0x01020304 and MEM_MONITOR_LOG_DATA_MASK_REG is configured to 0x1, then any writes of the data matching the 0x010203XX pattern by the bus will be recorded. 4. Configure the storage space for recorded data. • MEM_MONITOR_LOG_MEM_START_REG and MEM_MONITOR_LOG_MEM_END_REG specify the storage space for recorded data. The storage space must be in the range of 0x4080_0000 0x4085_FFFF. • Set MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG to update the value in MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG to MEM_MONITOR_LOG_MEM_START_REG. • Configure the permission of the Debug Assistant module to access the HP SRAM. The Debug Assistant module can only access HP SRAM when the access permission is enabled. For more information, please refer to Chapter 15 Permission Control (PMS). Espressif Systems 658 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 17 Debug Assistant 5. Configure the writing mode for the recorded data for loop mode or non-loop mode. • In loop mode, writing to the specified address space is performed in loops. When writing reaches the end address, it returns to the starting address and continues, overwriting the previously recorded data. Set MEM_MONITOR_LOG_MEM_LOOP_ENABLE to 1 to enable loop mode. For example, there are 10 write operations (1 10) to address space 0 4 during bus access. After the 5th operation writes to address 4, the 6th operation will start writing from address 0. The 6th to 10th operations will overwrite the previous data written by the 1st to 5th operations. • In non-loop mode, when writing reaches the end address, it stops at the end address and dumps the remaining data. The previously recorded data will not be overwritten. Clear MEM_MONITOR_LOG_MEM_LOOP_ENABLE to enable non-loop mode. For example, there are 10 write operations (1 10) to address space 0 4 during bus access. After the 5th operation writes to address 4, the 6th to 10th write operations will stop at address 4 and will not be performed any more. Therefore, the address 0 4 stores the values written by the 1st to 5th operations and the values of the 6th to 10th operations are dumped. 6. Configure bus enable registers. • Enable HP CPU, LP CPU, and DMA bus access logging respectively with MEM_MONITOR_LOG_CORE_ENA, MEM_MONITOR_LOG_DMA_1_ENA, and MEM_MONITOR_LOG_DMA_0_ENA. They can be enabled at the same time. The Debug Assistant module first writes the recorded data to the internal buffer A, and then fetches the data from the buffer and writes it to the configured memory space. When the monitored behaviors are triggered continuously, the generated recording packets may fill the buffer, preventing it from accepting new packets. In such cases, the module dumps the incoming packets and buffers a LOST packet instead before the buffer reaches full capacity. However, it is only possible to know the bus type of the dumped packets when the LOST packet was generated, but not the number of the dumped packets before the generation. When bus access logging is finished, the recorded data can be read from memory for decoding. The recorded data is in four packet formats, namely, HP CPU packet (corresponding to the HP CPU Data bus), LP CPU packet (corresponding to LP CPU Data bus), DMA packet (corresponding to DMA Data bus), and LOST packet. The packet formats are shown in Tables 17.5-1, 17.5-2, 17.5-3, and 17.5-4. Table 17.5-1. HP CPU Packet Format Bit[63:33] Bit[32] Bit[31:3] Bit[2:1] Bit[0] pc_offset anchored(1) addr_offset format anchored(0) Table 17.5-2. LP CPU Packet Format Bit[31:8] Bit[7:3] Bit[2:1] Bit[0] addr_offset reserved format anchored(0) Table 17.5-3. DMA Packet Format Bit[31:8] Bit[7:3] Bit[2:1] Bit[0] addr_offset dma_source format anchored(0) Espressif Systems 659 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 17 Debug Assistant Table 17.5-4. LOST Packet Format Bit[31:7] Bit[6:3] Bit[2:1] Bit[0] reserved lost_source format anchored(0) The data packet formats show that the HP CPU packet has 64 bits, and other packets have 32 bits each. These packets have the following fields: • format – the packet type: – 0: HP CPU packet – 1: DMA packet – 2: LP CPU packet – 3: LOST packet • pc_offset - the offset of the HP CPU PC register at the time of access. Actual PC = pc_offset + 0x0000_0000. • addr_offset - the address offset of a write operation. Actual address = addr_offset + {MEM_MONITOR_LOG_MIN_REG[31:2], 2’b0}. • dma_source - the source of DMA access. Details can be found in Table 17.5-5, where sources corresponding to value 16 31 are detailed in 3 GDMA Controller (GDMA). • lost_source - the dumped packets when the LOST packet was generated. – Bit[4:3]: * 0: HP CPU packets were not dumped * 3: HP CPU packets were dumped * Other values: reserved – Bit[5]: * 0: DMA packets were not dumped * 1: DMA packets were dumped – Bit[6]: * 0: LP CPU packets were not dumped * 1: LP CPU packets were dumped • anchored - the location of the 32 bits in the data packet: – 0: Lower 32 bits – 1: Higher 32 bits Espressif Systems 660 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 17 Debug Assistant Table 17.5-5. DMA Access Source Value Source 0 HP CPU 1 LP CPU 2 Reserved 3 Reserved 4 Reserved 5 MEM_MONITOR 6 TRACE 7 Reserved 8 PSRAM_MEM_MONITOR 9 15 Reserved 16 31 Refer to the peripheral corresponding to the value 0 15 in Chapter 3 GDMA Controller (GDMA) > Table 3.4- 1. For example, a value of 16 matches the peripheral corresponding to 0 in this table, a value of 17 matches the peripheral corresponding to 1 The internal buffer of the module is 32-bit wide. If HP CPU, LP CPU, and DMA bus access loggings are enabled at the same time, and the record data is generated at the same time, the HP CPU packets are cached into the buffer first, then the DMA packets, and finally the LP CPU packets. The Debug Assistant module will automatically fetch the buffered data and store it in 32-bit data width into the specified memory space. In loop mode, data looping several times in the storage memory may cause residual data, which can interfere with packet parsing. For example, the lower 32 bits of an HP CPU packet are overwritten, thus making its higher 32 bits residual data. Therefore, users need to filter out the possible residual data when determining the starting position of the first valid packet. Read MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG to identify the starting position of the packet, then check the anchored bit value of the packet. If it is 0, retain the data. If it is 1, discard it. The process of packet parsing is described below. • Read MEM_MONITOR_LOG_MEM_FULL_FLAG to determine whether there is a data overflow. – If no, the address space to read is MEM_MONITOR_LOG_MEM_START_REG MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG − 4. – If yes and the loop mode is enabled, the address space is MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG MEM_MONITOR_LOG_MEM_END_REG and MEM_MONITOR_LOG_MEM_START_REG MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG − 4. – If yes and loop mode is not enabled, the address space is MEM_MONITOR_LOG_MEM_START_REG MEM_MONITOR_LOG_MEM_END_REG. • Read and parse data from the starting address. Read 32 bits at a time. After packet parsing is completed, clear the MEM_MONITOR_LOG_MEM_FULL_FLAG flag bit by setting MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG to 1. Espressif Systems 661 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 17 Debug Assistant 17.5.3.2 Bus Access Logging 2 Configuration Bus access logging 2 includes DMA Bus access logging (external RAM monitoring). The configuration process is described below. 1. Configure monitored address space: Configure MEM_MONITOR_LOG_MIN_REG and MEM_MONITOR_LOG_MAX_REG to specify monitored address space. The monitored address space should range from 0x4200_0000 to 0x43FF_FFFF. 2. Configure the monitoring mode with MEM_MONITOR_LOG_MODE: • Write monitoring (detects bus write operations) • Word monitoring (detects writes of a specific word) • Halfword monitoring (detects writes of a specific halfword) • Byte monitoring (detects writes of a specific byte) 3. Configure the specific values to be monitored. • In word monitoring mode, MEM_MONITOR_LOG_CHECK_DATA_REG specifies the monitored word. • In halfword monitoring mode, MEM_MONITOR_LOG_CHECK_DATA_REG[15:0] specifies the monitored halfword. • In byte monitoring mode, MEM_MONITOR_LOG_CHECK_DATA_REG[7:0] specifies the monitored byte. • MEM_MONITOR_LOG_DATA_MASK_REG is used to mask the byte specified in MEM_MONITOR_LOG_CHECK_DATA_REG. A masked byte can be any value. For example, in word monitoring, if MEM_MONITOR_LOG_CHECK_DATA_REG is configured to 0x01020304 and MEM_MONITOR_LOG_DATA_MASK_REG is configured to 0x1, then any writes of the data matching the 0x010203XX pattern by the bus will be recorded. 4. Configure the storage space for recorded data. • MEM_MONITOR_LOG_MEM_START_REG and MEM_MONITOR_LOG_MEM_END_REG specify the storage space for recorded data. The storage space must be in the range of 0x4080_0000 0x4085_FFFF. • Set MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG to update the value in MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG to MEM_MONITOR_LOG_MEM_START_REG. • Configure the permission for the Debug Assistant module to access the HP SRAM. Only when the access permission is enabled can the Debug Assistant module access the HP SRAM. For more information, please refer to Chapter 15 Permission Control (PMS). 5. Configure the writing mode for the recorded data in loop mode or non-loop mode. • In loop mode, writing to the specified address space is performed in loops. When writing reaches the end address, it will return to the starting address and continue, overwriting the previously recorded data. Set MEM_MONITOR_LOG_MEM_LOOP_ENABLE to enable loop mode. • In non-loop mode, when writing reaches the end address, it will stop at the end address and dump the remaining data, not overwriting the previously recorded data. Clear MEM_MONITOR_LOG_MEM_LOOP_ENABLE to enable non-loop mode. Espressif Systems 662 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 17 Debug Assistant • See examples in Section 17.5.3.1 > step 5. 6. Configure MEM_MONITOR_LOG_DMA_0_ENA to enable DMA_0 channel groups bus access logging. The Debug Assistant module first writes the DMA recorded data to the internal buffer B, and then fetches the data from the buffer and writes it to the configured memory space. When the monitored behaviors are triggered continuously, the generated recording packets may fill the buffer, preventing it from accepting new packets. In such cases, the module dumps the incoming packets and buffers an DMA LOST packet instead before the buffer reaches full capacity. However, it is only possible to know the bus type of the dumped packets when the DMA LOST packet was generated, but not the number of the dumped packets before the generation. When bus access logging is finished, the recorded data can be read from memory for decoding. The recorded data is in two packet formats, namely, DMA_0 packet (corresponding to DMA_0 Data bus) and DMA LOST packet. The packet formats are shown in Table 17.5-6 and 17.5-7. Table 17.5-6. DMA_0 Packet Format Bit[31:7] Bit[6:2] Bit[1] Bit[0] addr_offset dma_source format anchored(0) Table 17.5-7. DMA LOST Packet Format Bit[31:3] Bit[2] Bit[1] Bit[0] reserved lost_source format anchored(0) The data packet formats show that the DMA_0 and DMA LOST packets both have 32 bits. These packets contain the following fields: • format – the packet type: – 0: DMA_0 packet – 1: DMA LOST packet • addr_offset0 - the address offset of a write operation. Actual address = addr_offset + {MEM_MONITOR_LOG_MIN_REG[31:2], 2’b0}. • dma_source - the source of DMA access. Details can be found in Table 17.5-5. • lost_source - the dumped packets when the DMA LOST packet was generated: – 0: DMA_0 packets were not dumped – 1: DMA_0 packets were dumped • anchored - the location of the 32 bits in the data packet: – 0: Lower 32 bits – 1: Higher 32 bits The internal buffer of the module is 32 bits wide. When the bus access logging of DMA_0 channel groups is enabled and the record data is generated, the DMA_0 data packets are buffered. The Debug Assistant module will automatically fetch the buffered data and store it in 32-bit data width into the specified memory space. The process of packet parsing is described below. Espressif Systems 663 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 17 Debug Assistant • Read MEM_MONITOR_LOG_MEM_FULL_FLAG to determine whether there is a data overflow. – If no, the address space to read is MEM_MONITOR_LOG_MEM_START_REG MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG − 4. – If yes and the loop mode is enabled, the address space is MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG MEM_MONITOR_LOG_MEM_END_REG and MEM_MONITOR_LOG_MEM_START_REG MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG − 4. – If yes and loop mode is not enabled, the address space is MEM_MONITOR_LOG_MEM_START_REG MEM_MONITOR_LOG_MEM_END_REG. • Read and parse data from the starting address. Read 32 bits at a time. After packet parsing is completed, clear the MEM_MONITOR_LOG_MEM_FULL_FLAG flag bit by setting MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG to 1. Espressif Systems 664 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 17 Debug Assistant 17.6 Register Summary The addresses of bus logging configuration registers in Section 17.6.1 are relative to the TCM_MEM_MONITOR base address and the PSRAM_MEM_MONITOR. The addresses of other registers in Section 17.6.2 are relative to the BUS_MONITOR base address. All base addresses are provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. 17.6.1 Bus Logging Configuration Register Summary Name Description Address Access Bus logging configuration registers MEM_MONITOR_LOG_SETTING_REG Configures bus access logging 0x0000 R/W MEM_MONITOR_LOG_SETTING1_REG Configures bus access logging 0x0004 R/W MEM_MONITOR_LOG_CHECK_DATA_REG Configures monitored data in bus access logging 0x0008 R/W MEM_MONITOR_LOG_DATA_MASK_REG Configures masked data in bus access logging 0x000C R/W MEM_MONITOR_LOG_MIN_REG Configures the monitored lower address for bus access logging 0x0010 R/W MEM_MONITOR_LOG_MAX_REG Configures the monitored upper address for bus access logging 0x0014 R/W MEM_MONITOR_LOG_MON_ADDR_UPDATE_0_REG Configures whether to update the monitored address space for HP CPU bus access logging 0x0018 WT MEM_MONITOR_LOG_MON_ADDR_UPDATE_1_REG Configures whether to update the monitored address space for DMA_0 bus access logging 0x001C WT MEM_MONITOR_LOG_MEM_START_REG Configures the starting address of the storage memory for recorded data 0x0020 R/W MEM_MONITOR_LOG_MEM_END_REG Configures the end address of the storage memory for recorded data 0x0024 R/W MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG Represents the address for the next write 0x0028 RO MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG Updates the address for the next write with the starting address for the recorded data 0x002C WT MEM_MONITOR_LOG_MEM_FULL_FLAG_REG Logging overflow status register 0x0030 varies Clock control register MEM_MONITOR_CLOCK_GATE_REG Clock control register 0x0034 R/W Version control register Espressif Systems 665 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 17 Debug Assistant Name Description Address Access MEM_MONITOR_DATE_REG Version control register 0x03FC R/W 17.6.2 Summary of Other Registers Name Description Address Access Monitor configuration registers BUS_MONITOR_CORE_0_MONTR_ENA_REG Configures whether to enable HP CPU monitoring 0x0000 R/W BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN_REG Configures lower boundary address of region 0 monitored on Data bus 0x0010 R/W BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX_REG Configures upper boundary address of region 0 monitored on Data bus 0x0014 R/W BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN_REG Configures lower boundary address of region 1 monitored on Data bus 0x0018 R/W BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX_REG Configures upper boundary address of region 1 monitored on Data bus 0x001C R/W BUS_MONITOR_CORE_0_AREA_PIF_0_MIN_REG Configures lower boundary address of region 0 monitored on Peripheral bus 0x0020 R/W BUS_MONITOR_CORE_0_AREA_PIF_0_MAX_REG Configures upper boundary address of region 0 monitored on Peripheral bus 0x0024 R/W BUS_MONITOR_CORE_0_AREA_PIF_1_MIN_REG Configures lower boundary address of region 1 monitored on Peripheral bus 0x0028 R/W BUS_MONITOR_CORE_0_AREA_PIF_1_MAX_REG Configures upper boundary address of region 1 monitored on Peripheral bus 0x002C R/W BUS_MONITOR_CORE_0_AREA_PC_REG Represents the PC status under HP CPU region monitoring 0x0030 RO BUS_MONITOR_CORE_0_AREA_SP_REG Represents the SP status under HP CPU region monitoring 0x0034 RO BUS_MONITOR_CORE_0_SP_MIN_REG Configures SP monitoring lower boundary address 0x0038 R/W BUS_MONITOR_CORE_0_SP_MAX_REG Configures SP monitoring upper boundary address 0x003C R/W BUS_MONITOR_CORE_0_SP_PC_REG Represents the PC status under HP CPU SP monitoring 0x0040 RO Interrupt configuration registers BUS_MONITOR_CORE_0_INTR_RAW_REG HP CPU monitor raw interrupt status register 0x0004 RO BUS_MONITOR_CORE_0_INTR_ENA_REG HP CPU monitor interrupt enable register 0x0008 R/W BUS_MONITOR_CORE_0_INTR_CLR_REG HP CPU monitor interrupt clear register 0x000C WT PC recording configuration register BUS_MONITOR_CORE_0_RCD_EN_REG HP CPU PC logging enable register 0x0044 R/W PC recording status registers BUS_MONITOR_CORE_0_RCD_PDEBUGPC_REG HP CPU PC logging register 0x0048 RO Espressif Systems 666 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 17 Debug Assistant Name Description Address Access BUS_MONITOR_CORE_0_RCD_PDEBUGSP_REG HP CPU SP logging register 0x004C RO CPU status registers BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXCEPTION_REG PC of the last command before HP CPU enters exception 0x0070 RO BUS_MONITOR_CORE_0_DEBUG_MODE_REG HP CPU debug mode status register 0x0074 RO Clock control register BUS_MONITOR_CLOCK_GATE_REG Clock control register 0x0108 R/W Version control register BUS_MONITOR_DATE_REG Version control register 0x03FC R/W Espressif Systems 667 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 17 Debug Assistant 17.7 Registers The addresses of bus logging configuration registers in Section 17.7.1 are relative to the TCM_MEM_MONITOR base address and the PSRAM_MEM_MONITOR. The addresses of other registers in Section 17.7.2 are relative to the BUS_MONITOR base address. All base addresses are provided in Table 4.3-2 in Chapter 4 System and Memory. For how to program reserved fields, please refer to Section Programming Reserved Register Field. 17.7.1 Bus Logging Configuration Registers Register 17.1. MEM_MONITOR_LOG_SETTING_REG (0x0000) MEM_MONITOR_LOG_DMA_1_ENA 0 31 24 MEM_MONITOR_LOG_DMA_0_ENA 0 23 16 MEM_MONITOR_LOG_CORE_ENA 0 15 8 (reserved) 0 0 0 7 5 MEM_MONITOR_LOG_MEM_LOOP_ENABLE 1 4 MEM_MONITOR_LOG_MODE 0 3 0 Reset MEM_MONITOR_LOG_MODE Configures monitoring modes. 1: Enable write monitoring 2: Enable word monitoring 4: Enable halfword monitoring 8: Enable byte monitoring. Other values: Invalid (R/W) MEM_MONITOR_LOG_MEM_LOOP_ENABLE Configures the writing mode for recorded data. 0: Non-loop mode 1: Loop mode (R/W) MEM_MONITOR_LOG_CORE_ENA Configures whether to enable HP CPU bus access logging. 0: Disable 1: Enable Other values: Invalid (R/W) Continued on the next page... Espressif Systems 668 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 17 Debug Assistant Register 17.1. MEM_MONITOR_LOG_SETTING_REG (0x0000) Continued from the previous page... MEM_MONITOR_LOG_DMA_0_ENA Configures whether to enable DMA_0 bus access logging. 0: Disable 1: Enable Other values: Invalid (R/W) MEM_MONITOR_LOG_DMA_1_ENA Configures whether to enable DMA_1 bus access logging. 0: Disable 1: Enable Other values: Invalid (R/W) Register 17.2. MEM_MONITOR_LOG_SETTING1_REG (0x0004) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 MEM_MONITOR_LOG_DMA_3_ENA 0 15 8 MEM_MONITOR_LOG_DMA_2_ENA 0 7 0 Reset MEM_MONITOR_LOG_DMA_2_ENA Configures whether to enable DMA_2 bus access logging. 0: Disable 1: Enable Other values: Invalid (R/W) MEM_MONITOR_LOG_DMA_3_ENA Configures whether to enableDMA_3 bus access logging. 0: Disable 1: Enable Other values: Invalid (R/W) Espressif Systems 669 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 17 Debug Assistant Register 17.3. MEM_MONITOR_LOG_CHECK_DATA_REG (0x0008) MEM_MONITOR_LOG_CHECK_DATA 0 31 0 Reset MEM_MONITOR_LOG_CHECK_DATA Configures the data to be monitored during bus accessing. (R/W) Espressif Systems 670 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 17 Debug Assistant Register 17.4. MEM_MONITOR_LOG_DATA_MASK_REG (0x000C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 4 MEM_MONITOR_LOG_DATA_MASK 0 3 0 Reset MEM_MONITOR_LOG_DATA_MASK Configures which byte(s) in MEM_MONITOR_LOG_CHECK_DATA_REG to mask. Multiple bytes can be masked at the same time. bit[0]: Configures whether to mask the least significant byte of MEM_MONITOR_LOG_CHECK_DATA_REG. 0: Not mask 1: Mask bit[1]: Configures whether to mask the second least significant byte of MEM_MONITOR_LOG_CHECK_DATA_REG. 0: Not mask 1: Mask bit[2]: Configures whether to mask the second most significant byte of MEM_MONITOR_LOG_CHECK_DATA_REG. 0: Not mask 1: Mask bit[3]: Configures whether to mask the most significant byte of MEM_MONITOR_LOG_CHECK_DATA_REG. 0: Not mask 1: Mask (R/W) Register 17.5. MEM_MONITOR_LOG_MIN_REG (0x0010) MEM_MONITOR_LOG_MIN 0 31 0 Reset MEM_MONITOR_LOG_MIN Configures the lower bound address of the monitored address space. (R/W) Espressif Systems 671 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 17 Debug Assistant Register 17.6. MEM_MONITOR_LOG_MAX_REG (0x0014) MEM_MONITOR_LOG_MAX 0 31 0 Reset MEM_MONITOR_LOG_MAX Configures the upper bound address of the monitored address space. (R/W) Register 17.7. MEM_MONITOR_LOG_MON_ADDR_UPDATE_0_REG (0x0018) MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 8 MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE 0 7 0 Reset MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE Configures whether to update the monitored address space of the HP CPU bus as the address space from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG. 0: Not update 1: Update Other values: Invalid (WT) MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE Configures whether to update the monitored address space of all masters as the address space from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG. 0: Not update 1: Update (WT) Espressif Systems 672 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 17 Debug Assistant Register 17.8. MEM_MONITOR_LOG_MON_ADDR_UPDATE_1_REG (0x001C) MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE 0 31 24 MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE 0 23 16 MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE 0 15 8 MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE 0 7 0 Reset MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE Configures whether to update the monitored address space of the DMA_0 bus as the address space from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG. 0: Not update 1: Update Other values: Invalid (WT) MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE Configures whether to update the monitored address space of the DMA_1 bus as the address space from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG. 0: Not update 1: Update Other values: Invalid (WT) MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE Configures whether to update the monitored address space of the DMA_2 bus as the address space from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG. 0: Not update 1: Update Other values: Invalid (WT) MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE Configures whether to update the monitored address space of the DMA_3 bus as the address space from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG. 0: Not update 1: Update Other values: Invalid (WT) Espressif Systems 673 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 17 Debug Assistant Register 17.9. MEM_MONITOR_LOG_MEM_START_REG (0x0020) MEM_MONITOR_LOG_MEM_START 0 31 0 Reset MEM_MONITOR_LOG_MEM_START Configures the starting address of the storage space for recorded data. (R/W) Register 17.10. MEM_MONITOR_LOG_MEM_END_REG (0x0024) MEM_MONITOR_LOG_MEM_END 0 31 0 Reset MEM_MONITOR_LOG_MEM_END Configures the ending address of the storage space for recorded data. (R/W) Register 17.11. MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG (0x0028) MEM_MONITOR_LOG_MEM_CURRENT_ADDR 0 31 0 Reset MEM_MONITOR_LOG_MEM_CURRENT_ADDR Represents the address of the next write. (RO) Espressif Systems 674 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 17 Debug Assistant Register 17.12. MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG (0x002C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 MEM_MONITOR_LOG_MEM_ADDR_UPDATE 0 0 Reset MEM_MONITOR_LOG_MEM_ADDR_UPDATE Configures whether to update the value in MEM_MONITOR_LOG_MEM_START_REG to the value of MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG. 0: Not update 1: Update (WT) Register 17.13. MEM_MONITOR_LOG_MEM_FULL_FLAG_REG (0x0030) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 2 MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG 0 1 MEM_MONITOR_LOG_MEM_FULL_FLAG 0 0 Reset MEM_MONITOR_LOG_MEM_FULL_FLAG Represents whether data overflows the storage space. 0: Not Overflow 1: Overflow (RO) MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG Configures whether to clear the- MEM_MONITOR_LOG_MEM_FULL_FLAG flag bit. 0: Not clear (default) 1: Clear (WT) Espressif Systems 675 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 17 Debug Assistant Register 17.14. MEM_MONITOR_CLOCK_GATE_REG (0x0034) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 MEM_MONITOR_CLK_EN 0 0 Reset MEM_MONITOR_CLK_EN Configures whether to enable the register clock gating. 0: Disable 1: Enable (R/W) Register 17.15. MEM_MONITOR_DATE_REG (0x03FC) (reserved) 0 0 0 0 31 28 MEM_MONITOR_DATE 0x2308140 27 0 Reset MEM_MONITOR_DATE Version control register. (R/W) Espressif Systems 676 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 17 Debug Assistant 17.7.2 Other Registers Register 17.16. BUS_MONITOR_CORE_0_MONTR_ENA_REG (0x0000) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 10 BUS_MONITOR_CORE_0_SP_SPILL_MAX_ENA 0 9 BUS_MONITOR_CORE_0_SP_SPILL_MIN_ENA 0 8 BUS_MONITOR_CORE_0_AREA_PIF_1_WR_ENA 0 7 BUS_MONITOR_CORE_0_AREA_PIF_1_RD_ENA 0 6 BUS_MONITOR_CORE_0_AREA_PIF_0_WR_ENA 0 5 BUS_MONITOR_CORE_0_AREA_PIF_0_RD_ENA 0 4 BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_ENA 0 3 BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_ENA 0 2 BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_ENA 0 1 BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_ENA 0 0 Reset BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_ENA Configures whether to monitor read opera- tions in region 0 by the Data bus. 0: Not monitor 1: Monitor (R/W) BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_ENA Configures whether to monitor write oper- ations in region 0 by the Data bus. 0: Not monitor 1: Monitor (R/W) BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_ENA Configures whether to monitor read opera- tions in region 1 by the Data bus. 0: Not Monitor 1: Monitor (R/W) BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_ENA Configures whether to monitor write oper- ations in region 1 by the Data bus. 0: Not Monitor 1: Monitor (R/W) BUS_MONITOR_CORE_0_AREA_PIF_0_RD_ENA Configures whether to monitor read operations in region 0 by the Peripheral bus. 0: Not Monitor 1: Monitor (R/W) Continued on the next page... Espressif Systems 677 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 17 Debug Assistant Register 17.16. BUS_MONITOR_CORE_0_MONTR_ENA_REG (0x0000) Continued from the previous page... BUS_MONITOR_CORE_0_AREA_PIF_0_WR_ENA Configures whether to monitor write operations in region 0 by the Peripheral bus. 0: Not Monitor 1: Monitor (R/W) BUS_MONITOR_CORE_0_AREA_PIF_1_RD_ENA Configures whether to monitor read operations in region 1 by the Peripheral bus. 0: Not Monitor 1: Monitor (R/W) BUS_MONITOR_CORE_0_AREA_PIF_1_WR_ENA Configures whether to monitor write operations in region 1 by the Peripheral bus. 0: Not Monitor 1: Monitor (R/W) BUS_MONITOR_CORE_0_SP_SPILL_MIN_ENA Configures whether to monitor SP exceeding the lower bound address of SP monitored region. 0: Not Monitor 1: Monitor (R/W) BUS_MONITOR_CORE_0_SP_SPILL_MAX_ENA Configures whether to monitor SP exceeding the upper bound address of SP monitored region. 0: Not Monitor 1: Monitor (R/W) Espressif Systems 678 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 17 Debug Assistant Register 17.17. BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN_REG (0x0010) BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN 0xffffffff 31 0 Reset BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN Configures the lower bound address of Data bus region 0. (R/W) Register 17.18. BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX_REG (0x0014) BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX 0 31 0 Reset BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX Configures the upper bound address of Data bus region 0. (R/W) Espressif Systems 679 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 17 Debug Assistant Register 17.19. BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN_REG (0x0018) BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN 0xffffffff 31 0 Reset BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN Configures the lower bound address of Data bus region 1. (R/W) Register 17.20. BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX_REG (0x001C) BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX 0 31 0 Reset BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX Configures the upper bound address of Data bus region 1. (R/W) Espressif Systems 680 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 17 Debug Assistant Register 17.21. BUS_MONITOR_CORE_0_AREA_PIF_0_MIN_REG (0x0020) BUS_MONITOR_CORE_0_AREA_PIF_0_MIN 0xffffffff 31 0 Reset BUS_MONITOR_CORE_0_AREA_PIF_0_MIN Configures the lower bound address of Peripheral bus region 0. (R/W) Register 17.22. BUS_MONITOR_CORE_0_AREA_PIF_0_MAX_REG (0x0024) BUS_MONITOR_CORE_0_AREA_PIF_0_MAX 0 31 0 Reset BUS_MONITOR_CORE_0_AREA_PIF_0_MAX Configures the upper bound address of Peripheral bus region 0. (R/W) Espressif Systems 681 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 17 Debug Assistant Register 17.23. BUS_MONITOR_CORE_0_AREA_PIF_1_MIN_REG (0x0028) BUS_MONITOR_CORE_0_AREA_PIF_1_MIN 0xffffffff 31 0 Reset BUS_MONITOR_CORE_0_AREA_PIF_1_MIN Configures the lower bound address of Peripheral bus region 1. (R/W) Register 17.24. BUS_MONITOR_CORE_0_AREA_PIF_1_MAX_REG (0x002C) BUS_MONITOR_CORE_0_AREA_PIF_1_MAX 0 31 0 Reset BUS_MONITOR_CORE_0_AREA_PIF_1_MAX Configures the upper bound address of Peripheral bus region 1. (R/W) Register 17.25. BUS_MONITOR_CORE_0_AREA_PC_REG (0x0030) BUS_MONITOR_CORE_0_AREA_PC 0 31 0 Reset BUS_MONITOR_CORE_0_AREA_PC Represents the PC value when an interrupt is triggered during region monitoring. (RO) Espressif Systems 682 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 17 Debug Assistant Register 17.26. BUS_MONITOR_CORE_0_AREA_SP_REG (0x0034) BUS_MONITOR_CORE_0_AREA_SP 0 31 0 Reset BUS_MONITOR_CORE_0_AREA_SP Represents the SP value when an interrupt is triggered during region monitoring. (RO) Register 17.27. BUS_MONITOR_CORE_0_SP_MIN_REG (0x0038) BUS_MONITOR_CORE_0_SP_MIN 0 31 0 Reset BUS_MONITOR_CORE_0_SP_MIN Configures the lower bound address of SP monitored region. (R/W) Register 17.28. BUS_MONITOR_CORE_0_SP_MAX_REG (0x003C) BUS_MONITOR_CORE_0_SP_MAX 0xffffffff 31 0 Reset BUS_MONITOR_CORE_0_SP_MAX Configures the upper bound address of SP monitored region. (R/W) Espressif Systems 683 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 17 Debug Assistant Register 17.29. BUS_MONITOR_CORE_0_SP_PC_REG (0x0040) BUS_MONITOR_CORE_0_SP_PC 0 31 0 Reset BUS_MONITOR_CORE_0_SP_PC Represents the PC value during SP monitoring. (RO) Espressif Systems 684 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 17 Debug Assistant Register 17.30. BUS_MONITOR_CORE_0_INTR_RAW_REG (0x0004) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 10 BUS_MONITOR_CORE_0_SP_SPILL_MAX_RAW 0 9 BUS_MONITOR_CORE_0_SP_SPILL_MIN_RAW 0 8 BUS_MONITOR_CORE_0_AREA_PIF_1_WR_RAW 0 7 BUS_MONITOR_CORE_0_AREA_PIF_1_RD_RAW 0 6 BUS_MONITOR_CORE_0_AREA_PIF_0_WR_RAW 0 5 BUS_MONITOR_CORE_0_AREA_PIF_0_RD_RAW 0 4 BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_RAW 0 3 BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_RAW 0 2 BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_RAW 0 1 BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_RAW 0 0 Reset BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_RAW The raw interrupt status of BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INT. (RO) BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_RAW The raw interrupt status of BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INT. (RO) BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_RAW The raw interrupt status of BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INT. (RO) BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_RAW The raw interrupt status of BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INT. (RO) BUS_MONITOR_CORE_0_AREA_PIF_0_RD_RAW The raw interrupt status of BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INT. (RO) BUS_MONITOR_CORE_0_AREA_PIF_0_WR_RAW The raw interrupt status of BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INT. (RO) BUS_MONITOR_CORE_0_AREA_PIF_1_RD_RAW The raw interrupt status of BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INT. (RO) BUS_MONITOR_CORE_0_AREA_PIF_1_WR_RAW The raw interrupt status of BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INT. (RO) BUS_MONITOR_CORE_0_SP_SPILL_MIN_RAW The raw interrupt status of BUS_MONITOR_CORE_0_SP_SPILL_MIN_INT. (RO) BUS_MONITOR_CORE_0_SP_SPILL_MAX_RAW The raw interrupt status of BUS_MONITOR_CORE_0_SP_SPILL_MAX_INT. (RO) Espressif Systems 685 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 17 Debug Assistant Register 17.31. BUS_MONITOR_CORE_0_INTR_ENA_REG (0x0008) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 10 BUS_MONITOR_CORE_0_SP_SPILL_MAX_INTR_ENA 0 9 BUS_MONITOR_CORE_0_SP_SPILL_MIN_INTR_ENA 0 8 BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INTR_ENA 0 7 BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INTR_ENA 0 6 BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INTR_ENA 0 5 BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INTR_ENA 0 4 BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INTR_ENA 0 3 BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INTR_ENA 0 2 BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INTR_ENA 0 1 BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INTR_ENA 0 0 Reset BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INTR_ENA Write 1 to enable BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INT. (R/W) BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INTR_ENA Write 1 to enable BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INT. (R/W) BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INTR_ENA Write 1 to enable BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INT. (R/W) BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INTR_ENA Write 1 to enable BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INT. (R/W) BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INTR_ENA Write 1 to enable BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INT. (R/W) BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INTR_ENA Write 1 to enable BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INT. (R/W) BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INTR_ENA Write 1 to enable BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INT. (R/W) BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INTR_ENA Write 1 to enable BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INT. (R/W) BUS_MONITOR_CORE_0_SP_SPILL_MIN_INTR_ENA Write 1 to enable BUS_MONITOR_CORE_0_SP_SPILL_MIN_INT. (R/W) BUS_MONITOR_CORE_0_SP_SPILL_MAX_INTR_ENA Write 1 to enable BUS_MONITOR_CORE_0_SP_SPILL_MAX_INT. (R/W) Espressif Systems 686 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 17 Debug Assistant Register 17.32. BUS_MONITOR_CORE_0_INTR_CLR_REG (0x000C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 10 BUS_MONITOR_CORE_0_SP_SPILL_MAX_CLR 0 9 BUS_MONITOR_CORE_0_SP_SPILL_MIN_CLR 0 8 BUS_MONITOR_CORE_0_AREA_PIF_1_WR_CLR 0 7 BUS_MONITOR_CORE_0_AREA_PIF_1_RD_CLR 0 6 BUS_MONITOR_CORE_0_AREA_PIF_0_WR_CLR 0 5 BUS_MONITOR_CORE_0_AREA_PIF_0_RD_CLR 0 4 BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_CLR 0 3 BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_CLR 0 2 BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_CLR 0 1 BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_CLR 0 0 Reset BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_CLR Write 1 to clear BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INT. (WT) BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_CLR Write 1 to clear BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INT. (WT) BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_CLR Write 1 to clear BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INT. (WT) BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_CLR Write 1 to clear BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INT. (WT) BUS_MONITOR_CORE_0_AREA_PIF_0_RD_CLR Write 1 to clear BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INT. (WT) BUS_MONITOR_CORE_0_AREA_PIF_0_WR_CLR Write 1 to clear BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INT. (WT) BUS_MONITOR_CORE_0_AREA_PIF_1_RD_CLR Write 1 to clear BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INT. (WT) BUS_MONITOR_CORE_0_AREA_PIF_1_WR_CLR Write 1 to clear BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INT. (WT) BUS_MONITOR_CORE_0_SP_SPILL_MIN_CLR Write 1 to clear BUS_MONITOR_CORE_0_SP_SPILL_MIN_INT. (WT) BUS_MONITOR_CORE_0_SP_SPILL_MAX_CLR Write 1 to clear BUS_MONITOR_CORE_0_SP_SPILL_MAX_INT. (WT) Espressif Systems 687 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 17 Debug Assistant Register 17.33. BUS_MONITOR_CORE_0_RCD_EN_REG (0x0044) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 2 BUS_MONITOR_CORE_0_RCD_PDEBUGEN 0 1 BUS_MONITOR_CORE_0_RCD_RECORDEN 0 0 Reset BUS_MONITOR_CORE_0_RCD_RECORDEN Configures whether to enable PC logging. 0: Disable 1: BUS_MONITOR_CORE_0_RCD_PDEBUGPC_REG starts to record PC in real time (R/W) BUS_MONITOR_CORE_0_RCD_PDEBUGEN Configures whether to enable HP CPU debugging. 0: Disable 1: HP CPU outputs PC (R/W) Register 17.34. BUS_MONITOR_CORE_0_RCD_PDEBUGPC_REG (0x0048) BUS_MONITOR_CORE_0_RCD_PDEBUGPC 0x000000 31 0 Reset BUS_MONITOR_CORE_0_RCD_PDEBUGPC Represents the PC value at HP CPU reset. (RO) Espressif Systems 688 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 17 Debug Assistant Register 17.35. BUS_MONITOR_CORE_0_RCD_PDEBUGSP_REG (0x004C) BUS_MONITOR_CORE_0_RCD_PDEBUGSP 0x000000 31 0 Reset BUS_MONITOR_CORE_0_RCD_PDEBUGSP Represents SP. (RO) Register 17.36. BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (0x0070) BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXC 0 31 0 Reset BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXC Represents the PC of the last command before the HP CPU enters exception. (RO) Espressif Systems 689 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 17 Debug Assistant Register 17.37. BUS_MONITOR_CORE_0_DEBUG_MODE_REG (0x0074) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 2 BUS_MONITOR_CORE_0_DEBUG_MODULE_ACTIVE 0 1 BUS_MONITOR_CORE_0_DEBUG_MODE 0 0 Reset BUS_MONITOR_CORE_0_DEBUG_MODE Represents whether RISC-V CPU (HP CPU) is in debug- ging mode. 1: In debugging mode 0: Not in debugging mode (RO) BUS_MONITOR_CORE_0_DEBUG_MODULE_ACTIVE Represents the status of the RISC-V CPU (HP CPU) debug module. 1: Active status Other: Inactive status (RO) Register 17.38. BUS_MONITOR_CLOCK_GATE_REG (0x0108) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 BUS_MONITOR_CLK_EN 1 0 Reset BUS_MONITOR_CLK_EN Configures whether to enable the register clock gating. 0: Disable 1: Enable (R/W) Espressif Systems 690 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 17 Debug Assistant Register 17.39. BUS_MONITOR_DATE_REG (0x03FC) (reserved) 0 0 0 0 31 28 BUS_MONITOR_DATE 0x2109130 27 0 Reset BUS_MONITOR_DATE Version control register. (R/W) Espressif Systems 691 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 18 Power Supply Detector Chapter 18 Power Supply Detector 18.1 Overview ESP32-C5 has a power supply detector that can monitor the voltage on the power pins related to the on-chip clock and digital circuits. The power supply detector includes a brown-out detector and four voltage glitch detectors. The brown-out detector prevents the SoC from brown-out resets, while the voltage glitch detectors protect the SoC against voltage glitch attacks. The power detector operates in the always-on power domain, allowing it to monitor voltage at any time. 18.2 Features • Brown-out detector supports two brown-out detection modes (Mode 0 and Mode 1) – Mode 0 supports: * interrupt generation * RF circuits power-down * flash suspend triggering * system reset – Mode 1 supports: * system reset until the voltage returns to normal • Voltage glitch detector can detect voltage glitches lasting 50 ns or longer and trigger a system reset. 18.3 Functional Description 18.3.1 Architecture Figure 18.3-1 shows the architecture of the power supply detector. As shown, the power supply detector consists of one brown-out detector and four voltage glitch detectors. Espressif Systems 692 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 18 Power Supply Detector Figure 18.3-1. Architecture of Power Supply Detector 18.3.2 Brown-out Detector The brown-out detector checks the voltage of pins VDDA3, VDDPST1, VDDPST2, and VDDPST3, about every 280 µs. When the voltage on these pins falls below a predefined threshold of 2.7 V (default setting), the detector activates a signal to power down the power-hungry RF circuits. This action provides additional time for the digital system to save and transfer important data. The brown-out detector consumes very little power and remains active as long as the chip is powered on. LP_ANA_BOD_MODE0_INT_RAW indicates the detection result from the brown-out detector. By default, this register reads a value of 0. It changes to 1 when the voltage on the monitored pin falls below a predefined threshold. When a brown-out signal is detected, the brown-out detector handles it in one of the following two modes (Mode 1 is the default): • Mode 0: – Mode 0 is enabled by setting the (LP_ANA_BOD_MODE0_INTR_ENA) signal. – The brown-out detector triggers an interrupt when the counter counts to the thresholds predefined in Int Comparer (LP_ANA_BOD_MODE0_INTR_WAIT). If LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA is set, flash suspend will be triggered; if LP_ANA_BOD_MODE0_PD_RF_ENA is set, the RF module will be powered down. – The brown-out detector resets the chip based on the configuration of (LP_ANA_BOD_MODE0_RESET_SEL) when the brown-out counter counts to the thresholds predefined in Rst Comparer (LP_ANA_BOD_MODE0_RESET_WAIT). The reset is enabled by (LP_ANA_BOD_MODE0_RESET_ENA). • Mode 1: Resets the system directly. The brown-out reset workflow is illustrated in the diagram below. Espressif Systems 693 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 18 Power Supply Detector Figure 18.3-2. Brown-out Reset Workflow Registers for controlling related signals are described below. • : LP_ANA_BOD_MODE0_INTR_ENA • : LP_ANA_BOD_MODE0_RESET_ENA • : LP_ANA_BOD_MODE0_RESET_SEL configures the reset type: – 0: chip reset – 1: system reset For more information regarding chip reset and system reset, please refer to Chapter 7 Reset and Clock. • : The first bit of LP_ANA_ANA_FIB_ENA. • : LP_ANA_BOD_MODE1_RESET_ENA 18.3.3 Voltage Glitch Detectors Figure 18.3-3 shows the structure of the voltage glitch detectors. Espressif Systems 694 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 18 Power Supply Detector Figure 18.3-3. Structure of Voltage Glitch Detectors The ESP32-C5 has four voltage glitch detectors, each of which can detect glitches longer than 50 ns on the corresponding power supply pins, including VDDPST1, VDDPST2, VDDPST3, VDDA8, and VDDA3. VDDPST2 and VDDPST3 are connected and thus share one voltage glitch detector. All resets generated by the detectors are combined into one voltage glitch reset. The voltage glitch detectors’ enable control is managed by SW_RESET_ENA_SEL. When set to 1, it is forcibly enabled by hardware, and when set to 0, it is controlled by the software register SW_RESET_ENA. The configuration for detecting different power pins is shown in the table below: Table 18.3-1. Configuration for Detecting Power Pins VDD Pins SW_RESET_ENA SW_RESET_ENA_SEL VDDPST2/3 LP_ANA_PWR_GLITCH_RESET_ENA[0] LP_ANA_ANA_FIB_ENA[2] VDDPST1 LP_ANA_PWR_GLITCH_RESET_ENA[1] LP_ANA_ANA_FIB_ENA[3] VDDA3 LP_ANA_PWR_GLITCH_RESET_ENA[2] LP_ANA_ANA_FIB_ENA[4] VDDA8 LP_ANA_PWR_GLITCH_RESET_ENA[3] LP_ANA_ANA_FIB_ENA[5] 18.4 Interrupts ESP32-C5’s power supply detector can generate the following interrupt signals that will be sent to the Interrupt Matrix. • LP_ANA_INTR (only for HP CPU) • LP_ANA_LP_INTR (only for LP CPU) The interrupt signals are generated by the power supply detector’s internal interrupt sources which are listed in Table 18.4-1 with their trigger conditions. Table 18.4-1. Power Supply Detector’s Internal Interrupt Source Internal Interrupt Source Trigger Condition Interrupt Signal LP_ANA_BOD_MODE0_INT Triggered when the brown-out detector detects that the voltage is below the threshold. LP_ANA_INTR LP_ANA_BOD_MODE0_LP_INT Triggered when the brown-out detector detects that the voltage is below the threshold. LP_ANA_LP_INTR Espressif Systems 695 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 18 Power Supply Detector Note: For definitions of interrupt, interrupt signal, interrupt source, and their correlations, please refer to Chapter 9 Interrupt Matrix > Section 9.2 Terminology. Each interrupt source can be configured by a common set of registers that are described in Section Interrupt Configuration Registers. The specific registers can be found in Section 18.5 Register Summary. Espressif Systems 696 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 18 Power Supply Detector 18.5 Register Summary The addresses in this section are relative to the Power Supply Detector base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Configuration Registers LP_ANA_BOD_MODE0_CNTL_REG Brownout detector mode 0 configuration register 0x0000 R/W LP_ANA_BOD_MODE1_CNTL_REG Brownout detector mode 1 configuration register 0x0004 R/W LP_ANA_POWER_GLITCH_CNTL_REG Voltage glitch configuration register 0x0008 R/W LP_ANA_FIB_ENABLE_REG Voltage glitch detectors’ enable control register 0x000C R/W LP_ANA_INT_RAW_REG LP_ANA_BOD_MODE0_INT raw interrupt 0x0010 R/WTC/SS LP_ANA_INT_ST_REG LP_ANA_BOD_MODE0_INT state interrupt 0x0014 RO LP_ANA_INT_ENA_REG LP_ANA_BOD_MODE0_INT enable register 0x0018 R/W LP_ANA_INT_CLR_REG LP_ANA_BOD_MODE0_INT clear register 0x001C WT LP_ANA_LP_INT_RAW_REG LP_ANA_BOD_MODE0_LP_INT raw interrupt 0x0020 R/WTC/SS LP_ANA_LP_INT_ST_REG LP_ANA_BOD_MODE0_LP_INT state interrupt 0x0024 RO LP_ANA_LP_INT_ENA_REG LP_ANA_BOD_MODE0_LP_INT enable register 0x0028 R/W LP_ANA_LP_INT_CLR_REG LP_ANA_BOD_MODE0_LP_INT clear register 0x002C WT Version Control Registers LP_ANA_DATE_REG Version control register 0x03FC R/W Espressif Systems 697 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 18 Power Supply Detector 18.6 Registers The addresses in this section are relative to the Power Supply Detector base address provided in Table 4.3-2 in Chapter 4 System and Memory. For how to program reserved fields, please refer to Section Programming Reserved Register Field. Espressif Systems 698 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 18 Power Supply Detector Register 18.1. LP_ANA_BOD_MODE0_CNTL_REG (0x0000) LP_ANA_BOD_MODE0_RESET_ENA 0 31 LP_ANA_BOD_MODE0_RESET_SEL 0 30 LP_ANA_BOD_MODE0_INTR_ENA 0 29 LP_ANA_BOD_MODE0_CNT_CLR 0 28 LP_ANA_BOD_MODE0_RESET_WAIT 0x3ff 27 18 LP_ANA_BOD_MODE0_INTR_WAIT 1 17 8 LP_ANA_BOD_MODE0_PD_RF_ENA 0 7 LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA 0 6 (reserved) 0 0 0 0 0 0 5 0 Reset LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA Configures whether to enable the brown-out detec- tor to trigger flash suspend. 0: Disable 1: Enable (R/W) LP_ANA_BOD_MODE0_PD_RF_ENA Configures whether to enable the brown-out detector to power down the RF module. 0: Disable 1: Enable (R/W) LP_ANA_BOD_MODE0_INTR_WAIT Configures the time to generate an interrupt after the brown- out signal is valid. The unit is LP_FAST_CLK cycles. (R/W) LP_ANA_BOD_MODE0_RESET_WAIT Configures the time to generate a reset after the brown-out signal is valid. The unit is LP_FAST_CLK cycles. (R/W) LP_ANA_BOD_MODE0_CNT_CLR Configures whether to clear the count value of the brown-out detector. 0: Do not clear 1: Clear (R/W) LP_ANA_BOD_MODE0_INTR_ENA Enables the interrupts for the brown-out detector mode 0. LP_ANA_BOD_MODE0_INT_RAW and LP_ANA_BOD_MODE0_LP_INT_RAW are valid only when this field is set to 1. 0: Disable 1: Enable (R/W) LP_ANA_BOD_MODE0_RESET_SEL Configures the reset type when the brown-out detector is trig- gered. 0: Chip reset 1: System reset (R/W) Continued on the next page... Espressif Systems 699 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 18 Power Supply Detector Register 18.1. LP_ANA_BOD_MODE0_CNTL_REG (0x0000) Continued from the previous page... LP_ANA_BOD_MODE0_RESET_ENA Configures whether to enable reset for the brown-out detec- tor. 0: Disable 1: Enable (R/W) Register 18.2. LP_ANA_BOD_MODE1_CNTL_REG (0x0004) LP_ANA_BOD_MODE1_RESET_ENA 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 0 Reset LP_ANA_BOD_MODE1_RESET_ENA Configures whether to enable brown-out detector mode 1. 0: Disable 1: Enable (R/W) Register 18.3. LP_ANA_POWER_GLITCH_CNTL_REG (0x0008) (reserved) 0 31 LP_ANA_PWR_GLITCH_RESET_ENA 0 30 27 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 26 0 Reset LP_ANA_PWR_GLITCH_RESET_ENA Configures whether to enable the voltage glitch detectors. Bit0, bit1, bit2, bit3 correspond to VDDPST2/3, VDDPST1, VDDA3, and VDDA8, respectively. 0: Disable 1: Enable (R/W) Espressif Systems 700 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 18 Power Supply Detector Register 18.4. LP_ANA_FIB_ENABLE_REG (0x000C) LP_ANA_ANA_FIB_ENA 0xffffffff 31 0 Reset LP_ANA_ANA_FIB_ENA Controls the enable of the voltage glitch detectors. Bit2, bit3, bit4, bit5 correspond to VDDPST2/3, VDDPST1, VDDA3, and VDDA8, respectively. 0: Controlled by LP_ANA_PWR_GLITCH_RESET_ENA 1: Forcibly enabled by hardware (R/W) Register 18.5. LP_ANA_INT_RAW_REG (0x0010) LP_ANA_BOD_MODE0_INT_RAW 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 0 Reset LP_ANA_BOD_MODE0_INT_RAW The raw interrupt status of LP_ANA_BOD_MODE0_INT. (R/WTC/SS) Register 18.6. LP_ANA_INT_ST_REG (0x0014) LP_ANA_BOD_MODE0_INT_ST 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 0 Reset LP_ANA_BOD_MODE0_INT_ST The masked interrupt status of LP_ANA_BOD_MODE0_INT. (RO) Espressif Systems 701 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 18 Power Supply Detector Register 18.7. LP_ANA_INT_ENA_REG (0x0018) LP_ANA_BOD_MODE0_INT_ENA 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 0 Reset LP_ANA_BOD_MODE0_INT_ENA Write 1 to enable LP_ANA_BOD_MODE0_INT. (R/W) Register 18.8. LP_ANA_INT_CLR_REG (0x001C) LP_ANA_BOD_MODE0_INT_CLR 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 0 Reset LP_ANA_BOD_MODE0_INT_CLR Write 1 to clear LP_ANA_BOD_MODE0_INT. (WT) Register 18.9. LP_ANA_LP_INT_RAW_REG (0x0020) LP_ANA_BOD_MODE0_LP_INT_RAW 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 0 Reset LP_ANA_BOD_MODE0_LP_INT_RAW The raw interrupt status of LP_ANA_BOD_MODE0_LP_INT. (R/WTC/SS) Espressif Systems 702 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 18 Power Supply Detector Register 18.10. LP_ANA_LP_INT_ST_REG (0x0024) LP_ANA_BOD_MODE0_LP_INT_ST 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 0 Reset LP_ANA_BOD_MODE0_LP_INT_ST The masked interrupt status of LP_ANA_BOD_MODE0_LP_INT. (RO) Register 18.11. LP_ANA_LP_INT_ENA_REG (0x0028) LP_ANA_BOD_MODE0_LP_INT_ENA 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 0 Reset LP_ANA_BOD_MODE0_LP_INT_ENA Write 1 to enable LP_ANA_BOD_MODE0_LP_INT. (R/W) Register 18.12. LP_ANA_LP_INT_CLR_REG (0x002C) LP_ANA_BOD_MODE0_LP_INT_CLR 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 0 Reset LP_ANA_BOD_MODE0_LP_INT_CLR Write 1 to clear LP_ANA_BOD_MODE0_LP_INT. (WT) Espressif Systems 703 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 18 Power Supply Detector Register 18.13. LP_ANA_DATE_REG (0x03FC) LP_ANA_CLK_EN 0 31 LP_ANA_LP_ANA_DATE 0x2312280 30 0 Reset LP_ANA_LP_ANA_DATE Version control register. (R/W) LP_ANA_CLK_EN Configures whether to force enable register clock. 0: Automatic clock gating 1: Force enable register clock The configuration of this field does not effect the access of registers. (R/W) Espressif Systems 704 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Part IV Cryptography/Security Component Dedicated to security features, this part explores cryptographic accelerators like AES and ECC. It also covers digital signatures, random number generation, and encryption/decryption algorithms, showcasing the SoC’s capabilities in cryptography and secure data processing. Espressif Systems 705 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 19 AES Accelerator (AES) Chapter 19 AES Accelerator (AES) 19.1 Introduction ESP32-C5 integrates an Advanced Encryption Standard (AES) accelerator, which is a hardware device that speeds up computation using AES algorithm significantly, compared to AES algorithms implemented solely in software. The AES accelerator integrated in ESP32-C5 has two working modes, which are Typical AES and DMA-AES. 19.2 Features The following functionality is supported: • Typical AES working mode – AES-128/AES-256 encryption and decryption • DMA-AES working mode – AES-128/AES-256 encryption and decryption – Block cipher mode * ECB (Electronic Codebook) * CBC (Cipher Block Chaining) * OFB (Output Feedback) * CTR (Counter) * CFB8 (8-bit Cipher Feedback) * CFB128 (128-bit Cipher Feedback) – Interrupt on completion of computation 19.3 Clock and Reset The AES accelerator is activated by setting the PCR_AES_CLK_EN bit and clearing the PCR_AES_RST_EN bit in the PCR_AES_CONF_REG register. Besides, due to resource reuse between cryptography accelerator modules, users also need to additionally clear the PCR_DS_RST_EN bit in the PCR_DS_CONF_REG register. Espressif Systems 706 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 19 AES Accelerator (AES) 19.4 AES Working Modes The AES accelerator integrated in ESP32-C5 has two working modes, which are Typical AES and DMA-AES. • Typical AES Working Mode: – Supports encryption and decryption using cryptographic keys of 128 and 256 bits, specified in NIST FIPS 197. In this working mode, the plaintext and ciphertext is written and read via CPU directly. • DMA-AES Working Mode: – Supports encryption and decryption using cryptographic keys of 128 and 256 bits, specified in NIST FIPS 197; – Supports block cipher modes ECB, CBC, OFB, CTR, CFB8, and CFB128 under NIST SP 800-38A. In this working mode, the plaintext and ciphertext are written and read via DMA. An interrupt will be generated when operation completes. Users can choose the working mode for AES accelerator by configuring the AES_DMA_ENABLE_REG register according to Table 19.4-1 below. Table 19.4-1. AES Accelerator Working Mode AES_DMA_ENABLE_REG Working Mode 0 Typical AES 1 DMA-AES Users can choose the length of cryptographic keys and encryption/decryption by configuring the AES_MODE_REG register according to Table 19.4-2 below. Table 19.4-2. Key Length and Encryption/Decryption AES_MODE_REG[2:0] Key Length and Encryption / Decryption 0 AES-128 encryption 1 reserved 2 AES-256 encryption 3 reserved 4 AES-128 decryption 5 reserved 6 AES-256 decryption 7 reserved For a detailed introduction to these two working modes, please refer to Section 19.5 and Section 19.6 below. Espressif Systems 707 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 19 AES Accelerator (AES) Notice: ESP32-C5’s Digital Signature Algorithm (DSA) module will call the AES accelerator. Therefore, users cannot access the AES accelerator when Digital Signature Algorithm (DSA) module is working. 19.5 Typical AES Working Mode In the Typical AES working mode, users can check the working status of the AES accelerator by inquiring the AES_STATE_REG register and comparing the return value against the Table 19.5-1 below. Table 19.5-1. Working Status under Typical AES Working Mode AES_STATE_REG Status Description 0 IDLE The AES accelerator is idle or completed operation. 1 WORK The AES accelerator is in the middle of an operation. 19.5.1 Key, Plaintext, and Ciphertext The encryption or decryption key is stored in AES_KEY_n_REG, which is a set of eight 32-bit registers. • For AES-128 encryption or decryption, the 128-bit key is stored in AES_KEY_0_REG AES_KEY_3_REG. • For AES-256 encryption or decryption, the 256-bit key is stored in AES_KEY_0_REG AES_KEY_7_REG. The plaintext and ciphertext are stored in AES_TEXT_IN_m_REG and AES_TEXT_OUT_m_REG, which are two sets of four 32-bit registers. • For AES-128 or AES-256 encryption, the AES_TEXT_IN_m_REG registers are initialized with plaintext. Then, the AES accelerator stores the ciphertext into AES_TEXT_OUT_m_REG after operation. • For AES-128 or AES-256 decryption, the AES_TEXT_IN_m_REG registers are initialized with ciphertext. Then, the AES accelerator stores the plaintext into AES_TEXT_OUT_m_REG after operation. Espressif Systems 708 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 19 AES Accelerator (AES) 19.5.2 Endianness Text Endianness In Typical AES working mode, the AES accelerator uses cryptographic keys to encrypt and decrypt data in blocks of 128 bits. When filling data into AES_TEXT_IN_m_REG register or reading result from AES_TEXT_OUT_m_REG registers, users should follow the text endianness type specified in Table 19.5-2. Table 19.5-2. Text Endianness Type for Typical AES Plaintext/Ciphertext State 1 c 2 0 1 2 3 r 0 AES_TEXT_x_0_REG[7:0] AES_TEXT_x_1_REG[7:0] AES_TEXT_x_2_REG[7:0] AES_TEXT_x_3_REG[7:0] 1 AES_TEXT_x_0_REG[15:8] AES_TEXT_x_1_REG[15:8] AES_TEXT_x_2_REG[15:8] AES_TEXT_x_3_REG[15:8] 2 AES_TEXT_x_0_REG[23:16] AES_TEXT_x_1_REG[23:16] AES_TEXT_x_2_REG[23:16] AES_TEXT_x_3_REG[23:16] 3 AES_TEXT_x_0_REG[31:24] AES_TEXT_x_1_REG[31:24] AES_TEXT_x_2_REG[31:24] AES_TEXT_x_3_REG[31:24] 1 The definition of “State (including c and r)” is described in Section 3.4 The State in NIST FIPS 197. 2 Where x = IN or OUT. Espressif Systems 709 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 19 AES Accelerator (AES) Key Endianness In Typical AES working mode, when filling keys into AES_KEY_m_REG registers, users should follow the key endianness type specified in Table 19.5-3 and Table 19.5-4. Table 19.5-3. Key Endianness Type for AES-128 Encryption and Decryption Bit 1 w[0] w[1] w[2] w[3] 2 [31:24] AES_KEY_0_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_3_REG[7:0] [23:16] AES_KEY_0_REG[15:8] AES_KEY_1_REG[15:8] AES_KEY_2_REG[15:8] AES_KEY_3_REG[15:8] [15:8] AES_KEY_0_REG[23:16] AES_KEY_1_REG[23:16] AES_KEY_2_REG[23:16] AES_KEY_3_REG[23:16] [7:0] AES_KEY_0_REG[31:24] AES_KEY_1_REG[31:24] AES_KEY_2_REG[31:24] AES_KEY_3_REG[31:24] 1 Column “Bit” specifies the bytes of each word stored in w[0] w[3]. 2 w[0] w[3] are “the first Nk words of the expanded key” as specified in Section 5.2 Key Expansion in NIST FIPS 197. Table 19.5-4. Key Endianness Type for AES-256 Encryption and Decryption Bit 1 w[0] w[1] w[2] w[3] w[4] w[5] w[6] w[7] 2 [31:24] AES_KEY_0_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_3_REG[7:0] AES_KEY_4_REG[7:0] AES_KEY_5_REG[7:0] AES_KEY_6_REG[7:0] AES_KEY_7_REG[7:0] [23:16] AES_KEY_0_REG[15:8] AES_KEY_1_REG[15:8] AES_KEY_2_REG[15:8] AES_KEY_3_REG[15:8] AES_KEY_4_REG[15:8] AES_KEY_5_REG[15:8] AES_KEY_6_REG[15:8] AES_KEY_7_REG[15:8] [15:8] AES_KEY_0_REG[23:16] AES_KEY_1_REG[23:16] AES_KEY_2_REG[23:16] AES_KEY_3_REG[23:16] AES_KEY_4_REG[23:16] AES_KEY_5_REG[23:16] AES_KEY_6_REG[23:16] AES_KEY_7_REG[23:16] [7:0] AES_KEY_0_REG[31:24] AES_KEY_1_REG[31:24] AES_KEY_2_REG[31:24] AES_KEY_3_REG[31:24] AES_KEY_4_REG[31:24] AES_KEY_5_REG[31:24] AES_KEY_6_REG[31:24] AES_KEY_7_REG[31:24] 1 Column “Bit” specifies the bytes of each word stored in w[0] w[7]. 2 w[0] w[7] are “the first Nk words of the expanded key” as specified in Chapter 5.2 Key Expansion in NIST FIPS 197. Espressif Systems 710 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 19 AES Accelerator (AES) 19.5.3 Operation Process Single Operation 1. Write 0 to the AES_DMA_ENABLE_REG register. 2. Initialize registers AES_MODE_REG, AES_KEY_n_REG, and AES_TEXT_IN_m_REG. 3. Start operation by writing 1 to the AES_TRIGGER_REG register. 4. Wait till the content of the AES_STATE_REG register becomes 0, which indicates the operation is completed. 5. Read results from the AES_TEXT_OUT_m_REG register. Consecutive Operations In consecutive operations, primarily the input AES_TEXT_IN_m_REG and output AES_TEXT_OUT_m_REG registers (m: 0-3) are being written and read, while the content of AES_DMA_ENABLE_REG, AES_MODE_REG, and AES_KEY_n_REG is kept unchanged. Therefore, the initialization can be simplified during the consecutive operation. 1. Write 0 to the AES_DMA_ENABLE_REG register before starting the first operation. 2. Initialize registers AES_MODE_REG and AES_KEY_n_REG before starting the first operation. 3. Update the content of AES_TEXT_IN_m_REG. 4. Start operation by writing 1 to the AES_TRIGGER_REG register. 5. Wait till the content of the AES_STATE_REG register becomes 0, which indicates the operation completes. 6. Read results from the AES_TEXT_OUT_m_REG register, and return to Step 3 to continue the next operation. Espressif Systems 711 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 19 AES Accelerator (AES) 19.6 DMA-AES Working Mode In the DMA-AES working mode, the AES accelerator supports six block cipher modes: ECB, CBC, OFB, CTR, CFB8, and CFB128. Users can choose the block cipher mode by configuring the AES_BLOCK_MODE_REG register according to Table 19.6-1 below. Table 19.6-1. Block Cipher Mode AES_BLOCK_MODE_REG[2:0] Block Cipher Mode 0 ECB (Electronic Codebook) 1 CBC (Cipher Block Chaining) 2 OFB (Output Feedback) 3 CTR (Counter) 4 CFB8 (8-bit Cipher Feedback) 5 CFB128 (128-bit Cipher Feedback) 6 reserved 7 reserved Users can check the working status of the AES accelerator by inquiring the AES_STATE_REG register and comparing the return value against the Table 19.6-2 below. Table 19.6-2. Working Status under DMA-AES Working mode AES_STATE_REG Status Description 0 IDLE The AES accelerator is idle. 1 WORK The AES accelerator is in the middle of an operation. 2 DONE The AES accelerator completed operations. When working in the DMA-AES working mode, the AES accelerator supports interrupt on the completion of computation. To enable this function, write 1 to the AES_INT_ENA_REG register. By default, the interrupt function is disabled. Also, note that the interrupt should be cleared by software after use. 19.6.1 Key, Plaintext, and Ciphertext Block Operation During the block operations, the AES accelerator reads source data from DMA, and writes result data to DMA after the computation. • For encryption, DMA reads plaintext from memory, then passes it to AES as source data. After computation, AES passes ciphertext as result data back to DMA to write into memory. • For decryption, DMA reads ciphertext from memory, then passes it to AES as source data. After computation, AES passes plaintext as result data back to DMA to write into memory. During block operations, the lengths of the source data and result data are the same. The total computation time is reduced because the DMA data operation and AES computation can happen concurrently. Espressif Systems 712 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 19 AES Accelerator (AES) The length of source data for AES accelerator under DMA-AES working mode must be 128 bits or the integral multiples of 128 bits. Otherwise, trailing zeros will be added to the original source data, so the length of source data equals to the nearest integral multiples of 128 bits. Please see details in Table 19.6-3 below. Table 19.6-3. TEXT-PADDING Function : TEXT-PADDING( ) Input : X, bit string. Output : Y = TEXT-PADDING(X), whose length is the nearest integral multiples of 128 bits. Steps Let us assume that X is a data-stream that can be split into n parts as following: X = X 1 ||X 2 || · · · ||X n−1 ||X n Here, the lengths of X 1 , X 2 , · · · , X n−1 all equal to 128 bits, and the length of X n is t (0<=t<=127). If t = 0 , then TEXT-PADDING(X) = X; If 0 < t <= 127, define a 128-bit block, X ∗ n , and let X ∗ n = X n ||0 128−t , then TEXT-PADDING(X) = X 1 ||X 2 || · · · ||X n−1 ||X ∗ n = X||0 128−t 19.6.2 Endianness Under the DMA-AES working mode, the transmission of source data and result data for AES accelerator is solely controlled by DMA. Therefore, the AES accelerator cannot control the Endianness of the source data and result data, but does have requirement on how these data should be stored in memory and on the length of the data. For example, let us assume DMA needs to write the following data into memory at address 0x0280. • Data represented in hexadecimal: – 0102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F20 • Data Length: – Equals to 2 blocks. Then, this data will be stored in memory as shown in Table 19.6-4 below. Table 19.6-4. Text Endianness for DMA-AES Address Byte Address Byte Address Byte Address Byte 0x0280 0x01 0x0281 0x02 0x0282 0x03 0x0283 0x04 0x0284 0x05 0x0285 0x06 0x0286 0x07 0x0287 0x08 0x0288 0x09 0x0289 0x0A 0x028A 0x0B 0x028B 0x0C 0x028C 0x0D 0x028D 0x0E 0x028E 0x0F 0x028F 0x10 0x0290 0x11 0x0291 0x12 0x0292 0x13 0x0293 0x14 0x0294 0x15 0x0295 0x16 0x0296 0x17 0x0297 0x18 0x0298 0x19 0x0299 0x1A 0x029A 0x1B 0x029B 0x1C 0x029C 0x1D 0x029D 0x1E 0x029E 0x1F 0x029F 0x20 Espressif Systems 713 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 19 AES Accelerator (AES) 19.6.3 Standard Incrementing Function AES accelerator provides two Standard Incrementing Functions for the CTR block operation, which are INC 32 and INC 128 Standard Incrementing Functions. By setting the AES_INC_SEL_REG register to 0 or 1, users can choose the INC 32 or INC 128 functions respectively. For details on the Standard Incrementing Function, please see Chapter B.1 The Standard Incrementing Function in NIST SP 800-38A. 19.6.4 Block Number Register AES_BLOCK_NUM_REG stores the Block Number of plaintext P or ciphertext C. The length of this register equals to length(TEXT-PADDING(P ))/128 or length(TEXT-PADDING(C))/128. The AES accelerator only uses this register when working in the DMA-AES mode. 19.6.5 Initialization Vector AES_IV_MEM is a 16-byte memory, which is only available for AES accelerator working in block operations. For CBC/OFB/CFB8/CFB128 operations, the AES_IV_MEM memory stores the Initialization Vector (IV). For the CTR operation, the AES_IV_MEM memory stores the Initial Counter Block (ICB). Both IV and ICB are 128-bit strings, which can be divided into Byte0, Byte1, Byte2 · · · Byte15 (from left to right). AES_IV_MEM stores data following the Endianness pattern presented in Table 19.6-4, i.e. the most significant (i.e., left-most) byte Byte0 is stored at the lowest address while the least significant (i.e., right-most) byte Byte15 at the highest address. For more details on IV and ICB, please refer to NIST SP 800-38A. 19.6.6 Block Operation Process 1. Select one of DMA channels to connect with AES, configure the DMA linked list, and then start DMA. For details, please refer to Chapter 3 GDMA Controller (GDMA). 2. Initialize the AES accelerator-related registers: • Write 1 to the AES_DMA_ENABLE_REG register. • Configure the AES_INT_ENA_REG register to enable or disable the interrupt function. • Initialize registers AES_MODE_REG and AES_KEY_n_REG. • Select block cipher mode by configuring the AES_BLOCK_MODE_REG register. For details, see Table 19.6-1. • Initialize the AES_BLOCK_NUM_REG register. For details, see Section 19.6.4. • Initialize the AES_INC_SEL_REG register (only needed when AES accelerator is working under CTR block operation). • Initialize the AES_IV_MEM memory (This is always needed except for ECB block operation). 3. Start operation by writing 1 to the AES_TRIGGER_REG register. 4. Wait for the completion of computation, which happens when the content of AES_STATE_REG becomes 2 or the AES interrupt occurs. Espressif Systems 714 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 19 AES Accelerator (AES) 5. Check if DMA completes data transmission from AES to memory. At this time, DMA had already written the result data in memory, which can be accessed directly. For details on DMA, please refer to Chapter 3 GDMA Controller (GDMA). 6. Clear interrupt by writing 1 to the AES_INT_CLEAR_REG register, if any AES interrupt occurred during the computation. 7. Release the AES accelerator by writing 1 to the AES_DMA_EXIT_REG register. After this, the content of the AES_STATE_REG register becomes 0. Note that, you can release DMA earlier, but only after Step 4 is completed. 19.7 Anti-Attack Pseudo-Round Function To enhance anti-attack performance, ESP32-C5’s AES incorporates a pseudo-round function. When the pseudo-round function is enabled, AES randomly inserts pseudo-rounds before and after the original operation rounds. During a pseudo-round, AES uses a pseudo-key, automatically generated by the hardware, to perform a round of dummy operations. These operations do not affect the original AES operation results. Users can enable the pseudo-round function by setting AES_PSEUDO_EN to 1. The pseudo-round configuration is as follows. Total number of pseudo-rounds The total number of pseudo-rounds randomly inserted into an AES operation is controlled by the following register fields: • pseudo_base: Equal to the value of AES_PSEUDO_BASE, which configures the basic number of pseudo-rounds. • pseudo_inc: Equal to the value of AES_PSEUDO_INC, which configures the random incremental number of pseudo-rounds. The total number of pseudo-rounds will randomly fall into the range: [pseudo_base, pseudo_base + (2 pseudo_inc − 1)] Random number update frequency Users can set the frequency of random key updates in the pseudo-round function by configuring AES_PSEUDO_RNG_CNT. A higher value results in a higher update frequency. It is generally recommended to set this value to the maximum of 7. Espressif Systems 715 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 19 AES Accelerator (AES) 19.8 Memory Summary The addresses in this section are relative to the AES accelerator base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Size (byte) Starting Address Ending Address Access AES_IV_MEM Memory IV 16 bytes 0x0050 0x005F R/W Espressif Systems 716 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 19 AES Accelerator (AES) 19.9 Register Summary The addresses in this section are relative to the AES accelerator base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Key Registers AES_KEY_0_REG AES key data register 0 0x0000 R/W AES_KEY_1_REG AES key data register 1 0x0004 R/W AES_KEY_2_REG AES key data register 2 0x0008 R/W AES_KEY_3_REG AES key data register 3 0x000C R/W AES_KEY_4_REG AES key data register 4 0x0010 R/W AES_KEY_5_REG AES key data register 5 0x0014 R/W AES_KEY_6_REG AES key data register 6 0x0018 R/W AES_KEY_7_REG AES key data register 7 0x001C R/W TEXT_IN Registers AES_TEXT_IN_0_REG Source text data register 0 0x0020 R/W AES_TEXT_IN_1_REG Source text data register 1 0x0024 R/W AES_TEXT_IN_2_REG Source text data register 2 0x0028 R/W AES_TEXT_IN_3_REG Source text data register 3 0x002C R/W TEXT_OUT Registers AES_TEXT_OUT_0_REG Result text data register 0 0x0030 R/W AES_TEXT_OUT_1_REG Result text data register 1 0x0034 R/W AES_TEXT_OUT_2_REG Result text data register 2 0x0038 R/W AES_TEXT_OUT_3_REG Result text data register 3 0x003C R/W Control/Configuration Registers AES_MODE_REG Key length and encryption/decryption configura- tion register 0x0040 R/W AES_TRIGGER_REG Operation start control register 0x0048 WT AES_DMA_ENABLE_REG Working mode configuration register 0x0090 R/W AES_BLOCK_MODE_REG Block cipher mode configuration register 0x0094 R/W AES_BLOCK_NUM_REG Block number configuration register 0x0098 R/W AES_INC_SEL_REG Standard incrementing function register 0x009C R/W AES_DMA_EXIT_REG Operation exit control register 0x00B8 WT AES_PSEUDO_REG Pseudo-round function configuration register 0x00D0 R/W Status Register AES_STATE_REG Operation status register 0x004C RO Interrupt Registers AES_INT_CLEAR_REG DMA-AES interrupt clear register 0x00AC WT AES_INT_ENA_REG DMA-AES interrupt enable register 0x00B0 R/W Version control register AES_DATE_REG AES version control register 0x00B4 R/W Espressif Systems 717 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 19 AES Accelerator (AES) 19.10 Registers The addresses in this section are relative to the AES accelerator base address provided in Table 4.3-2 in Chapter 4 System and Memory. For how to program reserved fields, please refer to Section VII . Register 19.1. AES_KEY_n_REG (n: 0-7) (0x0000+4*n) AES_KEY_n_REG (n: 0-7) 0x000000000 31 0 Reset AES_KEY_n_REG (n: 0-7) Represents AES key data. (R/W) Register 19.2. AES_TEXT_IN_m_REG (m: 0-3) (0x0020+4*m) AES_TEXT_IN_m_REG (m: 0-3) 0x000000000 31 0 Reset AES_TEXT_IN_m_REG (m: 0-3) Represents the source text data when the AES accelerator operates in the Typical AES working mode. (R/W) Register 19.3. AES_TEXT_OUT_m_REG (m: 0-3) (0x0030+4*m) AES_TEXT_OUT_m_REG (m: 0-3) 0x000000000 31 0 Reset AES_TEXT_OUT_m_REG (m: 0-3) Represents the result text data when the AES accelerator oper- ates in the Typical AES working mode. (RO) Espressif Systems 718 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 19 AES Accelerator (AES) Register 19.4. AES_MODE_REG (0x0040) (reserved) 0x00000000 31 3 AES_MODE 0 2 0 Reset AES_MODE Configures the key length and encryption/decryption of the AES accelerator. 0: AES-128 encryption 1: Reserved 2: AES-256 encryption 3: Reserved 4: AES-128 decryption 5: Reserved 6: AES-256 decryption 7: Reserved (R/W) Register 19.5. AES_TRIGGER_REG (0x0048) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 AES_TRIGGER 0 0 Reset AES_TRIGGER Configures whether to start AES operation. 0: No effect 1: Start (WT) Register 19.6. AES_DMA_ENABLE_REG (0x0090) (reserved) 0x00000000 31 1 AES_DMA_ENABLE 0 0 Reset AES_DMA_ENABLE Configures the working mode of the AES accelerator. 0: Typical AES 1: DMA-AES (R/W) Espressif Systems 719 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 19 AES Accelerator (AES) Register 19.7. AES_BLOCK_MODE_REG (0x0094) (reserved) 0x00000000 31 3 AES_BLOCK_MODE 0 2 0 Reset AES_BLOCK_MODE Configures the block cipher mode of the AES accelerator operating under the DMA-AES working mode. 0: ECB (Electronic Code Block) 1: CBC (Cipher Block Chaining) 2: OFB (Output FeedBack) 3: CTR (Counter) 4: CFB8 (8-bit Cipher FeedBack) 5: CFB128 (128-bit Cipher FeedBack) 6: Reserved 7: Reserved (R/W) Register 19.8. AES_BLOCK_NUM_REG (0x0098) AES_BLOCK_NUM 0x00000000 31 0 Reset AES_BLOCK_NUM Represents the Block Number of plaintext or ciphertext when the AES accelerator operates under the DMA-AES working mode. For details, see Section 19.6.4. (R/W) Register 19.9. AES_INC_SEL_REG (0x009C) (reserved) 0x00000000 31 1 AES_INC_SEL 0 0 Reset AES_INC_SEL Configures the Standard Incrementing Function for CTR block operation. 0: INC 32 1: INC 128 (R/W) Espressif Systems 720 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 19 AES Accelerator (AES) Register 19.10. AES_DMA_EXIT_REG (0x00B8) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 AES_DMA_EXIT 0 0 Reset AES_DMA_EXIT Configures whether to exit AES operation. 0: No effect 1: Exit Only valid for DMA-AES operation. (WT) Register 19.11. AES_PSEUDO_REG (0x00D0) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 10 AES_PSEUDO_RNG_CNT 7 9 7 AES_PSEUDO_INC 2 6 5 AES_PSEUDO_BASE 2 4 1 AES_PSEUDO_EN 0 0 Reset AES_PSEUDO_EN Configures whether to enable the pseudo-round function of AES. 0: Disabled 1: Enabled (R/W) AES_PSEUDO_BASE Configures the basic number of pseudo-rounds. (R/W) AES_PSEUDO_INC Configures the random incremental number of pseudo-rounds. (R/W) AES_PSEUDO_RNG_CNT Configures the frequency of pseudo-key updates in the pseudo-round function. (R/W) Espressif Systems 721 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 19 AES Accelerator (AES) Register 19.12. AES_STATE_REG (0x004C) (reserved) 0x00000000 31 2 AES_STATE 0x0 1 0 Reset AES_STATE Represents the working status of the AES accelerator. In Typical AES working mode: 0: IDLE 1: WORK 2: No effect 3: No effect In DMA-AES working mode: 0: IDLE 1: WORK 2: DONE 3: No effect (RO) Register 19.13. AES_INT_CLEAR_REG (0x00AC) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 AES_INT_CLEAR 0 0 Reset AES_INT_CLEAR Write 1 to clear the AES interrupt. (WT) Register 19.14. AES_INT_ENA_REG (0x00B0) (reserved) 0x00000000 31 1 AES_INT_ENA 0 0 Reset AES_INT_ENA Write 1 to enable the AES interrupt. (R/W) Espressif Systems 722 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 19 AES Accelerator (AES) Register 19.15. AES_DATE_REG (0x00B4) (reserved) 0 0 0 0 31 28 AES_DATE 0x2312070 27 0 Reset AES_DATE Version control register. (R/W) Espressif Systems 723 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 20 ECC Accelerator (ECC) Chapter 20 ECC Accelerator (ECC) 20.1 Overview Elliptic Curve Cryptography (ECC) is an approach to public-key cryptography based on the algebraic structure of elliptic curves. ECC uses smaller keys compared to RSA cryptography while providing equivalent security. ESP32-C5’s ECC accelerator can complete various calculations based on different elliptic curves, thus accelerating the ECC algorithm and ECC-derived algorithms such as ECDSA. 20.2 Feature List ESP32-C5’s ECC accelerator has the following features: • Three different elliptic curves, namely, P-192, P-256, and P-384 defined in FIPS 186-5 • 11 working modes • High-security mode • Interrupt upon completion of calculation 20.3 ECC Basics To better illustrate the functionality of the ECC accelerator, the basic knowledge and terminology used in this chapter are introduced in this section. 20.3.1 Elliptic Curve and Points on the Curves The ECC algorithm is based on elliptic curves over prime fields, which can be represented as: y 2 = x 3 + ax + b mod p where, • p is a prime number, • a and b are two non-negative integers smaller than p, • and (x, y) is a point on the curve satisfying the representation. 20.3.2 Affine Coordinates and Jacobian Coordinates An elliptic curve can be represented as below: Espressif Systems 724 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 20 ECC Accelerator (ECC) • In affine coordinates: y 2 = x 3 + ax + b mod p • In Jacobian coordinates: Y 2 = X 3 + aXZ 4 + bZ 6 mod p To convert affine coordinates (x, y) to/from Jacobian coordinates (X, Y, Z): • From Jacobian to Affine coordinates: x = X/Z 2 mod p y = Y /Z 3 mod p • From Affine to Jacobian coordinates: X = x Y = y Z = 1 20.3.3 Memory Blocks ECC’s memory blocks store the input and output data of the ECC operation. Table 20.3-1. ECC Accelerator Memory Blocks Memory Block 1 Size (byte) Starting Address 2 Ending Address 2 Access ECC_MULT_Mem_k 48 0x100 0x12F R/W ECC_MULT_Mem_Px 48 0x130 0x15F R/W ECC_MULT_Mem_Py 48 0x160 0x18F R/W ECC_MULT_Mem_Qx 48 0x190 0x1BF R/W ECC_MULT_Mem_Qy 48 0x1C0 0x1EF R/W ECC_MULT_Mem_Qz 48 0x1F0 0x21F R/W 1 The memory blocks store different types of data in different working modes. Refer to Section 20.4.2 for more details. 2 Address offset related to the ECC accelerator base address is provided in Table 4.3-2 in Chapter 4 System and Memory. 20.3.4 Data and Data Block ESP32-C5’s ECC can operate on 192-bit, 256-bit, or 384-bit data, depending on the elliptic curves. For example, the 256-bit data D[255 : 0] can be divided into eight 32-bit data blocks D[n][31 : 0](n = 0, 1, · · · , 7). Data blocks with smaller indexes correspond to lower binary bits. To be specific: D[255 : 0] = D[7][31 : 0], D[6][31 : 0], D[5][31 : 0], D[4][31 : 0] , D[3][31 : 0], D[2][31 : 0], D[1][31 : 0], D[0][31 : 0] Espressif Systems 725 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 20 ECC Accelerator (ECC) 20.3.5 Writing Data Writing data means writing data to an ECC memory block and using this data as the input to the ECC algorithm. To be specific, writing data to an ECC memory block means writing D[n][31 : 0](n = 0, 1, · · · , 7) to the “starting address of this ECC memory block + 4 × n” sequentially: • write D[0] to “starting address” • write D[1] to “starting address + 4” • · · · • write D[11] to “starting address + 44” Note: When storing data, write only the data block of the required length. Do not append a 0 to the most significant bit. For example, for 192-bit data, store only the 192 bits without appending 0. 20.3.6 Reading Data Reading data means reading data from the starting address of an ECC memory block and using this data as the output from the ECC algorithm. To be specific, reading data from an ECC memory block means reading D[n][31 : 0](n = 0, 1, · · · , 11) from the “starting address of this ECC memory block + 4 × n” successively: • read D[0] from “starting address” • read D[1] from “starting address + 4” • · · · • read D[11] from “starting address + 44” Note: When reading data, only the data block of the required length needs to be read. For example, to read 192-bit data, simply read the lower 192 bits (i.e., 6 data blocks). 20.3.7 Standard Calculation and Jacobian Calculation ESP32-C5’s ECC performs Affine Point Calculation (including Affine Point Verification, Affine Point Add, and Affine Point Multiplication) using the affine coordinates and Jacobian Calculation (including Jacobian Point Verification, Jacobian Point Add, and Jacobian Point Multiplication) using the Jacobian coordinates. 20.4 Function Description 20.4.1 Curve Mode ESP32-C5’s ECC supports acceleration based on three curve modes, each corresponding to an elliptic curve. By configuring the ECC_MULT_CURVE_MODE field, users can select the desired key size. For details, see Table 20.4-1 below. Espressif Systems 726 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 20 ECC Accelerator (ECC) Table 20.4-1. ECC Accelerator Curve Mode Selection ECC_MULT_CURVE_MODE Elliptic Curves * 0 FIPS P-192 1 FIPS P-256 2 FIPS P-384 * See definition of FIPS P-192, P-256, and P-384 defined in FIPS 186-5. 20.4.2 Working Modes ESP32-C5’s ECC accelerator supports 11 working modes based on two elliptic curves described in the above section. By configuring the ECC_MULT_WORK_MODE field, users can select the desired working mode. For details, see Table 20.4-2. Table 20.4-2. Working Modes of ECC Accelerator ECC_MULT_WORK_MODE Working Modes 0 Affine Point Multi 1 Reserved 2 Affine Point Verif 3 Affine Point Verif + Multi 4 Jacobian Point Multi 5 Point Add 6 Jacobian Point Verif 7 Affine Point Verif + Jacobian Point Multi 8 Mod Add 9 Mod Sub 10 Mod Multi 11 Mod Div Note: Note that the calculation of Jacobian Point Multi mode is about 10% faster than that of the Affine Point Multi mode. Detailed descriptions about different working modes are provided in the following sections. 20.4.2.1 Affine Point Multiplication (Affine Point Multi) Affine Point Multiplication can be represented as: Q = (Q x , Q y ) = (J x , J y , J z ) = k · (P x , P y ) where, • (Q x , Q y ) is the affine expression of point Q. • (J x , J y , J z ) is the Jacobian expression of point Q. Espressif Systems 727 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 20 ECC Accelerator (ECC) • Input: P x , P y , and k are stored in ECC_MULT_Mem_Px, ECC_MULT_Mem_Py, and ECC_MULT_Mem_k respectively. • Output: Q x and Q y are stored in ECC_MULT_Mem_Px and ECC_MULT_Mem_Py respectively. 20.4.2.2 Affine Point Verification (Affine Point Verif) Affine Point Verification can be used to verify if a point (P x , P y ) is on a selected elliptic curve. • Input: P x and P y are stored in ECC_MULT_Mem_Px and ECC_MULT_Mem_Py respectively. • Output: The verification result is stored in the ECC_MULT_VERIFICATION_RESULT bit. 20.4.2.3 Affine Point Verification + Affine Point Multiplication (Affine Point Verif + Multi) In this mode, ECC first verifies if point (P x , P y ) is on the selected elliptic curve. If so, the following multiplication is performed: Q = (Q x , Q y ) = (J x , J y , J z ) = k · (P x , P y ) where, • (Q x , Q y ) is the affine expression of point Q. • (J x , J y , J z ) is the Jacobian expression of point Q. • Input: P x , P y , and k are stored in ECC_MULT_Mem_Px, ECC_MULT_Mem_Py, and ECC_MULT_Mem_k respectively. • Output: – The verification result is stored in the ECC_MULT_VERIFICATION_RESULT bit. – Q x and Q y are stored in ECC_MULT_Mem_Px and ECC_MULT_Mem_Py respectively. – J x , J y , and J z are stored in ECC_MULT_Mem_Qx, ECC_MULT_Mem_Qy, and ECC_MULT_Mem_Qz. 20.4.2.4 Jacobian Point Multiplication (Jacobian Point Multi) Jacobian Point Multiplication can be represented as: Q = (Q x , Q y , Q z ) = k · (P x , P y , 1) where, • (Q x , Q y , Q z ) is the Jacobian expression of point Q. • 1 in the point’s Jacobian coordinates is automatically completed by hardware. • Input: P x , P y , and k are stored in ECC_MULT_Mem_Px, ECC_MULT_Mem_Py, and ECC_MULT_Mem_k respectively. • Output: Q x , Q y , and Q z are stored in ECC_MULT_Mem_Qx, ECC_MULT_Mem_Qy, and ECC_MULT_Mem_Qz respectively. Espressif Systems 728 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 20 ECC Accelerator (ECC) 20.4.2.5 Point Addition (Point Add) Point Addition can be represented as: R = (R x , R y ) = (J x , J y , J z ) = (P x , P y , 1) + (Q x , Q y , Q z ) where, • (R x , R y ) is the affine expression of point R. • (J x , J y , J z ) is the Jacobian expression of point R. • 1 in the point’s Jacobian coordinates is automatically completed by hardware. • Input: – P x and P y are stored in ECC_MULT_Mem_Px and ECC_MULT_Mem_Py. – Q x , Q y , and Q z are stored in ECC_MULT_Mem_Qx, ECC_MULT_Mem_Qy, and ECC_MULT_Mem_Qz. • Output: – R x and R y are stored in ECC_MULT_Mem_Px and ECC_MULT_Mem_Py. – J x , J y and J z are stored in ECC_MULT_Mem_Qx, ECC_MULT_Mem_Qy, and ECC_MULT_Mem_Qz. 20.4.2.6 Jacobian Point Verification (Jacobian Point Verif) Jacobian Point Verification can be used to verify if point (Q x , Q y , Q z ) is on a selected elliptic curve. • (Q x , Q y , Q z ) is the Jacobian expression of point Q. • Input: Q x , Q y , and Q z are stored in ECC_MULT_Mem_Qx, ECC_MULT_Mem_Qy, and ECC_MULT_Mem_Qz respectively. • Output: The verification result is stored in the ECC_MULT_VERIFICATION_RESULT bit. 20.4.2.7 Affine Point Verification + Jacobian Point Multiplication (Affine Point Verif + Jacobian Point Multi) In this mode, ECC first verifies if point (P x , P y ) is on the selected elliptic curve. If so, the following multiplication is performed: Q = (Q x , Q y , Q z ) = k · (P x , P y , 1) where, • (Q x , Q y , Q z ) is the Jacobian expression of point Q. • 1 in the point’s Jacobian coordinates is automatically completed by hardware. • Input: P x , P y , and k are stored in ECC_MULT_Mem_Px, ECC_MULT_Mem_Py, and ECC_MULT_Mem_k. • Output: – The verification result is stored in the ECC_MULT_VERIFICATION_RESULT bit. – Q x , Q y , and Q z are stored in ECC_MULT_Mem_Qx, ECC_MULT_Mem_Qy, and ECC_MULT_Mem_Qz. Espressif Systems 729 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 20 ECC Accelerator (ECC) 20.4.2.8 Mod Addition (Mod Add) Mod Addition can be represented as: R = A + B mod N where, • Input: – A and B are stored in ECC_MULT_Mem_Px and ECC_MULT_Mem_Py. – The value of N is related to the register fields below: * ECC_MULT_CURVE_MODE to select the related curve. * ECC_MULT_MOD_BASE to choose using mod base or order of the base point. • Output: R is stored in ECC_MULT_Mem_Px. 20.4.2.9 Mod Subtraction (Mod Sub) Mod Subtraction can be represented as: R = A − B mod N where, • Input: – A and B are stored in ECC_MULT_Mem_Px and ECC_MULT_Mem_Py. – The value of N is related to the register fields below: * ECC_MULT_CURVE_MODE to select the related curve. * ECC_MULT_MOD_BASE to choose using mod base or order of the base point. • Output: R is stored in ECC_MULT_Mem_Px. 20.4.2.10 Mod Multiplication (Mod Multi) Mod Multiplication can be represented as: R = A · B mod N where, • Input: – A and B are stored in ECC_MULT_Mem_Px and ECC_MULT_Mem_Py. – The value of N is related to the register fields below: * ECC_MULT_CURVE_MODE to select the related curve. * ECC_MULT_MOD_BASE to choose using mod base or order of the base point. • Output: R is stored in ECC_MULT_Mem_Py. Espressif Systems 730 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 20 ECC Accelerator (ECC) 20.4.2.11 Mod Division (Mod Div) Mod Division can be represented as: R = A · B −1 mod N where, • Input: – A and B are stored in ECC_MULT_Mem_Px and ECC_MULT_Mem_Py. – The value of N is related to the register fields below: * ECC_MULT_CURVE_MODE to select the related curve. * ECC_MULT_MOD_BASE to choose using mod base or order of the base point. • Output: R is stored in ECC_MULT_Mem_Py. 20.4.3 Enhancing Anti-Attack Performance When performing different types of point multiplication calculations, i.e., mode 0, 3, 4, and 7, ESP32-C5’s ECC accelerator offers an additional option to further enhance its anti-attack performance by ensuring that all point multiplication calculations take the same maximum runtime. To enable the enhanced anti-attack performance, set ECC_MULT_SECURITY_MODE to 1. If this setting is enabled, each point multiplication calculation of the ECC accelerator will: • consume the same amount of time; • consume the same amount of power. 20.4.4 Clock ECC uses two types of clocks: • clk_ecc: function clock for ECC to operate • clk_apb_ecc: bus clock used to configure ECC registers Espressif Systems 731 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 20 ECC Accelerator (ECC) Figure 20.4-1. clk_ecc Diagram As shown in Figure 20.4-1 clk_ecc Diagram, the secure function source clock clk_sec_ori can be sourced from: • XTAL_CLK • RC_FAST_CLK • PLL_F160M_CLK ECC’s function clock clk_ecc is configured by the clock gating register PCR_ECC_CLK_EN. When this register is set to 1, the clock gate is enabled, and clk_ecc is activated. Figure 20.4-2. clk_apb_ecc Diagram As shown in Figure 20.4-2 clk_apb_ecc Diagram, ECC’s configuration clock clk_apb_ecc can be sourced from SYSTEM_APB_CLK. ECC’s configuration clock clk_apb_ecc is controlled by the clock gating register PCR_ECC_CLK_EN. When this register is set to 1, the clock gate is enabled, and clk_apb_ecc is activated. For more information about clocks, see Section 7 Reset and Clock. 20.4.5 Reset The ECC module supports two types of resets: • Full self-reset: Write 1 and then 0 to PCR_ECC_RST_EN to reset the entire ECC module. Espressif Systems 732 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 20 ECC Accelerator (ECC) • Cryptographic protection reset: Write 1 and then 0 to PCR_ECDSA_RST_EN to reset the entire ECC module. Note: Due to shared resources among cryptographic accelerators, the ECDSA module reuses resources from the ECC module during computation. To protect ECDSA operation data, resetting the ECDSA module also resets the ECC module. 20.5 Interrupts ESP32-C5’s ECC accelerator can generate the ECC_INTR interrupt signal that will be sent to the Interrupt Matrix. ECC_INTR has only one interrupt source to generate the ECC_INTR interrupt signal, i.e., ECC_MULT_CALC_DONE_INT, which is triggered on the completion of an ECC calculation. Each interrupt source can be configured by a common set of registers that are described in Section Interrupt Configuration Registers. The ECC_MULT_CALC_DONE_INT interrupt source is configured by the following registers (refer to Section 20.7 Register Summary for more information): • ECC_MULT_CALC_DONE_INT_RAW: Stores the raw interrupt status of ECC_MULT_CALC_DONE_INT. • ECC_MULT_CALC_DONE_INT_ST: Indicates the status of the ECC_MULT_CALC_DONE_INT interrupt. This bit is generated by enabling or disabling the ECC_MULT_CALC_DONE_INT_RAW bit via ECC_MULT_CALC_DONE_INT_ENA. • ECC_MULT_CALC_DONE_INT_ENA: Enables or disables the ECC_MULT_CALC_DONE_INT interrupt. • ECC_MULT_CALC_DONE_INT_CLR: Set this bit to clear the ECC_MULT_CALC_DONE_INT interrupt status. By setting this bit to 1, the ECC_MULT_CALC_DONE_INT_RAW and ECC_MULT_CALC_DONE_INT_ST bits will be cleared. Note: For definitions of interrupt, interrupt signal, interrupt source, and their correlations, please refer to Chapter 9 Interrupt Matrix > Section 9.2 Terminology. 20.6 Programming Procedures The programming procedure for configuring ECC is described below: 1. Configure the ECC clock and reset. Refer to Sections 20.4.4 and 20.4.5 for detailed information. 2. Select the key size and working mode as described in Section 20.4. 3. Enable the ECC_MULT_CALC_DONE_INT interrupt as described in Section 20.5. 4. Set the ECC_MULT_START field to start ECC calculation. 5. Wait for the ECC_MULT_CALC_DONE_INT interrupt, which indicates the completion of the ECC calculation. 6. Check the result as described in Section 20.4. Espressif Systems 733 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 20 ECC Accelerator (ECC) 20.7 Register Summary The addresses in this section are relative to ECC accelerator base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Interrupt Registers ECC_MULT_INT_RAW_REG ECC raw interrupt status register 0x000C R/SS/WTC ECC_MULT_INT_ST_REG ECC masked interrupt status register 0x0010 RO ECC_MULT_INT_ENA_REG ECC interrupt enable register 0x0014 R/W ECC_MULT_INT_CLR_REG ECC interrupt clear register 0x0018 WT Configuration Register ECC_MULT_CONF_REG ECC configuration register 0x001C varies Version Register ECC_MULT_DATE_REG Version control register 0x00FC R/W Espressif Systems 734 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 20 ECC Accelerator (ECC) 20.8 Registers The addresses in this section are relative to ECC accelerator base address provided in Table 4.3-2 in Chapter 4 System and Memory. For how to program reserved fields, please refer to Section Programming Reserved Register Field. Register 20.1. ECC_MULT_INT_RAW_REG (0x000C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 ECC_MULT_CALC_DONE_INT_RAW 0 0 Reset ECC_MULT_CALC_DONE_INT_RAW The raw interrupt status of the ECC_MULT_CALC_DONE_INT interrupt. (R/SS/WTC) Register 20.2. ECC_MULT_INT_ST_REG (0x0010) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 ECC_MULT_CALC_DONE_INT_ST 0 0 Reset ECC_MULT_CALC_DONE_INT_ST The masked interrupt status of the ECC_MULT_CALC_DONE_INT interrupt. (RO) Espressif Systems 735 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 20 ECC Accelerator (ECC) Register 20.3. ECC_MULT_INT_ENA_REG (0x0014) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 ECC_MULT_CALC_DONE_INT_ENA 0 0 Reset ECC_MULT_CALC_DONE_INT_ENA Write 1 to enable the ECC_MULT_CALC_DONE_INT interrupt. (R/W) Register 20.4. ECC_MULT_INT_CLR_REG (0x0018) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 ECC_MULT_CALC_DONE_INT_CLR 0 0 Reset ECC_MULT_CALC_DONE_INT_CLR Write 1 to clear the ECC_MULT_CALC_DONE_INT interrupt. (WT) Espressif Systems 736 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 20 ECC Accelerator (ECC) Register 20.5. ECC_MULT_CONF_REG (0x001C) ECC_MULT_MEM_CLOCK_GATE_FORCE_ON 0 31 ECC_MULT_CLK_EN 0 30 ECC_MULT_VERIFICATION_RESULT 0 29 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28 10 ECC_MULT_SECURITY_MODE 0 9 ECC_MULT_WORK_MODE 0 8 5 ECC_MULT_MOD_BASE 0 4 ECC_MULT_CURVE_MODE 0 3 2 ECC_MULT_RESET 0 1 ECC_MULT_START 0 0 Reset ECC_MULT_START Configures whether to start the calculation of the ECC accelerator. This bit will be self-cleared when the calculation is done. 0: No effect 1: Start the calculation of the ECC accelerator (R/W/SC) ECC_MULT_RESET Configures whether to reset the ECC accelerator. 0: No effect 1: Reset (WT) ECC_MULT_CURVE_MODE Configures the curve mode of the ECC accelerator. 0: P-192 1: P-256 2: P-384 3: Invalid (R/W) ECC_MULT_MOD_BASE Configures whether to choose using the mod base or order of base point in the mod operation. Only valid in working modes 8-11. 0: n (order of base point) 1: p (mod base of curve) (R/W) Continued on the next page... Espressif Systems 737 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 20 ECC Accelerator (ECC) Register 20.5. ECC_MULT_CONF_REG (0x001C) Continued from the previous page... ECC_MULT_WORK_MODE Configures the working mode of the ECC accelerator. 0: Affine Point Multi mode 1: Reserved 2: Affine Point Verif mode 3: Affine Point Verif + Multi mode 4: Jacobian Point Multi mode 5: Point Add mode 6: Jacobian Point Verif mode 7: Affine Point Verif + Jacobian Point Multi mode 8: Mod Add mode 9. Mod Sub mode 10: Mod Multi mode 11: Mod Div mode (R/W) ECC_MULT_SECURITY_MODE Configures whether to enable high-security mode when calculating point multiplication. Only valid in working modes 0, 3, 4, and 7. 0: Disable 1: Enable (R/W) ECC_MULT_VERIFICATION_RESULT Represents the verification result of the ECC accelerator, valid only when the calculation is done. 0: Verification failed 1: Verification passed (R/SS) ECC_MULT_CLK_EN Configures whether to force on register clock gate. 0: No effect 1: Force on (R/W) ECC_MULT_MEM_CLOCK_GATE_FORCE_ON Configures whether to force the ECC memory clock gate on. 0: No effect 1: Force on (R/W) Espressif Systems 738 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 20 ECC Accelerator (ECC) Register 20.6. ECC_MULT_DATE_REG (0x00FC) (reserved) 0 0 0 0 31 28 ECC_MULT_DATE 0x2408120 27 0 Reset ECC_MULT_DATE Version control register. (R/W) Espressif Systems 739 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 21 HMAC Accelerator (HMAC) Chapter 21 HMAC Accelerator (HMAC) 21.1 Overview The Hash-based Message Authentication Code (HMAC) module computes Message Authentication Codes (MACs) using hash algorithm SHA-256 and keys as described in RFC 2104. The 256-bit HMAC key is stored in an eFuse key block and can be set as read-protected, i. e., the key is not accessible from outside the HMAC accelerator. 21.2 Feature List • Standard HMAC-SHA-256 algorithm • HMAC-SHA-256 calculation based on key in eFuse, – whose result cannot be accessed by software in downstream mode for high security – whose result can be accessed by software in upstream mode • Generates required keys for the Digital Signature Algorithm (DSA) peripheral in downstream mode • Re-enables soft-disabled JTAG in downstream mode 21.3 Functional Description The HMAC module operates in two modes: upstream mode and downstream mode. In upstream mode, users provide the HMAC message and read back the calculation result. In downstream mode, the HMAC module provides input to two possible other internal hardware modules: On the one hand, an HMAC can be used to enable JTAG after JTAG has been temporarily disabled before. On the other hand, an HMAC can be used as the decryption key for Digital Signature parameters stored in the memory for the DSA peripheral. Furthermore, the calculations happen internally and automatically in downstream mode, so that confidentiality of any key and derived key material is ensured, given correct configuration. Note: After the reset signal being released, the HMAC module will check whether the DSA key exists in the eFuse. If the key exists, the HMAC module will enter downstream digital signature algorithm mode and finish the DSA key calculation automatically. This process is automatically completed by hardware and does not require software participation. When the downstream operation after reset is completed, the HMAC will automatically return to the idle state. Espressif Systems 740 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 21 HMAC Accelerator (HMAC) 21.3.1 Upstream Mode To calculate the HMAC value in upstream mode, users should perform the following steps: 1. Initialize the HMAC module and enter upstream mode. 2. Write the correctly padded message to the HMAC, one block at a time. 3. Read back the result from HMAC. For details of this process, please see Section 21.5. Note: Common use cases for the upstream mode are challenge-response protocols supporting HMAC-SHA-256. Assume the two entities in the challenge-response protocol are A and B respectively, and the data message they expect to exchange is M. The general authentication process of this protocol is as follows: • A calculates a unique random number M. • A sends M to B. • B calculates the HMAC (through M and KEY) and sends the result to A. • A calculates the HMAC (through M and KEY) internally. • A compares the two results. If the results are the same, then the identity of B is authenticated. 21.3.2 Downstream Mode - JTAG Enable Feature JTAG debugging can be disabled by eFuse in a way which allows later re-enabling using the HMAC module. (For more details, please see Chapter 5 eFuse Controller (eFuse).) The HMAC module will expect the user to supply the HMAC result for one of the eFuse keys. The HMAC module will check whether the supplied HMAC matches the one calculated from the chosen key. If both HMACs are the same, JTAG will be enabled until the user calls the HMAC module to clear the results and consequently disable JTAG again. To re-enable JTAG, users should perform the following steps: 1. Enable the HMAC module by initializing clock and reset signals of HMAC, and enter downstream JTAG enable mode by configuring HMAC_SET_PARA_PURPOSE_REG. Then, wait for the calculation to complete. Please see Section 21.5 for more details. 2. Write 1 to the HMAC_SOFT_JTAG_CTRL_REG register to enter JTAG re-enable mode. 3. Write the 256-bit HMAC value to register HMAC_WR_JTAG_REG. This value is obtained by performing a local HMAC calculation from the 32-byte 0x00 using SHA-256 and the key that has been written to the eFuse. It needs to be written 8 times and 32-bit each time in big-endian word order. 4. If the HMAC result calculated from the key in the eFuse matches the value that users wrote in step 3, then JTAG is re-enabled. Otherwise, JTAG remains disabled. 5. After writing 1 to HMAC_SET_INVALIDATE_JTAG_REG or resetting the chip, JTAG will be disabled. If users want to re-enable JTAG again, they need to repeat the above steps again. Espressif Systems 741 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 21 HMAC Accelerator (HMAC) 21.3.3 Downstream Mode - Digital Signature Algorithm and Key Deriva- tion Feature The Digital Signature Algorithm (DSA) module encrypts its parameters using the AES-CBC algorithm. The HMAC module is used as a Key Derivation Function (KDF) to derive the AES key to decrypt these parameters (parameter decryption key). Before starting the DSA module, users need to obtain the parameter decryption key for the DSA module through HMAC calculation. For more information, please see Chapter 24 Digital Signature Algorithm (DSA). After the chip is powered on, the HMAC module will check whether the key required to calculate the parameter decryption key has been burned in the eFuse block. If the key has been burned, HMAC module will automatically enter the downstream digital signature algorithm mode and complete the HMAC calculation based on the chosen key. 21.4 HMAC eFuse Configuration Each HMAC key burned into an eFuse block has a key purpose, specifying for which functionality the key can be used. The HMAC module will not accept a key with a non-matching purpose for any functionality. The HMAC module provides three different functionalities: re-enabling JTAG, DSA KDF in downstream mode, and pure HMAC calculation in upstream mode. For each functionality, there exists a corresponding key purpose, listed in Table 21.4-1. Additionally, another purpose specifies a key which may be used for re-enabling JTAG as well as for serving as DSA KDF. Before enabling HMAC to do calculations, user should make sure the key to be used has been burned in eFuse by reading the registers EFUSE_KEY_PURPOSE_x (We have a total of 6 keys in eFuse, so the value of x is 0 5. Among which, EFUSE_KEY_PURPOSE_0 EFUSE_KEY_PURPOSE_1 belong to the register EFUSE_RD_REPEAT_DATA1_REG, and EFUSE_KEY_PURPOSE_2 EFUSE_KEY_PURPOSE_5 belong to the register EFUSE_RD_REPEAT_DATA2_REG) from 5 eFuse Controller (eFuse). Take upstream mode as an example, if there is no EFUSE_KEY_PURPOSE_HMAC_UP in EFUSE_KEY_PURPOSE_0 5, it means there is no key in eFuse that can be used for the HMAC upstream mode. Users can burn a key to eFuse as follows: 1. Prepare a secret 256-bit HMAC key and burn the key to an empty eFuse block y. As there are 6 blocks for storing a key in eFuse and the numbers of those blocks range from 4 to 9, the value of y is 4 9. Hence, when talking about key0, it means eFuse block4. Then, program the purpose to EFUSE_KEY_PURPOSE_(y − 4). Take upstream mode as an example: after programming the key, the user should program EFUSE_KEY_PURPOSE_HMAC_UP (corresponding value is 8) to EFUSE_KEY_PURPOSE_(y − 4). Please see Chapter 5 eFuse Controller (eFuse) on how to program eFuse keys. 2. If needed, configure this eFuse key block to be read protected, so that users cannot read its value. A copy of this key should be kept by any party who needs to verify this device. Please note that the key whose purpose is EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL can be used for both re-enabling JTAG or DSA. Espressif Systems 742 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 21 HMAC Accelerator (HMAC) Table 21.4-1. HMAC Purposes and Configuration Value Purpose(m) Mode Value Description JTAG Re-enable Downstream 6 EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG DSA KDF Downstream 7 EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE HMAC Calculation Upstream 8 EFUSE_KEY_PURPOSE_HMAC_UP Both JTAG Re-enable and DSA KDF Downstream 5 EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL Select eFuse Key Blocks and HMAC Purposes The eFuse controller provides six key blocks, i.e., KEY0 5. To select a particular KEYn for an HMAC calculation, write the key number n to register HMAC_SET_PARA_KEY_REG. Write a correct purpose to register HMAC_SET_PARA_PURPOSE_REG (see Section 21.5). Note that the purpose of the key has also been programmed to eFuse memory. Only when the configured HMAC purpose matches the defined purpose of KEYn, the HMAC module will execute the configured calculation. Otherwise, it will return a matching error and stop the current calculation. For example, suppose a user selects KEY3 for HMAC calculation, and the value programmed to EFUSE_KEY_PURPOSE_3 is 6 (EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG). Based on Table 21.4-1, KEY3 can be used to re-enable JTAG. If the value written to register HMAC_SET_PARA_PURPOSE_REG is also 6, then the HMAC module will start the process to re-enable JTAG. Select the Key from the Key Manager Users can deploy the HMAC key in the key manager. To select this key from the key manager, write the key number 7 to register HMAC_SET_PARA_KEY_REG. When users choose the HMAC key from the key manager, the HMAC purpose will automatically be ”HMAC Calculation”, and any configuration to register HMAC_SET_PARA_PURPOSE_REG takes no effect. 21.5 HMAC Process (Detailed) The process for users to call HMAC in ESP32-C5 is as follows: 21.5.1 Enable HMAC module 1. Set the peripheral clock bits for HMAC and SHA peripherals in register HP_SYS_CLKRST_REG_CRYPTO_HMAC_CLK_EN, and clear the corresponding peripheral reset bits in register HP_SYS_CLKRST_REG_RST_EN_HMAC. For information on those registers, please see Chapter 7 Reset and Clock. 2. Write 1 to register HMAC_SET_START_REG. 21.5.2 Configure HMAC keys and key purposes 1. Write the key purpose m to register HMAC_SET_PARA_PURPOSE_REG. The possible key purpose values are shown in Table 21.4-1. For more information, please refer to Section 21.4. 2. Select KEYn in eFuse memory as the key by writing n (ranges from 0 to 5, and 7) to register Espressif Systems 743 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 21 HMAC Accelerator (HMAC) HMAC_SET_PARA_KEY_REG. For more information, please refer to Section 21.4. 3. Write 1 to register HMAC_SET_PARA_FINISH_REG to complete the configuration. 4. Read register HMAC_QUERY_ERROR_REG. If its value is 1, it means the purpose of the selected block does not match the configured key purpose and the calculation will not proceed. If its value is 0, it means the purpose of the selected block matches the configured key purpose, and then the calculation can proceed. 5. When the value of HMAC_SET_PARA_PURPOSE_REG is not 8, it means the HMAC module is in downstream mode, proceed with 21.5.3. When the value is 8, it means the HMAC module is in upstream mode, proceed with 21.5.4. 21.5.3 Downstream mode process 1. Poll Status register HMAC_QUERY_BUSY_REG until it reads 0. 2. To clear the result and make further usage of the dependent hardware (JTAG or DSA) impossible, write 1 to either register HMAC_SET_INVALIDATE_JTAG_REG to clear the result generated by the JTAG key; or to register HMAC_SET_INVALIDATE_DS_REG to clear the result generated by DSA key. Afterwards, the HMAC process needs to be restarted to re-enable any of the dependent peripherals. 21.5.4 Upstream mode process 1. Write message in upstream mode: (a) Poll Status register HMAC_QUERY_BUSY_REG until it reads 0. (b) Apply SHA padding to message as described in Section 21.6.1, and get message block: Block_n (n >= 0) (c) Perform one of the following operations according to the block number n: • If there is only one message block in total which has included all padding bits: i. Write the 512-bit Block_n to register HMAC_WR_MESSAGE_n_REG (n: 0-15). Write 1 to register HMAC_SET_MESSAGE_ONE_REG, to trigger the processing of this message block. ii. Poll Status register HMAC_QUERY_BUSY_REG until it reads 0. iii. Write 1 to register HMAC_ONE_BLOCK_REG, and finish message transmission. • If Block_n is the last padded block: i. Write the 512-bit Block_0 to register HMAC_WR_MESSAGE_n_REG (n: 0-15). Write 1 to register HMAC_SET_MESSAGE_ONE_REG, to trigger the processing of this message block. ii. Poll Status register HMAC_QUERY_BUSY_REG until it reads 0. iii. Message transmission finished automatically. • If Block_n is the second last padded block: i. Write the 512-bit Block_n to register HMAC_WR_MESSAGE_n_REG (n: 0-15). Write 1 to register HMAC_SET_MESSAGE_ONE_REG, to trigger the processing of this message block. ii. Poll Status register HMAC_QUERY_BUSY_REG until it reads 0. Espressif Systems 744 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 21 HMAC Accelerator (HMAC) iii. Write 1 to register HMAC_SET_MESSAGE_PAD_REG, and continue message transmission (jump back to step(c)). • If Block_n is neither the last nor the second last message block: i. Write the 512-bit Block_n to register HMAC_WR_MESSAGE_n_REG (n: 0-15). Write 1 to register HMAC_SET_MESSAGE_ONE_REG, to trigger the processing of this message block. ii. Poll Status register HMAC_QUERY_BUSY_REG until it reads 0. iii. Write 1 to register HMAC_SET_MESSAGE_ING_REG, and continue message transmission (jump back to step(c)). 2. Read hash result in upstream mode: (a) Poll Status register HMAC_QUERY_BUSY_REG until it reads 0. (b) Read hash result from register HMAC_RD_RESULT_n_REG (n: 0-7). (c) Write 1 to register HMAC_SET_RESULT_FINISH_REG to finish calculation. The result will be cleared at the same time. (d) Upstream mode operation is completed. Note: The SHA accelerator can be called directly, or used internally by the DSA module and the HMAC module. However, they can not share the hardware resources simultaneously. Therefore, the SHA module must not be called neither by the CPU nor by the DSA module when the HMAC module is in use. 21.6 HMAC Algorithm Details 21.6.1 Padding Bits The HMAC module uses SHA-256 as hash algorithm. If the input message is not a multiple of 512 bits, the user must apply a SHA-256 padding algorithm in software. The SHA-256 padding algorithm is the same as described in Section Padding the Message of FIPS PUB 180-4. In downstream mode, users do not need to input any message or apply padding. The HMAC module uses a default 32-byte pattern of 0x00 for re-enabling JTAG and a 32-byte pattern of 0xff for deriving the AES key for the DSA module. For the convenience of reading, here we will briefly describe the process of message padding. As shown in Figure 21.6-1, suppose the length of the unpadded message is m bits. Padding steps are as follows: 1. Append one bit of value “1” to the end of the unpadded message. 2. Append k bits of value “0”, where k is the smallest non-negative number which satisfies m + 1 + k≡448(mod512). 3. Append a 64-bit integer value as a binary block. This block consists of the length of the unpadded message as a big-endian binary integer value m. In upstream mode, if the length of the unpadded message is a multiple of 512 bits, users can configure hardware to apply SHA padding by writing 1 to HMAC_SET_MESSAGE_END_REG or do padding work themselves by writing 1 to HMAC_SET_MESSAGE_PAD_REG. If the length is not a multiple of 512 bits, SHA padding must be Espressif Systems 745 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 21 HMAC Accelerator (HMAC) Figure 21.6-1. HMAC SHA-256 Padding Diagram manually applied by the user. After the user prepared the padding data, they should complete the subsequent configuration according to the Section 21.5. 21.6.2 HMAC Algorithm Structure The structure of the implemented algorithm in the HMAC module is shown in Figure 21.6-2. This is the standard HMAC algorithm as described in RFC 2104. Figure 21.6-2. HMAC Structure Schematic Diagram In Figure 21.6-2: 1. ipad is a 512-bit message block composed of 64 bytes of 0x36. 2. opad is a 512-bit message block composed of 64 bytes of 0x5c. The HMAC module appends a 256-bit 0 sequence after the bit sequence of the 256-bit key K in order to get a 512-bit K 0 . Then, the HMAC module XORs K 0 with ipad to get the 512-bit S1. Afterwards, the HMAC module appends the input message (multiple of 512 bits) after the 512-bit S1, and exercises the SHA-256 algorithm to get the 256-bit H1. The HMAC module appends the 256-bit SHA-256 hash result H1 to the 512-bit S2 value, which is calculated using the XOR operation of K 0 and opad. A 768-bit sequence will be generated. Then, the HMAC module uses the SHA padding algorithm described in Section 21.6.1 to pad the 768-bit sequence to a 1024-bit sequence, and applies the SHA-256 algorithm to get the final hash result (256-bit). Espressif Systems 746 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 21 HMAC Accelerator (HMAC) 21.6.3 Register Summary The addresses in this section are relative to HMAC Accelerator base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Control/Status Registers HMAC_SET_START_REG HMAC start control register 0x0040 WS HMAC_SET_PARA_FINISH_REG HMAC configuration completion register 0x004C WS HMAC_SET_MESSAGE_ONE_REG HMAC message control register 0x0050 WS HMAC_SET_MESSAGE_ING_REG HMAC message continue register 0x0054 WS HMAC_SET_MESSAGE_END_REG HMAC message end register 0x0058 WS HMAC_SET_RESULT_FINISH_REG HMAC result reading finish register 0x005C WS HMAC_SET_INVALIDATE_JTAG_REG Invalidate JTAG result register 0x0060 WS HMAC_SET_INVALIDATE_DS_REG Invalidate digital signature result register 0x0064 WS HMAC_QUERY_ERROR_REG Stores matching results between keys gener- ated by users and corresponding purposes 0x0068 RO HMAC_QUERY_BUSY_REG Busy state of HMAC module 0x006C RO HMAC_SET_MESSAGE_PAD_REG Software padding register 0x00F0 WO HMAC_ONE_BLOCK_REG One block message register 0x00F4 WS Configuration Registers HMAC_SET_PARA_PURPOSE_REG HMAC parameter configuration register 0x0044 WO HMAC_SET_PARA_KEY_REG HMAC parameters configuration register 0x0048 WO HMAC_WR_JTAG_REG Re-enable JTAG register 1 0x00FC WO Configuration Register HMAC_SOFT_JTAG_CTRL_REG Jtag register 0. 0x00F8 WS Version Register HMAC_DATE_REG Version control register 0x01FC R/W Espressif Systems 747 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 21 HMAC Accelerator (HMAC) 21.6.4 Registers The addresses in this section are relative to HMAC Accelerator base address provided in Table 4.3-2 in Chapter 4 System and Memory. For how to program reserved fields, please refer to Section Programming Reserved Register Field. Register 21.1. HMAC_SET_START_REG (0x0040) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 HMAC_SET_START 0 0 Reset HMAC_SET_START Configures whether or not to enable HMAC. 0: Disable HMAC 1: Enable HMAC (WS) Register 21.2. HMAC_SET_PARA_FINISH_REG (0x004C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 HMAC_SET_PARA_END 0 0 Reset HMAC_SET_PARA_END Configures whether to finish HMAC configuration. 0: No effect 1: Finish configuration (WS) Register 21.3. HMAC_SET_MESSAGE_ONE_REG (0x0050) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 HMAC_SET_TEXT_ONE 0 0 Reset HMAC_SET_TEXT_ONE Calls SHA to calculate one message block. (WS) Espressif Systems 748 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 21 HMAC Accelerator (HMAC) Register 21.4. HMAC_SET_MESSAGE_ING_REG (0x0054) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 HMAC_SET_TEXT_ING 0 0 Reset HMAC_SET_TEXT_ING Configures whether or not there are unprocessed message blocks. 0: No unprocessed message block 1: There are still some message blocks to be processed. (WS) Register 21.5. HMAC_SET_MESSAGE_END_REG (0x0058) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 HMAC_SET_TEXT_END 0 0 Reset HMAC_SET_TEXT_END Configures whether to start hardware padding. 0: No effect 1: Start hardware padding (WS) Register 21.6. HMAC_SET_RESULT_FINISH_REG (0x005C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 HMAC_SET_RESULT_END 0 0 Reset HMAC_SET_RESULT_END Configures whether to exit upstream mode and clear calculation results. 0: Not exit 1: Exit upstream mode and clear calculation results. (WS) Espressif Systems 749 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 21 HMAC Accelerator (HMAC) Register 21.7. HMAC_SET_INVALIDATE_JTAG_REG (0x0060) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 HMAC_SET_INVALIDATE_JTAG 0 0 Reset HMAC_SET_INVALIDATE_JTAG Configures whether or not to clear calculation results when re- enabling JTAG in downstream mode. 0: Not clear 1: Clear calculation results (WS) Register 21.8. HMAC_SET_INVALIDATE_DS_REG (0x0064) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 HMAC_SET_INVALIDATE_DS 0 0 Reset HMAC_SET_INVALIDATE_DS Configures whether or not to clear calculation results of the DSA mod- ule in downstream mode. 0: Not clear 1: Clear calculation results (WS) Espressif Systems 750 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 21 HMAC Accelerator (HMAC) Register 21.9. HMAC_QUERY_ERROR_REG (0x0068) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 HMAC_QUREY_CHECK 0 0 Reset HMAC_QUREY_CHECK Represents whether or not an HMAC key matches the purpose. 0: Match 1: Error (RO) Register 21.10. HMAC_QUERY_BUSY_REG (0x006C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 HMAC_BUSY_STATE 0 0 Reset HMAC_BUSY_STATE Represents whether or not HMAC is in a busy state. Before configuring HMAC, please make sure HMAC is in an IDLE state. 0: Idle 1: HMAC is still working on the calculation (RO) Register 21.11. HMAC_SET_MESSAGE_PAD_REG (0x00F0) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 HMAC_SET_TEXT_PAD 0 0 Reset HMAC_SET_TEXT_PAD Configures whether or not the padding is applied by software. 0: Not applied by software 1: Applied by software (WO) Espressif Systems 751 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 21 HMAC Accelerator (HMAC) Register 21.12. HMAC_ONE_BLOCK_REG (0x00F4) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 HMAC_SET_ONE_BLOCK 0 0 Reset HMAC_SET_ONE_BLOCK Write 1 to indicate there is only one block which already contains padding bits and there is no need for padding. (WS) Register 21.13. HMAC_SET_PARA_PURPOSE_REG (0x0044) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 4 HMAC_PURPOSE_SET 0 3 0 Reset HMAC_PURPOSE_SET Configures the HMAC purpose, refer to the Table link. ” (WO) Register 21.14. HMAC_SET_PARA_KEY_REG (0x0048) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 HMAC_KEY_SET 0 2 0 Reset HMAC_KEY_SET Configures HMAC key. There are six eFuse keys with index 0 verb+ + 5 and one key from the key manager with index 7. Write the index of the selected key to this field. (WO) Espressif Systems 752 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 21 HMAC Accelerator (HMAC) Register 21.15. HMAC_WR_JTAG_REG (0x00FC) HMAC_WR_JTAG 0 31 0 Reset HMAC_WR_JTAG Writes the comparing input used for re-enabling JTAG. (WO) Register 21.16. HMAC_SOFT_JTAG_CTRL_REG (0x00F8) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 HMAC_SOFT_JTAG_CTRL 0 0 Reset HMAC_SOFT_JTAG_CTRL Configures whether or not to enable JTAG authentication mode. 0: Disable 1: Enable (WS) Register 21.17. HMAC_DATE_REG (0x01FC) (reserved) 0 0 31 30 HMAC_DATE 0x20230901 29 0 Reset HMAC_DATE HMAC date information/ HMAC version information. (R/W) Espressif Systems 753 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 22 RSA Accelerator (RSA) Chapter 22 RSA Accelerator (RSA) 22.1 Introduction The RSA accelerator provides hardware support for high-precision computation used in various RSA asymmetric cipher algorithms, significantly reducing their run time and reducing their software complexity. Compared with RSA algorithms implemented solely in software, this hardware accelerator can speed up RSA algorithms significantly. The RSA accelerator also supports operands of different lengths, which provides more flexibility during the computation. 22.2 Features The following functionality is supported: • Large-number modular exponentiation with two acceleration options • Large-number modular multiplication • Large-number multiplication • Operands of different lengths • Interrupt on completion of computation 22.3 Functional Description The RSA accelerator is activated by setting the PCR_RSA_CLK_EN bit and clearing the PCR_RSA_RST_EN bit in the PCR_RSA_CONF_REG register. Additionally, users also need to clear PCR_DS_RST_EN and PCR_ECDSA_RST_EN bits to reset Digital Signature Algorithm (DSA) and Elliptic Curve Digital Signature Algorithm (ECDSA). The RSA accelerator is only available after the RSA-related memories are initialized. The content of the RSA_QUERY_CLEAN_REG register is 0 during initialization and will become 1 after the initialization is done. Therefore, wait until RSA_QUERY_CLEAN_REG becomes 1 before using the RSA accelerator. The RSA_INT_ENA_REG register is used to control the interrupt triggered on completion of computation. Write 1 or 0 to this field to enable or disable the interrupt. By default, the interrupt function of the RSA accelerator is enabled. Notice: ESP32-C5’s Digital Signature Algorithm (DSA) module also calls the RSA accelerator when working. Therefore, users cannot access the RSA accelerator when the Digital Signature Algorithm (DSA) module is working. Espressif Systems 754 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 22 RSA Accelerator (RSA) 22.3.1 Large-Number Modular Exponentiation Large-number modular exponentiation performs Z = X Y mod M. The computation is based on Montgomery multiplication. Therefore, aside from the X, Y , and M arguments, two additional ones are needed — r and M ′ , which need to be calculated in advance by software. The RSA accelerator supports operands of length N = 32 × x, where x ∈ {1, 2, 3, . . . , 96}. The bit lengths of arguments Z, X, Y , M , and r can be arbitrary N , but all numbers in a calculation must be of the same length. The bit length of M ′ must be 32. To represent the numbers used as operands, let us define a base-b positional notation, as follows: b = 2 32 Using this notation, each number is represented by a sequence of base-b digits: n = N 32 Z = (Z n−1 Z n−2 · · · Z 0 ) b X = (X n−1 X n−2 · · · X 0 ) b Y = (Y n−1 Y n−2 · · · Y 0 ) b M = (M n−1 M n−2 · · · M 0 ) b r = (r n−1 r n−2 · · · r 0 ) b Each of the values in Z n−1 · · · Z 0 , X n−1 · · · X 0 , Y n−1 · · · Y 0 , M n−1 · · · M 0 , r n−1 · · · r 0 represents one base-b digit (a 32-bit word). Z n−1 , X n−1 , Y n−1 , M n−1 and r n−1 are the most significant bits of Z , X , Y , M , and r , while Z 0 , X 0 , Y 0 , M 0 and r 0 are the least significant bits. If we define R = b n , the additional argument r can be calculated as r = R 2 mod M. Also, argument M ′ can be calculated using the formula below: M ′ = −M −1 mod b where, M −1 is the modular multiplicative inverse of M, and it can be calculated with the extended binary GCD algorithm. Large-number modular exponentiation on the ESP32-C5 can be implemented as follows: 1. Write 1 or 0 to the RSA_INT_ENA field of the register RSA_INT_ENA_REG to enable or disable the interrupt function. 2. Configure relevant registers: (a) Write ( N 32 − 1) to the RSA_MODE_REG register. (b) Write M ′ to the RSA_M_PRIME_REG register. (c) Configure registers related to the acceleration options, which are described later in Section 22.3.4. 3. Write X i , Y i , M i and r i for i ∈ {0, 1, . . . , n − 1} to memory blocks RSA_X_MEM, RSA_Y_MEM, RSA_M_MEM and RSA_Z_MEM. The capacity of each memory block is 96 words. Each word of each Espressif Systems 755 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 22 RSA Accelerator (RSA) memory block can store one base-b digit. The memory blocks use the little endian format for storage, i.e., the least significant digit of each number is in the lowest address. Users need to write data to each memory block only according to the length of the number; data beyond this length is ignored. 4. Write 1 to the RSA_SET_START_MODEXP field of the register RSA_SET_START_MODEXP_REG to start computation. 5. Wait for the completion of computation, which happens when the content of RSA_QUERY_IDLE becomes 1 or the RSA interrupt occurs. 6. Read the result Z i for i ∈ {0, 1, . . . , n − 1} from RSA_Z_MEM. 7. Write 1 to RSA_CLEAR_INTERRUPT to clear the interrupt, if you have the interrupt enabled. After the computation, the RSA_MODE_REG register, memory blocks RSA_Y_MEM and RSA_M_MEM, as well as the RSA_M_PRIME_REG remain unchanged. However, X i in RSA_X_MEM and r i in RSA_Z_MEM computation are overwritten, and only these overwritten memory blocks need to be re-initialized before starting another computation. 22.3.2 Large-Number Modular Multiplication Large-number modular multiplication performs Z = X × Y mod M . This computation is based on Montgomery multiplication. Therefore, similar to the large-number modular exponentiation, two additional arguments are needed – r and M ′ , which need to be calculated in advance by software. The RSA accelerator supports large-number modular multiplication with operands of 96 different lengths. The computation can be executed as follows: 1. Write 1 or 0 to the RSA_INT_ENA_REG register to enable or disable the interrupt function. 2. Configure relevant registers: (a) Write ( N 32 − 1) to the RSA_MODE_REG register. (b) Write M ′ to the RSA_M_PRIME_REG register. 3. Write X i , Y i , M i , and r i for i ∈ {0, 1, . . . , n − 1} to memory blocks RSA_X_MEM, RSA_Y_MEM, RSA_M_MEM, and RSA_Z_MEM, respectively. The capacity of each memory block is 96 words. Each word of each memory block can store one base-b digit. The memory blocks use the little endian format for storage, i.e., the least significant digit of each number is in the lowest address. Users need to write data to each memory block only according to the length of the number; data beyond this length are ignored. 4. Write 1 to the RSA_SET_START_MODMULT field. 5. Wait for the completion of computation, which happens when the content of RSA_QUERY_IDLE becomes 1 or the RSA interrupt occurs. 6. Read the result Z i for i ∈ {0, 1, . . . , n − 1} from RSA_Z_MEM. 7. Write 1 to RSA_CLEAR_INTERRUPT to clear the interrupt, if you have the interrupt enabled. After the computation, the length of operands in RSA_MODE_REG, the X i in memory RSA_X_MEM, the Y i in memory RSA_Y_MEM, the M i in memory RSA_M_MEM, and the M ′ in memory RSA_M_PRIME_REG remain Espressif Systems 756 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 22 RSA Accelerator (RSA) unchanged. However, the r i in memory RSA_Z_MEM has already been overwritten, and only this overwritten memory block needs to be re-initialized before starting another computation. 22.3.3 Large-Number Multiplication Large-number multiplication performs Z = X × Y . The length of result Z is twice that of operand X and operand Y . Therefore, the RSA accelerator only supports large-number multiplication with operand length N = 32 × x, where x ∈ {1, 2, 3, . . . , 48}. The length ˆ N of result Z is 2 × N. The computation can be executed as follows: 1. Write 1 or 0 to the RSA_INT_ENA_REG register to enable or disable the interrupt function. 2. Write ( ˆ N 32 − 1), i.e., ( N 16 − 1) to the RSA_MODE_REG register. 3. Write X i and Y i for ∈ {0, 1, . . . , n − 1} to memory blocks RSA_X_MEM and RSA_Z_MEM. Each word of each memory block can store one base-b digit. The memory blocks use the little endian format for storage, i.e., the least significant digit of each number is in the lowest address. n is N 32 . Write X i for i ∈ {0, 1, . . . , n − 1} to the address of the i words of the RSA_X_MEM memory block. Note that Y i for i ∈ {0, 1, . . . , n − 1} will not be written to the address of the i words of the RSA_Z_MEM register, but the address of the n + i words, i.e., the base address of the RSA_Z_MEM memory plus the address offset 4 × (n + i). Users need to write data to each memory block only according to the length of the number; data beyond this length is ignored. 4. Write 1 to the RSA_SET_START_MULT register. 5. Wait for the completion of computation, which happens when the content of RSA_QUERY_IDLE becomes 1 or the RSA interrupt occurs. 6. Read the result Z i for i ∈ {0, 1, . . . , ˆn − 1} from the RSA_Z_MEM register. ˆn is 2 × n. 7. Write 1 to RSA_CLEAR_INTERRUPT to clear the interrupt, if you have the interrupt enabled. After the computation, the length of operands in RSA_MODE_REG and the X i in memory RSA_X_MEM remain unchanged. However, the Y i in memory RSA_Z_MEM has already been overwritten, and only this overwritten memory block needs to be re-initialized before starting another computation. 22.3.4 Options for Additional Acceleration The ESP32-C5 RSA accelerator also provides SEARCH and CONSTANT_TIME options that can be configured to further accelerate the large-number modular exponentiation. By default, both options are configured as no additional acceleration. Users can choose to use one or two of these options to further accelerate the computation. Note that, even when none of these two options is configured, using the hardware RSA accelerator is still much faster than implementing the RSA algorithm in software. To be more specific, when neither of these two options are configured for additional acceleration, the time required to calculate Z = X Y mod M is solely determined by the lengths of operands. When either or both of these two options are configured for additional acceleration, the time required is also correlated with the 0/1 distribution of Y . Espressif Systems 757 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 22 RSA Accelerator (RSA) To better illustrate how these two options work, first assume Y is represented in binaries as Y = ( e Y N−1 e Y N−2 · · · e Y t+1 e Y t e Y t−1 · · · e Y 0 ) 2 where, • N is the length of Y , • e Y t is 1, • e Y N−1 , e Y N−2 , …, e Y t+1 are all equal to 0, • and e Y t−1 , e Y t−2 , …, e Y 0 are either 0 or 1 but exactly m bits should be equal to 0 and t − m bits 1, i.e., the Hamming weight of e Y t−1 e Y t−2 , · · · , e Y 0 is t − m. When either of these two options is configured for additional acceleration: • SEARCH Option (Configuring RSA_SEARCH_ENABLE to 1 for additional acceleration) – The accelerator ignores the bit positions of e Y i , where i > α. Search position α is set by configuring the RSA_SEARCH_POS_REG register. Set α to a number smaller than N -1, which otherwise leads to the same result as if this option is not used for additional acceleration. The best acceleration performance can be achieved by setting α to t, in which case all the 0 bits in e Y N−1 , e Y N−2 , …, e Y t+1 are ignored during the calculation. Note that if you set α to be less than t, then the result of the modular exponentiation Z = X Y mod M will be incorrect. – Note that this option compromises the security because it ignores some bits, which essentially shortens the key length, thus should not be enabled for applications with high security requirement. • CONSTANT_TIME Option (Configuring RSA_CONSTANT_TIME_REG to 0 for additional acceleration) – The accelerator speeds up the calculation by simplifying the calculation concerning the 0 bits of Y . Therefore, the higher the proportion of bits 0 against bits 1, the better is the acceleration performance. – Note that this option also compromises the security because its time cost correlates with the 0/1 distribution of the key, which may be used in a Side Channel Attack (SCA), thus should not be enabled for applications with high security requirement. Below is an example to demonstrate the performance of the RSA accelerator under different combinations of SEARCH and CONSTANT_TIME configuration. In this example: • We perform Z = X Y mod M • N = 3072 • Y = 65537 • X and M are taken at random • When the SEARCH option is enabled, α, i.e., the position register RSA_SEARCH_POS_REG, is set to 16. Table 22.3-1 below demonstrates the time cost in clock cycles under different combinations of SEARCH and CONSTANT_TIME configuration when performing Z = X Y mod M as described above. Espressif Systems 758 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 22 RSA Accelerator (RSA) Table 22.3-1. Acceleration Performance SEARCH Option CONSTANT_TIME Option Time Cost (clock cycle) No acceleration No acceleration 174.7 × 10 6 Acceleration No acceleration 1.023 × 10 6 No acceleration Acceleration 0.546 × 10 6 Acceleration Acceleration 0.540 × 10 6 As shown in Table 22.3-1: • The time cost is the biggest when none of these two options is configured for additional acceleration. • The time cost is the smallest when both of these two options are configured for additional acceleration. • The time cost can be dramatically reduced when either or both option(s) are configured for additional acceleration. 22.4 Interrupts ESP32-C5’s RSA accelerator can generate the following interrupt signal that will be sent to the Interrupt Matrix. • RSA_INTR There is one internal interrupt source from the RSA accelerator that can generate the above interrupt signal. The interrupt source from the RSA accelerator is listed with its trigger condition and the resulting interrupt signal in Table 22.4-1. Table 22.4-1. RSA’s Internal Interrupt Source Internal Interrupt Source Trigger Condition Interrupt Signal RSA_CALC_DONE_INT Completion of an RSA calculation RSA_INTR Note: For definitions of interrupt , interrupt signal , interrupt source , and their correlations, please refer to Chapter 9 Interrupt Matrix > Section 9.2 Terminology. Espressif Systems 759 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 22 RSA Accelerator (RSA) 22.5 Memory Summary The addresses in this section are relative to the RSA accelerator base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Size (byte) Starting Address Ending Address Access RSA_M_MEM Represents M 384 0x0000 0x017F R/W RSA_Z_MEM Represents Z 384 0x0200 0x037F R/W RSA_Y_MEM Represents Y 384 0x0400 0x057F R/W RSA_X_MEM Represents X 384 0x0600 0x077F R/W 22.6 Register Summary The addresses in this section are relative to the RSA accelerator base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Control/Configuration Registers RSA_M_PRIME_REG Configures M ′ 0x0800 R/W RSA_MODE_REG Configures RSA length 0x0804 R/W RSA_SET_START_MODEXP_REG Starts modular exponentiation 0x080C WT RSA_SET_START_MODMULT_REG Starts modular multiplication 0x0810 WT RSA_SET_START_MULT_REG Starts multiplication 0x0814 WT RSA_QUERY_IDLE_REG Represents the RSA status 0x0818 RO RSA_CONSTANT_TIME_REG Configures the CONSTANT_TIME option 0x0820 R/W RSA_SEARCH_ENABLE_REG Configures the SEARCH option 0x0824 R/W RSA_SEARCH_POS_REG Configures the SEARCH position 0x0828 R/W Status Register RSA_QUERY_CLEAN_REG RSA initialization status 0x0808 RO Interrupt Registers RSA_INT_CLR_REG Clears RSA interrupt 0x081C WT RSA_INT_ENA_REG Enables the RSA interrupt 0x082C R/W Version Control Register RSA_DATE_REG Version control register 0x0830 R/W Espressif Systems 760 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 22 RSA Accelerator (RSA) 22.7 Registers The addresses in this section are relative to the RSA accelerator base address provided in Table 4.3-2 in Chapter 4 System and Memory. For how to program reserved fields, please refer to Section Programming Reserved Register Field. Register 22.1. RSA_M_PRIME_REG (0x0800) RSA_M_PRIME 0x000000 31 0 Reset RSA_M_PRIME Configures M ′ . (R/W) Register 22.2. RSA_MODE_REG (0x0804) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 7 RSA_MODE 0 6 0 Reset RSA_MODE Configures the RSA length. (R/W) Register 22.3. RSA_SET_START_MODEXP_REG (0x080C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 RSA_SET_START_MODEXP 0 0 Reset RSA_SET_START_MODEXP Configures whether or not to start the modular exponentiation. 0: No effect 1: Start (WT) Espressif Systems 761 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 22 RSA Accelerator (RSA) Register 22.4. RSA_SET_START_MODMULT_REG (0x0810) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 RSA_SET_START_MODMULT 0 0 Reset RSA_SET_START_MODMULT Configures whether or not to start the modular multiplication. 0: No effect 1: Start (WT) Register 22.5. RSA_SET_START_MULT_REG (0x0814) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 RSA_SET_START_MULT 0 0 Reset RSA_SET_START_MULT Configures whether or not to start the multiplication. 0: No effect 1: Start (WT) Register 22.6. RSA_QUERY_IDLE_REG (0x0818) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 RSA_QUERY_IDLE 0 0 Reset RSA_QUERY_IDLE Represents the RSA status. 0: Busy 1: Idle (RO) Espressif Systems 762 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 22 RSA Accelerator (RSA) Register 22.7. RSA_CONSTANT_TIME_REG (0x0820) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 RSA_CONSTANT_TIME 1 0 Reset RSA_CONSTANT_TIME Configures the CONSTANT_TIME option. 0: Acceleration 1: No acceleration (default) (R/W) Register 22.8. RSA_SEARCH_ENABLE_REG (0x0824) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 RSA_SEARCH_ENABLE 0 0 Reset RSA_SEARCH_ENABLE Configures the SEARCH option. 0: No acceleration (default) 1: Acceleration This option should be used together with RSA_SEARCH_POS_REG. (R/W) Register 22.9. RSA_SEARCH_POS_REG (0x0828) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 12 RSA_SEARCH_POS 0 11 0 Reset RSA_SEARCH_POS Configures the starting address to start search. This field should be used together with RSA_SEARCH_ENABLE_REG. The field is only valid when RSA_SEARCH_ENABLE is 1. (R/W) Espressif Systems 763 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 22 RSA Accelerator (RSA) Register 22.10. RSA_QUERY_CLEAN_REG (0x0808) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 RSA_QUERY_CLEAN 0 0 Reset RSA_QUERY_CLEAN Represents whether or not the RSA memory completes initialization. 0: Not complete 1: Completed (RO) Register 22.11. RSA_INT_CLR_REG (0x081C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 RSA_CLEAR_INTERRUPT 0 0 Reset RSA_CLEAR_INTERRUPT Write 1 to clear the RSA interrupt. (WT) Register 22.12. RSA_INT_ENA_REG (0x082C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 RSA_INT_ENA 0 0 Reset RSA_INT_ENA Write 1 to enable the RSA interrupt. (R/W) Espressif Systems 764 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 22 RSA Accelerator (RSA) Register 22.13. RSA_DATE_REG (0x0830) (reserved) 0 0 31 30 RSA_DATE 0x20200618 29 0 Reset RSA_DATE Version control register. (R/W) Espressif Systems 765 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 23 SHA Accelerator (SHA) Chapter 23 SHA Accelerator (SHA) 23.1 Introduction ESP32-C5 integrates an SHA accelerator, which is a hardware device that speeds up the SHA algorithm significantly, compared to a SHA algorithm implemented solely in software. The SHA accelerator integrated in ESP32-C5 has two working modes, which are Typical SHA and DMA-SHA. 23.2 Features The following functionality is supported: • The following hash algorithms introduced in FIPS PUB 180-4 Spec – SHA-1 – SHA-224 – SHA-256 • Two working modes – Typical SHA – DMA-SHA • Interleaved function when working in Typical SHA working mode • Interrupt function when working in DMA-SHA working mode 23.3 Working Modes The SHA accelerator integrated in ESP32-C5 has two working modes. • Typical SHA Working Mode: all the data is written and read via CPU directly. • DMA-SHA Working Mode: all the data is read via DMA. That is, users can configure the DMA controller to read all the data needed for hash operation, thus releasing CPU for completing other tasks. The SHA accelerator is activated by setting the PCR_SHA_CLK_EN bit and clearing the PCR_SHA_RST_EN bit in the PCR_SHA_CONF_REG register. Additionally, users also need to clear PCR_DS_RST_EN, PCR_HMAC_RST_EN, and PCR_ECDSA_RST_EN bits to reset Digital Signature Algorithm (DSA), HMAC Accelerator (HMAC), and Elliptic Curve Digital Signature Algorithm (ECDSA). Users can start the SHA accelerator with different working modes by configuring registers SHA_START_REG and SHA_DMA_START_REG. For details, please see Table 23.3-1. Espressif Systems 766 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 23 SHA Accelerator (SHA) Table 23.3-1. SHA Accelerator Working Mode Working Mode Configuration Method Typical SHA Set SHA_START_REG to 1 DMA-SHA Set SHA_DMA_START_REG to 1 Users can choose hash algorithms by configuring the SHA_MODE_REG register. For details, please see Table 23.3-2. Table 23.3-2. SHA Hash Algorithm Selection Hash Algorithm SHA_MODE_REG Configuration SHA-1 0 SHA-224 1 SHA-256 2 Notice: ESP32-C5’s Digital Signature Algorithm (DSA) and HMAC Accelerator (HMAC) modules also call the SHA accelerator when working. Therefore, users cannot access the SHA accelerator when these modules are working. 23.4 Function Description The SHA accelerator generates the message digest via two steps: Preprocessing and Hash operation. 23.4.1 Preprocessing Preprocessing consists of three steps: padding the message, parsing the message into message blocks and setting the initial hash value. 23.4.1.1 Padding the Message The SHA accelerator can only process message blocks of 512 bits. Thus, all the messages should be padded to a multiple of 512 bits before the hash operation. Suppose that the length of the message M is m bits. Then M shall be padded as introduced below: 1. First, append the bit “1” to the end of the message; 2. Second, append k bits of zeros, where k is the smallest, non-negative solution to the equation m + 1 + k ≡ 448 mod 512; 3. Last, append the 64-bit block of value equal to the number m expressed using a binary representation. For more details, please refer to FIPS PUB 180-4 Spec > Section “Padding the Message”. 23.4.1.2 Parsing the Message The message and its padding must be parsed into N 512-bit blocks, M (1) , M (2) , …, M (N) . Since the 512 bits of the input block may be expressed as sixteen 32-bit words, the first 32 bits of message block i are denoted Espressif Systems 767 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 23 SHA Accelerator (SHA) M (i) 0 , the next 32 bits are M (i) 1 , and so on up to M (i) 15 . During the task, all the message blocks are written into the SHA_M_n_REG: M (i) 0 is stored in SHA_M_0_REG, M (i) 1 stored in SHA_M_1_REG, …, and M (i) 15 stored in SHA_M_15_REG. Note: For more information about “message block”, please refer to FIPS PUB 180-4 Spec > Section “Glossary of Terms and Acronyms”. 23.4.1.3 Setting the Initial Hash Value Before hash operation begins for any secure hash algorithms, the initial Hash value H (0) must be set based on different algorithms. However, the SHA accelerator uses the initial Hash values (constant C) stored in the hardware for hash tasks. 23.4.2 Hash Operation After the preprocessing, the ESP32-C5 SHA accelerator starts to hash a message M and generates message digest of different lengths, depending on different hash algorithms. As described above, the ESP32-C5 SHA accelerator supports two working modes, which are Typical SHA and DMA-SHA. The operation process for the SHA accelerator under two working modes is described in the following subsections. 23.4.2.1 Typical SHA Mode Process Usually, the SHA accelerator will process all blocks of a message and produce a message digest before starting the computation of the next message digest. However, ESP32-C5 SHA also supports optional “interleaved” message digest calculation in Typical SHA mode, which means before SHA completes all blocks of the current message, users are given a chance to insert new computation of another message digest upon the completion of each individual block of the current message. Specifically, users can read out the message digest from registers SHA_H_n_REG after completing part of a message digest calculation, and use the SHA accelerator for a different calculation. After the different calculation completes, users can restore the previous message digest to registers SHA_H_n_REG, and resume the accelerator with the previously paused calculation. Typical SHA Process 1. Select a hash algorithm. • Configure the SHA_MODE_REG register based on Table 23.3-2. 2. Process the current message block. • Write the message block in registers SHA_M_n_REG. 3. Start the SHA accelerator 1 . • If this is the first time to execute this step, set the SHA_START_REG register to 1 to start the SHA accelerator. In this case, the accelerator uses the initial hash value stored in hardware for a given algorithm configured in Step 1 to start the calculation; Espressif Systems 768 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 23 SHA Accelerator (SHA) • If this is not the first time to execute this step 2 , set the SHA_CONTINUE_REG register to 1 to start the SHA accelerator. In this case, the accelerator uses the hash value stored in the SHA_H_n_REG register to start the calculation. 4. Check the progress of the current message block. • Poll register SHA_BUSY_REG until the content of this register becomes 0, indicating the accelerator has completed the calculation for the current message block and now is in the “idle” status 3 . 5. Decide if you have more message blocks to process: • If yes, please go back to Step 2. • Otherwise, please continue. 6. Obtain the message digest. • Read the message digest from registers SHA_H_n_REG. Note: 1. In this step, the software can also write the next message block (to be processed) in registers SHA_M_n_REG, if any, while the hardware starts SHA calculation, to save time. 2. You are resuming the SHA accelerator with the previously paused calculation. 3. Here you can decide if you want to insert other calculations. If yes, please go to the process for interleaved calculations for details. As mentioned above, ESP32-C5 SHA accelerator supports “interleaving” calculation under the Typical SHA working mode. The process to implement interleaved calculation is described below. 1. Prepare to hand the SHA accelerator over for an interleaved calculation by storing the following data of the previous calculation. • The selected hash algorithm configured in the SHA_MODE_REG register. • The message digest stored in registers SHA_H_n_REG. 2. Perform the interleaved calculation. For the detailed process of the interleaved calculation, please refer to Typical SHA process or DMA-SHA process, depending on the working mode of your interleaved calculation. 3. Prepare to hand the SHA accelerator back to the previously paused calculation by restoring the following data of the previous calculation. • Write the previously stored hash algorithm back to register SHA_MODE_REG. • Write the previously stored message digest back to registers SHA_H_n_REG. 4. Write the next message block from the previous paused calculation in registers SHA_M_n_REG, and set the SHA_CONTINUE_REG register to 1 to restart the SHA accelerator with the previously paused calculation. 23.4.2.2 DMA-SHA Mode Process ESP32-C5 SHA accelerator does not support “interleaving” message digest calculation at the level of individual message blocks when using DMA, which means you cannot insert new calculation before a complete DMA-SHA process (of one or more message blocks) completes. In this case, users who need interleaved operation are Espressif Systems 769 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 23 SHA Accelerator (SHA) recommended to divide the message blocks and perform several DMA-SHA calculations, instead of trying to compute all the messages in one go. Single DMA-SHA calculation supports up to 63 data blocks. In contrast to the Typical SHA working mode, when the SHA accelerator is working under the DMA-SHA mode, all data read are completed via DMA. Therefore, users are required to configure the DMA controller following the description in Chapter 3 GDMA Controller (GDMA). DMA-SHA process 1. Select a hash algorithm. • Select a hash algorithm by configuring the SHA_MODE_REG register. For details, please refer to Table 23.3-2. 2. Configure the SHA_INT_ENA_REG register to enable or disable interrupt (Set 1 to enable). 3. Configure the number of message blocks. • Write the number of message blocks M to the SHA_DMA_BLOCK_NUM_REG register. 4. Start the DMA-SHA calculation. • If the current DMA-SHA calculation follows a previous calculation, firstly write the message digest from the previous calculation to registers SHA_H_n_REG, then write 1 to register SHA_DMA_CONTINUE_REG to start SHA accelerator; • Otherwise, write 1 to register SHA_DMA_START_REG to start the accelerator. 5. Wait till the completion of the DMA-SHA calculation, which happens when: • The content of SHA_BUSY_REG register becomes 0, or • An SHA interrupt occurs. In this case, please clear interrupt by writing 1 to the SHA_INT_CLEAR_REG register. 6. Obtain the message digest: • Read the message digest from registers SHA_H_n_REG. 23.4.3 Message Digest After the hash task completes, the SHA accelerator writes the message digest from the task to registers SHA_H_n_REG(n: 07). The lengths of the generated message digest are different depending on different hash algorithms. For details, see Table 23.4-1 below: Espressif Systems 770 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 23 SHA Accelerator (SHA) Table 23.4-1. The Storage and Length of Message Digest from Different Algorithms Hash Algorithm Length of Message Digest (in bits) Storage 1 SHA-1 160 SHA_H_0_REGSHA_H_4_REG SHA-224 224 SHA_H_0_REGSHA_H_6_REG SHA-256 256 SHA_H_0_REGSHA_H_7_REG 1 The message digest is stored in registers from most significant bits to the least significant bits, with the first word stored in register SHA_H_0_REG and the second word stored in register SHA_H_1_REG... For details, please see subsection 23.4.1.2. 23.4.4 Interrupt ESP32-C5’s SHA accelerator can generate the following interrupt signal(s) that will be sent to the Interrupt Matrix. • SHA_INTR There is an internal interrupt source from SHA that can generate the above interrupt signal(s). The interrupt source from SHA is listed with their trigger conditions and the resulted interrupt signal(s) in Table 23.4-2. Table 23.4-2. SHA’s Internal Interrupt Sources Internal Interrupt Source Trigger Condition Interrupt Signal SHA_CALC_DONE_INT Completion of an message digest calculation in DMA-SHA mode SHA_INTR Note: • For definitions of interrupt, interrupt signal, interrupt source, and their correlations, please refer to Chapter 9 Interrupt Matrix > Section 9.2 Terminology. • Different from the standard interrupt register group, the interrupt register group of SHA only contains the INT_ENA (SHA_INT_ENA_REG) and INT_CLR (SHA_INT_CLEAR_REG) fields, and does not support users to read the INT_RAW and INT_ST fields. Espressif Systems 771 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 23 SHA Accelerator (SHA) 23.5 Register Summary The addresses in this section are relative to the SHA accelerator base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Control/Configuration Registers SHA_MODE_REG Configures SHA algorithm 0x0000 R/W SHA_CONTINUE_REG Continues SHA operation (only effective in Typical SHA mode) 0x0014 WO SHA_DMA_START_REG Starts the SHA accelerator for DMA-SHA operation 0x001C WO SHA_START_REG Starts the SHA accelerator for Typical SHA operation 0x0010 WO SHA_DMA_CONTINUE_REG Continues SHA operation (only effective in DMA-SHA mode) 0x0020 WO SHA_DMA_BLOCK_NUM_REG Block number register (only effective in DMA-SHA mode) 0x000C R/W Status Registers SHA_BUSY_REG Represents if SHA Accelerator is busy or not 0x0018 RO Interrupt Registers SHA_INT_CLEAR_REG DMA-SHA interrupt clear register 0x0024 WO SHA_INT_ENA_REG DMA-SHA interrupt enable register 0x0028 R/W Data Registers SHA_H_0_REG Hash value 0x0040 R/W SHA_H_1_REG Hash value 0x0044 R/W SHA_H_2_REG Hash value 0x0048 R/W SHA_H_3_REG Hash value 0x004C R/W SHA_H_4_REG Hash value 0x0050 R/W SHA_H_5_REG Hash value 0x0054 R/W SHA_H_6_REG Hash value 0x0058 R/W SHA_H_7_REG Hash value 0x005C R/W SHA_M_0_REG Message 0x0080 R/W SHA_M_1_REG Message 0x0084 R/W SHA_M_2_REG Message 0x0088 R/W SHA_M_3_REG Message 0x008C R/W SHA_M_4_REG Message 0x0090 R/W SHA_M_5_REG Message 0x0094 R/W SHA_M_6_REG Message 0x0098 R/W SHA_M_7_REG Message 0x009C R/W SHA_M_8_REG Message 0x00A0 R/W SHA_M_9_REG Message 0x00A4 R/W SHA_M_10_REG Message 0x00A8 R/W SHA_M_11_REG Message 0x00AC R/W SHA_M_12_REG Message 0x00B0 R/W SHA_M_13_REG Message 0x00B4 R/W SHA_M_14_REG Message 0x00B8 R/W SHA_M_15_REG Message 0x00BC R/W Espressif Systems 772 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 23 SHA Accelerator (SHA) Name Description Address Access Version Register SHA_DATE_REG Version control register 0x002C R/W 23.6 Registers The addresses in this section are relative to the SHA accelerator base address provided in Table 4.3-2 in Chapter 4 System and Memory. Register 23.1. SHA_START_REG (0x0010) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 SHA_START 0 0 Reset SHA_START Write 1 to start Typical SHA calculation. (WO) Register 23.2. SHA_CONTINUE_REG (0x0014) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 SHA_CONTINUE 0 0 Reset SHA_CONTINUE Write 1 to continue Typical SHA calculation. (WO) Register 23.3. SHA_BUSY_REG (0x0018) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 SHA_BUSY_STATE 0 0 Reset SHA_BUSY_STATE Represents the states of SHA accelerator. 0: idle 1: busy (RO) Espressif Systems 773 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 23 SHA Accelerator (SHA) Register 23.4. SHA_DMA_START_REG (0x001C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 SHA_DMA_START 0 0 Reset SHA_DMA_START Write 1 to start DMA-SHA calculation. (WO) Register 23.5. SHA_DMA_CONTINUE_REG (0x0020) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 SHA_DMA_CONTINUE 0 0 Reset SHA_DMA_CONTINUE Write 1 to continue DMA-SHA calculation. (WO) Register 23.6. SHA_INT_CLEAR_REG (0x0024) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 SHA_CLEAR_INTERRUPT 0 0 Reset SHA_CLEAR_INTERRUPT Write 1 to clear DMA-SHA interrupt. (WO) Register 23.7. SHA_INT_ENA_REG (0x0028) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 SHA_INTERRUPT_ENA 0 0 Reset SHA_INTERRUPT_ENA Write 1 to enable DMA-SHA interrupt. (R/W) Espressif Systems 774 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 23 SHA Accelerator (SHA) Register 23.8. SHA_DATE_REG (0x002C) (reserved) 0 0 31 30 SHA_DATE 0x20201229 29 0 Reset SHA_DATE Version control register. (R/W) Register 23.9. SHA_MODE_REG (0x0000) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 SHA_MODE 0x0 2 0 Reset SHA_MODE Configures the SHA algorithm. 0: SHA-1 1: SHA-224 2: SHA-256 3 7: invalid value (R/W) Register 23.10. SHA_DMA_BLOCK_NUM_REG (0x000C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 6 SHA_DMA_BLOCK_NUM 0x0 5 0 Reset SHA_DMA_BLOCK_NUM Configures the DMA-SHA block number. (R/W) Register 23.11. SHA_H_n_REG (n: 0-7) (0x0040+4*n) SHA_H_n 0x000000 31 0 Reset SHA_H_n Represents the nth 32-bit piece of the Hash value. (R/W) Espressif Systems 775 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 23 SHA Accelerator (SHA) Register 23.12. SHA_M_n_REG (n: 0-15) (0x0080+4*n) SHA_M_n 0x000000 31 0 Reset SHA_M_n Represents the nth 32-bit piece of the message. (R/W) Espressif Systems 776 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 24 Digital Signature Algorithm (DSA) Chapter 24 Digital Signature Algorithm (DSA) 24.1 Overview The Digital Signature Algorithm (DSA) is used to verify the authenticity and integrity of a message using a cryptographic algorithm. This can be used to validate a device’s identity to a server or to check the integrity of a message. ESP32-C5 includes a Digital Signature Algorithm (DSA) module providing hardware acceleration of messages’ signatures based on RSA. HMAC is used as the key derivation function (KDF) to output the DSA_KEY key using a key stored in eFuse or deployed by the Key Manager as the input key. Subsequently, the DSA module uses DSA_KEY to decrypt the pre-encrypted parameters and calculate the signature. The whole process happens in hardware so that neither the decryption key for the RSA parameters nor the input key for the HMAC key derivation function can be seen by users while calculating the signature. 24.2 Features • RSA digital signatures with key length up to 3072 bits • Encrypted private key data, only decryptable by the DSA module • SHA-256 digest to protect private key data against tampering by an attacker 24.3 Functional Description 24.3.1 Overview The DSA peripheral calculates RSA signatures as Z = X Y mod M, where Z is the signature, X is the input message, and Y and M are the RSA private key parameters. Private key parameters are stored in flash as ciphertext. They are decrypted using a key (DSA_KEY ) which can: • Only be calculated by the DSA peripheral via the HMAC peripheral. The required inputs (HM AC_KEY ) to generate the key (DSA_KEY ) are only stored in eFuse and can only be accessed by the HMAC peripheral. That is to say, the DSA peripheral hardware can decrypt the private key, and the private key in plaintext is never accessed by the software. For more detailed information about eFuse and HMAC peripherals, please refer to Chapter 5 eFuse Controller (eFuse) and Chapter 21 HMAC Accelerator (HMAC). • Deploy from Key Manager module. The DSA_KEY must be deployed by the Key Manager in a secured way. Espressif Systems 777 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 24 Digital Signature Algorithm (DSA) The input message X will be sent directly to the DSA peripheral by the software each time a signature is needed. After the RSA signature operation, the signature Z is read back by the software. For better understanding, we define some symbols and functions here, which are only applicable to this chapter: • 1 s : A bit string consisting of s bits with the value of “1”. • [x] s : A bit string of s bits, in which s is an integer multiple of 8 bits. If x is a number (x < 2 s ), it is represented in little-endian byte order in the bit string. x may be a variable such as [Y ] 4096 or a hexadecimal constant such as [0x0C] 8 . If necessary, the value [x] t can be right-padded with (s − t) number of zeros to reach s bits in length, and finally get [x] s . For example, [0x05] 8 = 00000101, [0x05] 16 = 0000010100000000, [0x0005] 16 = 0000000000000101, [0x13] 8 = 00010011, [0x13] 16 = 0001001100000000, [0x0013] 16 = 0000000000010011. • ||: A bit string concatenation operator for joining multiple-bit strings into a longer bit string. 24.3.2 Private Key Operands Private key operands Y (private key exponent) and M (key modulus) are generated by the user. They have a particular RSA key length (up to 3072 bits). Two additional private key operands are needed: r and M ′ . These two operands are derived from Y and M . Operands Y , M , r, and M ′ are encrypted by the user along with an authentication digest and stored as a single ciphertext C. C is input to the DSA peripheral in this encrypted format, decrypted by the hardware, and then used for RSA signature calculation. A detailed description of how to generate C is provided in Section 24.3.3. The DSA peripheral supports RSA signature calculation Z = X Y mod M, in which the length of operands should be N = 32 × x where x ∈ {1, 2, 3, . . . , 96}. The bit lengths of arguments Z, X, Y , M , and r should be an arbitrary value in N, and all of them in a calculation must be of the same length, while the bit length of M ′ should always be 32. For more detailed information about RSA calculation, please refer to Section 22.3.1 Large-Number Modular Exponentiation in Chapter 22 RSA Accelerator (RSA). 24.3.3 Software Prerequisites If you want to use the DSA module, the software needs a series of preparations, as shown in Figure 24.3-1. The left side lists preparations required by the software before the hardware starts the RSA signature calculation, while the right side lists the hardware workflow during the entire calculation procedure. Espressif Systems 778 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 24 Digital Signature Algorithm (DSA) Figure 24.3-1. Software Preparations and Hardware Working Process Note: 1. The software preparation (left side in Figure 24.3-1) is a one-time operation before any signature is calculated, while the hardware calculation (right side in Figure 24.3-1) repeats for every signature calculation. 2. Software preparation requires configuring the clock reset. For more information, please refer to Chapter 7 Reset and Clock. Users need to follow the steps shown in the left part of Figure 24.3-1 to calculate C. Detailed instructions are as follows: • Step 1: Prepare operands Y and M whose lengths should meet the requirements in Section 24.3.2. Define [L] 32 = N 32 − 1 (i.e., for RSA 3072, [L] 32 == [0x60-1] 32 ). Prepare [DSA_KEY ] 256 : – when calculated by the DSA peripheral via the HMAC peripheral: DSA_KEY = HMAC-SHA256 ([HM AC_KEY ] 256 , 1 256 ). – when from Key Manager module: just use the deployed DSA_KEY Generate a random [IV ] 128 which should meet the requirements of the AES-CBC block encryption algorithm. For more information on AES, please refer to Chapter 19 AES Accelerator (AES). • Step 2 : Calculate r and M ′ based on M . • Step 3: Extend Y , M , and r in order to get [Y ] 3072 , [M] 3072 , and [r] 3072 , respectively. This step is only required for Y , M , and r whose length are less than 3072 bits, since their largest length are 3072 bits. • Step 4: Calculate MD authentication code using the SHA-256: [MD] 256 = SHA256 ([Y ] 3072 ||[M] 3072 ||[r] 3072 ||[M ′ ] 32 ||[L] 32 ||[IV ] 128 ) • Step 5: Build [P ] 9600 = ( [Y ] 3072 ||[M] 3072 ||[r] 3072 ||[Box] 384 ), where [Box ] 384 = ( [MD] 256 ||[M ′ ] 32 ||[L] 32 ||[β] 64 ) and [β] 64 is a PKCS#7 padding value, i.e., a [0x0808080808080808] 64 string composed of 8 bytes (0x80). The purpose of [β] 64 is to make the bit length of P a multiple of 128. Espressif Systems 779 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 24 Digital Signature Algorithm (DSA) • Step 6: Calculate C = [C] 9600 = AES-CBC-ENC ([P ] 9600 , [DSA_KEY ] 256 , [IV ] 128 ), where C is the ciphertext with a length of 1200 bytes. C can also be calculated as C = [C] 9600 = ([ b Y ] 3072 ||[ c M] 3072 ||[ b r] 3072 ||[ d Box] 384 ), where [ b Y ] 3072 , [ c M] 3072 , [ b r] 3072 , [ d Box] 384 are the four sub-parameters of C, and correspond to the ciphertext of [Y ] 3072 , [M] 3072 , [r] 3072 , [Box] 384 respectively. 24.3.4 DSA Operation at the Hardware Level The hardware operation is triggered each time a digital signature needs to be calculated. The inputs are the pre-generated private key ciphertext C, a unique message X, and IV . The DSA operation at the hardware level can be divided into the following three stages: 1. Decryption: Step 7 and 8 in Figure 24.3-1 The decryption process is the inverse of Step 6 in Figure 24.3-1. The DSA module will call the AES accelerator to decrypt C in CBC block mode and get the resulting plaintext. The decryption process can be represented by P = AES-CBC-DEC ( C , DSA _ KEY , IV ), where IV (i.e., [ IV ] 128 ) is defined by the user. [DSA_KEY ] 256 is • when calculated by the DSA peripheral via the HMAC peripheral: provided by the HMAC module, derived from HM AC_KEY stored in eFuse, which is not readable by users. • when from Key Manager module: DSA_KEY deployed by Key Manager, which is not readable by users. With P , the DSA module can derive [Y ] 3072 , [M] 3072 , [r] 3072 , [M ′ ] 32 , [L] 32 , MD authentication code, and the padding value [β] 64 . This process is the inverse of Step 5. 2. Check: Step 9 and 10 in Figure 24.3-1 The DSA module will perform two checks: MD check and padding check. The padding check is not shown in Figure 24.3-1, as it happens at the same time as the MD check. • MD check: The DSA module calls SHA-256 to calculate the hash value [CALC_M D] 256 ([CALC_MD] 256 is calculated the same way and with same parameters as [MD] 256 , see step 4). Then, [CALC_MD] 256 is compared against the MD authentication code [M D] 256 from step 4. Only when the two match does the MD check pass. • Padding check: The DSA module checks if [β] 64 complies with the aforementioned PKCS#7 format. Only when [β] 64 complies with the format does the padding check pass. The DSA module will only perform subsequent operations if MD check passes. If the padding check fails, a warning is generated, but it does not affect the subsequent operations. 3. Calculation: Step 11 and 12 in Figure 24.3-1 The DSA module treats X (input by the user) and Y , M , r (decrypted in step 8) as big numbers. With M ′ , all operands to perform X Y mod M are in place. The operand length is defined by L only. The DSA module will calculate the signed result Z by calling RSA to perform Z = X Y mod M. 24.3.5 DSA Operation at the Software Level The software steps below should be followed each time a digital signature needs to be calculated. The inputs are the pre-generated private key ciphertext C, a unique message X, and IV . These software steps trigger the Espressif Systems 780 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 24 Digital Signature Algorithm (DSA) hardware steps described in Section 24.3.4. We assume that the software has called the HMAC peripheral and the HMAC peripheral has calculated DSA_KEY based on HMAC_KEY . 1. Prerequisites: Prepare operands C, X, IV according to Section 24.3.3. 2. Activate the DSA peripheral: Write 1 to DS_SET_START_REG. 3. Check if DSA_KEY is ready depending on from where the DSA_KEY comes from: • Write 1 to DS_KEY_SOURCE_REG to select the DSA_KEY deployed by the Key Manager. Verify that DSA K EY has been successfully deployed by checking the register field KEYMNG_KEY_DS_VLD. When its value is 1, it indicates that DSA K EY has been successfully deployed and is ready. • Write 0 to DS_KEY_SOURCE_REG to select the DSA_KEY from HMAC. Poll DS_QUERY_BUSY_REG until the software reads 0. If the software does not read 0 in DS_QUERY_BUSY_REG after approximately 1 ms, it indicates a problem with HMAC initialization. In such a case, the software can read register DS_QUERY_KEY_WRONG_REG to get more information: • If the software reads 0 in DS_QUERY_KEY_WRONG_REG, it indicates that the HMAC peripheral has not been called. • If the software reads any value from 1 to 15 in DS_QUERY_KEY_WRONG_REG, it indicates that HMAC was called, but the DSA module did not successfully get the DSA_KEY value from the HMAC peripheral. This may indicate that the HMAC operation has been interrupted due to a software concurrency problem. 4. Write IV to memory block DS_IV_MEM: Write the content in the IV block to the memmory block DS_IV_MEM, which is 16 bytes. For more information on the IV block, please refer to Chapter 19 AES Accelerator (AES). 5. Write X to memory block DS_X_MEM: Write X i (i ∈ {0, 1, . . . , n − 1}), where n = N 32 , to memory block DS_X_MEM whose capacity is 96 words. Each word can store one base-b digit. The memory block uses the little endian format for storage, i.e., the least significant digit of the operand is in the lowest address. Words in DS_X_MEM block after the configured length of X (N bits, as described in Section 24.3.2), are ignored. 6. Write C to corresponding memory blocks: Write the four sub-parameters of C to corresponding memory blocks: • Write b Y i (i ∈ {0, 1, . . . , 95}) to DS_Y_MEM. • Write c M i (i ∈ {0, 1, . . . , 95}) to DS_M_MEM. • Write b r i (i ∈ {0, 1, . . . , 95}) to DS_RB_MEM. • write d Box i (i ∈ {0, 1, . . . , 11}) to DS_BOX_MEM. The capacity of DS_Y_MEM, DS_M_MEM, and DS_RB_MEM is 96 words, whereas the capacity of DS_BOX_MEM is only 12 words. Each word can store one base-b digit. The memory blocks use the little endian format for storage, i.e., the least significant digit of the operand is in the lowest address. 7. Start DSA operation: Write 1 to register DS_SET_CONTINUE_REG. Espressif Systems 781 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 24 Digital Signature Algorithm (DSA) 8. Wait for the operation to be completed: Poll register DS_QUERY_BUSY_REG until the software reads 0. 9. Query check result: Read register DS_QUERY_CHECK_REG and conduct subsequent operations as illustrated below based on the return value: • If the value is 0, it indicates that both the padding check and MD check pass. Users can continue to get the signed result Z. • If the value is 1, it indicates that the padding check passes but MD check fails. The signed result Z is invalid. The operation will resume directly from Step 11. • If the value is 2, it indicates that the padding check fails but the MD check passes. Users can continue to get the signed result Z. But please note that the data does not comply with the aforementioned PKCS#7 padding format, which may not be what you want. • If the value is 3, it indicates that both the padding check and MD check fail. In this case, some fatal errors have occurred and the signed result Z is invalid. The operation will resume directly from Step 11. 10. Read the signed result: Read the signed result Z i (i ∈ {0, 1, . . . , n − 1}), where n = N 32 , from memory block DS_Z_MEM. The memory block stores Z in little-endian byte order. 11. Exit the operation: Write 1 to DS_SET_FINISH_REG, and then poll DS_QUERY_BUSY_REG until the software reads 0. After the operation, all the input/output registers and memory blocks are cleared. Espressif Systems 782 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 24 Digital Signature Algorithm (DSA) 24.4 Memory Summary The addresses in this section are relative to the Digital Signature Algorithm base address provided in Table 4.3-2 in Chapter 4 System and Memory. Name Description Size (byte) Starting Address Ending Address Access DS_Y_MEM Memory block Y 512 0x0000 0x01FF R/W DS_M_MEM Memory block M 512 0x0200 0x03FF R/W DS_RB_MEM Memory block r 512 0x0400 0x05FF R/W DS_BOX_MEM Memory block Box 48 0x0600 0x062F R/W DS_IV_MEM Memory block IV 16 0x0630 0x063F R/W DS_X_MEM Memory block X 512 0x0800 0x09FF R/W DS_Z_MEM Memory block Box Z 512 0x0A00 0x0BFF R/W Espressif Systems 783 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 24 Digital Signature Algorithm (DSA) 24.5 Register Summary The addresses in this section are relative to Digital Signature Algorithm base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Control/Status registers DS_SET_START_REG Activates the DSA module 0x0E00 WT DS_SET_CONTINUE_REG Continues DSA operation 0x0E04 WT DS_SET_FINISH_REG Ends DSA operation 0x0E08 WT DS_QUERY_BUSY_REG Status of the DSA module 0x0E0C RO DS_QUERY_KEY_WRONG_REG Checks the reason why DS_KEY is not ready 0x0E10 RO DS_QUERY_CHECK_REG Queries DSA check result 0x0E14 RO Configuration registers DS_KEY_SOURCE_REG Configures DSA key source 0x0E18 R/W version control register DS_DATE_REG Version control register 0x0E20 R/W Espressif Systems 784 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 24 Digital Signature Algorithm (DSA) 24.6 Registers The addresses in this section are relative to Digital Signature Algorithm base address provided in Table 4.3-2 in Chapter 4 System and Memory. Register 24.1. DS_SET_START_REG (0x0E00) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 DS_SET_START 0 0 Reset DS_SET_START Configures whether or not to activate the DSA peripheral. 0: Invalid 1: Activate the DSA peripheral (WT) Register 24.2. DS_SET_CONTINUE_REG (0x0E04) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 DS_SET_CONTINUE 0 0 Reset DS_SET_CONTINUE Configures whether or not to continue the DSA operation. 0: No effect 1: Continue the DSA operation (WT) Register 24.3. DS_SET_FINISH_REG (0x0E08) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 DS_SET_FINISH 0 0 Reset DS_SET_FINISH Configures whether or not to end the DSA operation. 0: No effect 1: End the DSA operation (WT) Espressif Systems 785 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 24 Digital Signature Algorithm (DSA) Register 24.4. DS_QUERY_BUSY_REG (0x0E0C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 DS_QUERY_BUSY 0 0 Reset DS_QUERY_BUSY Represents whether or not the DSA module is idle. 0: The DSA module is idle 1: The DSA module is busy (RO) Register 24.5. DS_QUERY_KEY_WRONG_REG (0x0E10) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 4 DS_QUERY_KEY_WRONG 0 3 0 Reset DS_QUERY_KEY_WRONG Represents the specific problem with HMAC initialization. 0: HMAC is not called 1-15: HMAC was activated, but the DSA peripheral did not successfully receive the DSA_KEY from the HMAC peripheral. Larger than 15: invalid (RO) Espressif Systems 786 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 24 Digital Signature Algorithm (DSA) Register 24.6. DS_QUERY_CHECK_REG (0x0E14) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 2 DS_PADDING_BAD 0 1 DS_MD_ERROR 0 0 Reset DS_MD_ERROR Represents whether or not the MD check passes. 0: The MD check passes 1: The MD check fails (RO) DS_PADDING_BAD Represents whether or not the padding check passes. 0: The padding check passes 1: The padding check fails (RO) Register 24.7. DS_KEY_SOURCE_REG (0x0E18) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 DS_KEY_SOURCE 0 0 Reset DS_KEY_SOURCE Represents the source of the DSA_KEY . 0: HMAC 1: Key Manager (R/W) Register 24.8. DS_DATE_REG (0x0E20) (reserved) 0 0 31 30 DS_DATE 0x20230901 29 0 Reset DS_DATE Version control register (R/W) Espressif Systems 787 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 25 Elliptic Curve Digital Signature Algorithm (ECDSA) Chapter 25 Elliptic Curve Digital Signature Algorithm (ECDSA) 25.1 Introduction In cryptography, the Elliptic Curve Digital Signature Algorithm (ECDSA) offers a variant of the Digital Signature Algorithm (DSA) which uses elliptic-curve cryptography. ESP32-C5’s ECDSA accelerator provides a secure and efficient environment for computing ECDSA signatures. It offers fast computations while ensuring the confidentiality of the signing process to prevent information leakage. This makes it a valuable tool for applications that require high-speed cryptographic operations with strong security guarantees. By using the ECDSA accelerator, users can be confident that their data is protected without sacrificing performance. 25.2 Features ESP32-C5’s ECDSA accelerator supports: • Digital signature generation and verification • Three different elliptic curves, namely, P-192, P-256, and P-384 defined in FIPS 186-5 • Multiple hash algorithms for message hash in the ECDSA operation, including SHA-224, SHA-256, SHA-384, SHA-512, SHA-512-224, and SHA-512-256, defined in FIPS PUB 180-4 Spec • Dynamic access permission in different operation statuses to ensure information security 25.3 ECDSA Basics 25.3.1 Domain Parameters ECDSA uses parameters that define the elliptic curve over a finite field, as well as the generator point and the order of the base point. These parameters are usually referred to as domain parameters, and they are required for key generation, signature generation, and signature verification. The domain parameters used in ECDSA consist of the followings: • The elliptic curve domain parameters, which include: – The prime modulus p, which specifies the size of the finite field over which the elliptic curve is defined. – The base point G on the curve, which can be used to generate public keys. – The order n of the base point, which is the number of points on the curve that can be generated by repeatedly adding G to itself. Espressif Systems 788 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 25 Elliptic Curve Digital Signature Algorithm (ECDSA) • The parameters for the hash function, which include: – The hash algorithm used to generate a fixed-length hash value from the message being signed. – The length of the hash value, which determines the size of the signature. Together, these parameters define the ECDSA domain. 25.3.2 Key Generation The process of key generation in ECDSA is described below: 1. Select an elliptic curve domain by defining: • the prime modulus p • the coefficients a and b • the base point G and its order n 2. Generate a private key: • A private key d is a randomly chosen integer between 1 and n-1. It is essential to use a secure Random Number Generator (RNG) to ensure that the private key is truly random and cannot be predicted or reproduced. • The private key is used for signature generation. This key must be kept secret and secure. • Once a private key is chosen, it should be burned into the eFuse in ESP32-C5. (Please refer to Chapter 5 eFuse Controller (eFuse)). 3. Compute the public key: • The public key Q is calculated as Q = dG. 4. Export the public key: • The public key Q is typically represented as a pair of coordinates (Qx, Qy) that can be shared with others. 25.3.3 Signature Generation The ECDSA signature generation process is described below: 1. Select a message m to be signed. 2. Calculate the hash of the message e: e is equal to HASH(m), where HASH is a cryptographic hash function, such as SHA-256. 3. Compute the digest of the message hash z: Let z be the L n leftmost bits of e, where L n is the bit length of the base point order n. 4. Select a random number k, which is chosen between 1 and n-1, where n is the order of the base point on the elliptic curve. 5. Compute the signature: The signature is calculated as follows: (a) Compute the point (x, y) = kG Espressif Systems 789 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 25 Elliptic Curve Digital Signature Algorithm (ECDSA) (b) Calculate r = x mod n. If r is equal to zero, return to the previous step and select a new random value of k. (c) Calculate s = k −1 * (z + d ∗ r) mod n. If s is equal to zero, return to step 4 and select a new random value of k. (d) The signature is the pair (r, s). 6. Send the message m and signature (r, s) to the recipient. 25.3.4 Signature Verification The recipient can then use the public key associated with the private key used for signature generation to verify the signature. The verification process involves checking that the signature was generated using the correct private key and that the signature is valid for the given message. The ECDSA signature verification process is described below: 1. Obtain public key Q and receive the message m and signature (r, s). 2. Calculate the hash of the message e: e is equal to HASH(m), where HASH is a cryptographic hash function, such as SHA-256. 3. Compute the digest of the message z: Let z be the L n leftmost bits of e, where L n is the bit length of the base point order n. 4. Verify the signature: The signature is verified as follows: (a) Verify that r and s are integers between 1 and n-1, where n is the order of the base point on the elliptic curve. If either r or s is outside of this range, the signature is invalid. (b) Calculate u 1 = z ∗ s −1 mod n and u 2 = r ∗ s −1 mod n. (c) Calculate the point (x 1 , y 1 ) = u 1 ∗ G + u 2 ∗ Q, where G is the base point on the elliptic curve, and Q is the public key associated with the private key used for signature generation. (d) Verify that r = x 1 mod n. If r is not equal to x 1 mod n, the signature is invalid. 5. Accept or reject the signature: If the signature is valid, the recipient can be confident that the message was not tampered with and that it came from the expected sender, thus can accept the message as authentic. Otherwise, the recipient rejects the message as invalid. 25.4 Functional Description This section describes the details of ESP32-C5’s ECDSA accelerator. 25.4.1 ECDSA Working Modes The ECDSA accelerator integrated in the ESP32-C5 has three working modes, which are Signature Generation, Signature Verification and Public Key Export modes. Users can select the working mode for the ECDSA accelerator by configuring ECDSA_WORK_MODE according to Table 25.4-1 below. Espressif Systems 790 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 25 Elliptic Curve Digital Signature Algorithm (ECDSA) Table 25.4-1. ECDSA Working Mode ECDSA_WORK_MODE Working Mode 0 Signature Verification 1 Signature Generation 2 Public Key Export Users can select the elliptic curves used by configuring ECDSA_ECC_CURVE according to Table 25.4-2. Table 25.4-2. ECDSA Elliptic Curves Selection ECDSA_ECC_CURVE Elliptic Curve 0 P-192 1 P-256 2 P-384 Users can select the SHA algorithms for message hash by configuring ECDSA_SHA_MODE according to Table 25.4-3. Table 25.4-3. ECDSA SHA Algorithm ECDSA_SHA_MODE SHA Algorithm 1 SHA-224 2 SHA-256 3 SHA-384 4 SHA-512 5 SHA-512-224 6 SHA-512-256 Others Invalid Additionally, users can check the working status of the ECDSA accelerator by inquiring the ECDSA_STATE_REG register and comparing the return value against the Table 25.4-4 below. Table 25.4-4. ECDSA Working Status ECDSA_STATE_REG Status Description 0 IDLE Idle or completed operation. Corresponding to IDLE stage. 1 LOAD Waiting for users to load information into ECDSA. Corresponding to LOAD stage. 2 GAIN Waiting for users to gain information from ECDSA. Corresponding to GAIN stage. 3 BUSY In the middle of a hardware operation. Corresponding to PREP, PROC, and POST stage. Espressif Systems 791 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 25 Elliptic Curve Digital Signature Algorithm (ECDSA) 25.4.2 Data and Data Block ESP32-C5’s ECDSA accelerator can operate on data of 192, 256, 384, or 512 bits. For example, the data (D[255 : 0]) can be divided into 32-bit data blocks. Take 256-bit long data as an example, D[n][31 : 0](n = 0, 1, · · · , 7). Data blocks with the smaller serial number correspond to the lower binary bits. To be specific: D[255 : 0] = D[7][31 : 0], D[6][31 : 0], D[5][31 : 0], D[4][31 : 0] , D[3][31 : 0], D[2][31 : 0], D[1][31 : 0], D[0][31 : 0] 25.4.2.1 Writing Data Writing data means writing data to an ECDSA memory block and using this data as the input to the ECDSA algorithm. To be specific, writing data to an ECDSA memory block means writing D[n][31 : 0] to the “starting address of this ECDSA memory block + 4 × n”. For a 256-bit long data: • write D[0] to “starting address” • write D[1] to “starting address + 4” • · · · • write D[7] to “starting address + 28” Note: When storing data, write only the data block of the required length. Do not append a 0 to the most significant bit. For example, for 192-bit data, store only the 192 bits without appending 0. 25.4.2.2 Reading Data Reading data means reading data from the starting address of an ECDSA memory block and using this data as the output from the ECDSA algorithm. To be specific, reading data from an ECDSA memory block means reading D[n][31 : 0] from the “starting address of this ECDSA memory block + 4 × n”. For a 256-bit long data: • read D[0] from “starting address” • read D[1] from “starting address + 4” • · · · • read D[7] from “starting address + 28” Note: When reading data, only the data block of the required length needs to be read. For example, to read 192-bit data, simply read the lower 192 bits (i.e., 6 data blocks). 25.4.2.3 Padding the Message The SHA accelerator can only process message blocks of 512 bits. Thus, all the messages should be padded to a multiple of 512 bits before the hash operation. Suppose that the length of the message M is L M bits. Then M shall be padded as introduced below: Espressif Systems 792 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 25 Elliptic Curve Digital Signature Algorithm (ECDSA) 1. First, append the bit “1” to the end of the message; 2. Second, append L A bits of zeros, where L A is the smallest, non-negative solution to the equation L M + 1 + L A ≡ 448 mod 512; 3. Last, append the 64-bit block of value equal to the number L M expressed using a binary representation. For more details, please refer to FIPS PUB 180-4 Spec > Section “Padding the Message”. 25.4.2.4 Parsing the Message The message and its padding must be parsed into N 512-bit message blocks: M (1) , M (2) , …, M (N) . Note: 1. For more details about “parsing the message”, please refer to FIPS PUB 180-4 Spec > Section “Parsing the Mes- sage”. 2. For more information on “message block”, please refer to FIPS PUB 180-4 Spec > Section “Glossary of Terms and Acronyms”. 25.4.3 Security Features To ensure the security of the ECDSA operation process, the ECDSA accelerator implements a variety of security functions. 25.4.3.1 High Anti-Attack Performance ESP32-C5’s ECDSA accelerator leverages ECC’s enhanced anti-attack performance (refer to Section 20.4.3 Enhancing Anti-Attack Performance) every time it performs an operation. This means that each time a signature is generated and verified, ECDSA consumes: • the same amount of time; • the same amount of power. This provides ESP32-C5’s ECDSA accelerator strong anti-attack performance. 25.4.3.2 Dynamic Access Permission ESP32-C5’s ECDSA accelerator has implemented a dynamic access permission mechanism to prevent any possibility of key theft by tampering with the configuration or accessing the data during the operation. By implementing this dynamic access permission mechanism, the accesses for ECDSA registers are designed to vary in different statuses. For example, ECDSA_CONF_REG is only available for reading and writing when the accelerator is in the IDLE status. In this way, the configuration information is protected from reading or writing when the accelerator is in other statuses, such as LOAD, GAIN, and BUSY. For details about all ECDSA working statuses, please refer to Table 25.4-4. For detailed information on the dynamic access permission of each ECDSA register, please refer to Section Register Summary. Espressif Systems 793 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 25 Elliptic Curve Digital Signature Algorithm (ECDSA) 25.4.3.3 Hardware Occupation During the ECDSA operation, the following hardware modules will be occupied by ESP32-C5’s ECDSA accelerator: • SHA Accelerator • ECC Accelerator Among them, the SHA accelerator will be released when ECDSA_SHA_RELEASE_INT is triggered, while the ECC accelerator will be occupied during the whole ECDSA operation. Note: Hardware occupation is a mechanism to protect multiplexed modules and storage space. When a module is hardware occupied, the user will fail to: • read or write data to the module’s registers or memories. • disable the module clock. • reset the module. After hardware occupation is finished, the occupied module will be automatically reset. In addition, when the user performs a software reset to the master module, all the occupied modules will be reset at the same time. 25.5 Programming Procedures 25.5.1 ECDSA Process The overall ECDSA process consists of the following six stages. Espressif Systems 794 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 25 Elliptic Curve Digital Signature Algorithm (ECDSA) IDLE Yes No POST GAIN PREP LOAD PROC Signature Verification? Figure 25.5-1. ECDSA Process The detailed programming procedures of each stage are described in the following sections. 25.5.1.1 IDLE Stage In the IDLE stage: 1. Configure the static parameters including eFuse bits: (a) ECDSA_KEY: The value of private key d in ECDSA. To correctly configure the key value in eFuse, users need to write the key value in KEYn (n = 0-5), and set the corresponding EFUSE_KEY_PURPOSE_n as ECDSA_KEY. Please refer to Chapter 5 eFuse Controller (eFuse) for more detailed configuration steps. 2. Configure ECDSA_CONF_REG, including the following fields: (a) ECDSA_WORK_MODE: Select the working mode of the ECDSA accelerator. (b) ECDSA_ECC_CURVE: Select the elliptic curve of the ECDSA accelerator. (c) ECDSA_SOFTWARE_SET_Z: Configure whether to use direct input z. (d) ECDSA_DETERMINISTIC_K: Configure whether to use deterministic k. 3. Configure the register field ECDSA_START to enter the PREP stage. Note: For more details about Deterministic ECDSA, please refer to RFC6979. Espressif Systems 795 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 25 Elliptic Curve Digital Signature Algorithm (ECDSA) 25.5.1.2 PREP Stage In the PREP stage, ECDSA_STATE_REG is BUSY, and the ECDSA accelerator performs preparation. Wait till the PREP stage to end by polling ECDSA_BUSY until it is not BUSY. Then the ECDSA accelerator will automatically enter the LOAD stage. 25.5.1.3 LOAD Stage In the LOAD stage: 1. Provide input z into the ECDSA accelerator using one of the following options: • Direct input z: write z to ECDSA_MEM_Z. • ECDSA SHA interface: generate z from the message. For details, please refer to Section 25.5.1.7. 2. According to the selected ECDSA_WORK_MODE, configure as follows: • Signature Verification: (a) write signature (r, s) to ECDSA_MEM_R and ECDSA_MEM_S. (b) write public key (Qx, Qy) to ECDSA_MEM_Qx and ECDSA_MEM_Qy. • Signature Generation: (a) no other configuration is required. • Public Key Export: (a) no other configuration is required. 3. Write 1 to ECDSA_LOAD_DONE, indicating that the configuration is done. Then the accelerator will automatically enter the PROC stage. 25.5.1.4 PROC Stage In the PROC stage, ECDSA_STATE_REG is BUSY, and the ECDSA accelerator performs ECDSA operation based on the selected working mode. Wait till the PROC stage to end by polling ECDSA_BUSY until it is not BUSY. Then the ECDSA accelerator will automatically enter the either the GAIN stage or the POST stage depending on the selected working mode: • Signature generation: GAIN stage • Signature verification: POST stage 25.5.1.5 GAIN Stage When the Signature Generation mode or the Public Key Export mode is selected, the ECDSA accelerator enters the GAIN stage after PROC stage: 1. Read data from the ECDSA memory: • read signature (r, s) from ECDSA_MEM_R and ECDSA_MEM_S only in the Signature Generation mode. Espressif Systems 796 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 25 Elliptic Curve Digital Signature Algorithm (ECDSA) • read public key (Qx, Qy) from ECDSA_MEM_Qx and ECDSA_MEM_Qy both in the Signature Generation mode and the Public Key Export mode. 2. Write 1 to ECDSA_GET_DONE, indicating that the GAIN stage is done. Then the accelerator will automatically enter the POST stage. 25.5.1.6 POST Stage In the POST stage, ECDSA_STATE_REG is BUSY, and the ECDSA accelerator performs some wrap-up work of ECDSA operation. Wait till the POST stage to end by polling ECDSA_BUSY until it is not BUSY. Then the ECDSA accelerator will automatically return to the IDLE stage. 25.5.1.7 ECDSA SHA Interface ESP32-C5’s ECDSA accelerator can automatically execute hash operation and generates z based on a direct input message. For message hash, ECDSA accelerator supports SHA algorithms SHA-224 (only valid when P-192 is selected as the elliptic curve) and SHA-256. To use the ECDSA SHA interface, complete the following steps: 1. Pad the message by following the steps described in Section 25.4.2.3. 2. Parse the message and its padding into message blocks. See details in Section 25.4.2.4. 3. Process the current message block. • Write the current message block into ECDSA_MEM_M. 4. Start the ECDSA SHA interface 1 . • If this is the first time to execute this step, write 1 to ECDSA_SHA_START to start the ECDSA SHA interface; • If this is not the first time to execute this step 2 , write 1 to ECDSA_SHA_CONTINUE to continue the operation. 5. Check the progress of the current message block processing by polling. • Poll register ECDSA_SHA_BUSY until it’s IDLE, indicating that the interface has completed the operation for the current message block. 6. Process the next message block: • If there is message block to process, go back to Step 3. • If there is no more message blocks, exit. Note: 1. In this step, the software can also write the next message block to be processed, if any, in register ECDSA_MEM_M, while the interface starts SHA operation, to save time. 2. You are resuming the ECDSA SHA interface with the previously paused operation. Espressif Systems 797 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 25 Elliptic Curve Digital Signature Algorithm (ECDSA) 25.5.2 Clock ECDSA uses two types of clocks: • clk_ecdsa: function clock for ECDSA to operate • clk_apb_ecdsa: bus clock used to configure ECDSA registers Figure 25.5-2. clk_ecdsa Diagram As shown in Figure 25.5-2 clk_ecdsa Diagram, the secure function source clock clk_sec_ori can be sourced from: • XTAL_CLK • RC_FAST_CLK • PLL_F160M_CLK ECDSA’s function clock clk_ecdsa is configured by the clock gating register PCR_ECDSA_CLK_EN. When this register is set to 1, the clock gate is enabled, and clk_ecdsa is activated. Figure 25.5-3. clk_apb_ecdsa Diagram As shown in Figure 25.5-3 clk_apb_ecdsa Diagram, ECDSA’s configuration clock clk_apb_ecdsa can be sourced from SYSTEM_APB_CLK. ECDSA’s configuration clock clk_apb_ecdsa is controlled by the clock gating register PCR_ECDSA_CLK_EN. When this register is set to 1, the clock gate is enabled, and clk_apb_ecdsa is activated. For more information about clocks, see Section 7 Reset and Clock. Espressif Systems 798 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 25 Elliptic Curve Digital Signature Algorithm (ECDSA) 25.5.3 Reset The ECDSA module supports full reset. Write 1 and then 0 to PCR_ECDSA_RST_EN to reset the entire ECDSA module. 25.6 Interrupts ESP32-C5’s ECDSA accelerator can generate the interrupt signal ECDSA_INTR and send it to Interrupt Matrix. The ECDSA accelerator has four interrupt sources that can generate the ECDSA_INTR interrupt signal as follows. Each interrupt source can be configured by a common set of registers that are described in Section Interrupt Configuration Registers. • ECDSA_PREP_DONE_INT: triggered on the completion of the PREP stage. This interrupt source is configured by the following registers: – ECDSA_PREP_DONE_INT_RAW: stores the raw interrupt status of ECDSA_PREP_DONE_INT. – ECDSA_PREP_DONE_INT_ST: indicates the status of the ECDSA_PREP_DONE_INT interrupt. This field is generated by enabling/disabling the ECDSA_PREP_DONE_INT_RAW field. – ECDSA_PREP_DONE_INT_ENA: enables/disables the ECDSA_PREP_DONE_INT interrupt. – ECDSA_PREP_DONE_INT_CLR: set this bit to clear the ECDSA_PREP_DONE_INT interrupt status. By setting this bit to 1, fields ECDSA_PREP_DONE_INT_RAW and ECDSA_PREP_DONE_INT_ST will be cleared. • ECDSA_PROC_DONE_INT: triggered on the completion of the PROC stage. This interrupt source is configured by the following registers: – ECDSA_PROC_DONE_INT_RAW: stores the raw interrupt status of ECDSA_PROC_DONE_INT. – ECDSA_PROC_DONE_INT_ST: indicates the status of the ECDSA_PROC_DONE_INT interrupt. This field is generated by enabling/disabling the ECDSA_PROC_DONE_INT_RAW field. – ECDSA_PROC_DONE_INT_ENA: enables/disables the ECDSA_PROC_DONE_INT interrupt. – ECDSA_PROC_DONE_INT_CLR: set this bit to clear the ECDSA_PROC_DONE_INT interrupt status. By setting this bit to 1, fields ECDSA_PROC_DONE_INT_RAW and ECDSA_PROC_DONE_INT_ST will be cleared. • ECDSA_POST_DONE_INT: triggered on the completion of the POST stage. This interrupt source is configured by the following registers: – ECDSA_POST_DONE_INT_RAW: stores the raw interrupt status of ECDSA_POST_DONE_INT. – ECDSA_POST_DONE_INT_ST: indicates the status of the ECDSA_POST_DONE_INT interrupt. This field is generated by enabling/disabling the ECDSA_POST_DONE_INT_RAW field. – ECDSA_POST_DONE_INT_ENA: enables/disables the ECDSA_POST_DONE_INT interrupt. – ECDSA_POST_DONE_INT_CLR: set this bit to clear the ECDSA_POST_DONE_INT interrupt status. By setting this bit to 1, fields ECDSA_POST_DONE_INT_RAW and ECDSA_POST_DONE_INT_ST will be cleared. Espressif Systems 799 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 25 Elliptic Curve Digital Signature Algorithm (ECDSA) • ECDSA_SHA_RELEASE_INT: triggered when SHA is released.This interrupt source is configured by the following registers: – ECDSA_SHA_RELEASE_INT_RAW: stores the raw interrupt status of ECDSA_SHA_RELEASE_INT. – ECDSA_SHA_RELEASE_INT_ST: indicates the status of the ECDSA_SHA_RELEASE_INT interrupt. This field is generated by enabling/disabling the ECDSA_SHA_RELEASE_INT_RAW field via ECDSA_SHA_RELEASE_INT_ENA. – ECDSA_SHA_RELEASE_INT_ENA: enables/disables the ECDSA_SHA_RELEASE_INT interrupt. – ECDSA_SHA_RELEASE_INT_CLR: set this bit to clear the ECDSA_SHA_RELEASE_INT interrupt status. By setting this bit to 1, fields ECDSA_SHA_RELEASE_INT_RAW and ECDSA_SHA_RELEASE_INT_ST will be cleared. Note: For definitions of interrupt, interrupt signal, interrupt source, and their correlations, please refer to Chapter 9 Interrupt Matrix > Section 9.2 Terminology. Espressif Systems 800 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 25 Elliptic Curve Digital Signature Algorithm (ECDSA) 25.7 Memory Blocks ECDSA’s memory blocks store input data and output data of the ECDSA operation. Table 25.7-1. ECDSA Memory Blocks Memory Size (byte) Starting Address * Ending Address * Access ECDSA_MEM_M 128 0x280 0x2FF R/W ECDSA_MEM_R 48 0x3E0 0x40F R/W ECDSA_MEM_S 48 0x410 0x43F R/W ECDSA_MEM_Z 48 0x440 0x46F R/W ECDSA_MEM_Qx 48 0x470 0x49F R/W ECDSA_MEM_Qy 48 0x4A0 0x4CF R/W * Address offset related to the ECDSA accelerator base address is provided in Table 4.3- 2 in Chapter 4 System and Memory. Espressif Systems 801 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 25 Elliptic Curve Digital Signature Algorithm (ECDSA) 25.8 Register Summary The addresses in this section are relative to the ECDSA base address provided in Table 4.3-2 in Chapter 4 System and Memory. To enhance security, ECDSA registers have different read and write permissions in different operating statuses. The following is the abbreviation and corresponding relationship of each state: • PI: IDLE status, corresponding to IDLE stage. • PL: LOAD status, corresponding to LOAD stage. • PG: GAIN status, corresponding to GAIN stage. • PB: BUSY status, corresponding to PREP, PROC, and POST stage. Other abbreviations given in Column Access are explained in Section Access Types for Registers. Access Name Description Address PI PL PG PB Data Memory See Table 25.7-1. Configuration Registers ECDSA_CONF_REG ECDSA configuration register 0x0004 R/W N/A ECDSA_START_REG ECDSA start register 0x001C WT N/A Clock and Reset Register ECDSA_CLK_REG ECDSA clock gate register 0x0008 R/W N/A Interrupt Registers ECDSA_INT_RAW_REG ECDSA interrupt raw register 0x000C RO/WTC/SS ECDSA_INT_ST_REG ECDSA interrupt status register 0x0010 RO ECDSA_INT_ENA_REG ECDSA interrupt enable register 0x0014 R/W ECDSA_INT_CLR_REG ECDSA interrupt clear register 0x0018 WT Status Registers ECDSA_STATE_REG ECDSA status register 0x0020 RO Result Register ECDSA_RESULT_REG ECDSA result register 0x0024 RO/SS N/A SHA Registers ECDSA_SHA_MODE_REG ECDSA SHA-control register (Hash algorithm) 0x0200 N/A R/W N/A ECDSA_SHA_START_REG ECDSA SHA-control register (operation) 0x0210 N/A WT N/A ECDSA_SHA_CONTINUE_REG ECDSA SHA-control register (operation) 0x0214 N/A WT N/A ECDSA_SHA_BUSY_REG ECDSA SHA-control status register 0x0218 N/A RO N/A Version Register ECDSA_DATE_REG Version control register 0x00FC R/W N/A Espressif Systems 802 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 25 Elliptic Curve Digital Signature Algorithm (ECDSA) 25.9 Registers The addresses in this section are relative to the ECDSA base address provided in Table 4.3-2 in Chapter 4 System and Memory. For how to program reserved fields, please refer to Section Programming Reserved Register Field. Register 25.1. ECDSA_CONF_REG (0x0004) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 7 ECDSA_DETERMINISTIC_K 0 6 ECDSA_SOFTWARE_SET_Z 0 5 (reserved) 0 4 ECDSA_ECC_CURVE 0 3 2 ECDSA_WORK_MODE 0 1 0 Reset ECDSA_WORK_MODE Configures the working mode of ECDSA accelerator. 0: Signature Verification Mode 1: Signature Generation Mode 2: Public Key Export Mode 3: Invalid (R/W) ECDSA_ECC_CURVE Configures the elliptic curve used. 0: P-192 1: P-256 2: P-384 3: Invalid (R/W) ECDSA_SOFTWARE_SET_Z Configures how the parameter z is set. 0: Generated from SHA result 1: Written by software (R/W) ECDSA_DETERMINISTIC_K Configures how the parameter k is set. 0: Automatically generated by TRNG 1: Generated by the deterministic derivation algorithm (R/W) Espressif Systems 803 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 25 Elliptic Curve Digital Signature Algorithm (ECDSA) Register 25.2. ECDSA_START_REG (0x001C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 ECDSA_GET_DONE 0 2 ECDSA_LOAD_DONE 0 1 ECDSA_START 0 0 Reset ECDSA_START Configures whether to start the ECDSA operation. This bit will be self-cleared after configuration. 0: No effect 1: Start the ECDSA operation (WT) ECDSA_LOAD_DONE Write 1 to generate a signal indicating the ECDSA accelerator’s LOAD opera- tion is done. This bit will be self-cleared after configuration. (WT) ECDSA_GET_DONE Write 1 to generate a signal indicating the ECDSA accelerator’s GAIN operation is done. This bit will be self-cleared after configuration. (WT) Register 25.3. ECDSA_CLK_REG (0x0008) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 ECDSA_CLK_GATE_FORCE_ON 0 0 Reset ECDSA_CLK_GATE_FORCE_ON Configures whether to force on ECDSA memory clock gate. 0: No effect 1: Force on (R/W) Espressif Systems 804 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 25 Elliptic Curve Digital Signature Algorithm (ECDSA) Register 25.4. ECDSA_INT_RAW_REG (0x000C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 4 ECDSA_SHA_RELEASE_INT_RAW 0 3 ECDSA_POST_DONE_INT_RAW 0 2 ECDSA_PROC_DONE_INT_RAW 0 1 ECDSA_PREP_DONE_INT_RAW 0 0 Reset ECDSA_PREP_DONE_INT_RAW The raw interrupt status of the ECDSA_PREP_DONE_INT inter- rupt. (R/SS/WTC) ECDSA_PROC_DONE_INT_RAW The raw interrupt status of the ECDSA_PROC_DONE_INT inter- rupt. (R/SS/WTC) ECDSA_POST_DONE_INT_RAW The raw interrupt status of the ECDSA_POST_DONE_INT inter- rupt. (R/SS/WTC) ECDSA_SHA_RELEASE_INT_RAW The raw interrupt status of the ECDSA_SHA_RELEASE_INT in- terrupt. (R/SS/WTC) Register 25.5. ECDSA_INT_ST_REG (0x0010) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 4 ECDSA_SHA_RELEASE_INT_ST 0 3 ECDSA_POST_DONE_INT_ST 0 2 ECDSA_PROC_DONE_INT_ST 0 1 ECDSA_PREP_DONE_INT_ST 0 0 Reset ECDSA_PREP_DONE_INT_ST The masked interrupt status of the ECDSA_PREP_DONE_INT inter- rupt. (RO) ECDSA_PROC_DONE_INT_ST The masked interrupt status of the ECDSA_PROC_DONE_INT inter- rupt. (RO) ECDSA_POST_DONE_INT_ST The masked interrupt status of the ECDSA_POST_DONE_INT inter- rupt. (RO) ECDSA_SHA_RELEASE_INT_ST The masked interrupt status of the ECDSA_SHA_RELEASE_INT interrupt. (RO) Espressif Systems 805 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 25 Elliptic Curve Digital Signature Algorithm (ECDSA) Register 25.6. ECDSA_INT_ENA_REG (0x0014) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 4 ECDSA_SHA_RELEASE_INT_ENA 0 3 ECDSA_POST_DONE_INT_ENA 0 2 ECDSA_PROC_DONE_INT_ENA 0 1 ECDSA_PREP_DONE_INT_ENA 0 0 Reset ECDSA_PREP_DONE_INT_ENA Write 1 to enable the ECDSA_PREP_DONE_INT interrupt. (R/W) ECDSA_PROC_DONE_INT_ENA Write 1 to enable the ECDSA_PROC_DONE_INT interrupt. (R/W) ECDSA_POST_DONE_INT_ENA Write 1 to enable the ECDSA_POST_DONE_INT interrupt. (R/W) ECDSA_SHA_RELEASE_INT_ENA Write 1 to enable the ECDSA_SHA_RELEASE_INT interrupt. (R/W) Register 25.7. ECDSA_INT_CLR_REG (0x0018) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 4 ECDSA_SHA_RELEASE_INT_CLR 0 3 ECDSA_POST_DONE_INT_CLR 0 2 ECDSA_PROC_DONE_INT_CLR 0 1 ECDSA_PREP_DONE_INT_CLR 0 0 Reset ECDSA_PREP_DONE_INT_CLR Write 1 to clear the ECDSA_PREP_DONE_INT interrupt. (WT) ECDSA_PROC_DONE_INT_CLR Write 1 to clear the ECDSA_PROC_DONE_INT interrupt. (WT) ECDSA_POST_DONE_INT_CLR Write 1 to clear the ECDSA_POST_DONE_INT interrupt. (WT) ECDSA_SHA_RELEASE_INT_CLR Write 1 to clear the ECDSA_SHA_RELEASE_INT interrupt. (WT) Espressif Systems 806 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 25 Elliptic Curve Digital Signature Algorithm (ECDSA) Register 25.8. ECDSA_STATE_REG (0x0020) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 2 ECDSA_BUSY 0 1 0 Reset ECDSA_BUSY Represents the working status of the ECDSA accelerator. 0: IDLE 1: LOAD 2: GAIN 3: BUSY (RO) Register 25.9. ECDSA_RESULT_REG (0x0024) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 ECDSA_OPERATION_RESULT 0 0 Reset ECDSA_OPERATION_RESULT Indicates if the ECDSA operation is successful. 0: Not successful 1: Successful Only valid when the ECDSA operation is done. (RO/SS) Espressif Systems 807 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 25 Elliptic Curve Digital Signature Algorithm (ECDSA) Register 25.10. ECDSA_SHA_MODE_REG (0x0200) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 4 ECDSA_SHA_MODE 0x0 3 0 Reset ECDSA_SHA_MODE Configures SHA algorithms for message hash. 1:SHA-224 2:SHA-256 3: SHA-384 4: SHA-512 5: SHA-512-224 6: SHA-512-256 Others: invalid (R/W) Register 25.11. ECDSA_SHA_START_REG (0x0210) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 ECDSA_SHA_START 0 0 Reset ECDSA_SHA_START Write 1 to start the first SHA operation in the ECDSA process. This bit will be self-cleared after configuration. (WT) Register 25.12. ECDSA_SHA_CONTINUE_REG (0x0214) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 ECDSA_SHA_CONTINUE 0 0 Reset ECDSA_SHA_CONTINUE Write 1 to start the latter SHA operation in the ECDSA process. This bit will be self-cleared after configuration. (WT) Espressif Systems 808 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 25 Elliptic Curve Digital Signature Algorithm (ECDSA) Register 25.13. ECDSA_SHA_BUSY_REG (0x0218) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 ECDSA_SHA_BUSY 0 0 Reset ECDSA_SHA_BUSY Represents the working status of the SHA accelerator in the ECDSA process. 0: IDLE 1: BUSY (RO) Register 25.14. ECDSA_DATE_REG (0x00FC) (reserved) 0 0 0 0 31 28 ECDSA_DATE 0x2409180 27 0 Reset ECDSA_DATE The ECDSA version control register. (R/W) Espressif Systems 809 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 26 External Memory Encryption and Decryption (XTS_AES) Chapter 26 External Memory Encryption and Decryption (XTS_AES) 26.1 Overview The ESP32-C5 integrates an External Memory Encryption and Decryption module that complies with the XTS-AES standard algorithm specified in IEEE Std 1619-2007, providing security for users’ application code and data stored in the external memory (flash and RAM). Users can store proprietary firmware and sensitive data (e.g., credentials for gaining access to a private network) in the external flash, or store general data in the external RAM. 26.2 Features • General XTS-AES algorithm, compliant with IEEE Std 1619-2007 • Software-based manual encryption • High-speed auto encryption and decryption without software’s participation • Encryption and decryption functions jointly enabled/disabled by registers configuration, eFuse parameters, and boot mode • Configurable Anti-DPA 26.3 Module Structure The External Memory Encryption and Decryption module consists of three blocks, namely the Manual Encryption block, Auto Encryption block and Auto Decryption block. The module architecture is shown in Figure 26.3-1. Espressif Systems 810 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 26 External Memory Encryption and Decryption (XTS_AES) Manual Encryption Auto Decryption System Register External Memory Encryption/Decryption eFuse Controller EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT EFUSE_SPI_BOOT_CRYPT_CNT Boot Mode HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT Auto Encryption Key HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT Figure 26.3-1. Architecture of the External Memory Encryption and Decryption The Manual Encryption block can encrypt instructions and data, which will then be written to the external flash as ciphertext via SPI1. When the CPU writes data to the external RAM through cache, the Auto Encryption block will automatically encrypt the data first, then the data will be written to the external RAM as ciphertext. When the CPU reads from the external flash or external RAM through cache, the Auto Decryption block will automatically decrypt the ciphertext to retrieve instructions and data. In the System Registers peripheral (see 16 System Registers), the following three bits in register HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG are relevant to the external memory encryption and decryption: • HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT • HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT • HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT • HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT The XTS_AES module also fetches two parameters from the peripheral eFuse Controller, which are: EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT and EFUSE_SPI_BOOT_CRYPT_CNT. For detailed information, please see Chapter 5 eFuse Controller (eFuse). 26.4 Functional Description Espressif Systems 811 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 26 External Memory Encryption and Decryption (XTS_AES) 26.4.1 XTS Algorithm Both manual encryption and auto encryption/decryption use the XTS algorithm. During implementation, the XTS algorithm is characterized by a ”data unit” of 1024 bits, defined in the Section XTS-AES encryption procedure of XTS-AES Tweakable Block Cipher Standard. For more information about the XTS-AES algorithm, please refer to IEEE Std 1619-2007. 26.4.2 Key The Manual Encryption block, Auto Encryption block, and Auto Decryption block share the same Key when implementing the XTS algorithm. The Key is provided by the eFuse hardware and cannot be accessed by software. The Key is 256-bit long. The value of the Key is determined by the content in one eFuse block from BLOCK4 BLOCK9. For easier description, we define: • Block A : the block whose key purpose is EFUSE_KEY_PURPOSE_XTS_AES_128_KEY (please refer to Table 5.3-2 Secure Key Purpose Values) in Chapter 5 eFuse Controller (eFuse). If Block A exists, a 256-bit Key A is stored in it. There are two possibilities of how the Key is generated depending on whether Block A exists or not, as shown in Table 26.4-1. In each case, the Key can be uniquely determined. Table 26.4-1. Key Generated Based on Key A Block A Key Key Length (bit) Exists Key A 256 Does not exist 0 256 256 Notes: • “0 256 ” indicates a bit string that consists of 256-bit zeros. • Using 0 256 as Key is not secure. It is recommended to configure a valid key. For more information of key purposes, please refer to Table 5.3-2 Secure Key Purpose Values in Chapter 5 eFuse Controller (eFuse). 26.4.3 Target Memory Space The target memory space refers to a continuous address space in the external memory where the first encrypted ciphertext is stored. The target memory space can be uniquely determined by three relevant parameters: type, size, and base address, whose definitions are listed below. • Type: the type of the target memory space, either external flash or external RAM. Value 0 indicates external flash, while 1 indicates external RAM. • Size: the size of the target memory space, indicating the number of bytes encrypted in one encryption operation, which supports 16, 32, or 64 bytes. • Base address: the base_addr of the target memory space. It is a 24-bit physical address, with range of 0x0000_0000 0x00FF_FFFF. It should be aligned to size, i.e., base_addr%size == 0. Espressif Systems 812 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 26 External Memory Encryption and Decryption (XTS_AES) For example, if there are 16 bytes of instruction data that need to be encrypted and written to address 0x130 0x13F in the external flash, then the target space is 0x130 0x13F, type is 0 (external flash), size is 16 (bytes), and the base address is 0x130. The encryption of any length (must be multiples of 16 bytes) of plaintext instruction/data can be completed separately in multiple operations, and each operation has its individual target memory space and the relevant parameters. For Auto Encryption/Decryption blocks, these parameters are automatically determined by hardware. For the Manual Encryption blocks, these parameters should be configured manually by users. Note: The “tweak” defined in Chapter 5.1 Data units and tweaks of IEEE Std 1619-2007 is a 128-bit non-negative integer (tweak), which can be generated according to tweak = type ∗ 2 30 + (base_addr & 0x3FFFFF80). The lowest 7 bits and the highest 97 bits in tweak are always zero. 26.4.4 Data Writing For Auto Encryption/Decryption blocks, data writing is automatically applied in hardware. For Manual Encryption blocks, data writing should be applied by users. The Manual Encryption block has a register block which consists of 16 registers, i.e., XTS_AES_PLAIN_n_REG (n: 0 15), that are dedicated to data writing and can store up to 512 bits of plaintext at a time. Actually, the Manual Encryption block does not care where the plaintext comes from, but only where the ciphertext will be stored. Because of the strict correspondence between plaintext and ciphertext, in order to better describe how the plaintext is stored in the register block, we assume that the plaintext is stored in the target memory space in the first place and replaced by ciphertext after encryption. Therefore, the following description in this section no longer has the concept of “plaintext”, but uses “target memory space” instead. How mapping between target memory space and registers works: Assume a word in the target memory space is stored in address, define offset = address%64, n = offset/4, then the word will be stored in register XTS_AES_PLAIN_n_REG. For example, when the size is 64, all registers in the register block will be used. The mapping between offset and registers now is shown in Table 26.4-2. Table 26.4-2. Mapping Between Offsets and Registers offset Register offset Register 0x00 XTS_AES_PLAIN_0_REG 0x20 XTS_AES_PLAIN_8_REG 0x04 XTS_AES_PLAIN_1_REG 0x24 XTS_AES_PLAIN_9_REG 0x08 XTS_AES_PLAIN_2_REG 0x28 XTS_AES_PLAIN_10_REG 0x0C XTS_AES_PLAIN_3_REG 0x2C XTS_AES_PLAIN_11_REG 0x10 XTS_AES_PLAIN_4_REG 0x30 XTS_AES_PLAIN_12_REG 0x14 XTS_AES_PLAIN_5_REG 0x34 XTS_AES_PLAIN_13_REG 0x18 XTS_AES_PLAIN_6_REG 0x38 XTS_AES_PLAIN_14_REG 0x1C XTS_AES_PLAIN_7_REG 0x3C XTS_AES_PLAIN_15_REG Espressif Systems 813 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 26 External Memory Encryption and Decryption (XTS_AES) 26.4.5 Manual Encryption Block The Manual Encryption block is a peripheral module. It is equipped with registers and can be accessed by the CPU directly. Registers embedded in this block, the System Registers peripheral, eFuse parameters, and boot mode jointly configure and use this module. The Manual Encryption block is operational only under certain conditions: • In SPI Boot mode: If bit HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT in register HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG is 1, the Manual Encryption block can be enabled. Otherwise, it is not operational. • In Download Boot mode: If bit HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT in register HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG is 1 and the eFuse parameter EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT is 0, the Manual Encryption block can be enabled. Otherwise, it is not operational. Note: Even though the CPU can skip cache and get the encrypted instruction/data directly by reading the external mem- ory, users can by no means access Key. 26.4.6 Auto Encryption Block The Auto Encryption block is not a conventional peripheral, so it does not have any registers and cannot be accessed by the CPU directly. The System Registers peripheral, eFuse parameters, and boot mode jointly configure and use this block. The Auto Encryption block is operational only under certain conditions: • In SPI Boot mode: when EFUSE_SPI_BOOT_CRYPT_CNT (3 bits in total) is set to 1, 2,4 or 7 (i.e., there is an odd number of 1s in its binary representation), then the Auto Encryption block can be enabled. Otherwise, it is not operational. • In Joint Download Boot mode: If bit SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT in register SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG is 1, the Auto Encryption block can be enabled. Otherwise, it is not operational. Note: • When the Auto Encryption block is enabled, it automatically encrypts data written by the CPU to external RAM. The encrypted data is stored in the external RAM, and this encryption process is fully hardware-based, requiring no software intervention. The operation is transparent to the cache, and the encryption key remains inaccessible to the user during the process. • When the Auto Encryption block is disabled, it bypasses the CPU’s access request to the cache and does not process the data. As a result, data is written directly to external RAM in plaintext. Espressif Systems 814 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 26 External Memory Encryption and Decryption (XTS_AES) 26.4.7 Auto Decryption Block The Auto Decryption block is not a conventional peripheral, so it does not have any registers and cannot be accessed by the CPU directly. The System Registers peripheral, eFuse parameters, and boot mode jointly configure and use this block. The Auto Decryption block is operational only under certain conditions: • In SPI Boot mode when EFUSE_SPI_BOOT_CRYPT_CNT (3 bits in total) is set to 1, 2,4 or 7 (i.e., there is an odd number of 1s in its binary representation), then the Auto Decryption block can be enabled. Otherwise, it is not operational. • In Download Boot mode when bit HP_SYS_ENABLE_DOWNLOAD_G0CB_DECRYPT in register HP_SYS_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG is 1, the Auto Decryption block can be enabled. Otherwise, it is not operational. Note: • When the Auto Decryption block is enabled, it automatically decrypts encrypted data or instructions read by the CPU from external memory via the cache. This decryption process is hardware-based and requires no software intervention, remaining transparent to the cache. The decryption key is not accessible to the software during this process. • When the Auto Decryption block is disabled, it does not affect the contents stored in external memory, regardless of whether they are encrypted. Consequently, the CPU reads the original data stored in external memory via the cache. 26.5 Software Process When the Manual Encryption block operates, software needs to be involved in the process. The steps are as follows: 1. Configure XTS_AES: • Write 0 to register XTS_AES_DESTINATION_REG. • Set register XTS_AES_PHYSICAL_ADDRESS_REG to base_addr. • Set register XTS_AES_LINESIZE_REG to size 32 . For definitions of base_addr and size, please refer to Section 26.4.3. 2. Write plaintext instructions/data to the registers block XTS_AES_PLAIN_n_REG (n: 0-15). For detailed information, please refer to Section 26.4.4. Please write data to registers according to your actual needs, and the unused ones could be set to arbitrary values. 3. Wait for Manual Encryption block to be idle. Poll register XTS_AES_STATE_REG until it reads 0 which indicates the Manual Encryption block is idle. 4. Trigger manual encryption by writing 1 to register XTS_AES_TRIGGER_REG. Espressif Systems 815 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 26 External Memory Encryption and Decryption (XTS_AES) 5. Wait for the encryption process completion. Poll register XTS_AES_STATE_REG until it reads 2. Step 1 to 5 are the steps of encrypting plaintext instructions/data with the Manual Encryption block using the Key. 6. Write 1 to register XTS_AES_RELEASE_REG to grant SPI1 the access to the encrypted ciphertext. After this, the value of register XTS_AES_STATE_REG will become 3. 7. Call SPI1 to write the ciphertext in the external flash (see Section API Reference - Flash Encrypt in ESP-IDF Programming Guide). 8. Write 1 to register XTS_AES_DESTROY_REG to destroy the ciphertext. After this, the value of register XTS_AES_STATE_REG will become 0. Repeat the above steps according to the amount of plaintext instructions/data that need to be encrypted. 26.6 Anti-DPA DPA (Differential Power Analysis) is a side-channel attack method in cryptography, through which an attacker can statistically analyze data collected from multiple encryption operations to calculate intermediate values in the encryption computation. ESP32-C5 XTS_AES supports two Anti-DPA methods to defend against external DPA attacks. The XTS-AES algorithm can be divided into two steps, according to IEEE Std 1619-2007: • Step 1: Calculating Tweak value. • Step 2: Calculating Cipher/Plain text. In this section, we define this step as calculating Data units. ESP32-C5 allows users to enable anti-DPA function separately during the above-mentioned two steps to enhance security. See details in the following sections. 26.6.1 Clock Anti-DPA Function Clock Anti-DPA function is the first method to defend against external DPA attacks. Different security levels can be configured through registers: • First we define the below parameters for a better description: – select_reg = XTS_AES_CRYPT_DPA_SELECT_REGISTER – reg_d_dpa_en = XTS_AES_CRYPT_CALC_D_DPA_EN – efuse_dpa_en = EFUSE_CRYPT_DPA_ENABLE – reg_anti_dpa_level = XTS_AES_CRYPT_SECURITY_LEVEL – efuse_anti_dpa_level = 3 • Configure the security level of Anti-DPA for the XTS_AES module: Anti_DP A_level = select _reg ? (reg_anti_dpa_level) : (efuse_dpa_en ∗ efuse_anti_dpa_level) When Anti_DP A_level equals 0, Anti-DPA is disabled. The higher the value of Anti_DP A_level is, the stronger the Anti-DPA ability is. Espressif Systems 816 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 26 External Memory Encryption and Decryption (XTS_AES) • Configure whether to enable Anti-DPA when the XTS-AES algorithm is calculating Data units: Anti_DP A_enabled_in_calc_D = select_reg ? reg_d_dpa_en : efuse_dpa_en If Anti_DP A_level is not 0, when Anti_DP A_enabled_in_calc_D equals to 1, Anti-DPA is enabled when XTS-AES algorithm is calculating Data units. If Anti_DP A_level is not 0, Anti-DPA is always enabled when the XTS-AES algorithm is calculating Tweak value. Note: • Even if efuse_dpa_en is set to 1, you can still disable anti-DPA by configuring select_reg = 1 and reg_anti_dpa_level = 0. • Configuring whether or not to enable Anti-DPA will have an impact on the external storage access bandwidth: – When Anti-DPA is enabled during the calculation of Data units, the read and write bandwidth will be reduced by more than 50% when the Anti-DPA level >= 4. – When Anti-DPA is disabled during the calculation of Data units, the read and write bandwidth will be reduced by more than 50% when the Anti-DPA level >= 6. 26.6.2 Pseudo-round Anti-DPA Function The pseudo-round function of ESP32-C5’s XTS-AES is the second method to achieve higher anti-attack performance. When the pseudo-round function is enabled, XTS-AES will randomly add pseudo-rounds before and after the original operation rounds. In a pseudo-round, XTS-AES will use the pseudo-key, which is automatically generated by the hardware, to perform a round of fake operations. The operations in the pseudo-round do not affect the original XTS-AES operation results. The configuration related to pseudo-round is as follows: Mode of pseudo-round function Users can choose to enable pseudo-round function in different calculation steps of XTS-AES: • 0: not enable pseudo-round function during calculation; • 1: enable pseudo-round function when calculating Tweak value; • 2: enable pseudo-round function when calculating Tweak value and some rounds of calculating Data units; • 3: enable pseudo-round function when calculating Tweak value and all rounds of calculating Data units. Total number of pseudo-rounds The total number of pseudo-rounds that will be randomly inserted into each XTS-AES operation round is controlled by: • pseudo_base: configures the basic round number of pseudo-round function. • pseudo_inc: configures the random incremental round number of pseudo-round function. The total number of pseudo-rounds will be randomly in the range [pseudo_base, pseudo_base + (2 pseudo_inc − 1)] Random number update frequency Espressif Systems 817 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 26 External Memory Encryption and Decryption (XTS_AES) pseudo_rnd_cnt configures the frequency of random key updates in the pseudo-round function. The higher the configured value, the higher the update frequency. This value is usually recommended to be set to maximum (7). Configuration The parameters mentioned above can be configured through eFuse bits or XTS_AES related registers, depending on the value of EFUSE_XTS_DPA_PSEUDO_LEVEL: • 0: The user can configure using XTS_AES related registers. • 1, 2, or 3: User configuration is not allowed. See Table 26.6-1 for details. Table 26.6-1. Configuration of XTS_AES Pseudo-round Anti-DPA EFUSE_XTS_DPA_PSEUDO_LEVEL pseudo_mode pseudo_base pseudo_inc pseudo_rnd_cnt 0 XTS_AES_PSEUDO_MODE XTS_AES_PSEUDO_BASE XTS_AES_PSEUDO_INC XTS_AES_PSEUDO_RNG_CNT 1 1 4 2 7 2 2 4 2 7 3 3 4 2 7 Espressif Systems 818 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 26 External Memory Encryption and Decryption (XTS_AES) 26.7 Register Summary The addresses in this section are relative to the External Memory Encryption and Decryption base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Plaintext Register Heap XTS_AES_PLAIN_0_REG Plaintext register 0 0x0300 R/W XTS_AES_PLAIN_1_REG Plaintext register 1 0x0304 R/W XTS_AES_PLAIN_2_REG Plaintext register 2 0x0308 R/W XTS_AES_PLAIN_3_REG Plaintext register 3 0x030C R/W XTS_AES_PLAIN_4_REG Plaintext register 4 0x0310 R/W XTS_AES_PLAIN_5_REG Plaintext register 5 0x0314 R/W XTS_AES_PLAIN_6_REG Plaintext register 6 0x0318 R/W XTS_AES_PLAIN_7_REG Plaintext register 7 0x031C R/W XTS_AES_PLAIN_8_REG Plaintext register 8 0x0320 R/W XTS_AES_PLAIN_9_REG Plaintext register 9 0x0324 R/W XTS_AES_PLAIN_10_REG Plaintext register 10 0x0328 R/W XTS_AES_PLAIN_11_REG Plaintext register 11 0x032C R/W XTS_AES_PLAIN_12_REG Plaintext register 12 0x0330 R/W XTS_AES_PLAIN_13_REG Plaintext register 13 0x0334 R/W XTS_AES_PLAIN_14_REG Plaintext register 14 0x0338 R/W XTS_AES_PLAIN_15_REG Plaintext register 15 0x033C R/W Configuration Registers XTS_AES_LINESIZE_REG Configures the size of target memory space 0x0340 R/W XTS_AES_DESTINATION_REG Configures the type of the exter- nal memory 0x0344 R/W XTS_AES_PHYSICAL_ADDRESS_REG Stores the physical address of the external memory 0x0348 R/W XTS_AES_DPA_CTRL_REG Configures the Anti-DPA function 0x0388 R/W XTS_AES_PSEUDO_ROUND_CONF_REG XTS-AES pseudo-round function configuration register 0x038C R/W Control/status Registers XTS_AES_TRIGGER_REG Activates AES algorithm 0x034C WT XTS_AES_RELEASE_REG Releases control 0x0350 WT XTS_AES_DESTROY_REG Destroys control 0x0354 WT XTS_AES_STATE_REG Status register 0x0358 RO Version control register XTS_AES_DATE_REG Version control register 0x035C R/W Espressif Systems 819 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 26 External Memory Encryption and Decryption (XTS_AES) 26.8 Registers The addresses in this section are relative to the External Memory Encryption and Decryption base address provided in Table 4.3-2 in Chapter 4 System and Memory. Register 26.1. XTS_AES_PLAIN_n_REG (n: 0-15) (0x0300+4*n) XTS_AES_PLAIN_n 0x000000 31 0 Reset XTS_AES_PLAIN_n Configures the nth 32-bit piece of plain text. (R/W) Register 26.2. XTS_AES_LINESIZE_REG (0x0340) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 2 XTS_AES_LINESIZE 0x0 1 0 Reset XTS_AES_LINESIZE Configures the data size of one encryption operation. 0: 16 bytes 1: 32 bytes 2: 64 bytes 3: Invalid (R/W) Espressif Systems 820 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 26 External Memory Encryption and Decryption (XTS_AES) Register 26.3. XTS_AES_DESTINATION_REG (0x0344) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 XTS_AES_DESTINATION 0 0 Reset XTS_AES_DESTINATION Configures the type of external memory for Manual Encryption. Currently, it must be set to 0, as the Manual Encryption block only supports flash encryption. Set this bit to 1 may cause an error. 0: flash 1: external RAM (R/W) Register 26.4. XTS_AES_PHYSICAL_ADDRESS_REG (0x0348) (reserved) 0 0 31 30 XTS_AES_PHYSICAL_ADDRESS 0x000000 29 0 Reset XTS_AES_PHYSICAL_ADDRESS Configures the physical address which will be used in Manual En- cryption. This value should be aligned with the byte number configured via the XTS_AES_LINESIZE parameter. (R/W) Espressif Systems 821 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 26 External Memory Encryption and Decryption (XTS_AES) Register 26.5. XTS_AES_DPA_CTRL_REG (0x0388) (reserved) 0x0000000 31 5 XTS_AES_CRYPT_DPA_SELECT_REGISTER 0x0 4 XTS_AES_CRYPT_CALC_D_DPA_EN 0x1 3 XTS_AES_CRYPT_SECURITY_LEVEL 0x7 2 0 Reset XTS_AES_CRYPT_DPA_SELECT_REGISTER Configures whether the clock Anti-DPA function is controlled by eFuse or register. 0: The clock Anti-DPA function is configured by register. 1: The clock Anti-DPA function is configured by eFuse. (R/W) XTS_AES_CRYPT_CALC_D_DPA_EN Configures whether to enable the clock Anti-DPA in the XTS_AES algorithm. 0: Enable the clock Anti-DPA only when calculating Tweak value 1: Enable the clock Anti-DPA both when calculating Tweak value and Date units Note that this field is only effective when XTS_AES_CRYPT_SECURITY_LEVEL is not 0. (R/W) XTS_AES_CRYPT_SECURITY_LEVEL Configures the security level of external memory encryption and decryption. 0: Disable the clock Anti-DPA function 1-7: The bigger the number is, the more secure the encryption and decryption are (R/W) Espressif Systems 822 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 26 External Memory Encryption and Decryption (XTS_AES) Register 26.6. XTS_AES_PSEUDO_ROUND_CONF_REG (0x038C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 11 XTS_AES_PSEUDO_INC 2 10 9 XTS_AES_PSEUDO_BASE 2 8 5 XTS_AES_PSEUDO_RNG_CNT 7 4 2 XTS_AES_PSEUDO_MODE 0 1 0 Reset XTS_AES_MODE_PSEUDO Set the calculation steps of XTS-AES to enable pseudo-round Anti-DPA function. 0: not enable the pseudo-round Anti-DPA function during calculation 1: enable the pseudo-round Anti-DPA function when calculating Tweak value 2: enable the pseudo-round Anti-DPA function when calculating Tweak value and some rounds of calculating Data units 3: enable the pseudo-round Anti-DPA function when calculating Tweak value and all rounds of calculating Data units (R/W) XTS_AES_PSEUDO_RNG_CNT Configures the update frequency of the pseudo-key in the pseudo- round Anti-DPA function. (R/W) XTS_AES_PSEUDO_BASE Configures the basic round number of pseudo-round Anti-DPA function. (R/W) XTS_AES_PSEUDO_INC Configures the incremental round number of pseudo-round Anti-DPA func- tion. (R/W) Register 26.7. XTS_AES_TRIGGER_REG (0x034C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 XTS_AES_TRIGGER 0 0 Reset XTS_AES_TRIGGER Set this bit to trigger the process of manual encryption calculation. 0: Disable manual encryption 1: Enable manual encryption This action should only be asserted when manual encryption status is 0. After this action, manual encryption status becomes 1. After calculation is done, manual encryption status becomes 2. (WT) Espressif Systems 823 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 26 External Memory Encryption and Decryption (XTS_AES) Register 26.8. XTS_AES_RELEASE_REG (0x0350) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 XTS_AES_RELEASE 0 0 Reset XTS_AES_RELEASE Set this bit to release encrypted result to MSPI. 0: do not release 1: release This action should only be asserted when manual encryption status is 2. After this action, manual encryption status will become 3. (WT) Register 26.9. XTS_AES_DESTROY_REG (0x0354) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 XTS_AES_DESTROY 0 0 Reset XTS_AES_DESTROY Set this bit to destroy encrypted result. 0: No effect 1: Destroy encrypted result This action should be asserted only when manual encryption status is 3. After this action, manual encryption status will become 0. (WT) Register 26.10. XTS_AES_STATE_REG (0x0358) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 2 XTS_AES_STATE 0x0 1 0 Reset XTS_AES_STATE Represents the status of the Manual Encryption block. 0 (XTS_AES_IDLE): Idle 1 (XTS_AES_BUSY): Busy with encryption 2 (XTS_AES_DONE): Encryption completed, but the encrypted result is not accessible to MSPI 3 (XTS_AES_RELEASE): Encrypted result is accessible to MSPI (RO) Espressif Systems 824 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 26 External Memory Encryption and Decryption (XTS_AES) Register 26.11. XTS_AES_DATE_REG (0x035C) (reserved) 0 0 31 30 XTS_AES_DATE 0x20210907 29 0 Reset XTS_AES_DATE Version control register. (R/W) Espressif Systems 825 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 27 Random Number Generator (RNG) Chapter 27 Random Number Generator (RNG) 27.1 Introduction The ESP32-C5 contains a true random number generator, which generates 32-bit random numbers that can be used for cryptographical operations, among other things. 27.2 Features The random number generator in ESP32-C5 generates true random numbers, which means random numbers derived from a physical process, rather than by means of an algorithm. All generated random numbers have an equal probability of appearing within a specific range. 27.3 Functional Description Every 32-bit value read from the LPPERI_RNG_DATA_SYNC_REG register of the random number generator is a true random number. These true random numbers are generated based on the thermal noise in the system, the asynchronous clock mismatch, and the asynchronous counter. • Thermal noise comes from the high-speed ADC, or SAR ADC, or both. Whenever the high-speed ADC or SAR ADC is enabled, bit streams will be generated and fed into the random number generator through an XOR logic gate as random seeds. • RC_FAST_CLK is an asynchronous clock source that can generate metastability in the circuit. This metastability can be used as a random number entropy to feed into the random number generator. • Asynchronous counters count using an asynchronous clock source. The asynchronous clock source generates circuit metastability, which can be used as a random number seed to feed into the random number generator. There are two types of asynchronous counters: – On-chip RTC Timer (RTC_TIMER): The counter directly counts using the on-chip RTC timer. The count value is fed into the random number generator as a random number seed after applying XOR logic. – Ring buffer (BUF_CHAIN) as the noise source. These two types of asynchronous counters can work independently or in combination. Note: For limitations of particular noise sources, please check notes in Section Programming Procedures. Espressif Systems 826 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 27 Random Number Generator (RNG) SAR ADC Random Number Generator High-Speed ADC LPPERI_RNG_SYNC_DATA_REG XOR XOR RC_FAST_CLK RTC_TIMER BUF_CHAIN XOR random bit seeds random bit seeds random bit seeds random bit seeds random bit seeds Figure 27.3-1. Noise Source When there is noise coming from the SAR ADC, the random number generator is fed with a 2-bit entropy in one clock cycle of RC_FAST_CLK, which is generated from an internal RC oscillator (see Chapter 7 Reset and Clock for details). Thus, it is advisable to read the LPPERI_RNG_DATA_SYNC_REG register at a maximum rate of 1 MHz to obtain the maximum entropy. When there is noise coming from the high-speed ADC, the random number generator is fed with a 2-bit entropy in one APB clock cycle, which is normally 80 MHz. Thus, it is advisable to read the LPPERI_RNG_DATA_SYNC_REG register at a maximum rate of 5 MHz to obtain the maximum entropy. A data sample of 2 GB, which is read from the random number generator at a rate of 5 MHz with only the high-speed ADC being enabled, has been tested using the Dieharder Random Number Testsuite (version 3.31.1). The sample passed all tests. 27.4 Programming Procedure To use the random number generator, set LPPERI_RNG_CK_EN to enable its clock. The clock is automatically enabled when Elliptic Curve Digital Signature Algorithm (ECDSA) is used, regardless of LPPERI_RNG_CK_EN. When using the random number generator, ensure the entropy source is enabled. Otherwise, pseudo-random numbers will be returned. • SAR ADC can be enabled by using the DIG ADC controller. For details, please refer to Chapter 41 ADC Controller. • High-speed ADC is enabled automatically when the Wi-Fi or Bluetooth module is enabled. • RC_FAST_CLK is always enabled • Asynchronous counters – RTC timer (RTC_TIMER) is enabled by setting the LPPERI_RTC_TIMER_EN field. – Ring buffer (BUF_CHAIN) is enabled by setting the LPPERI_RNG_SAMPLE_ENABLE bit. Note: 1. When the Wi-Fi module is enabled, the value read from the high-speed ADC can be saturated in some extreme Espressif Systems 827 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 27 Random Number Generator (RNG) cases, which lowers the entropy. Thus, it is advisable to also enable the SAR ADC as the noise source for the random number generator for such cases. 2. Enabling RC_FAST_CLK and asynchronous counters increases the RNG entropy. However, to ensure maximum entropy, it’s recommended to always enable the SAR ADC or high-speed ADC as well. Read the LPPERI_RNG_DATA_SYNC_REG register multiple times until sufficient random numbers have been generated. Ensure the rate at which the register is read does not exceed the frequencies described in Section 27.3 above. Espressif Systems 828 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 27 Random Number Generator (RNG) 27.5 Register Summary The addresses in this section are relative to Random Number Generator base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access LPPERI_RNG_CFG_REG RNG configuration register 0x0024 varies LPPERI_RNG_DATA_SYNC_REG RNG result synchronization register 0x0028 RO Espressif Systems 829 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 27 Random Number Generator (RNG) 27.6 Registers The addresses in this section are relative to Random Number Generator base address provided in Table 4.3-2 in Chapter 4 System and Memory. For how to program reserved fields, please refer to Section Programming Reserved Register Field. Register 27.1. LPPERI_RNG_CFG_REG (0x0024) (reserved) 0x0 31 24 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 23 12 LPPERI_RTC_TIMER_EN 3 11 10 (reserved) 0 0 0 0 0 0 0 0 0 9 1 LPPERI_RNG_SAMPLE_ENABLE 0 0 Reset LPPERI_RNG_SAMPLE_ENABLE Configures whether to enable BUF_CHAIN. 0: Disable 1: Enable (R/W) LPPERI_RTC_TIMER_EN Bit[0]: Configures whether to enable the RTC timer before CRC. Bit[1]: Configures whether to enable the RTC timer after CRC. 0: Disable 1: Enable (R/W) Register 27.2. LPPERI_RNG_DATA_SYNC_REG (0x0028) LPPERI_RND_SYNC_DATA 0 31 0 Reset LPPERI_RND_SYNC_DATA Represents the RNG synchronization result. (RO) Espressif Systems 830 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Part V Connectivity Interface This part addresses the connectivity aspects of the system, describing components related to various communication interfaces like I2C, I2S, SPI, UART, USB, and more. The part also covers interfaces to generate signals used in remote control, motor control, LED control, etc. Espressif Systems 831 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Chapter 28 UART Controller (UART) 28.1 Overview A UART is a character-oriented data link for asynchronous communication between devices. Such communication does not add clock signals to the data sent. Therefore, in order to communicate successfully, the transmitter and the receiver must operate at the same baud rate with the same stop bit(s) and parity bit(s). A UART data frame usually begins with one start bit, followed by data bits, one parity bit (optional), and one or more stop bits. UART controllers on ESP32-C5 support various lengths of data bits and stop bits. These controllers also support software and hardware flow control as well as GDMA for high-speed data transfer. This allows developers to use multiple UART ports at minimal software cost. ESP32-C5 has three UART controllers, including two regular UARTs and one low-power (LP) UART. These UARTs are compatible with various UART devices, and support Infrared Data Association (IrDA) and RS485 communication. In this chapter, the two regular UART controllers are referred to as UARTn, in which n denotes 0, 1. LP UART is the cut-down version of the regular UART, with a separate group of registers. For differences between UART and LP UART, please refer to Table 28.2-1. 28.2 Features Table 28.2-1 lists the feature comparison between UART and LP UART: Table 28.2-1. UART and LP UART Feautre Comparison UART Feature LP UART Feature Programmable baud rate up to 5 MBaud 128 x 8 bit RAM respectively for the TX channel and RX channel of a UART controller 20 x 8-bit RAM, shared by the TX FIFO and RX FIFO of LP UART Full-duplex asynchronous communication Data bits (5 to 8 bits) Stop bits (1, 1.5, or 2 bits) Parity bit Special character AT_CMD detection RS485 protocol — IrDA protocol — High-speed data communication using GDMA — Cont’d on next page Espressif Systems 832 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Table 28.2-1 – cont’d from previous page UART Feature LP_UART Feature Receive timeout UART as wakeup source Software and hardware flow control Three prescalable clock sources: 1. XTAL_CLK 2. RC_FAST_CLK 3. PLL_F80M_CLK Three prescalable clock sources 1. RC_FAST_CLK 2. XTAL_DIV_CLK 3. PLL_F8M_CLK The following description mainly covers regular UART controllers. 28.3 UART Structure Tx_FIFO Tx_FIFO_Ctrl GDMA Tx_FSM Hardware Flow Control Software Flow Control Start_Detect Baudrate_Detect 1 0 Wakeup_Ctrl UART_TXD_INV ... Divider UART0 Rx_FIFO UART0 Tx_FIFO fifo_rdata fifo_rd Rx_FIFO Rx_FIFO_Ctrl Rx_FSM fifo_wdata fifo_wr APB_CLK Clock source UART_RXD_INV wake_up UART_LOOPBACK txd_out rtsn_out ctsn_in CLOCK ... apb_rdata Transmitter Receiver Clock source RAM apb_wdata XTAL_CLK RC_FAST_CLK PLL_F80M_CLK CTS RTS Configuration registers AHB_CLK Clock source APB_CLK Domain AHB_CLK Domain UART_FCLK Domain UART_SCLK Domain rxd_in Figure 28.3-1. UART Structure Figure 28.3-1 shows the basic structure of a UART controller. A UART controller works in four clock domains, namely APB_CLK, AHB_CLK, UART_SCLK, and UART_FCLK. APB_CLK and AHB_CLK are synchronized but with different frequencies (APB_CLK is derived from AHB_CLK by division), and likewise UART_SCLK and UART_FCLK are synchronized but with different frequencies (UART_SCLK is derived from UART_FCLK by division). UART_FCLK has three clock sources: PLL_F80M_CLK, RC_FAST_CLK, and crystal clock XTAL_CLK (for details, please refer to Chapter 7 Reset and Clock), which are selected by configuring PCR_UARTn_SCLK_SEL. The selected clock source is divided by a divider to generate UART_SCLK clock signals. The divisor is configured by PCR_UARTn_SCLK_DIV_NUM for the integral part, PCR_UARTn_SCLK_DIV_A for the denominator of the fractional part, and PCR_UARTn_SCLK_DIV_B for the numerator of the fractional part. The divisor ranges from 1 256. Only regular UART has such a divider; LP UART does not. A UART controller can be broken down into two parts based on functions: a transmitter and a receiver. Espressif Systems 833 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) The transmitter contains a TX FIFO (i.e., Tx_FIFO in Figure 28.3-1), which buffers data to be sent. Software can write data to Tx_FIFO via the APB bus, or move data to Tx_FIFO using GDMA. Tx_FIFO_Ctrl controls writing and reading Tx_FIFO. When Tx_FIFO is not empty, Tx_FSM reads data bits in the data frame via Tx_FIFO_Ctrl, and converts them into a bitstream. The levels of output bitstream signal txd_out can be inverted by configuring the UART_TXD_INV field. The receiver contains an RX FIFO (i.e., Rx_FIFO in Figure 28.3-1), which buffers data to be processed. The input bitstream signal rxd_in is transferred to the UART controller, and its level can be inverted by configuring UART_RXD_INV field. Baudrate_Detect measures the baud rate of input bitstream signal rxd_in by detecting its minimum pulse width. Start_Detect detects the start bit in a data frame. If the start bit is detected, Rx_FSM stores data bits in the data frame into Rx_FIFO by Rx_FIFO_Ctrl. Software can read data from Rx_FIFO via the APB bus, or receive data using GDMA. HW_Flow_Ctrl controls rxd_in and txd_out data flows by standard UART RTS and CTS flow control signals (rtsn_out and ctsn_in). SW_Flow_Ctrl controls data flows by adding special characters to outgoing data and detecting special characters in incoming data. When a UART controller is in Light-sleep mode (see Chapter 2 Low-power Management [to be added later] for more details), a wake_up signal can be generated in four ways and sent to PMU, which then wakes up the ESP32-C5 chip. For more information about wakeup, please refer to Section 28.4.8. 28.4 Functional Description 28.4.1 Clock and Reset UART controllers are asynchronous. Their register configuration module works in the APB_CLK domain. TX FIFO and RX FIFO work across the AHB_CLK and UART_FCLK domains. The UART RAM control unit works in the UART_FCLK domain. The UART transmission and reception control module works in the UART_SCLK domain, i.e., UART Core’s clock domain. When the frequency of the UART_SCLK is higher than the frequency needed to generate the baud rate, the UART Core can be clocked at a lower frequency by the divider, in order to reduce power consumption. Usually, the UART Core’s clock frequency is lower than the APB_CLK’s frequency, and can be divided by the largest divisor when higher than the frequency needed to generate the baud rate. The frequency of the UART Core’s clock can also be at most twice higher than the APB_CLK. The clock for the UART transmitter and the UART receiver can be controlled independently. To enable the clock for the UART transmitter, UART_TX_SCLK_EN shall be set; to enable the clock for the UART receiver, UART_RX_SCLK_EN shall be set. To ensure that the configured register values are synchronized from APB_CLK domain to the UART_SCLK domain, please follow the procedures in Section28.6. To reset the whole UART, please: • Enable the UART Core’s clock by setting PCR_UARTn_CLK_EN to 1. • Write 1 to PCR_UARTn_RST_EN. • Clear PCR_UARTn_RST_EN to 0. Espressif Systems 834 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) 28.4.2 UART FIFO The transmitter and the receiver on the UART controller each use a 128 x 8-bit RAM, and access their respective RAM through a separate 4 x 8-bit asynchronous FIFO interface. The RAM and asynchronous FIFO interface for the transmitter and the receiver are independent and cannot be shared. UART Tx_FIFO is reset by setting UART_TXFIFO_RST. UART Rx_FIFO is reset by setting UART_RXFIFO_RST. Data to be sent is written to TX FIFO via the APB bus or using GDMA, read automatically, and converted from a frame into a bitstream by hardware Tx_FSM. Data received is converted from a bitstream into a frame by hardware Rx_FSM, written into RX FIFO, and then stored into RAM via the APB bus or using GDMA. The two UART controllers share one GDMA channel. The empty signal threshold for Tx_FIFO is configured by setting UART_TXFIFO_EMPTY_THRHD. When data stored in Tx_FIFO is less than UART_TXFIFO_EMPTY_THRHD, a UART_TXFIFO_EMPTY_INT interrupt is generated. The full signal threshold for Rx_FIFO is configured by setting UART_RXFIFO_FULL_THRHD. When data stored in Rx_FIFO is greater than or equal to UART_RXFIFO_FULL_THRHD, a UART_RXFIFO_FULL_INT interrupt is generated. In addition, when Rx_FIFO receives more data than its capacity, a UART_RXFIFO_OVF_INT interrupt is generated. UARTn can access FIFO via register UART_FIFO_REG. You can put data into TX FIFO by writing UART_RXFIFO_RD_BYTE, and get data in RX FIFO by reading UART_RXFIFO_RD_BYTE. 28.4.3 Baud Rate Generation and Detection 28.4.3.1 Baud Rate Generation Before a UART controller sends or receives data, the baud rate should be configured by setting corresponding registers. The baud rate generator of a UART controller functions by dividing the input clock source. It can divide the clock source by a fractional amount. The divisor is configured by UART_CLKDIV_SYNC_REG: UART_CLKDIV for the integral part, and UART_CLKDIV_FRAG for the fractional part. When using the 80 MHz input clock, the UART controller supports a maximum baud rate of 5 MBaud. The divisor of the baud rate divider is equal to UART _CLKDIV + UART _CLKDIV _F RAG 16 meaning that the final baud rate is equal to INP UT _F REQ UART _CLKDIV + UART _CLKDIV _F RAG 16 where INPUT_FREQ is the frequency of UART Core’s source clock. For example, if UART_CLKDIV = 694 and UART_CLKDIV_FRAG = 7, then the divisor value is 694 + 7 16 = 694.4375 When UART_CLKDIV_FRAG is 0, the baud rate generator is an integer clock divider where an output pulse is generated every UART_CLKDIV input pulses. When UART_CLKDIV_FRAG is not 0, the divider is fractional and the output baud rate clock pulses are not strictly uniform. As shown in Figure 28.4-1, for every 16 output pulses, the generator divides either (UART_CLKDIV + 1) Espressif Systems 835 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) input pulses or UART_CLKDIV input pulses per output pulse. A total of UART_CLKDIV_FRAG output pulses are generated by dividing (UART_CLKDIV + 1) input pulses, and the remaining (16 - UART_CLKDIV_FRAG) output pulses are generated by dividing UART_CLKDIV input pulses. The output pulses are interleaved as shown in Figure 28.4-1 below, to make the output timing more uniform: Figure 28.4-1. UART Controllers Division To support IrDA (see Section 28.4.7 for details), the fractional clock divider for IrDA data transmission generates clock signals divided by 16 × UART_CLKDIV_SYNC_REG. This divider works similarly as the one elaborated above: it takes UART_CLKDIV/16 as the integer value and the lowest four bits of UART_CLKDIV as the fractional value. 28.4.3.2 Baud Rate Detection Automatic baud rate detection (Autobaud) on UARTs is enabled by setting UART_AUTOBAUD_EN. The Baudrate_Detect module shown in Figure 28.4-2 filters any noise whose pulse width is shorter than UART_GLITCH_FILT. Before communication starts, the transmitter could send random data to the receiver for baud rate detection. UART_LOWPULSE_MIN_CNT stores the minimum low pulse width, UART_HIGHPULSE_MIN_CNT stores the minimum high pulse width, UART_POSEDGE_MIN_CNT stores the minimum pulse width between two positive edges, and UART_NEGEDGE_MIN_CNT stores the minimum pulse width between two negative edges. These four fields are read by software to determine the transmitter’s baud rate. Figure 28.4-2. The Timing Diagram of Weak UART Signals Along Negative Edges The baud rate can be determined in the following three ways: 1. Normally, to avoid sampling erroneous data along positive or negative edges in a metastable state, which results in the inaccuracy of UART_LOWPULSE_MIN_CNT or UART_HIGHPULSE_MIN_CNT, use a Espressif Systems 836 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) weighted average of these two values to eliminate errors for 1-bit pulses. In this case, the baud rate is calculated as follows: B uart = f clk (UART_LOWPULSE_MIN_CNT + UART_HIGHPULSE_MIN_CNT + 2)/2 2. If UART signals are weak along negative edges as shown in Figure 28.4-2, which leads to an inaccurate average of UART_LOWPULSE_MIN_CNT and UART_HIGHPULSE_MIN_CNT, use UART_POSEDGE_MIN_CNT to determine the transmitter’s baud rate as follows: B uart = f clk (UART_POSEDGE_MIN_CNT + 1)/2 3. If UART signals are weak along positive edges, use UART_NEGEDGE_MIN_CNT to determine the transmitter’s baud rate as follows: B uart = f clk (UART_NEGEDGE_MIN_CNT + 1)/2 28.4.4 UART Data Frame Figure 28.4-3. Structure of UART Data Frame Figure 28.4-3 shows the basic structure of a data frame. A frame starts with one start bit, and ends with stop bits which can be 1, 1.5, or 2 bit-long, configured by UART_STOP_BIT_NUM (in RS485 mode turnaround delay may be added. See details in Section 28.4.6.2). The start bit is logical low, whereas stop bits are logical high. The actual data length can be anywhere between 5 8 bit, configured by UART_BIT_NUM. When UART_PARITY_EN is set, a parity bit is added after data bits. UART_PARITY is used to choose even parity or odd parity. When the receiver detects a parity bit error in the data received, a UART_PARITY_ERR_INT interrupt is generated, and the data received will still be stored into RX FIFO. When the receiver detects a data frame error, a UART_FRM_ERR_INT interrupt is generated, and the data received by default is stored into RX FIFO. If all data in Tx_FIFO has been sent, a UART_TX_DONE_INT interrupt is generated. After this, if the UART_TXD_BRK bit is set, then the transmitter will enter the break condition and send several NULL characters. After the NULL characters are sent, the TX data line is logical low. The number of NULL characters is configured by UART_TX_BRK_NUM. Once the transmitter has sent all NULL characters, a UART_TX_BRK_DONE_INT interrupt is generated. The minimum interval between data frames can be configured using UART_TX_IDLE_NUM. If the transmitter stays idle for UART_TX_IDLE_NUM or more time, a UART_TX_BRK_IDLE_DONE_INT interrupt is generated. The receiver can also detect the Break conditions when the RX data line detects any low logical level for one NULL character transmission, and a UART_BRK_DET_INT interrupt will be triggered to detect when a break condition has been completed. Espressif Systems 837 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) The receiver can detect the current bus state through the timeout interrupt UART_RXFIFO_TOUT_INT. The UART_RXFIFO_TOUT_INT interrupt will be triggered when the bus is in the idle state for more than UART_RX_TOUT_THRHD bit time on current baud rate after the receiver has received at least one byte. You can use this interrupt to detect whether all the data from the transmitter has been sent. 28.4.5 AT_CMD Character Structure Figure 28.4-4. AT_CMD Character Structure Figure 28.4-4 is the structure of a special character AT_CMD. If the receiver constantly receives AT_CMD_CHAR and the following conditions are met, a UART_AT_CMD_CHAR_DET_INT interrupt is generated. • The interval between the first AT_CMD_CHAR and the last non-AT_CMD_CHAR character is at least UART _PRE_IDLE_NUM cycles. • The interval between two AT_CMD_CHAR characters is less than UART_RX_GAP_TOUT in the unit of baud rate cycles. • The number of AT_CMD_CHAR characters is equal to or greater than UART_CHAR_NUM. • The interval between the last AT_CMD_CHAR character and next non-AT_CMD_CHAR character is at least UART_POST_IDLE_NUM cycles. Note: Given that the interval between AT_CMD_CHAR characters is less than UART_RX_GAP_TOUT in the unit of baud rate cycles, the APB_CLK frequency is suggested not to be lower than 8 MHz. 28.4.6 RS485 The two regular UART controllers support RS485 communication mode. In this mode differential signals are used to transmit data, so it can communicate over longer distances at higher bit rates than RS232. RS485 has two-wire half-duplex and four-wire full-duplex options. UART controllers support two-wire half-duplex transmission and bus snooping. 28.4.6.1 Driver Control As shown in Figure 28.4-5, in a two-wire multidrop network, an external RS485 transceiver is needed for differential to single-ended conversion or the other way around. An RS485 transceiver contains a driver and a receiver. When a UART controller is not in transmitter mode, the connection to the differential line can be broken by disabling the driver. When DE is 1, the driver is enabled; when DE is 0, the driver is disabled. The UART receiver converts differential signals to single-ended signals via an external receiver. RE is the enable control signal for the receiver. When RE is 0, the receiver is enabled; when RE is 1, the receiver is disabled. If RE is configured as 0, the UART controller is allowed to snoop data on the bus, including the data sent by itself. DE can be controlled by either software or hardware. To reduce the cost of software, in our design DE is controlled by hardware. As shown in Figure 28.4-5, DE is connected to dtrn_out of UART (please refer to Section Espressif Systems 838 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) 28.4.9.1 for more details). Figure 28.4-5. Driver Control Diagram in RS485 Mode 28.4.6.2 Turnaround Delay By default, the UART controllers work in receiver mode. When a UART controller is switched from transmitter mode to receiver mode, the RS485 protocol requires a turnaround delay of one cycle after the stop bit. The UART transmitter supports adding a turnaround delay of one cycle before the start bit or after the stop bit. When UART_DL0_EN is set, a turnaround delay of one cycle is added before the start bit; when UART_DL1_EN is set, a turnaround delay of one cycle is added after the stop bit. 28.4.6.3 Bus Snooping In a two-wire multidrop network, UART controllers support bus snooping if RE of the external RS485 transceiver is 0. By default, a UART controller is not allowed to transmit and receive data simultaneously. If UART_RS485TX_RX_EN is set and the external RS485 transceiver is configured as in Figure 28.4-5, a UART controller may receive data in transmitter mode and snoop the bus. If UART_RS485RXBY_TX_EN is set, a UART controller may transmit data in receiver mode. The two UART controllers can snoop the data sent by themselves. In transmitter mode, when a UART controller monitors a collision between the data sent and the data received, a UART_RS485_CLASH_INT is generated; when a UART controller monitors a data frame error, a UART_RS485_FRM_ERR_INT interrupt is generated; when a UART controller monitors a parity bit error, a UART_RS485_PARITY_ERR_INT is generated. 28.4.7 IrDA IrDA protocol consists of three layers, namely the physical layer, the link access protocol, and the link management protocol. The UART controllers implement IrDA’s physical layer. In IrDA encoding, a UART controller supports data rates up to 115.2 kbit/s (SIR, or serial infrared mode). As shown in Figure 28.4-6, the IrDA encoder converts a non-return to zero code (NRZ) signal to a return to zero inverted code (RZI) signal and sends it to the external driver and infrared LED. This encoder uses modulated signals whose pulse width is 3/16 bits to indicate logic ”0”, and low levels to indicate logic ”1”. The IrDA decoder receives signals from the infrared receiver and converts them to NRZ signals. In most cases, the receiver is high when it is idle, and the parity bit of the encoder output is opposite to that of the decoder input. If a low pulse is detected, it indicates that a start bit has been received. When IrDA function is enabled, one bit is divided into 16 clock cycles. If the bit to be sent is zero, then the 9th, 10th, and 11th clock cycle are high. Espressif Systems 839 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Figure 28.4-6. The Timing Diagram of Encoding and Decoding in SIR mode The IrDA transceiver is half-duplex, meaning that it cannot send and receive data simultaneously. As shown in Figure 28.4-7, IrDA function is enabled by setting UART_IRDA_EN. When UART_IRDA_TX_EN is set to 1, the IrDA transceiver is enabled to send data and not allowed to receive data; when UART_IRDA_TX_EN is reset to 0, the IrDA transceiver is enabled to receive data and not allowed to send data. Figure 28.4-7. IrDA Encoding and Decoding Diagram 28.4.8 Wakeup UART can be set as wakeup source. When a UART controller is in Light-sleep mode, a wake_up signal can be generated in four ways and be sent to the PMU module, which then wakes up ESP32-C5. • UART_WK_MODE_SEL = 0: When all the clocks are disabled, the chip can be woken up by reverting RXD for multiple cycles until the number of positive edges is greater than or equal to UART_ACTIVE_THRESHOLD + 3. • UART_WK_MODE_SEL = 1: UART Core keeps working, so the UART receiver can still receive data and store the received data in RX FIFO. When the number of data bytes in RX FIFO is greater than UART_RX_WAKE_UP_THRHD, the chip can be woken up from the Light-sleep mode. • UART_WK_MODE_SEL = 2: When the UART receiver detects a start bit, the chip will be woken up. Espressif Systems 840 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) • UART_WK_MODE_SEL = 3: When the UART receiver receives a specific character sequence, the chip will be woken up. The wakeup characters can be defined by configuring UART_WK_CHAR0, UART_WK_CHAR1, UART_WK_CHAR2, UART_WK_CHAR3, and UART_WK_CHAR4. These characters can be formed into different character sequences by configuring UART_CHAR_NUM and UART_WK_CHAR_MASK, as shown in Table 28.4-1. Once the sequence is detected, the chip will be woken up. For the last configuration in Table 28.4-1, UART will detect for CHAR0 CHAR4 in order. Table 28.4-1. UART_CHAR_WAKEUP Mode Configuration UART_CHAR_NAME UART_WP_CHAR_MASK Character Sequence 1 0xF CHAR4 2 0x7 CHAR3/CHAR4 3 0x3 CHAR2/CHAR3/CHAR4 4 0x1 CHAR1/CHAR2/CHAR3/CHAR4 5 0x0 CHAR0/CHAR1/CHAR2/CHAR3/CHAR4 After the chip is woken up by UART, it is necessary to clear the wake_up signal by transmitting data to UART in Active mode or resetting the whole UART, otherwise the number of rising edges required for the next wakeup will be reduced. 28.4.9 Flow Control UART controllers have two ways to control data flow, namely hardware flow control and software flow control. Hardware flow control is achieved using output signal rtsn_out and input signal ctsn_in. Software flow control is achieved by inserting special characters in the data flow sent and detecting special characters in the data flow received. 28.4.9.1 Hardware Flow Control Figure 28.4-8 shows the hardware flow control of a UART controller. Hardware flow control uses output signal rtsn_out and input signal dsrn_in. Figure 28.4-9 illustrates how these signals are connected between UART on ESP32-C5 (hereinafter referred to as IU0) and the external UART (hereinafter referred to as EU0). Espressif Systems 841 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) UART_LOOPBACK 1 0 Comparator rts_int UART_RX_FLOW_EN 1 0 UART_SW_RTS cts_int UART_RTS_INV rtsn_out UART_CTS_INV ctsn_in UART_LOOPBACK 1 0 DE Control Logic UART_RS485_EN 1 0 UART_SW_DTR UART_DTR_INV dtrn_out UART_DSR_INV dsrn_in UART_RXFIFO_CNT UART_RX_FLOW_THRHD Figure 28.4-8. Hardware Flow Control Diagram When rtsn_out of IU0 is low, EU0 is allowed to send data. When rtsn_out of IU0 is high, EU0 is notified to stop sending data until rtsn_out of IU0 returns to low. The output signal rtsn_out can be controlled in two ways. • Software control: Enter this mode by clearing UART_RX_FLOW_EN to 0. In this mode, the level of rtsn_out is changed by configuring UART_SW_RTS. • Hardware control: Enter this mode by setting UART_RX_FLOW_EN to 1. In this mode, rtsn_out is pulled high when data in Rx_FIFO exceeds UART_RX_FLOW_THRHD. Figure 28.4-9. Connection between Hardware Flow Control Signals When ctsn_in of IU0 is low, IU0 is allowed to send data; when ctsn_in is high, IU0 is not allowed to send data. When IU0 detects an edge change of ctsn_in, a UART_CTS_CHG_INT interrupt is generated. If dtrn_out of IU0 is high, it indicates that IU0 is ready to transmit data. dtrn_out is generated by configuring the Espressif Systems 842 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) UART_SW_DTR field. When the IU0 transmitter detects an edge change of dsrn_in, a UART_DSR_CHG_INT interrupt is generated. After this interrupt is detected, software can obtain the level of input signal dsrn_in by reading UART_DSRN. If dsrn_in is high, it indicates that EU0 is ready to transmit data. In a two-wire RS485 multidrop network enabled by setting UART_RS485_EN, dtrn_out is generated by hardware and used for transmit/receive turnaround. When data transmission starts, dtrn_out is pulled high and the external driver is enabled; when data transmission completes, dtrn_out is pulled low and the external driver is disabled. Please note that when there is a turnaround delay of one cycle added after the stop bit, dtrn_out is pulled low after the delay. UART loopback test is enabled by setting UART_LOOPBACK. In the test, UART output signal txd_out is connected to its input signal rxd_in, rtsn_out is connected to ctsn_in, and dtrn_out is connected to dsrn_out. If the data sent matches the data received, it indicates that UART controllers are working properly. 28.4.9.2 Software Flow Control Instead of CTS/RTS lines, software flow control uses XON/XOFF characters to start or stop data transmission. Such flow control is enabled by setting UART_SW_FLOW_CON_EN to 1. When using software flow control, hardware automatically detects if there are XON/XOFF characters in the data flow received, and generate a UART_SW_XOFF_INT or a UART_SW_XON_INT interrupt accordingly. If an XOFF character is detected, the transmitter stops data transmission once the current byte has been transmitted; if an XON character is detected, the transmitter starts data transmission. In addition, software can force the transmitter to stop sending data by setting UART_FORCE_XOFF, or to start sending data by setting UART_FORCE_XON. Software determines whether to insert flow control characters based on the remaining room in RX FIFO. When UART_SEND_XOFF is set, the transmitter sends an XOFF character configured by UART_XOFF_CHAR after the current byte in transmission; when UART_SEND_XON is set, the transmitter sends an XON character configured by UART_XON_CHAR after the current byte in transmission. If the RX FIFO of a UART controller stores more data than UART_XOFF_THRESHOLD, UART_SEND_XOFF is set by hardware. As a result, the transmitter sends an XOFF character configured by UART_XOFF_CHAR after the current byte in transmission. If the RX FIFO of a UART controller stores less data than UART_XON_THRESHOLD, UART_SEND_XON is set by hardware. As a result, the transmitter sends an XON character configured by UART_XON_CHAR after the current byte in transmission. In full-duplex mode, when the UART receiver receives an XOFF character, the UART transmitter is not allowed to send any data including XOFF even if the UART receiver receives more data than its threshold. To avoid deadlocks in software flow control or overflow caused thereby, you can set UART_XON_XOFF_STILL_SEND. In this way, the UART transmitter can still send an XOFF character when it is not allowed to send any data. 28.4.10 GDMA Mode The two UART controllers on ESP32-C5 share one TX/RX GDMA (General Direct Memory Access) channel via UHCI (Universal Host Controller Interface). In GDMA mode, UART controllers support the decoding and encoding of HCI data packets. The UHCI_UART_SEL field determines which UART controller occupies the GDMA TX/RX channel. Espressif Systems 843 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Figure 28.4-10. Data Transfer in GDMA Mode Figure 28.4-10 shows how data is transferred using GDMA. Before GDMA receives data, software prepares an inlink. GDMA_INLINK_ADDR_CHn points to the first receive descriptor in the inlink. After GDMA_INLINK_START_CHn is set, UHCI sends data that UART has received to the decoder. The decoded data is then stored into the RAM pointed by the inlink under the control of GDMA. Before GDMA sends data, software prepares an outlink and data to be sent. GDMA_OUTLINK_ADDR_CHn points to the first transmit descriptor in the outlink. After GDMA_OUTLINK_START_CHn is set, GDMA reads data from the RAM pointed by outlink. The data is then encoded by the encoder, and sent sequentially by the UART transmitter. HCI data packets have separators at the beginning and the end, with data bits in the middle (separators + data bits + separators). The encoder inserts separators in front of and after data bits, and replaces data bits identical to separators with special characters. The decoder removes separators in front of and after data bits, and replaces special characters with separators. There can be more than one continuous separator at the beginning and the end of a data packet. The separator is configured by UHCI_SEPER_CHAR, 0xC0 by default. The special character is configured by UHCI_ESC_SEQ0_CHAR0 (0xDB by default) and UHCI_ESC_SEQ0_CHAR1 (0xDD by default). When all data has been sent, a GDMA_OUT_TOTAL_EOF_CHn_INT interrupt is generated. When all data has been received, a GDMA_IN_SUC_EOF_CHn_INT is generated. 28.5 Interrupts ESP32-C5’s UARTn and UHCI can generate the following interrupt signals that will be sent to the Interrupt Matrix. • UARTn_INTR • UHCI_INTR There are several internal interrupt sources from UARTn and UHCI that can generate the above interrupt signals. UARTn interrupt sources are listed as follows: • UART_AT_CMD_CHAR_DET_INT: Triggered when the receiver detects an AT_CMD character. • UART_RS485_CLASH_INT: Triggered when a collision is detected between the transmitter and the receiver in RS485 mode. • UART_RS485_FRM_ERR_INT: Triggered when an error is detected in the data frame sent by the transmitter in RS485 mode. Espressif Systems 844 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) • UART_RS485_PARITY_ERR_INT: Triggered when an error is detected in the parity bit sent by the transmitter in RS485 mode. • UART_TX_DONE_INT: Triggered when all data in the transmitter’s TX FIFO has been sent. • UART_TX_BRK_IDLE_DONE_INT: Triggered when the transmitter stays idle for the minimum interval (threshold) after sending the last data bit. • UART_TX_BRK_DONE_INT: Triggered when the transmitter has sent all NULL characters after all data in TX FIFO had been sent. • UART_GLITCH_DET_INT: Triggered when the receiver detects a glitch in the middle of the start bit. • UART_SW_XOFF_INT: Triggered when UART_SW_FLOW_CON_EN is set and the receiver receives a XOFF character. • UART_SW_XON_INT: Triggered when UART_SW_FLOW_CON_EN is set and the receiver receives a XON character. • UART_RXFIFO_TOUT_INT: Triggered when the receiver has received at least one byte, and the bus remains idle for UART_RX_TOUT_THRHD bit time. • UART_BRK_DET_INT: Triggered when the receiver detects a NULL character (i.e., logic 0 for one NULL character transmission) after stop bits. • UART_CTS_CHG_INT: Triggered when the receiver detects an edge change of CTSn signals. • UART_DSR_CHG_INT: Triggered when the receiver detects an edge change of DSRn signals. • UART_RXFIFO_OVF_INT: Triggered when the amount of data received by the receiver exceeds the storage capacity of the FIFO. • UART_FRM_ERR_INT: Triggered when the receiver detects a data frame error. • UART_PARITY_ERR_INT: Triggered when the receiver detects a parity error. • UART_TXFIFO_EMPTY_INT: Triggered when TX FIFO stores less data than what UART_TXFIFO_EMPTY_THRHD specifies. • UART_RXFIFO_FULL_INT: Triggered when the receiver receives more data than what UART_RXFIFO_FULL_THRHD specifies. • UART_WAKEUP_INT: Triggered when UART is woken up. UHCI interrupt sources are listed as follows: • UHCI_APP_CTRL1_INT: Triggered when software sets UHCI_APP_CTRL1_INT_RAW. • UHCI_APP_CTRL0_INT: Triggered when software sets UHCI_APP_CTRL0_INT_RAW. • UHCI_OUTLINK_EOF_ERR_INT: Triggered when an EOF error is detected in a transmit descriptor. • UHCI_SEND_A_REG_Q_INT: Triggered when UHCI has sent a series of short packets using always_send. • UHCI_SEND_S_REG_Q_INT: Triggered when UHCI has sent a series of short packets using single_send. • UHCI_TX_HUNG_INT: Triggered when UHCI takes too long to read RAM using a GDMA transmit channel. • UHCI_RX_HUNG_INT: Triggered when UHCI takes too long to receive data using a GDMA receive channel. • UHCI_TX_START_INT: Triggered when GDMA detects a separator character. Espressif Systems 845 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) • UHCI_RX_START_INT: Triggered when a separator character has been sent. Each interrupt source can be configured by a common set of registers that are described in Section Interrupt Configuration Registers. The specific registers can be found in Section 28.7 Register Summary. 28.6 Programming Procedures 28.6.1 Register Type All UART registers are in the APB_CLK domain. UART configuration registers can be classified into two groups. One group of registers are read in the APB_CLK or AHB_CLK domains, so once such registers are configured no extra operations are required. The other group of registers are read in the UART_SCLK domain, and therefore need to implement the clock domain crossing design. Once these registers are configured, the configured values need to be synchronized to the UART Core’s clock domain by writing to UART_REG_UPDATE. Once all values have been synchronized, UART_REG_UPDATE will be automatically cleared by hardware. After configuring registers that need synchronization, it is recommended to check whether UART_REG_UPDATE is 0. This is to ensure that register values configured before have already been synchronized. To distinguish between these two groups of registers easily, all registers that implement the clock domain crossing design have the _SYNC suffix, and are put together in Section 28.7. Those without the _SYNC suffix in Section 28.7 are configuration registers that require no clock domain crossing. Espressif Systems 846 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) 28.6.2 Detailed Steps Figure 28.6-1 illustrates the process to program UART controllers, namely initialize UART, configure registers, enable the UART transmitter or receiver, and finish data transmission. Figure 28.6-1. UART Programming Procedures 28.6.2.1 Initializing UARTn To initialize UARTn: • Write 1 to HP_SYS_CLKRST_RST_EN_UARTn_APB. • Clear HP_SYS_CLKRST_RST_EN_UARTn_APB to 0. • Write 1 to HP_SYS_CLKRST_RST_EN_UARTn_CORE. • Clear HP_SYS_CLKRST_RST_EN_UARTn_CORE to 0. 28.6.2.2 Configuring UARTn Communication To configure UARTn communication: • Wait for UART_REG_UPDATE to become 0, which indicates the completion of the last synchronization. • Select the clock source via HP_SYS_CLKRST_UARTn_CLK_SRC_SEL. • Configure divisor of the divider via HP_SYS_CLKRST_UARTn_SCLK_DIV_NUM, HP_SYS_CLKRST_UARTn_SCLK_DIV_DENOMINATOR, and Espressif Systems 847 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) HP_SYS_CLKRST_UARTn_SCLK_DIV_NUMERATOR. • Configure the baud rate for transmission via UART_CLKDIV and UART_CLKDIV_FRAG. • Configure data length via UART_BIT_NUM. • Configure odd or even parity check via UART_PARITY_EN and UART_PARITY. • Optional steps depending on application ... • Synchronize the configured values to the Core Clock domain by writing 1 to UART_REG_UPDATE. 28.6.2.3 Enabling UARTn To enable UARTn transmitter: • Configure TX FIFO’s empty threshold via UART_TXFIFO_EMPTY_THRHD. • Disable UART_TXFIFO_EMPTY_INT interrupt by clearing UART_TXFIFO_EMPTY_INT_ENA. • Write data to be sent to UART_RXFIFO_RD_BYTE. • Clear UART_TXFIFO_EMPTY_INT interrupt by setting UART_TXFIFO_EMPTY_INT_CLR. • Enable UART_TXFIFO_EMPTY_INT interrupt by setting UART_TXFIFO_EMPTY_INT_ENA. • Check UART_TXFIFO_EMPTY_INT_ST and wait for the completion of data transmission. To enable UARTn receiver: • Configure RX FIFO’s full threshold via UART_RXFIFO_FULL_THRHD. • Enable UART_RXFIFO_FULL_INT interrupt by setting UART_RXFIFO_FULL_INT_ENA. • Check UART_RXFIFO_FULL_INT_ST and wait until the RX FIFO is full. • Read data from RX FIFO via UART_RXFIFO_RD_BYTE, and obtain the number of bytes received in RX FIFO via UART_RXFIFO_CNT. Espressif Systems 848 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) 28.7 Register Summary 28.7.1 UART Register Summary The addresses in this section are relative to UART Controller base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access FIFO Configuration Register UART_FIFO_REG FIFO data register 0x0000 RO UART_TOUT_CONF_SYNC_REG UART threshold and allocation configuration 0x0064 R/W UART Interrupt Register UART_INT_RAW_REG Raw interrupt status 0x0004 R/WTC/SS UART_INT_ST_REG Masked interrupt status 0x0008 RO UART_INT_ENA_REG Interrupt enable bits 0x000C R/W UART_INT_CLR_REG Interrupt clear bits 0x0010 WT Configuration Register UART_CLKDIV_SYNC_REG Clock divider configuration 0x0014 R/W UART_RX_FILT_REG RX filter configuration 0x0018 R/W UART_CONF0_SYNC_REG Configuration register 0 0x0020 R/W UART_CONF1_REG Configuration register 1 0x0024 R/W UART_HWFC_CONF_SYNC_REG Hardware flow control configuration 0x002C R/W UART_SLEEP_CONF0_REG UART sleep configuration register 0 0x0030 R/W UART_SLEEP_CONF1_REG UART sleep configuration register 1 0x0034 R/W UART_SLEEP_CONF2_REG UART sleep configuration register 2 0x0038 R/W UART_SWFC_CONF0_SYNC_REG Software flow control character configuration 0x003C varies UART_SWFC_CONF1_REG Software flow control character configuration 0x0040 R/W UART_TXBRK_CONF_SYNC_REG TX break character configuration 0x0044 R/W UART_IDLE_CONF_SYNC_REG Frame end idle time configuration 0x0048 R/W UART_RS485_CONF_SYNC_REG RS485 mode configuration 0x004C R/W UART_CLK_CONF_REG UART core clock configuration 0x0088 R/W UART_REG_UPDATE_REG UART register configuration update 0x0098 R/W/SC UART_ID_REG UART ID register 0x009C R/W Status Register UART_STATUS_REG UART status register 0x001C RO UART_MEM_TX_STATUS_REG TX FIFO write and read offset address 0x0068 RO UART_MEM_RX_STATUS_REG Rx FIFO write and read offset address 0x006C RO UART_FSM_STATUS_REG UART transmit and receive status 0x0070 RO UART_AFIFO_STATUS_REG UART asynchronous FIFO status 0x0090 RO AT Escape Sequence Selection Configuration Register UART_AT_CMD_PRECNT_SYNC_REG Pre-sequence timing configuration 0x0050 R/W UART_AT_CMD_POSTCNT_SYNC_REG Post-sequence timing configuration 0x0054 R/W UART_AT_CMD_GAPTOUT_SYNC_REG Timeout configuration 0x0058 R/W Espressif Systems 849 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Name Description Address Access UART_AT_CMD_CHAR_SYNC_REG AT escape sequence detection configuration 0x005C R/W Autobaud Register UART_POSPULSE_REG Autobaud high pulse register 0x0074 RO UART_NEGPULSE_REG Autobaud low pulse register 0x0078 RO UART_LOWPULSE_REG Autobaud minimum low pulse duration register 0x007C RO UART_HIGHPULSE_REG Autobaud minimum high pulse duration register 0x0080 RO UART_RXD_CNT_REG Autobaud edge change count register 0x0084 RO Version Register UART_DATE_REG UART version control register 0x008C R/W 28.7.2 LP UART Register Summary The addresses in this section are relative to LP UART base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access FIFO Configuration Register LP_UART_FIFO_REG FIFO data register 0x0000 RO LP_UART_TOUT_CONF_SYNC_REG LP UART threshold and allocation configu- ration 0x0064 R/W LP UART Interrupt Register LP_UART_INT_RAW_REG Raw interrupt status 0x0004 R/WTC/SS LP_UART_INT_ST_REG Masked interrupt status 0x0008 RO LP_UART_INT_ENA_REG Interrupt enable bits 0x000C R/W LP_UART_INT_CLR_REG Interrupt clear bits 0x0010 WT Configuration Register LP_UART_CLKDIV_SYNC_REG Clock divider configuration 0x0014 R/W LP_UART_RX_FILT_REG RX filter configuration 0x0018 R/W LP_UART_CONF0_SYNC_REG Configuration register 0 0x0020 R/W LP_UART_CONF1_REG Configuration register 1 0x0024 R/W LP_UART_HWFC_CONF_SYNC_REG Hardware flow control configuration 0x002C R/W LP_UART_SLEEP_CONF0_REG LP UART sleep configuration register 0 0x0030 R/W LP_UART_SLEEP_CONF1_REG LP UART sleep configuration register 1 0x0034 R/W LP_UART_SLEEP_CONF2_REG LP UART sleep configuration register 2 0x0038 R/W LP_UART_SWFC_CONF0_SYNC_REG Software flow control character configura- tion 0x003C varies LP_UART_SWFC_CONF1_REG Software flow control character configura- tion 0x0040 R/W LP_UART_TXBRK_CONF_SYNC_REG TX break character configuration 0x0044 R/W LP_UART_IDLE_CONF_SYNC_REG Frame end idle time configuration 0x0048 R/W LP_UART_DELAY_CONF_SYNC_REG RS485 mode configuration 0x004C R/W LP_UART_CLK_CONF_REG LP UART core clock configuration 0x0088 R/W Espressif Systems 850 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Name Description Address Access LP_UART_REG_UPDATE_REG LP UART register configuration update reg- ister 0x0098 R/W/SC LP_UART_ID_REG LP UART ID register 0x009C R/W Status Register LP_UART_STATUS_REG LP UART status register 0x001C RO LP_UART_MEM_TX_STATUS_REG TX FIFO write and read offset address 0x0068 RO LP_UART_MEM_RX_STATUS_REG RX FIFO write and read offset address 0x006C RO LP_UART_FSM_STATUS_REG LP UART transmit and receive status 0x0070 RO LP_UART_AFIFO_STATUS_REG LP UART asynchronous FIFO Status 0x0090 RO AT Escape Sequence Selection Configuration Register LP_UART_AT_CMD_PRECNT_SYNC_REG Pre-sequence timing configuration 0x0050 R/W LP_UART_AT_CMD_POSTCNT_SYNC_REG Post-sequence timing configuration 0x0054 R/W LP_UART_AT_CMD_GAPTOUT_SYNC_REG Timeout configuration 0x0058 R/W LP_UART_AT_CMD_CHAR_SYNC_REG AT escape sequence detection configura- tion 0x005C R/W Version Register LP_UART_DATE_REG LP UART version register 0x008C R/W 28.7.3 UHCI Register Summary The addresses in this section are relative to UHCI base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Configuration Register UHCI_CONF0_REG UHCI configuration register 0x0000 R/W UHCI_CONF1_REG UHCI configuration register 0x0014 varies UHCI_ESCAPE_CONF_REG Escape character configuration 0x0020 R/W UHCI_HUNG_CONF_REG Timeout configuration 0x0024 R/W UHCI_ACK_NUM_REG UHCI ACK number configuration 0x0028 varies UHCI_QUICK_SENT_REG UHCI quick send configuration register 0x0030 varies UHCI_REG_Q0_WORD0_REG Q0 WORD0 quick send register 0x0034 R/W UHCI_REG_Q0_WORD1_REG Q0 WORD1 quick send register 0x0038 R/W UHCI_REG_Q1_WORD0_REG Q1 WORD0 quick send register 0x003C R/W UHCI_REG_Q1_WORD1_REG Q1 WORD1 quick send register 0x0040 R/W UHCI_REG_Q2_WORD0_REG Q2 WORD0 quick send register 0x0044 R/W UHCI_REG_Q2_WORD1_REG Q2 WORD1 quick send register 0x0048 R/W UHCI_REG_Q3_WORD0_REG Q3 WORD0 quick send register 0x004C R/W UHCI_REG_Q3_WORD1_REG Q3 WORD1 quick send register 0x0050 R/W UHCI_REG_Q4_WORD0_REG Q4 WORD0 quick send register 0x0054 R/W UHCI_REG_Q4_WORD1_REG Q4 WORD1 quick send register 0x0058 R/W UHCI_REG_Q5_WORD0_REG Q5 WORD0 quick send register 0x005C R/W Espressif Systems 851 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Name Description Address Access UHCI_REG_Q5_WORD1_REG Q5 WORD1 quick send register 0x0060 R/W UHCI_REG_Q6_WORD0_REG Q6 WORD0 quick send register 0x0064 R/W UHCI_REG_Q6_WORD1_REG Q6 WORD1 quick register 0x0068 R/W UHCI_ESC_CONF0_REG Escape sequence configuration register 0 0x006C R/W UHCI_ESC_CONF1_REG Escape sequence configuration register 1 0x0070 R/W UHCI_ESC_CONF2_REG Escape sequence configuration register 2 0x0074 R/W UHCI_ESC_CONF3_REG Escape sequence configuration register 3 0x0078 R/W UHCI_PKT_THRES_REG Configuration register for packet length 0x007C R/W UHCI Interrupt Register UHCI_INT_RAW_REG Raw interrupt status 0x0004 varies UHCI_INT_ST_REG Masked interrupt status 0x0008 RO UHCI_INT_ENA_REG Interrupt enable bits 0x000C R/W UHCI_INT_CLR_REG Interrupt clear bits 0x0010 WT UHCI Status Register UHCI_STATE0_REG UHCI receive status 0x0018 RO UHCI_STATE1_REG UHCI transmit status 0x001C RO UHCI_RX_HEAD_REG UHCI packet header register 0x002C RO Version Register UHCI_DATE_REG UHCI version control register 0x0080 R/W Espressif Systems 852 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) 28.8 Registers 28.8.1 UART Registers The addresses in this section are relative to UART Controller base address provided in Table 4.3-2 in Chapter 4 System and Memory. For how to program reserved fields, please refer to Section Programming Reserved Register Field. Register 28.1. UART_FIFO_REG (0x0000) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 UART_RXFIFO_RD_BYTE 0 7 0 Reset UART_RXFIFO_RD_BYTE Represents the data UARTn reads from FIFO. Measurement unit: byte. (RO) Register 28.2. UART_TOUT_CONF_SYNC_REG (0x0064) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 12 UART_RX_TOUT_THRHD 0xa 11 2 UART_RX_TOUT_FLOW_DIS 0 1 UART_RX_TOUT_EN 0 0 Reset UART_RX_TOUT_EN Configures whether or not to enable UART receiver’s timeout function. 0: Disable 1: Enable (R/W) UART_RX_TOUT_FLOW_DIS Configures whether or not to disable the idle status counter when hardware flow control is enabled. 0: Enable 1: Disable (R/W) UART_RX_TOUT_THRHD Configures the amount of time that the bus can remain idle before timeout. Measurement unit: bit time (the time to transmit 1 bit). (R/W) Espressif Systems 853 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.3. UART_INT_RAW_REG (0x0004) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 31 20 UART_WAKEUP_INT_RAW 0 19 UART_AT_CMD_CHAR_DET_INT_RAW 0 18 UART_RS485_CLASH_INT_RAW 0 17 UART_RS485_FRM_ERR_INT_RAW 0 16 UART_RS485_PARITY_ERR_INT_RAW 0 15 UART_TX_DONE_INT_RAW 0 14 UART_TX_BRK_IDLE_DONE_INT_RAW 0 13 UART_TX_BRK_DONE_INT_RAW 0 12 UART_GLITCH_DET_INT_RAW 0 11 UART_SW_XOFF_INT_RAW 0 10 UART_SW_XON_INT_RAW 0 9 UART_RXFIFO_TOUT_INT_RAW 0 8 UART_BRK_DET_INT_RAW 0 7 UART_CTS_CHG_INT_RAW 0 6 UART_DSR_CHG_INT_RAW 0 5 UART_RXFIFO_OVF_INT_RAW 0 4 UART_FRM_ERR_INT_RAW 0 3 UART_PARITY_ERR_INT_RAW 0 2 UART_TXFIFO_EMPTY_INT_RAW 1 1 UART_RXFIFO_FULL_INT_RAW 0 0 Reset UART_RXFIFO_FULL_INT_RAW The raw interrupt status of UART_RXFIFO_FULL_INT. (R/WTC/SS) UART_TXFIFO_EMPTY_INT_RAW The raw interrupt status of UART_TXFIFO_EMPTY_INT. (R/WTC/SS) UART_PARITY_ERR_INT_RAW The raw interrupt status of UART_PARITY_ERR_INT. (R/WTC/SS) UART_FRM_ERR_INT_RAW The raw interrupt status of UART_FRM_ERR_INT. (R/WTC/SS) UART_RXFIFO_OVF_INT_RAW The raw interrupt status of UART_RXFIFO_OVF_INT. (R/WTC/SS) UART_DSR_CHG_INT_RAW The raw interrupt status of UART_DSR_CHG_INT. (R/WTC/SS) UART_CTS_CHG_INT_RAW The raw interrupt status of UART_CTS_CHG_INT. (R/WTC/SS) UART_BRK_DET_INT_RAW The raw interrupt status of UART_BRK_DET_INT. (R/WTC/SS) UART_RXFIFO_TOUT_INT_RAW The raw interrupt status of UART_RXFIFO_TOUT_INT. (R/WTC/SS) UART_SW_XON_INT_RAW The raw interrupt status of UART_SW_XON_INT. (R/WTC/SS) UART_SW_XOFF_INT_RAW UART_SW_XOFF_INT. (R/WTC/SS) UART_GLITCH_DET_INT_RAW The raw interrupt status of UART_GLITCH_DET_INT. (R/WTC/SS) UART_TX_BRK_DONE_INT_RAW The raw interrupt status of UART_TX_BRK_DONE_INT. (R/WTC/SS) UART_TX_BRK_IDLE_DONE_INT_RAW The raw interrupt status of UART_TX_BRK_IDLE_DONE_INT. (R/WTC/SS) UART_TX_DONE_INT_RAW The raw interrupt status of UART_TX_DONE_INT. (R/WTC/SS) UART_RS485_PARITY_ERR_INT_RAW The raw interrupt status of UART_RS485_PARITY_ERR_INT. (R/WTC/SS) UART_RS485_FRM_ERR_INT_RAW The raw interrupt status of UART_RS485_FRM_ERR_INT. (R/WTC/SS) Continued on the next page... Espressif Systems 854 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.3. UART_INT_RAW_REG (0x0004) Continued from the previous page... UART_RS485_CLASH_INT_RAW The raw interrupt status of UART_RS485_CLASH_INT. (R/WTC/SS) UART_AT_CMD_CHAR_DET_INT_RAW The raw interrupt status of UART_AT_CMD_CHAR_DET_INT. (R/WTC/SS) UART_WAKEUP_INT_RAW The raw interrupt status of UART_WAKEUP_INT. (R/WTC/SS) Espressif Systems 855 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.4. UART_INT_ST_REG (0x0008) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 31 20 UART_WAKEUP_INT_ST 0 19 UART_AT_CMD_CHAR_DET_INT_ST 0 18 UART_RS485_CLASH_INT_ST 0 17 UART_RS485_FRM_ERR_INT_ST 0 16 UART_RS485_PARITY_ERR_INT_ST 0 15 UART_TX_DONE_INT_ST 0 14 UART_TX_BRK_IDLE_DONE_INT_ST 0 13 UART_TX_BRK_DONE_INT_ST 0 12 UART_GLITCH_DET_INT_ST 0 11 UART_SW_XOFF_INT_ST 0 10 UART_SW_XON_INT_ST 0 9 UART_RXFIFO_TOUT_INT_ST 0 8 UART_BRK_DET_INT_ST 0 7 UART_CTS_CHG_INT_ST 0 6 UART_DSR_CHG_INT_ST 0 5 UART_RXFIFO_OVF_INT_ST 0 4 UART_FRM_ERR_INT_ST 0 3 UART_PARITY_ERR_INT_ST 0 2 UART_TXFIFO_EMPTY_INT_ST 0 1 UART_RXFIFO_FULL_INT_ST 0 0 Reset UART_RXFIFO_FULL_INT_ST The masked interrupt status of UART_RXFIFO_FULL_INT.(RO) UART_TXFIFO_EMPTY_INT_ST The masked interrupt status of UART_TXFIFO_EMPTY_INT. (RO) UART_PARITY_ERR_INT_ST The masked interrupt status of UART_PARITY_ERR_INT. (RO) UART_FRM_ERR_INT_ST The masked interrupt status of UART_FRM_ERR_INT. (RO) UART_RXFIFO_OVF_INT_ST The masked interrupt status of UART_RXFIFO_OVF_INT. (RO) UART_DSR_CHG_INT_ST The masked interrupt status of UART_DSR_CHG_INT. (RO) UART_CTS_CHG_INT_ST The masked interrupt status of UART_CTS_CHG_INT. (RO) UART_BRK_DET_INT_ST The masked interrupt status of UART_BRK_DET_INT. (RO) UART_RXFIFO_TOUT_INT_ST The masked interrupt status of UART_RXFIFO_TOUT_INT. (RO) UART_SW_XON_INT_ST The masked interrupt status of UART_SW_XON_INT. (RO) UART_SW_XOFF_INT_ST The masked interrupt status of UART_SW_XOFF_INT. (RO) UART_GLITCH_DET_INT_ST The masked interrupt status of UART_GLITCH_DET_INT. (RO) UART_TX_BRK_DONE_INT_ST The masked interrupt status of UART_TX_BRK_DONE_INT. (RO) UART_TX_BRK_IDLE_DONE_INT_ST The masked interrupt status of UART_TX_BRK_IDLE_DONE_INT. (RO) UART_TX_DONE_INT_ST The masked interrupt status of UART_TX_DONE_INT. (RO) UART_RS485_PARITY_ERR_INT_ST The masked interrupt status of UART_RS485_PARITY_ERR_INT. (RO) UART_RS485_FRM_ERR_INT_ST The masked interrupt status of UART_RS485_FRM_ERR_INT. (RO) UART_RS485_CLASH_INT_ST The masked interrupt status of UART_RS485_CLASH_INT. (RO) UART_AT_CMD_CHAR_DET_INT_ST The masked interrupt status of UART_AT_CMD_CHAR_DET_INT. (RO) UART_WAKEUP_INT_ST The masked interrupt status of UART_WAKEUP_INT. (RO) Espressif Systems 856 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.5. UART_INT_ENA_REG (0x000C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 31 20 UART_WAKEUP_INT_ENA 0 19 UART_AT_CMD_CHAR_DET_INT_ENA 0 18 UART_RS485_CLASH_INT_ENA 0 17 UART_RS485_FRM_ERR_INT_ENA 0 16 UART_RS485_PARITY_ERR_INT_ENA 0 15 UART_TX_DONE_INT_ENA 0 14 UART_TX_BRK_IDLE_DONE_INT_ENA 0 13 UART_TX_BRK_DONE_INT_ENA 0 12 UART_GLITCH_DET_INT_ENA 0 11 UART_SW_XOFF_INT_ENA 0 10 UART_SW_XON_INT_ENA 0 9 UART_RXFIFO_TOUT_INT_ENA 0 8 UART_BRK_DET_INT_ENA 0 7 UART_CTS_CHG_INT_ENA 0 6 UART_DSR_CHG_INT_ENA 0 5 UART_RXFIFO_OVF_INT_ENA 0 4 UART_FRM_ERR_INT_ENA 0 3 UART_PARITY_ERR_INT_ENA 0 2 UART_TXFIFO_EMPTY_INT_ENA 0 1 UART_RXFIFO_FULL_INT_ENA 0 0 Reset UART_RXFIFO_FULL_INT_ENA Write 1 to enable UART_RXFIFO_FULL_INT. (R/W) UART_TXFIFO_EMPTY_INT_ENA Write 1 to enable UART_TXFIFO_EMPTY_INT. (R/W) UART_PARITY_ERR_INT_ENA Write 1 to enable UART_PARITY_ERR_INT. (R/W) UART_FRM_ERR_INT_ENA Write 1 to enable UART_FRM_ERR_INT. (R/W) UART_RXFIFO_OVF_INT_ENA Write 1 to enable UART_RXFIFO_OVF_INT. (R/W) UART_DSR_CHG_INT_ENA Write 1 to enable UART_DSR_CHG_INT. (R/W) UART_CTS_CHG_INT_ENA Write 1 to enable UART_CTS_CHG_INT. (R/W) UART_BRK_DET_INT_ENA Write 1 to enable UART_BRK_DET_INT. (R/W) UART_RXFIFO_TOUT_INT_ENA Write 1 to enable UART_RXFIFO_TOUT_INT. (R/W) UART_SW_XON_INT_ENA Write 1 to enable UART_SW_XON_INT.(R/W) UART_SW_XOFF_INT_ENA Write 1 to enable UART_SW_XOFF_INT. (R/W) UART_GLITCH_DET_INT_ENA Write 1 to enable UART_GLITCH_DET_INT. (R/W) UART_TX_BRK_DONE_INT_ENA Write 1 to enable UART_TX_BRK_DONE_INT. (R/W) UART_TX_BRK_IDLE_DONE_INT_ENA Write 1 to enable UART_TX_BRK_IDLE_DONE_INT. (R/W) UART_TX_DONE_INT_ENA Write 1 to enable UART_TX_DONE_INT. (R/W) UART_RS485_PARITY_ERR_INT_ENA Write 1 to enable UART_RS485_PARITY_ERR_INT. (R/W) UART_RS485_FRM_ERR_INT_ENA Write 1 to enable UART_RS485_FRM_ERR_INT. (R/W) UART_RS485_CLASH_INT_ENA Write 1 to enable UART_RS485_CLASH_INT. (R/W) UART_AT_CMD_CHAR_DET_INT_ENA Write 1 to enable UART_AT_CMD_CHAR_DET_INT. (R/W) UART_WAKEUP_INT_ENA Write 1 to enable UART_WAKEUP_INT. (R/W) Espressif Systems 857 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.6. UART_INT_CLR_REG (0x0010) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 31 20 UART_WAKEUP_INT_CLR 0 19 UART_AT_CMD_CHAR_DET_INT_CLR 0 18 UART_RS485_CLASH_INT_CLR 0 17 UART_RS485_FRM_ERR_INT_CLR 0 16 UART_RS485_PARITY_ERR_INT_CLR 0 15 UART_TX_DONE_INT_CLR 0 14 UART_TX_BRK_IDLE_DONE_INT_CLR 0 13 UART_TX_BRK_DONE_INT_CLR 0 12 UART_GLITCH_DET_INT_CLR 0 11 UART_SW_XOFF_INT_CLR 0 10 UART_SW_XON_INT_CLR 0 9 UART_RXFIFO_TOUT_INT_CLR 0 8 UART_BRK_DET_INT_CLR 0 7 UART_CTS_CHG_INT_CLR 0 6 UART_DSR_CHG_INT_CLR 0 5 UART_RXFIFO_OVF_INT_CLR 0 4 UART_FRM_ERR_INT_CLR 0 3 UART_PARITY_ERR_INT_CLR 0 2 UART_TXFIFO_EMPTY_INT_CLR 0 1 UART_RXFIFO_FULL_INT_CLR 0 0 Reset UART_RXFIFO_FULL_INT_CLR Write 1 to clear UART_RXFIFO_FULL_INT. (WT) UART_TXFIFO_EMPTY_INT_CLR Write 1 to clear UART_TXFIFO_EMPTY_INT. (WT) UART_PARITY_ERR_INT_CLR Write 1 to clear UART_PARITY_ERR_INT. (WT) UART_FRM_ERR_INT_CLR Write 1 to clear UART_FRM_ERR_INT. (WT) UART_RXFIFO_OVF_INT_CLR Write 1 to clear UART_RXFIFO_OVF_INT. (WT) UART_DSR_CHG_INT_CLR Write 1 to clear UART_DSR_CHG_INT. (WT) UART_CTS_CHG_INT_CLR Write 1 to clear UART_CTS_CHG_INT. (WT) UART_BRK_DET_INT_CLR Write 1 to clear UART_BRK_DET_INT. (WT) UART_RXFIFO_TOUT_INT_CLR Write 1 to clear UART_RXFIFO_TOUT_INT. (WT) UART_SW_XON_INT_CLR Write 1 to clear UART_SW_XON_INT. (WT) UART_SW_XOFF_INT_CLR Write 1 to clear UART_SW_XOFF_INT. (WT) UART_GLITCH_DET_INT_CLR Write 1 to clear UART_GLITCH_DET_INT. (WT) UART_TX_BRK_DONE_INT_CLR Write 1 to clear UART_TX_BRK_DONE_INT. (WT) UART_TX_BRK_IDLE_DONE_INT_CLR Write 1 to clear UART_TX_BRK_IDLE_DONE_INT. (WT) UART_TX_DONE_INT_CLR Write 1 to clear UART_TX_DONE_INT. (WT) UART_RS485_PARITY_ERR_INT_CLR Write 1 to clear UART_RS485_PARITY_ERR_INT. (WT) UART_RS485_FRM_ERR_INT_CLR Write 1 to clear UART_RS485_FRM_ERR_INT. (WT) UART_RS485_CLASH_INT_CLR Write 1 to clear UART_RS485_CLASH_INT. (WT) UART_AT_CMD_CHAR_DET_INT_CLR Write 1 to clear UART_AT_CMD_CHAR_DET_INT. (WT) UART_WAKEUP_INT_CLR Write 1 to clear UART_WAKEUP_INT. (WT) Espressif Systems 858 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.7. UART_CLKDIV_SYNC_REG (0x0014) (reserved) 0 0 0 0 0 0 0 0 31 24 UART_CLKDIV_FRAG 0x0 23 20 (reserved) 0 0 0 0 0 0 0 0 19 12 UART_CLKDIV 0x2b6 11 0 Reset UART_CLKDIV Configures the integral part of the divisor for baud rate generation. (R/W) UART_CLKDIV_FRAG Configures the fractional part of the divisor for baud rate generation. (R/W) Register 28.8. UART_RX_FILT_REG (0x0018) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 9 UART_GLITCH_FILT_EN 0 8 UART_GLITCH_FILT 0x8 7 0 Reset UART_GLITCH_FILT Configures the width of a pulse to be filtered. Measurement unit: UART Core’s clock cycle. Pulses whose width is lower than this value will be ignored. (R/W) UART_GLITCH_FILT_EN Configures whether or not to enable RX signal filter. 0: Disable 1: Enable (R/W) Espressif Systems 859 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.9. UART_CONF0_SYNC_REG (0x0020) (reserved) 0 0 0 0 0 0 0 0 31 24 UART_TXFIFO_RST 0 23 UART_RXFIFO_RST 0 22 UART_SW_RTS 0 21 UART_MEM_CLK_EN 0 20 UART_AUTOBAUD_EN 0 19 UART_ERR_WR_MASK 0 18 UART_DIS_RX_DAT_OVF 0 17 UART_TXD_INV 0 16 UART_RXD_INV 0 15 UART_IRDA_EN 0 14 UART_TX_FLOW_EN 0 13 UART_LOOPBACK 0 12 UART_IRDA_RX_INV 0 11 UART_IRDA_TX_INV 0 10 UART_IRDA_WCTL 0 9 UART_IRDA_TX_EN 0 8 UART_IRDA_DPLX 0 7 UART_TXD_BRK 0 6 UART_STOP_BIT_NUM 1 5 4 UART_BIT_NUM 3 3 2 UART_PARITY_EN 0 1 UART_PARITY 0 0 Reset UART_PARITY Configures the parity check mode. 0: Even parity 1: Odd parity (R/W) UART_PARITY_EN Configures whether or not to enable UART parity check. 0: Disable 1: Enable (R/W) UART_BIT_NUM Configures the number of data bits. 0: 5 bits 1: 6 bits 2: 7 bits 3: 8 bits (R/W) UART_STOP_BIT_NUM Configures the number of stop bits. 0: Invalid. No effect 1: 1 bit 2: 1.5 bits 3: 2 bits (R/W) UART_TXD_BRK Configures whether or not to send NULL characters when finishing data transmis- sion. 0: Not send 1: Send (R/W) UART_IRDA_DPLX Configures whether or not to enable IrDA loopback test. 0: Disable 1: Enable (R/W) UART_IRDA_TX_EN Configures whether or not to enable the IrDA transmitter. 0: Disable 1: Enable (R/W) Continued on the next page... Espressif Systems 860 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.9. UART_CONF0_SYNC_REG (0x0020) Continued from the previous page... UART_IRDA_WCTL Configures the 11th bit of the IrDA transmitter. 0: This bit is 0. 1: This bit is the same as the 10th bit. (R/W) UART_IRDA_TX_INV Configures whether or not to invert the level of the IrDA transmitter. 0: Not invert 1: Invert (R/W) UART_IRDA_RX_INV Configures whether or not to invert the level of the IrDA receiver. 0: Not invert 1: Invert (R/W) UART_LOOPBACK Configures whether or not to enable UART loopback test. 0: Disable 1: Enable (R/W) UART_TX_FLOW_EN Configures whether or not to enable flow control for the transmitter. 0: Disable 1: Enable (R/W) UART_IRDA_EN Configures whether or not to enable IrDA protocol. 0: Disable 1: Enable (R/W) UART_RXD_INV Configures whether or not to invert the level of UART RXD signal. 0: Not invert 1: Invert (R/W) UART_TXD_INV Configures whether or not to invert the level of UART TXD signal. 0: Not invert 1: Invert (R/W) UART_DIS_RX_DAT_OVF Configures whether or not to disable data overflow detection for the UART receiver. 0: Enable 1: Disable (R/W) Continued on the next page... Espressif Systems 861 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.9. UART_CONF0_SYNC_REG (0x0020) Continued from the previous page... UART_ERR_WR_MASK Configures whether or not to store the received data with errors into FIFO. 0: Store 1: Not store (R/W) UART_AUTOBAUD_EN Configures whether or not to enable baud rate detection. 0: Disable 1: Enable (R/W) UART_MEM_CLK_EN Configures whether or not to enable clock gating for UART memory. 0: Disable 1: Enable (R/W) UART_SW_RTS Configures the RTS signal used in software flow control. 0: The UART transmitter is not allowed to send data. 1: The UART transmitted is allowed to send data. (R/W) UART_RXFIFO_RST Configures whether or not to reset the UART RX FIFO. 0: Not reset 1: Reset (R/W) UART_TXFIFO_RST Configures whether or not to reset the UART TX FIFO. 0: Not reset 1: Reset (R/W) Espressif Systems 862 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.10. UART_CONF1_REG (0x0024) (reserved) 0 0 0 0 0 0 0 0 0 0 31 22 UART_CLK_EN 0 21 UART_SW_DTR 0 20 UART_DTR_INV 0 19 UART_RTS_INV 0 18 UART_DSR_INV 0 17 UART_CTS_INV 0 16 UART_TXFIFO_EMPTY_THRHD 0x60 15 8 UART_RXFIFO_FULL_THRHD 0x60 7 0 Reset UART_RXFIFO_FULL_THRHD Configures the threshold for RX FIFO being full. Measurement unit: byte. (R/W) UART_TXFIFO_EMPTY_THRHD Configures the threshold for TX FIFO being empty. Measurement unit: byte. (R/W) UART_CTS_INV Configures whether or not to invert the level of UART CTS signal. 0: Not invert 1: Invert (R/W) UART_DSR_INV Configures whether or not to invert the level of UART DSR signal. 0: Not invert 1: Invert (R/W) UART_RTS_INV Configures whether or not to invert the level of UART RTS signal. 0: Not invert 1: Invert (R/W) UART_DTR_INV Configures whether or not to invert the level of UART DTR signal. 0: Not invert 1: Invert (R/W) UART_SW_DTR Configures the DTR signal used in software flow control. 0: Data to be transmitted is not ready. 1: Data to be transmitted is ready. (R/W) UART_CLK_EN Configures clock gating. 0: Support clock only when the application writes registers. 1: Always force the clock on for registers. (R/W) Espressif Systems 863 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.11. UART_HWFC_CONF_SYNC_REG (0x002C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 9 UART_RX_FLOW_EN 0 8 UART_RX_FLOW_THRHD 0x0 7 0 Reset UART_RX_FLOW_THRHD Configures the maximum number of data bytes that can be received dur- ing hardware flow control. Measurement unit: byte. (R/W) UART_RX_FLOW_EN Configures whether or not to enable the UART receiver. 0: Disable 1: Enable (R/W) Register 28.12. UART_SLEEP_CONF0_REG (0x0030) UART_WK_CHAR4 0x0 31 24 UART_WK_CHAR3 0x0 23 16 UART_WK_CHAR2 0x0 15 8 UART_WK_CHAR1 0x0 7 0 Reset UART_WK_CHAR1 Configures wakeup character 1. (R/W) UART_WK_CHAR2 Configures wakeup character 2. (R/W) UART_WK_CHAR3 Configures wakeup character 3. (R/W) UART_WK_CHAR4 Configures wakeup character 4. (R/W) Register 28.13. UART_SLEEP_CONF1_REG (0x0034) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 UART_WK_CHAR0 0x0 7 0 Reset UART_WK_CHAR0 Configures wakeup character 0. (R/W) Espressif Systems 864 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.14. UART_SLEEP_CONF2_REG (0x0038) (reserved) 0 0 0 0 31 28 UART_WK_MODE_SEL 0 27 26 UART_WK_CHAR_MASK 0x0 25 21 UART_WK_CHAR_NUM 0x5 20 18 UART_RX_WAKE_UP_THRHD 1 17 10 UART_ACTIVE_THRESHOLD 0xf0 9 0 Reset UART_ACTIVE_THRESHOLD Configures the number of RXD edge changes to wake up the chip in wakeup mode 0. (R/W) UART_RX_WAKE_UP_THRHD Configures the number of received data bytes to wake up the chip in wakeup mode 1. (R/W) UART_WK_CHAR_NUM Configures the number of wakeup characters. (R/W) UART_WK_CHAR_MASK Configures whether or not to mask wakeup characters. 0: Not mask 1: Mask (R/W) UART_WK_MODE_SEL Configures which wakeup mode to select. See Section 28.4.8 Wakeup for the explanation of each mode. 0: Mode 0 1: Mode 1 2: Mode 2 3: Mode 3 (R/W) Espressif Systems 865 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.15. UART_SWFC_CONF0_SYNC_REG (0x003C) (reserved) 0 0 0 0 0 0 0 0 0 31 23 UART_SEND_XOFF 0 22 UART_SEND_XON 0 21 UART_FORCE_XOFF 0 20 UART_FORCE_XON 0 19 UART_XONOFF_DEL 0 18 UART_SW_FLOW_CON_EN 0 17 UART_XON_XOFF_STILL_SEND 0 16 UART_XOFF_CHAR 0x13 15 8 UART_XON_CHAR 0x11 7 0 Reset UART_XON_CHAR Configures the XON character for flow control. (R/W) UART_XOFF_CHAR Configures the XOFF character for flow control. (R/W) UART_XON_XOFF_STILL_SEND Configures whether the UART transmitter can send XON or XOFF characters when it is disabled. 0: Cannot send 1: Can send (R/W) UART_SW_FLOW_CON_EN Configures whether or not to enable software flow control. 0: Disable 1: Enable (R/W) UART_XONOFF_DEL Configures whether or not to remove flow control characters from the received data. 0: Not move 1: Move (R/W) UART_FORCE_XON Configures whether the transmitter continues to sending data. 0: Not send 1: Send (R/W) UART_FORCE_XOFF Configures whether or not to stop the transmitter from sending data. 0: Not stop 1: Stop (R/W) UART_SEND_XON Configures whether or not to send XON characters. 0: Not send 1: Send (R/W/SS/SC) UART_SEND_XOFF Configures whether or not to send XOFF characters. 0: Not send 1: Send (R/W/SS/SC) Espressif Systems 866 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.16. UART_SWFC_CONF1_REG (0x0040) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 UART_XOFF_THRESHOLD 0xe0 15 8 UART_XON_THRESHOLD 0x0 7 0 Reset UART_XON_THRESHOLD Configures the threshold for data in RX FIFO to send XON characters in software flow control. Measurement unit: byte. (R/W) UART_XOFF_THRESHOLD Configures the threshold for data in RX FIFO to send XOFF characters in software flow control. Measurement unit: byte. (R/W) Register 28.17. UART_TXBRK_CONF_SYNC_REG (0x0044) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 UART_TX_BRK_NUM 0xa 7 0 Reset UART_TX_BRK_NUM Configures the number of NULL characters to be sent after finishing data trans- mission. Valid only when UART_TXD_BRK is 1. (R/W) Register 28.18. UART_IDLE_CONF_SYNC_REG (0x0048) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 31 20 UART_TX_IDLE_NUM 0x100 19 10 UART_RX_IDLE_THRHD 0x100 9 0 Reset UART_RX_IDLE_THRHD Configures the threshold to generate a frame end signal when the receiver takes more time to receive one data byte data. Measurement unit: bit time (the time to transmit 1 bit). (R/W) UART_TX_IDLE_NUM Configures the interval between two data transfers. Measurement unit: bit time (the time to transmit 1 bit). (R/W) Espressif Systems 867 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.19. UART_RS485_CONF_SYNC_REG (0x004C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 10 UART_RS485_TX_DLY_NUM 0 9 6 UART_RS485_RX_DLY_NUM 0 5 UART_RS485RXBY_TX_EN 0 4 UART_RS485TX_RX_EN 0 3 UART_DL1_EN 0 2 UART_DL0_EN 0 1 UART_RS485_EN 0 0 Reset UART_RS485_EN Configures whether or not to enable RS485 mode. 0: Disable 1: Enable (R/W) UART_DL0_EN Configures whether or not to add a turnaround delay of 1 bit before the start bit. 0: Not add 1: Add (R/W) UART_DL1_EN Configures whether or not to add a turnaround delay of 1 bit after the stop bit. 0: Not add 1: Add (R/W) UART_RS485TX_RX_EN Configures whether or not to enable the receiver for data reception when the transmitter is transmitting data in RS485 mode. 0: Disable 1: Enable (R/W) UART_RS485RXBY_TX_EN Configures whether to enable the RS485 transmitter for data transmis- sion when the RS485 receiver is busy. 0: Disable 1: Enable (R/W) UART_RS485_RX_DLY_NUM Configures the delay of internal data signals in the receiver. Measurement unit: bit time (the time to transmit 1 bit). (R/W) UART_RS485_TX_DLY_NUM Configures the delay of internal data signals in the transmitter. Measurement unit: bit time (the time to transmit 1 bit). (R/W) Espressif Systems 868 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.20. UART_CLK_CONF_REG (0x0088) (reserved) 0 0 0 0 31 28 UART_RX_RST_CORE 0 27 UART_TX_RST_CORE 0 26 UART_RX_SCLK_EN 1 25 UART_TX_SCLK_EN 1 24 (reserved) 0 23 0 Reset UART_TX_SCLK_EN Configures whether or not to enable UART TX clock. 0: Disable 1: Enable (R/W) UART_RX_SCLK_EN Configures whether or not to enable UART RX clock. 0: Disable 1: Enable (R/W) UART_TX_RST_CORE Write 1 and then write 0 to reset UART TX. (R/W) UART_RX_RST_CORE Write 1 and then write 0 to reset UART RX. (R/W) Register 28.21. UART_STATUS_REG (0x001C) UART_TXD 1 31 UART_RTSN 1 30 UART_DTRN 1 29 (reserved) 0 0 0 0 0 28 24 UART_TXFIFO_CNT 0 23 16 UART_RXD 1 15 UART_CTSN 1 14 UART_DSRN 0 13 (reserved) 0 0 0 0 0 12 8 UART_RXFIFO_CNT 0 7 0 Reset UART_RXFIFO_CNT Represents the number of valid data bytes in RX FIFO. (RO) UART_DSRN Represents the level of the internal UART DSR signal. (RO) UART_CTSN Represents the level of the internal UART CTS signal. (RO) UART_RXD Represents the level of the internal UART RXD signal. (RO) UART_TXFIFO_CNT Represents the number of valid data bytes in RX FIFO. (RO) UART_DTRN Represents the level of the internal UART DTR signal. (RO) UART_RTSN Represents the level of the internal UART RTS signal. (RO) UART_TXD Represents the level of the internal UART TXD signal. (RO) Espressif Systems 869 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.22. UART_MEM_TX_STATUS_REG (0x0068) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 17 UART_TX_SRAM_RADDR 0x0 16 9 (reserved) 0 8 UART_TX_SRAM_WADDR 0x0 7 0 Reset UART_TX_SRAM_WADDR Represents the offset address to write TX FIFO. (RO) UART_TX_SRAM_RADDR Represents the offset address to read TX FIFO. (RO) Register 28.23. UART_MEM_RX_STATUS_REG (0x006C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 17 UART_RX_SRAM_WADDR 0x80 16 9 (reserved) 0 8 UART_RX_SRAM_RADDR 0x80 7 0 Reset UART_RX_SRAM_RADDR Represents the offset address to read RX FIFO. (RO) UART_RX_SRAM_WADDR Represents the offset address to write RX FIFO. (RO) Register 28.24. UART_FSM_STATUS_REG (0x0070) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 UART_ST_UTX_OUT 0 7 4 UART_ST_URX_OUT 0 3 0 Reset UART_ST_URX_OUT Represents the status of the receiver. (RO) UART_ST_UTX_OUT Represents the status of the transmitter. (RO) Espressif Systems 870 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.25. UART_AFIFO_STATUS_REG (0x0090) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 4 UART_RX_AFIFO_EMPTY 1 3 UART_RX_AFIFO_FULL 0 2 UART_TX_AFIFO_EMPTY 1 1 UART_TX_AFIFO_FULL 0 0 Reset UART_TX_AFIFO_FULL Represents whether or not the APB TX asynchronous FIFO is full. 0: Not full 1: Full (RO) UART_TX_AFIFO_EMPTY Represents whether or not the APB TX asynchronous FIFO is empty. 0: Not empty 1: Empty (RO) UART_RX_AFIFO_FULL Represents whether or not the APB RX asynchronous FIFO is full. 0: Not full 1: Full (RO) UART_RX_AFIFO_EMPTY Represents whether or not the APB RX asynchronous FIFO is empty. 0: Not empty 1: Empty (RO) Register 28.26. UART_AT_CMD_PRECNT_SYNC_REG (0x0050) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 UART_PRE_IDLE_NUM 0x901 15 0 Reset UART_PRE_IDLE_NUM Configures the idle time before the receiver receives the first AT_CMD. Measurement unit: bit time (the time to transmit 1 bit). (R/W) Espressif Systems 871 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.27. UART_AT_CMD_POSTCNT_SYNC_REG (0x0054) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 UART_POST_IDLE_NUM 0x901 15 0 Reset UART_POST_IDLE_NUM Configures the interval between the last AT_CMD and subsequent data. Measurement unit: bit time (the time to transmit 1 bit). (R/W) Register 28.28. UART_AT_CMD_GAPTOUT_SYNC_REG (0x0058) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 UART_RX_GAP_TOUT 11 15 0 Reset UART_RX_GAP_TOUT Configures the interval between two AT_CMD characters. Measurement unit: bit time (the time to transmit 1 bit). (R/W) Register 28.29. UART_AT_CMD_CHAR_SYNC_REG (0x005C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 UART_CHAR_NUM 0x3 15 8 UART_AT_CMD_CHAR 0x2b 7 0 Reset UART_AT_CMD_CHAR Configures the AT_CMD character. (R/W) UART_CHAR_NUM Configures the number of continuous AT_CMD characters a receiver can receive. (R/W) Espressif Systems 872 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.30. UART_POSPULSE_REG (0x0074) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 12 UART_POSEDGE_MIN_CNT 0xfff 11 0 Reset UART_POSEDGE_MIN_CNT Represents the minimal input clock counter value between two positive edges. It is used for baud rate detection. (RO) Register 28.31. UART_NEGPULSE_REG (0x0078) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 12 UART_NEGEDGE_MIN_CNT 0xfff 11 0 Reset UART_NEGEDGE_MIN_CNT Represents the minimal input clock counter value between two nega- tive edges. It is used for baud rate detection. (RO) Register 28.32. UART_LOWPULSE_REG (0x007C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 12 UART_LOWPULSE_MIN_CNT 0xfff 11 0 Reset UART_LOWPULSE_MIN_CNT Represents the minimum duration time of a low-level pulse. It is used for baud rate detection. Measurement unit: APB_CLK clock cycle. (RO) Espressif Systems 873 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.33. UART_HIGHPULSE_REG (0x0080) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 12 UART_HIGHPULSE_MIN_CNT 0xfff 11 0 Reset UART_HIGHPULSE_MIN_CNT Represents the maximum duration time for a high-level pulse. It is used for baud rate detection. Measurement unit: APB_CLK clock cycle. (RO) Register 28.34. UART_RXD_CNT_REG (0x0084) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 10 UART_RXD_EDGE_CNT 0x0 9 0 Reset UART_RXD_EDGE_CNT Represents the number of RXD edge changes. It is used for baud rate detection. (RO) Register 28.35. UART_DATE_REG (0x008C) UART_DATE 0x2201260 31 0 Reset UART_DATE Version control register. (R/W) Espressif Systems 874 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.36. UART_REG_UPDATE_REG (0x0098) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 UART_REG_UPDATE 0 0 Reset UART_REG_UPDATE Configures whether or not to synchronize registers. 0: Not synchronize 1: Synchronize (R/W/SC) Register 28.37. UART_ID_REG (0x009C) UART_ID 0x000500 31 0 Reset UART_ID Configures the UART ID. (R/W) Espressif Systems 875 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) 28.8.2 LP UART Registers The addresses in this section are relative to LP UART base address provided in Table 4.3-2 in Chapter 4 System and Memory. For how to program reserved fields, please refer to Section Programming Reserved Register Field. Register 28.38. LP_UART_FIFO_REG (0x0000) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 LP_UART_RXFIFO_RD_BYTE 0 7 0 Reset LP_UART_RXFIFO_RD_BYTE Represents the data LP UART n read from FIFO. Measurement unit: byte. (RO) Register 28.39. LP_UART_TOUT_CONF_SYNC_REG (0x0064) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 12 LP_UART_RX_TOUT_THRHD 0xa 11 2 LP_UART_RX_TOUT_FLOW_DIS 0 1 LP_UART_RX_TOUT_EN 0 0 Reset LP_UART_RX_TOUT_EN Configures whether or not to enable LP UART receiver’s timeout function. 0: Disable 1: Enable (R/W) LP_UART_RX_TOUT_FLOW_DIS Configures whether or not to disable the idle status counter when hardware flow control is enabled. 0: Invalid. No effect 1: Disable (R/W) LP_UART_RX_TOUT_THRHD Configures the amount of time that the bus can remain idle before timeout. Measurement unit: bit time (the time to transmit 1 bit). (R/W) Espressif Systems 876 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.40. LP_UART_INT_RAW_REG (0x0004) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 31 20 LP_UART_WAKEUP_INT_RAW 0 19 LP_UART_AT_CMD_CHAR_DET_INT_RAW 0 18 (reserved) 0 0 0 17 15 LP_UART_TX_DONE_INT_RAW 0 14 LP_UART_TX_BRK_IDLE_DONE_INT_RAW 0 13 LP_UART_TX_BRK_DONE_INT_RAW 0 12 LP_UART_GLITCH_DET_INT_RAW 0 11 LP_UART_SW_XOFF_INT_RAW 0 10 LP_UART_SW_XON_INT_RAW 0 9 LP_UART_RXFIFO_TOUT_INT_RAW 0 8 LP_UART_BRK_DET_INT_RAW 0 7 LP_UART_CTS_CHG_INT_RAW 0 6 LP_UART_DSR_CHG_INT_RAW 0 5 LP_UART_RXFIFO_OVF_INT_RAW 0 4 LP_UART_FRM_ERR_INT_RAW 0 3 LP_UART_PARITY_ERR_INT_RAW 0 2 LP_UART_TXFIFO_EMPTY_INT_RAW 1 1 LP_UART_RXFIFO_FULL_INT_RAW 0 0 Reset LP_UART_RXFIFO_FULL_INT_RAW The raw interrupt status of LP_UART_RXFIFO_FULL_INT. (R/WTC/SS) LP_UART_TXFIFO_EMPTY_INT_RAW The raw interrupt status of LP_UART_TXFIFO_EMPTY_INT. (R/WTC/SS) LP_UART_PARITY_ERR_INT_RAW The raw interrupt status of LP_UART_PARITY_ERR_INT. (R/WTC/SS) LP_UART_FRM_ERR_INT_RAW The raw interrupt status of LP_UART_FRM_ERR_INT. (R/WTC/SS) LP_UART_RXFIFO_OVF_INT_RAW The raw interrupt status of LP_UART_RXFIFO_OVF_INT. (R/WTC/SS) LP_UART_DSR_CHG_INT_RAW The raw interrupt status of LP_UART_DSR_CHG_INT. (R/WTC/SS) LP_UART_CTS_CHG_INT_RAW The raw interrupt status of LP_UART_CTS_CHG_INT. (R/WTC/SS) LP_UART_BRK_DET_INT_RAW The raw interrupt status of LP_UART_BRK_DET_INT. (R/WTC/SS) LP_UART_RXFIFO_TOUT_INT_RAW The raw interrupt status of LP_UART_RXFIFO_TOUT_INT. (R/WTC/SS) LP_UART_SW_XON_INT_RAW The raw interrupt status of LP_UART_SW_XON_INT. (R/WTC/SS) LP_UART_SW_XOFF_INT_RAW LP_UART_SW_XOFF_INT. (R/WTC/SS) LP_UART_GLITCH_DET_INT_RAW The raw interrupt status of LP_UART_GLITCH_DET_INT. (R/WTC/SS) LP_UART_TX_BRK_DONE_INT_RAW The raw interrupt status of LP_UART_TX_BRK_DONE_INT. (R/WTC/SS) LP_UART_TX_BRK_IDLE_DONE_INT_RAW The raw interrupt status of LP_UART_TX_BRK_IDLE_DONE_INT. (R/WTC/SS) Continued on the next page... Espressif Systems 877 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.40. LP_UART_INT_RAW_REG (0x0004) Continued from the previous page... LP_UART_TX_DONE_INT_RAW The raw interrupt status of LP_UART_TX_DONE_INT. (R/WTC/SS) LP_UART_AT_CMD_CHAR_DET_INT_RAW The raw interrupt status of LP_UART_AT_CMD_CHAR_DET_INT. (R/WTC/SS) LP_UART_WAKEUP_INT_RAW The raw interrupt status of LP_UART_WAKEUP_INT. (R/WTC/SS) Espressif Systems 878 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.41. LP_UART_INT_ST_REG (0x0008) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 31 20 LP_UART_WAKEUP_INT_ST 0 19 LP_UART_AT_CMD_CHAR_DET_INT_ST 0 18 (reserved) 0 0 0 17 15 LP_UART_TX_DONE_INT_ST 0 14 LP_UART_TX_BRK_IDLE_DONE_INT_ST 0 13 LP_UART_TX_BRK_DONE_INT_ST 0 12 LP_UART_GLITCH_DET_INT_ST 0 11 LP_UART_SW_XOFF_INT_ST 0 10 LP_UART_SW_XON_INT_ST 0 9 LP_UART_RXFIFO_TOUT_INT_ST 0 8 LP_UART_BRK_DET_INT_ST 0 7 LP_UART_CTS_CHG_INT_ST 0 6 LP_UART_DSR_CHG_INT_ST 0 5 LP_UART_RXFIFO_OVF_INT_ST 0 4 LP_UART_FRM_ERR_INT_ST 0 3 LP_UART_PARITY_ERR_INT_ST 0 2 LP_UART_TXFIFO_EMPTY_INT_ST 0 1 LP_UART_RXFIFO_FULL_INT_ST 0 0 Reset LP_UART_RXFIFO_FULL_INT_ST The masked interrupt status of LP_UART_RXFIFO_FULL_INT.(RO) LP_UART_TXFIFO_EMPTY_INT_ST The masked interrupt status of LP_UART_TXFIFO_EMPTY_INT. (RO) LP_UART_PARITY_ERR_INT_ST The masked interrupt status of LP_UART_PARITY_ERR_INT. (RO) LP_UART_FRM_ERR_INT_ST The masked interrupt status of LP_UART_FRM_ERR_INT. (RO) LP_UART_RXFIFO_OVF_INT_ST The masked interrupt status of LP_UART_RXFIFO_OVF_INT. (RO) LP_UART_DSR_CHG_INT_ST The masked interrupt status of LP_UART_DSR_CHG_INT. (RO) LP_UART_CTS_CHG_INT_ST The masked interrupt status of LP_UART_CTS_CHG_INT. (RO) LP_UART_BRK_DET_INT_ST The masked interrupt status of LP_UART_BRK_DET_INT. (RO) LP_UART_RXFIFO_TOUT_INT_ST The masked interrupt status of LP_UART_RXFIFO_TOUT_INT. (RO) LP_UART_SW_XON_INT_ST The masked interrupt status of LP_UART_SW_XON_INT. (RO) LP_UART_SW_XOFF_INT_ST The masked interrupt status of LP_UART_SW_XOFF_INT. (RO) LP_UART_GLITCH_DET_INT_ST The masked interrupt status of LP_UART_GLITCH_DET_INT. (RO) LP_UART_TX_BRK_DONE_INT_ST The masked interrupt status of LP_UART_TX_BRK_DONE_INT. (RO) LP_UART_TX_BRK_IDLE_DONE_INT_ST The masked interrupt status of LP_UART_TX_BRK_IDLE_DONE_INT. (RO) LP_UART_TX_DONE_INT_ST The masked interrupt status of LP_UART_TX_DONE_INT. (RO) LP_UART_AT_CMD_CHAR_DET_INT_ST The masked interrupt status of LP_UART_AT_CMD_CHAR_DET_INT. (RO) LP_UART_WAKEUP_INT_ST The masked interrupt status of LP_UART_WAKEUP_INT. (RO) Espressif Systems 879 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.42. LP_UART_INT_ENA_REG (0x000C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 31 20 LP_UART_WAKEUP_INT_ENA 0 19 LP_UART_AT_CMD_CHAR_DET_INT_ENA 0 18 (reserved) 0 0 0 17 15 LP_UART_TX_DONE_INT_ENA 0 14 LP_UART_TX_BRK_IDLE_DONE_INT_ENA 0 13 LP_UART_TX_BRK_DONE_INT_ENA 0 12 LP_UART_GLITCH_DET_INT_ENA 0 11 LP_UART_SW_XOFF_INT_ENA 0 10 LP_UART_SW_XON_INT_ENA 0 9 LP_UART_RXFIFO_TOUT_INT_ENA 0 8 LP_UART_BRK_DET_INT_ENA 0 7 LP_UART_CTS_CHG_INT_ENA 0 6 LP_UART_DSR_CHG_INT_ENA 0 5 LP_UART_RXFIFO_OVF_INT_ENA 0 4 LP_UART_FRM_ERR_INT_ENA 0 3 LP_UART_PARITY_ERR_INT_ENA 0 2 LP_UART_TXFIFO_EMPTY_INT_ENA 0 1 LP_UART_RXFIFO_FULL_INT_ENA 0 0 Reset LP_UART_RXFIFO_FULL_INT_ENA Write 1 to enable LP_UART_RXFIFO_FULL_INT. (R/W) LP_UART_TXFIFO_EMPTY_INT_ENA Write 1 to enable LP_UART_TXFIFO_EMPTY_INT. (R/W) LP_UART_PARITY_ERR_INT_ENA Write 1 to enable LP_UART_PARITY_ERR_INT. (R/W) LP_UART_FRM_ERR_INT_ENA Write 1 to enable LP_UART_FRM_ERR_INT. (R/W) LP_UART_RXFIFO_OVF_INT_ENA Write 1 to enable LP_UART_RXFIFO_OVF_INT. (R/W) LP_UART_DSR_CHG_INT_ENA Write 1 to enable LP_UART_DSR_CHG_INT. (R/W) LP_UART_CTS_CHG_INT_ENA Write 1 to enable LP_UART_CTS_CHG_INT. (R/W) LP_UART_BRK_DET_INT_ENA Write 1 to enable LP_UART_BRK_DET_INT. (R/W) LP_UART_RXFIFO_TOUT_INT_ENA Write 1 to enable LP_UART_RXFIFO_TOUT_INT. (R/W) LP_UART_SW_XON_INT_ENA Write 1 to enable LP_UART_SW_XON_INT.(R/W) LP_UART_SW_XOFF_INT_ENA Write 1 to enable LP_UART_SW_XOFF_INT. (R/W) LP_UART_GLITCH_DET_INT_ENA Write 1 to enable LP_UART_GLITCH_DET_INT. (R/W) LP_UART_TX_BRK_DONE_INT_ENA Write 1 to enable LP_UART_TX_BRK_DONE_INT. (R/W) LP_UART_TX_BRK_IDLE_DONE_INT_ENA Write 1 to enable LP_UART_TX_BRK_IDLE_DONE_INT. (R/W) LP_UART_TX_DONE_INT_ENA Write 1 to enable LP_UART_TX_DONE_INT. (R/W) LP_UART_AT_CMD_CHAR_DET_INT_ENA Write 1 to enable LP_UART_AT_CMD_CHAR_DET_INT. (R/W) LP_UART_WAKEUP_INT_ENA Write 1 to enable LP_UART_WAKEUP_INT. (R/W) Espressif Systems 880 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.43. LP_UART_INT_CLR_REG (0x0010) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 31 20 LP_UART_WAKEUP_INT_CLR 0 19 LP_UART_AT_CMD_CHAR_DET_INT_CLR 0 18 (reserved) 0 0 0 17 15 LP_UART_TX_DONE_INT_CLR 0 14 LP_UART_TX_BRK_IDLE_DONE_INT_CLR 0 13 LP_UART_TX_BRK_DONE_INT_CLR 0 12 LP_UART_GLITCH_DET_INT_CLR 0 11 LP_UART_SW_XOFF_INT_CLR 0 10 LP_UART_SW_XON_INT_CLR 0 9 LP_UART_RXFIFO_TOUT_INT_CLR 0 8 LP_UART_BRK_DET_INT_CLR 0 7 LP_UART_CTS_CHG_INT_CLR 0 6 LP_UART_DSR_CHG_INT_CLR 0 5 LP_UART_RXFIFO_OVF_INT_CLR 0 4 LP_UART_FRM_ERR_INT_CLR 0 3 LP_UART_PARITY_ERR_INT_CLR 0 2 LP_UART_TXFIFO_EMPTY_INT_CLR 0 1 LP_UART_RXFIFO_FULL_INT_CLR 0 0 Reset LP_UART_RXFIFO_FULL_INT_CLR Write 1 to clear LP_UART_RXFIFO_FULL_INT. (WT) LP_UART_TXFIFO_EMPTY_INT_CLR Write 1 to clear LP_UART_TXFIFO_EMPTY_INT. (WT) LP_UART_PARITY_ERR_INT_CLR Write 1 to clear LP_UART_PARITY_ERR_INT. (WT) LP_UART_FRM_ERR_INT_CLR Write 1 to clear LP_UART_FRM_ERR_INT. (WT) LP_UART_RXFIFO_OVF_INT_CLR Write 1 to clear LP_UART_RXFIFO_OVF_INT. (WT) LP_UART_DSR_CHG_INT_CLR Write 1 to clear LP_UART_DSR_CHG_INT. (WT) LP_UART_CTS_CHG_INT_CLR Write 1 to clear LP_UART_CTS_CHG_INT. (WT) LP_UART_BRK_DET_INT_CLR Write 1 to clear LP_UART_BRK_DET_INT. (WT) LP_UART_RXFIFO_TOUT_INT_CLR Write 1 to clear LP_UART_RXFIFO_TOUT_INT. (WT) LP_UART_SW_XON_INT_CLR Write 1 to clear LP_UART_SW_XON_INT. (WT) LP_UART_SW_XOFF_INT_CLR Write 1 to clear LP_UART_SW_XOFF_INT. (WT) LP_UART_GLITCH_DET_INT_CLR Write 1 to clear LP_UART_GLITCH_DET_INT. (WT) LP_UART_TX_BRK_DONE_INT_CLR Write 1 to clear LP_UART_TX_BRK_DONE_INT. (WT) LP_UART_TX_BRK_IDLE_DONE_INT_CLR Write 1 to clear LP_UART_TX_BRK_IDLE_DONE_INT. (WT) LP_UART_TX_DONE_INT_CLR Write 1 to clear LP_UART_TX_DONE_INT. (WT) LP_UART_AT_CMD_CHAR_DET_INT_CLR Write 1 to clear LP_UART_AT_CMD_CHAR_DET_INT. (WT) LP_UART_WAKEUP_INT_CLR Write 1 to clear LP_UART_WAKEUP_INT. (WT) Espressif Systems 881 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.44. LP_UART_CLKDIV_SYNC_REG (0x0014) (reserved) 0 0 0 0 0 0 0 0 31 24 LP_UART_CLKDIV_FRAG 0x0 23 20 (reserved) 0 0 0 0 0 0 0 0 19 12 LP_UART_CLKDIV 0x2b6 11 0 Reset LP_UART_CLKDIV Configures the integral part of the divisor for baud rate generation. (R/W) LP_UART_CLKDIV_FRAG Configures the fractional part of the divisor for baud rate generation. (R/W) Register 28.45. LP_UART_RX_FILT_REG (0x0018) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 9 LP_UART_GLITCH_FILT_EN 0 8 LP_UART_GLITCH_FILT 0x8 7 0 Reset LP_UART_GLITCH_FILT Configures the width of a pulse to be filtered. Measurement unit: UART Core’s clock cycle. Pulses whose width is lower than this value will be ignored. (R/W) LP_UART_GLITCH_FILT_EN Configures whether or not to enable RX signal filter. 0: Disable 1: Enable (R/W) Espressif Systems 882 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.46. LP_UART_CONF0_SYNC_REG (0x0020) (reserved) 0 0 0 0 0 0 0 0 31 24 LP_UART_TXFIFO_RST 0 23 LP_UART_RXFIFO_RST 0 22 LP_UART_SW_RTS 0 21 LP_UART_MEM_CLK_EN 0 20 (reserved) 0 19 LP_UART_ERR_WR_MASK 0 18 LP_UART_DIS_RX_DAT_OVF 0 17 LP_UART_TXD_INV 0 16 LP_UART_RXD_INV 0 15 (reserved) 0 14 LP_UART_TX_FLOW_EN 0 13 LP_UART_LOOPBACK 00000 12 (reserved) 0 11 7 LP_UART_TXD_BRK 0 6 LP_UART_STOP_BIT_NUM 1 5 4 LP_UART_BIT_NUM 3 3 2 LP_UART_PARITY_EN 0 1 LP_UART_PARITY 0 0 Reset LP_UART_PARITY Configures the parity check mode. 0: Even parity 1: Odd parity (R/W) LP_UART_PARITY_EN Configures whether or not to enable LP UART parity check. 0: Disable 1: Enable (R/W) LP_UART_BIT_NUM Configures the number of data bits. 0: 5 bits 1: 6 bits 2: 7 bits 3: 8 bits (R/W) LP_UART_STOP_BIT_NUM Configures the number of stop bits. 0: Invalid. No effect 1: 1 bit 2: 1.5 bits 3: 2 bits (R/W) LP_UART_TXD_BRK Configures whether or not to send NULL characters when finishing data trans- mission. 0: Not send 1: Send (R/W) LP_UART_LOOPBACK Configures whether or not to enable LP UART loopback test. 0: Disable 1: Enable (R/W) Continued on the next page... Espressif Systems 883 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.46. LP_UART_CONF0_SYNC_REG (0x0020) Continued from the previous page... LP_UART_TX_FLOW_EN Configures whether or not to enable flow control for the transmitter. 0: Disable 1: Enable (R/W) LP_UART_RXD_INV Configures whether or not to invert the level of LP UART RXD signal. 0: Not invert 1: Invert (R/W) LP_UART_TXD_INV Configures whether or not to invert the level of LP UART TXD signal. 0: Not invert 1: Invert (R/W) LP_UART_DIS_RX_DAT_OVF Configures whether or not to disable data overflow detection for the LP UART receiver. 0: Enable 1: Disable (R/W) LP_UART_ERR_WR_MASK Configures whether or not to store the received data with errors into FIFO. 0: Store 1: Not store (R/W) LP_UART_MEM_CLK_EN Configures whether or not to enable clock gating for LP UART memory. 0: Disable 1: Enable (R/W) LP_UART_SW_RTS Configures the RTS signal used in software flow control. 0: The LP UART transmitter is not allowed to send data. 1: The LP UART transmitted is allowed to send data. (R/W) LP_UART_RXFIFO_RST Configures whether or not to reset the LP UART RX FIFO. 0: Not reset 1: Reset (R/W) LP_UART_TXFIFO_RST Configures whether or not to reset the LP UART TX FIFO. 0: Not reset 1: Reset (R/W) Espressif Systems 884 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.47. LP_UART_CONF1_REG (0x0024) (reserved) 0 0 0 0 0 0 0 0 0 0 31 22 LP_UART_CLK_EN 0 21 LP_UART_SW_DTR 0 20 LP_UART_DTR_INV 0 19 LP_UART_RTS_INV 0 18 LP_UART_DSR_INV 0 17 LP_UART_CTS_INV 0 16 LP_UART_TXFIFO_EMPTY_THRHD 0xc 15 11 (reserved) 0 0 0 10 8 LP_UART_RXFIFO_FULL_THRHD 0xc 7 3 (reserved) 0 0 0 2 0 Reset LP_UART_RXFIFO_FULL_THRHD Configures the threshold for RX FIFO being full. Measurement unit: byte. (R/W) LP_UART_TXFIFO_EMPTY_THRHD Configures the threshold for TX FIFO being empty. Measurement unit: byte. (R/W) LP_UART_CTS_INV Configures whether or not to invert the level of LP UART CTS signal. 0: Not invert 1: Invert (R/W) LP_UART_DSR_INV Configures whether or not to invert the level of LP UART DSR signal. 0: Not invert 1: Invert (R/W) LP_UART_RTS_INV Configures whether or not to invert the level of LP UART RTS signal. 0: Not invert 1: Invert (R/W) LP_UART_DTR_INV Configures whether or not to invert the level of LP UART DTR signal. 0: Not invert 1: Invert (R/W) LP_UART_SW_DTR Configures the DTR signal used in software flow control. 0: Data to be transmitted is not ready. 1: Data to be transmitted is ready. (R/W) LP_UART_CLK_EN Configures clock gating. 0: Support clock only when the application writes registers. 1: Always force the clock on for registers. (R/W) Espressif Systems 885 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.48. LP_UART_HWFC_CONF_SYNC_REG (0x002C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 9 LP_UART_RX_FLOW_EN 0 8 LP_UART_RX_FLOW_THRHD 0x0 7 3 (reserved) 0 0 0 2 0 Reset LP_UART_RX_FLOW_THRHD Configures the maximum number of data bytes that can be received during hardware flow control. Measurement unit: byte. (R/W) LP_UART_RX_FLOW_EN Configures whether or not to enable the LP UART receiver. 0: Disable 1: Enable (R/W) Register 28.49. LP_UART_SLEEP_CONF0_REG (0x0030) LP_UART_WK_CHAR4 0x0 31 24 LP_UART_WK_CHAR3 0x0 23 16 LP_UART_WK_CHAR2 0x0 15 8 LP_UART_WK_CHAR1 0x0 7 0 Reset LP_UART_WK_CHAR1 Configures wakeup character 1. (R/W) LP_UART_WK_CHAR2 Configures wakeup character 2. (R/W) LP_UART_WK_CHAR3 Configures wakeup character 3. (R/W) LP_UART_WK_CHAR4 Configures wakeup character 4. (R/W) Register 28.50. LP_UART_SLEEP_CONF1_REG (0x0034) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 LP_UART_WK_CHAR0 0x0 7 0 Reset LP_UART_WK_CHAR0 Configures wakeup character 0. (R/W) Espressif Systems 886 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.51. LP_UART_SLEEP_CONF2_REG (0x0038) (reserved) 0 0 0 0 31 28 LP_UART_WK_MODE_SEL 0 27 26 LP_UART_WK_CHAR_MASK 0x0 25 21 LP_UART_WK_CHAR_NUM 0x5 20 18 LP_UART_RX_WAKE_UP_THRHD 1 17 13 (reserved) 0 0 0 12 10 LP_UART_ACTIVE_THRESHOLD 0xf0 9 0 Reset LP_UART_ACTIVE_THRESHOLD Configures the number of RXD edge changes to wake up the chip in wakeup mode 0. (R/W) LP_UART_RX_WAKE_UP_THRHD Configures the number of received data bytes to wake up the chip in wakeup mode 1. (R/W) LP_UART_WK_CHAR_NUM Configures the number of wakeup characters. (R/W) LP_UART_WK_CHAR_MASK Configures whether or not to mask wakeup characters. 0: Not mask 1: Mask (R/W) LP_UART_WK_MODE_SEL Configures which wakeup mode to select. 0: Mode 0 1: Mode 1 2: Mode 2 3: Mode 3 (R/W) Espressif Systems 887 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.52. LP_UART_SWFC_CONF0_SYNC_REG (0x003C) (reserved) 0 0 0 0 0 0 0 0 0 31 23 LP_UART_SEND_XOFF 0 22 LP_UART_SEND_XON 0 21 LP_UART_FORCE_XOFF 0 20 LP_UART_FORCE_XON 0 19 LP_UART_XONOFF_DEL 0 18 LP_UART_SW_FLOW_CON_EN 0 17 LP_UART_XON_XOFF_STILL_SEND 0 16 LP_UART_XOFF_CHAR 0x13 15 8 LP_UART_XON_CHAR 0x11 7 0 Reset LP_UART_XON_CHAR Configures the XON character for flow control. (R/W) LP_UART_XOFF_CHAR Configures the XOFF character for flow control. (R/W) LP_UART_XON_XOFF_STILL_SEND Configures whether the LP UART transmitter can send XON or XOFF characters when it is disabled. 0: Cannot send 1: Can send (R/W) LP_UART_SW_FLOW_CON_EN Configures whether or not to enable software flow control. 0: Disable 1: Enable (R/W) LP_UART_XONOFF_DEL Configures whether or not to remove flow control characters from the re- ceived data. 0: Not move 1: Move (R/W) LP_UART_FORCE_XON Configures whether the transmitter continues to sending data. 0: Not send 1: Send (R/W) LP_UART_FORCE_XOFF Configures whether or not to stop the transmitter from sending data. 0: Not stop 1: Stop (R/W) LP_UART_SEND_XON Configures whether or not to send XON characters. 0: Not send 1: Send (R/W/SS/SC) LP_UART_SEND_XOFF Configures whether or not to send XOFF characters. 0: Not send 1: Send (R/W/SS/SC) Espressif Systems 888 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.53. LP_UART_SWFC_CONF1_REG (0x0040) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 LP_UART_XOFF_THRESHOLD 0xc 15 11 (reserved) 0 0 0 10 8 LP_UART_XON_THRESHOLD 0x0 7 3 (reserved) 0 0 0 2 0 Reset LP_UART_XON_THRESHOLD Configures the threshold for data in RX FIFO to send XON characters in software flow control. Measurement unit: byte. (R/W) LP_UART_XOFF_THRESHOLD Configures the threshold for data in RX FIFO to send XOFF charac- ters in software flow control. Measurement unit: byte. (R/W) Register 28.54. LP_UART_TXBRK_CONF_SYNC_REG (0x0044) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 LP_UART_TX_BRK_NUM 0xa 7 0 Reset LP_UART_TX_BRK_NUM Configures the number of NULL characters to be sent after finishing data transmission. Valid only when LP_UART_TXD_BRK is 1. (R/W) Espressif Systems 889 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.55. LP_UART_IDLE_CONF_SYNC_REG (0x0048) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 31 20 LP_UART_TX_IDLE_NUM 0x100 19 10 LP_UART_RX_IDLE_THRHD 0x100 9 0 Reset LP_UART_RX_IDLE_THRHD Configures the threshold to generate a frame end signal when the re- ceiver takes more time to receive one data byte data. Measurement unit: bit time (the time to transmit 1 bit). (R/W) LP_UART_TX_IDLE_NUM Configures the interval between two data transfers. Measurement unit: bit time (the time to transmit 1 bit). (R/W) Register 28.56. LP_UART_DELAY_CONF_SYNC_REG (0x004C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 LP_UART_DL1_EN 0 2 LP_UART_DL0_EN 0 1 (reserved) 0 0 Reset LP_UART_DL0_EN Configures whether to add a turnaround delay of 1 bit before the start bit. 0: Not add 1: Add (R/W) LP_UART_DL1_EN Configures whether to add a turnaround delay of 1 bit after the stop bit. 0: Not add 1: Add (R/W) Espressif Systems 890 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.57. LP_UART_CLK_CONF_REG (0x0088) (reserved) 0 0 0 0 31 28 LP_UART_RX_RST_CORE 0 27 LP_UART_TX_RST_CORE 0 26 LP_UART_RX_SCLK_EN 1 25 LP_UART_TX_SCLK_EN 1 24 (reserved) 0 23 0 Reset LP_UART_TX_SCLK_EN Configures whether or not to enable LP UART TX clock. 0: Disable 1: Enable (R/W) LP_UART_RX_SCLK_EN Configures whether or not to enable LP UART RX clock. 0: Disable 1: Enable (R/W) LP_UART_TX_RST_CORE Write 1 and then write 0 to reset LP UART TX. (R/W) LP_UART_RX_RST_CORE Write 1 and then write 0 to reset LP UART RX. (R/W) Register 28.58. LP_UART_STATUS_REG (0x001C) LP_UART_TXD 1 31 LP_UART_RTSN 1 30 LP_UART_DTRN 1 29 (reserved) 0 0 0 0 0 28 24 LP_UART_TXFIFO_CNT 0 23 19 (reserved) 0 0 0 18 16 LP_UART_RXD 1 15 LP_UART_CTSN 1 14 LP_UART_DSRN 0 13 (reserved) 0 0 0 0 0 12 8 LP_UART_RXFIFO_CNT 0 7 3 (reserved) 0 0 0 2 0 Reset LP_UART_RXFIFO_CNT Represents the number of valid data bytes in RX FIFO. (RO) LP_UART_DSRN Represents the level of the internal LP UART DSR signal. (RO) LP_UART_CTSN Represents the level of the internal LP UART CTS signal. (RO) LP_UART_RXD Represents the level of the internal LP UART RXD signal. (RO) LP_UART_TXFIFO_CNT Represents the number of valid data bytes in RX FIFO. (RO) LP_UART_DTRN Represents the level of the internal LP UART DTR signal. (RO) LP_UART_RTSN Represents the level of the internal LP UART RTS signal. (RO) LP_UART_TXD Represents the level of the internal LP UART TXD signal. (RO) Espressif Systems 891 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.59. LP_UART_MEM_TX_STATUS_REG (0x0068) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 17 LP_UART_TX_SRAM_RADDR 0x0 16 12 (reserved) 0 0 0 0 11 8 LP_UART_TX_SRAM_WADDR 0x0 7 3 (reserved) 0 0 0 2 0 Reset LP_UART_TX_SRAM_WADDR Represents the offset address to write TX FIFO. (RO) LP_UART_TX_SRAM_RADDR Represents the offset address to read TX FIFO. (RO) Register 28.60. LP_UART_MEM_RX_STATUS_REG (0x006C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 17 LP_UART_RX_SRAM_WADDR 0x10 16 12 (reserved) 0 0 0 0 11 8 LP_UART_RX_SRAM_RADDR 0x10 7 3 (reserved) 0 0 0 2 0 Reset LP_UART_RX_SRAM_RADDR Represents the offset address to read RX FIFO. (RO) LP_UART_RX_SRAM_WADDR Represents the offset address to write RX FIFO. (RO) Register 28.61. LP_UART_FSM_STATUS_REG (0x0070) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 LP_UART_ST_UTX_OUT 0 7 4 LP_UART_ST_URX_OUT 0 3 0 Reset LP_UART_ST_URX_OUT Represents the status of the receiver. (RO) LP_UART_ST_UTX_OUT Represents the status of the transmitter. (RO) Espressif Systems 892 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.62. LP_UART_AFIFO_STATUS_REG (0x0090) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 4 LP_UART_RX_AFIFO_EMPTY 1 3 LP_UART_RX_AFIFO_FULL 0 2 LP_UART_TX_AFIFO_EMPTY 1 1 LP_UART_TX_AFIFO_FULL 0 0 Reset LP_UART_TX_AFIFO_FULL Represents whether or not the APB TX asynchronous FIFO is full. 0: Not full 1: Full (RO) LP_UART_TX_AFIFO_EMPTY Represents whether or not the APB TX asynchronous FIFO is empty. 0: Not empty 1: Empty (RO) LP_UART_RX_AFIFO_FULL Represents whether or not the APB RX asynchronous FIFO is full. 0: Not full 1: Full (RO) LP_UART_RX_AFIFO_EMPTY Represents whether or not the APB RX asynchronous FIFO is empty. 0: Not empty 1: Empty (RO) Register 28.63. LP_UART_AT_CMD_PRECNT_SYNC_REG (0x0050) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 LP_UART_PRE_IDLE_NUM 0x901 15 0 Reset LP_UART_PRE_IDLE_NUM Configures the idle time before the receiver receives the first AT_CMD. Measurement unit: bit time (the time to transmit 1 bit). (R/W) Espressif Systems 893 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.64. LP_UART_AT_CMD_POSTCNT_SYNC_REG (0x0054) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 LP_UART_POST_IDLE_NUM 0x901 15 0 Reset LP_UART_POST_IDLE_NUM Configures the interval between the last AT_CMD and subsequent data. Measurement unit: bit time (the time to transmit 1 bit). (R/W) Register 28.65. LP_UART_AT_CMD_GAPTOUT_SYNC_REG (0x0058) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 LP_UART_RX_GAP_TOUT 11 15 0 Reset LP_UART_RX_GAP_TOUT Configures the interval between two AT_CMD characters. Measurement unit: bit time (the time to transmit 1 bit). (R/W) Register 28.66. LP_UART_AT_CMD_CHAR_SYNC_REG (0x005C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 LP_UART_CHAR_NUM 0x3 15 8 LP_UART_AT_CMD_CHAR 0x2b 7 0 Reset LP_UART_AT_CMD_CHAR Configures the AT_CMD character. (R/W) LP_UART_CHAR_NUM Configures the number of continuous AT_CMD characters a receiver can receive. (R/W) Espressif Systems 894 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.67. LP_UART_DATE_REG (0x008C) LP_UART_DATE 0x2305050 31 0 Reset LP_UART_DATE Version control register. (R/W) Register 28.68. LP_UART_REG_UPDATE_REG (0x0098) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 LP_UART_REG_UPDATE 0 0 Reset LP_UART_REG_UPDATE Configures whether or not to synchronize registers. 0: Not synchronize 1: Synchronize (R/W/SC) Register 28.69. LP_UART_ID_REG (0x009C) LP_UART_ID 0x000500 31 0 Reset LP_UART_ID Configures the LP UART ID. (R/W) Espressif Systems 895 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) 28.8.3 UHCI Registers The addresses in this section are relative to UHCI base address provided in Table 4.3-2 in Chapter 4 System and Memory. For how to program reserved fields, please refer to Section Programming Reserved Register Field. Register 28.70. UHCI_CONF0_REG (0x0000) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 13 UHCI_UART_RX_BRK_EOF_EN 0 12 UHCI_CLK_EN 0 11 UHCI_ENCODE_CRC_EN 1 10 UHCI_LEN_EOF_EN 1 9 UHCI_UART_IDLE_EOF_EN 0 8 UHCI_CRC_REC_EN 1 7 UHCI_HEAD_EN 1 6 UHCI_SEPER_EN 1 5 UHCI_UART_SEL 0 4 2 UHCI_RX_RST 0 1 UHCI_TX_RST 0 0 Reset UHCI_TX_RST Write 1 and then write 0 to reset the decoder state machine. (R/W) UHCI_RX_RST Write 1 and then write 0 to reset the encoder state machine. (R/W) UHCI_UART_SEL Select one UART from UART 0 1 to connect with UHCI. 0: Select UART0 1: Select UART1 2 7: No effect, as no UART will connect with UHCI (R/W) UHCI_UART1_CE Configures whether or not to connect UHCI with UART1. 0: Not connect 1: Connect (R/W) UHCI_SEPER_EN Configures whether or not to separate the data frame with a special character. 0: Not separate 1: Separate (R/W) UHCI_HEAD_EN Configures whether or not to encode the data packet with a formatting header. 0: Not use formatting header 1: Use formatting header (R/W) Continued on the next page... Espressif Systems 896 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.70. UHCI_CONF0_REG (0x0000) Continued from the previous page... UHCI_CRC_REC_EN Configures whether or not to enable the reception of the 16-bit CRC. 0: Disable 1: Enable (R/W) UHCI_UART_IDLE_EOF_EN Configures whether or not to stop receiving data when UART is idle. 0: Not stop 1: Stop (R/W) UHCI_LEN_EOF_EN Configures when the UHCI decoder stops receiving data. 0: Stops after receiving 0xC0 1: Stops when the number of received data bytes reach the specified value. When UHCI_HEAD_EN is 1, the specified value is the data length indicated by the UHCI packet header; when UHCI_HEAD_EN is 0, the specified value is the configured value. (R/W) UHCI_ENCODE_CRC_EN Configures whether or not to enable data integrity check by appending a 16 bit CCITT-CRC to the end of the data. 0: Disable 1: Enable (R/W) UHCI_CLK_EN Configures clock gating. 0: Support clock only when the application writes registers. 1: Always force the clock on for registers. (R/W) UHCI_UART_RX_BRK_EOF_EN Configures whether or not to stop UHCI from receiving data after UART has received a NULL frame. 0: Not stop 1: Stop (R/W) Espressif Systems 897 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.71. UHCI_CONF1_REG (0x0014) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 9 UHCI_SW_START 0 8 UHCI_WAIT_SW_START 0 7 (reserved) 0 6 UHCI_TX_ACK_NUM_RE 1 5 UHCI_TX_CHECK_SUM_RE 1 4 UHCI_SAVE_HEAD 0 3 UHCI_CRC_DISABLE 0 2 UHCI_CHECK_SEQ_EN 1 1 UHCI_CHECK_SUM_EN 1 0 Reset UHCI_CHECK_SUM_EN Configures whether or not to enable header checksum validation when UHCI receives a data packet. 0: Disable 1: Enable (R/W) UHCI_CHECK_SEQ_EN Configures whether or not to enable the sequence number check when UHCI receives a data packet. 0: Disable 1: Enable (R/W) UHCI_CRC_DISABLE Configures whether or not to enable CRC calculation. 0: Disable 1: Enable Valid only when the Data Integrity Check Present bit in UHCI packet is 1. (R/W) UHCI_SAVE_HEAD Configures whether or not to save the packet header when UHCI receives a data packet. 0: Not save 1: Save (R/W) UHCI_TX_CHECK_SUM_RE Configures whether or not to encode the data packet with a checksum. 0: Not use checksum 1: Use checksum (R/W) UHCI_TX_ACK_NUM_RE Configures whether or not to encode the data packet with an acknowl- edgment when a reliable packet is to be transmitted. 0: Not use acknowledgement 1: Use acknowledgement (R/W) Continued on the next page... Espressif Systems 898 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.71. UHCI_CONF1_REG (0x0014) Continued from the previous page... UHCI_WAIT_SW_START Configures whether or not to put the UHCI encoder state machine to ST_SW_WAIT state. 0: No 1: Yes (R/W) UHCI_SW_START Configures whether or not to send data packets when the encoder state machine is in ST_SW_WAIT state. 0: Not send 1: Send (R/W/SC) Espressif Systems 899 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.72. UHCI_ESCAPE_CONF_REG (0x0020) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 UHCI_RX_13_ESC_EN 0 7 UHCI_RX_11_ESC_EN 0 6 UHCI_RX_DB_ESC_EN 1 5 UHCI_RX_C0_ESC_EN 1 4 UHCI_TX_13_ESC_EN 0 3 UHCI_TX_11_ESC_EN 0 2 UHCI_TX_DB_ESC_EN 1 1 UHCI_TX_C0_ESC_EN 1 0 Reset UHCI_TX_C0_ESC_EN Configures whether or not to decode character 0xC0 when DMA receives data. 0: Not decode 1: Decode (R/W) UHCI_TX_DB_ESC_EN Configures whether or not to decode character 0xDB when DMA receives data. 0: Not decode 1: Decode (R/W) UHCI_TX_11_ESC_EN Configures whether or not to decode flow control character 0x11 when DMA receives data. 0: Not decode 1: Decode (R/W) UHCI_TX_13_ESC_EN Configures whether or not to decode flow control character 0x13 when DMA receives data. 0: Not decode 1: Decode (R/W) UHCI_RX_C0_ESC_EN Configures whether or not to replace 0xC0 by special characters when DMA sends data. 0: Not replace 1: Replace (R/W) UHCI_RX_DB_ESC_EN Configures whether or not to replace 0xDB by special characters when DMA sends data. 0: Not replace 1: Replace (R/W) Continued on the next page... Espressif Systems 900 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.72. UHCI_ESCAPE_CONF_REG (0x0020) Continued from the previous page... UHCI_RX_11_ESC_EN Configures whether or not to replace flow control character 0x11 by special characters when DMA sends data. 0: Not replace 1: Replace (R/W) UHCI_RX_13_ESC_EN Configures whether or not to replace flow control character 0x13 by special characters when DMA sends data. 0: Not replace 1: Replace (R/W) Espressif Systems 901 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.73. UHCI_HUNG_CONF_REG (0x0024) (reserved) 0 0 0 0 0 0 0 0 31 24 UHCI_RXFIFO_TIMEOUT_ENA 1 23 UHCI_RXFIFO_TIMEOUT_SHIFT 0 22 20 UHCI_RXFIFO_TIMEOUT 0x10 19 12 UHCI_TXFIFO_TIMEOUT_ENA 1 11 UHCI_TXFIFO_TIMEOUT_SHIFT 0 10 8 UHCI_TXFIFO_TIMEOUT 0x10 7 0 Reset UHCI_TXFIFO_TIMEOUT Configures the timeout value for DMA data reception. Measurement unit: ms. (R/W) UHCI_TXFIFO_TIMEOUT_SHIFT Configures the upper limit of the timeout counter for TX FIFO. (R/W) UHCI_TXFIFO_TIMEOUT_ENA Configures whether or not to enable the data reception timeout for TX FIFO. 0: Disable 1: Enable (R/W) UHCI_RXFIFO_TIMEOUT Configures the timeout value for DMA to read data from RAM. Measurement unit: ms. (R/W) UHCI_RXFIFO_TIMEOUT_SHIFT Configures the upper limit of the timeout counter for RX FIFO. (R/W) UHCI_RXFIFO_TIMEOUT_ENA Configures whether or not to enable the DMA data transmission timeout. 0: Disable 1: Enable (R/W) Espressif Systems 902 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.74. UHCI_ACK_NUM_REG (0x0028) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 4 UHCI_ACK_NUM_LOAD 0 3 UHCI_ACK_NUM 0x0 2 0 Reset UHCI_ACK_NUM Configures the number of acknowledgements used in software flow control. (R/W) UHCI_ACK_NUM_LOAD Configures whether or not load acknowledgements. 0: Not load 1: Load (WT) Espressif Systems 903 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.75. UHCI_QUICK_SENT_REG (0x0030) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 UHCI_ALWAYS_SEND_EN 0 7 UHCI_ALWAYS_SEND_NUM 0x0 6 4 UHCI_SINGLE_SEND_EN 0 3 UHCI_SINGLE_SEND_NUM 0x0 2 0 Reset UHCI_SINGLE_SEND_NUM Configures the source of data to be transmitted in single_send mode. 0: Q0 register 1: Q1 register 2: Q2 register 3: Q3 register 4: Q4 register 5: Q5 register 6: Q6 register 7: Invalid. No effect (R/W) UHCI_SINGLE_SEND_EN Configures whether or not to enable single_send mode. 0: Disable 1: Enable (R/W/SC) UHCI_ALWAYS_SEND_NUM Configures the source of data to be transmitted in always_send mode. 0: Q0 register 1: Q1 register 2: Q2 register 3: Q3 register 4: Q4 register 5: Q5 register 6: Q6 register 7: Invalid. No effect (R/W) UHCI_ALWAYS_SEND_EN Configures whether or not to enable always_send mode. 0: Disable 1: Enable (R/W) Espressif Systems 904 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.76. UHCI_REG_Q0_WORD0_REG (0x0034) UHCI_SEND_Q0_WORD0 0x000000 31 0 Reset UHCI_SEND_Q0_WORD0 Data to be transmitted in Q0 register. (R/W) Register 28.77. UHCI_REG_Q0_WORD1_REG (0x0038) UHCI_SEND_Q0_WORD1 0x000000 31 0 Reset UHCI_SEND_Q0_WORD1 Data to be transmitted in Q0 register. (R/W) Register 28.78. UHCI_REG_Q1_WORD0_REG (0x003C) UHCI_SEND_Q1_WORD0 0x000000 31 0 Reset UHCI_SEND_Q1_WORD0 Data to be transmitted in Q1 register. (R/W) Espressif Systems 905 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.79. UHCI_REG_Q1_WORD1_REG (0x0040) UHCI_SEND_Q1_WORD1 0x000000 31 0 Reset UHCI_SEND_Q1_WORD1 Data to be transmitted in Q1 register. (R/W) Register 28.80. UHCI_REG_Q2_WORD0_REG (0x0044) UHCI_SEND_Q2_WORD0 0x000000 31 0 Reset UHCI_SEND_Q2_WORD0 Data to be transmitted in Q2 register. (R/W) Register 28.81. UHCI_REG_Q2_WORD1_REG (0x0048) UHCI_SEND_Q2_WORD1 0x000000 31 0 Reset UHCI_SEND_Q2_WORD1 Data to be transmitted in Q2 register. (R/W) Espressif Systems 906 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.82. UHCI_REG_Q3_WORD0_REG (0x004C) UHCI_SEND_Q3_WORD0 0x000000 31 0 Reset UHCI_SEND_Q3_WORD0 Data to be transmitted in Q3 register. (R/W) Register 28.83. UHCI_REG_Q3_WORD1_REG (0x0050) UHCI_SEND_Q3_WORD1 0x000000 31 0 Reset UHCI_SEND_Q3_WORD1 Data to be transmitted in Q3 register. (R/W) Register 28.84. UHCI_REG_Q4_WORD0_REG (0x0054) UHCI_SEND_Q4_WORD0 0x000000 31 0 Reset UHCI_SEND_Q4_WORD0 Data to be transmitted in Q4 register. (R/W) Espressif Systems 907 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.85. UHCI_REG_Q4_WORD1_REG (0x0058) UHCI_SEND_Q4_WORD1 0x000000 31 0 Reset UHCI_SEND_Q4_WORD1 Data to be transmitted in Q4 register. (R/W) Register 28.86. UHCI_REG_Q5_WORD0_REG (0x005C) UHCI_SEND_Q5_WORD0 0x000000 31 0 Reset UHCI_SEND_Q5_WORD0 Data to be transmitted in Q5 register. (R/W) Register 28.87. UHCI_REG_Q5_WORD1_REG (0x0060) UHCI_SEND_Q5_WORD1 0x000000 31 0 Reset UHCI_SEND_Q5_WORD1 Data to be transmitted in Q5 register. (R/W) Espressif Systems 908 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.88. UHCI_REG_Q6_WORD0_REG (0x0064) UHCI_SEND_Q6_WORD0 0x000000 31 0 Reset UHCI_SEND_Q6_WORD0 Data to be transmitted in Q6 register. (R/W) Register 28.89. UHCI_REG_Q6_WORD1_REG (0x0068) UHCI_SEND_Q6_WORD1 0x000000 31 0 Reset UHCI_SEND_Q6_WORD1 Data to be transmitted in Q6 register. (R/W) Register 28.90. UHCI_ESC_CONF0_REG (0x006C) (reserved) 0 0 0 0 0 0 0 0 31 24 UHCI_SEPER_ESC_CHAR1 0xdc 23 16 UHCI_SEPER_ESC_CHAR0 0xdb 15 8 UHCI_SEPER_CHAR 0xc0 7 0 Reset UHCI_SEPER_CHAR Configures separators to encode data packets. The default value is 0xC0. (R/W) UHCI_SEPER_ESC_CHAR0 Configures the first character of SLIP escape sequence. The default value is 0xDB. (R/W) UHCI_SEPER_ESC_CHAR1 Configures the second character of SLIP escape sequence. The default value is 0xDC. (R/W) Espressif Systems 909 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.91. UHCI_ESC_CONF1_REG (0x0070) (reserved) 0 0 0 0 0 0 0 0 31 24 UHCI_ESC_SEQ0_CHAR1 0xdd 23 16 UHCI_ESC_SEQ0_CHAR0 0xdb 15 8 UHCI_ESC_SEQ0 0xdb 7 0 Reset UHCI_ESC_SEQ0 Configures the character that needs to be encoded. The default value is 0xDB used as the first character of SLIP escape sequence. (R/W) UHCI_ESC_SEQ0_CHAR0 Configures the first character of SLIP escape sequence. The default value is 0xDB. (R/W) UHCI_ESC_SEQ0_CHAR1 Configures the second character of SLIP escape sequence. The default value is 0xDD. (R/W) Register 28.92. UHCI_ESC_CONF2_REG (0x0074) (reserved) 0 0 0 0 0 0 0 0 31 24 UHCI_ESC_SEQ1_CHAR1 0xde 23 16 UHCI_ESC_SEQ1_CHAR0 0xdb 15 8 UHCI_ESC_SEQ1 0x11 7 0 Reset UHCI_ESC_SEQ1 Configures a character that need to be encoded. The default value is 0x11 used as a flow control character. (R/W) UHCI_ESC_SEQ1_CHAR0 Configures the first character of SLIP escape sequence. The default value is 0xDB. (R/W) UHCI_ESC_SEQ1_CHAR1 Configures the second character of SLIP escape sequence. The default value is 0xDE. (R/W) Espressif Systems 910 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.93. UHCI_ESC_CONF3_REG (0x0078) (reserved) 0 0 0 0 0 0 0 0 31 24 UHCI_ESC_SEQ2_CHAR1 0xdf 23 16 UHCI_ESC_SEQ2_CHAR0 0xdb 15 8 UHCI_ESC_SEQ2 0x13 7 0 Reset UHCI_ESC_SEQ2 Configures the character that needs to be decoded. The default value is 0x13 used as a flow control character. (R/W) UHCI_ESC_SEQ2_CHAR0 Configures the first character of SLIP escape sequence. The default value is 0xDB. (R/W) UHCI_ESC_SEQ2_CHAR1 Configures the second character of SLIP escape sequence. The default value is 0xDF. (R/W) Register 28.94. UHCI_PKT_THRES_REG (0x007C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 13 UHCI_PKT_THRS 0x80 12 0 Reset UHCI_PKT_THRS Configures the maximum value of the packet length. Measurement unit: byte. Valid only when UHCI_HEAD_EN is 0. (R/W) Espressif Systems 911 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.95. UHCI_INT_RAW_REG (0x0004) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 9 UHCI_APP_CTRL1_INT_RAW 0 8 UHCI_APP_CTRL0_INT_RAW 0 7 UHCI_OUT_EOF_INT_RAW 0 6 UHCI_SEND_A_REG_Q_INT_RAW 0 5 UHCI_SEND_S_REG_Q_INT_RAW 0 4 UHCI_TX_HUNG_INT_RAW 0 3 UHCI_RX_HUNG_INT_RAW 0 2 UHCI_TX_START_INT_RAW 0 1 UHCI_RX_START_INT_RAW 0 0 Reset UHCI_RX_START_INT_RAW The raw interrupt status of UHCI_RX_START_INT. (R/WTC/SS) UHCI_TX_START_INT_RAW The raw interrupt status of UHCI_TX_START_INT. (R/WTC/SS) UHCI_RX_HUNG_INT_RAW The raw interrupt status of UHCI_RX_HUNG_INT. (R/WTC/SS) UHCI_TX_HUNG_INT_RAW The raw interrupt status of UHCI_TX_HUNG_INT. (R/WTC/SS) UHCI_SEND_S_REG_Q_INT_RAW The raw interrupt status of UHCI_SEND_S_REG_Q_INT. (R/WTC/SS) UHCI_SEND_A_REG_Q_INT_RAW The raw interrupt status of UHCI_SEND_A_REG_Q_INT. (R/WTC/SS) UHCI_OUT_EOF_INT_RAW The raw interrupt status of UHCI_OUT_EOF_INT. (R/WTC/SS) UHCI_APP_CTRL0_INT_RAW The raw interrupt status of UHCI_APP_CTRL0_INT. (R/W) UHCI_APP_CTRL1_INT_RAW The raw interrupt status of UHCI_APP_CTRL1_INT. (R/W) Espressif Systems 912 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.96. UHCI_INT_ST_REG (0x0008) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 9 UHCI_APP_CTRL1_INT_ST 0 8 UHCI_APP_CTRL0_INT_ST 0 7 UHCI_OUTLINK_EOF_ERR_INT_ST 0 6 UHCI_SEND_A_REG_Q_INT_ST 0 5 UHCI_SEND_S_REG_Q_INT_ST 0 4 UHCI_TX_HUNG_INT_ST 0 3 UHCI_RX_HUNG_INT_ST 0 2 UHCI_TX_START_INT_ST 0 1 UHCI_RX_START_INT_ST 0 0 Reset UHCI_RX_START_INT_ST The masked interrupt status of UHCI_RX_START_INT. (RO) UHCI_TX_START_INT_ST The masked interrupt status of UHCI_TX_START_INT. (RO) UHCI_RX_HUNG_INT_ST The masked interrupt status of UHCI_RX_HUNG_INT. (RO) UHCI_TX_HUNG_INT_ST The masked interrupt status of UHCI_TX_HUNG_INT. (RO) UHCI_SEND_S_REG_Q_INT_ST The masked interrupt status of UHCI_SEND_S_REG_Q_INT. (RO) UHCI_SEND_A_REG_Q_INT_ST The masked interrupt status of UHCI_SEND_A_REG_Q_INT. (RO) UHCI_OUTLINK_EOF_ERR_INT_ST The masked interrupt status of UHCI_OUTLINK_EOF_ERR_INT. (RO) UHCI_APP_CTRL0_INT_ST The masked interrupt status of UHCI_APP_CTRL0_INT. (RO) UHCI_APP_CTRL1_INT_ST The masked interrupt status of UHCI_APP_CTRL1_INT. (RO) Espressif Systems 913 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.97. UHCI_INT_ENA_REG (0x000C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 9 UHCI_APP_CTRL1_INT_ENA 0 8 UHCI_APP_CTRL0_INT_ENA 0 7 UHCI_OUTLINK_EOF_ERR_INT_ENA 0 6 UHCI_SEND_A_REG_Q_INT_ENA 0 5 UHCI_SEND_S_REG_Q_INT_ENA 0 4 UHCI_TX_HUNG_INT_ENA 0 3 UHCI_RX_HUNG_INT_ENA 0 2 UHCI_TX_START_INT_ENA 0 1 UHCI_RX_START_INT_ENA 0 0 Reset UHCI_RX_START_INT_ENA Write 1 to enable UHCI_RX_START_INT. (R/W) UHCI_TX_START_INT_ENA Write 1 to enable UHCI_TX_START_INT. (R/W) UHCI_RX_HUNG_INT_ENA Write 1 to enable UHCI_RX_HUNG_INT. (R/W) UHCI_TX_HUNG_INT_ENA Write 1 to enable UHCI_TX_HUNG_INT. (R/W) UHCI_SEND_S_REG_Q_INT_ENA Write 1 to enable UHCI_SEND_S_REG_Q_INT. (R/W) UHCI_SEND_A_REG_Q_INT_ENA Write 1 to enable UHCI_SEND_A_REG_Q_INT. (R/W) UHCI_OUTLINK_EOF_ERR_INT_ENA Write 1 to enable UHCI_OUTLINK_EOF_ERR_INT. (R/W) UHCI_APP_CTRL0_INT_ENA Write 1 to enable UHCI_APP_CTRL0_INT. (R/W) UHCI_APP_CTRL1_INT_ENA Write 1 to enable UHCI_APP_CTRL1_INT. (R/W) Espressif Systems 914 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.98. UHCI_INT_CLR_REG (0x0010) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 9 UHCI_APP_CTRL1_INT_CLR 0 8 UHCI_APP_CTRL0_INT_CLR 0 7 UHCI_OUTLINK_EOF_ERR_INT_CLR 0 6 UHCI_SEND_A_REG_Q_INT_CLR 0 5 UHCI_SEND_S_REG_Q_INT_CLR 0 4 UHCI_TX_HUNG_INT_CLR 0 3 UHCI_RX_HUNG_INT_CLR 0 2 UHCI_TX_START_INT_CLR 0 1 UHCI_RX_START_INT_CLR 0 0 Reset UHCI_RX_START_INT_CLR Write 1 to clear UHCI_RX_START_INT. (WT) UHCI_TX_START_INT_CLR Write 1 to clear UHCI_TX_START_INT. (WT) UHCI_RX_HUNG_INT_CLR Write 1 to clear UHCI_RX_HUNG_INT. (WT) UHCI_TX_HUNG_INT_CLR Write 1 to clear UHCI_TX_HUNG_INT. (WT) UHCI_SEND_S_REG_Q_INT_CLR Write 1 to clear UHCI_SEND_S_REG_Q_INT. (WT) UHCI_SEND_A_REG_Q_INT_CLR Write 1 to clear UHCI_SEND_A_REG_Q_INT. (WT) UHCI_OUTLINK_EOF_ERR_INT_CLR Write 1 to clear UHCI_OUTLINK_EOF_ERR_INT. (WT) UHCI_APP_CTRL0_INT_CLR Write 1 to clear UHCI_APP_CTRL0_INT. (WT) UHCI_APP_CTRL1_INT_CLR Write 1 to clear UHCI_APP_CTRL1_INT. (WT) Espressif Systems 915 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.99. UHCI_STATE0_REG (0x0018) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 6 UHCI_DECODE_STATE 0 5 3 UHCI_RX_ERR_CAUSE 0 2 0 Reset UHCI_RX_ERR_CAUSE Represents the error type when DMA has received a packet with error. 0: Invalid. No effect 1: Checksum error in the HCI packet 2: Sequence number error in the HCI packet 3: CRC bit error in the HCI packet 4: 0xC0 is found but the received HCI packet is not complete 5: 0xC0 is not found when the HCI packet has been received 6: CRC check error 7: Invalid. No effect (RO) UHCI_DECODE_STATE Represents the UHCI decoder status. (RO) Register 28.100. UHCI_STATE1_REG (0x001C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 UHCI_ENCODE_STATE 0 2 0 Reset UHCI_ENCODE_STATE Represents the UHCI encoder status. (RO) Register 28.101. UHCI_RX_HEAD_REG (0x002C) UHCI_RX_HEAD 0x000000 31 0 Reset UHCI_RX_HEAD Represents the header of the current received packet. (RO) Espressif Systems 916 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 28 UART Controller (UART) Register 28.102. UHCI_DATE_REG (0x0080) UHCI_DATE 0x2201100 31 0 Reset UHCI_DATE Version control register. (R/W) Espressif Systems 917 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Chapter 29 SPI Controller (SPI) 29.1 Overview The Serial Peripheral Interface (SPI) is a synchronous serial interface useful for communication with external peripherals. The ESP32-C5 chip integrates three SPI controllers: • SPI0 • SPI1 • General Purpose SPI2 (GP-SPI2) SPI0 and SPI1 controllers (MSPI) are primarily reserved for internal use to communicate with external flash and PSRAM memory. This chapter mainly focuses on the GP-SPI2 controller. 29.2 Glossary To better illustrate the functions of GP-SPI2, the following terms are used in this chapter. Master Mode GP-SPI2 acts as an SPI master and initiates SPI transactions. Slave Mode GP-SPI2 acts as an SPI slave and exchanges data with its master when its CS is asserted. MISO Master in, slave out, data transmission from a slave to a master. MOSI Master out, slave in, data transmission from a master to a slave Transaction One instance of a master asserting a CS line, transferring data to and from a slave, and de-asserting the CS line. Transactions are atomic, which means they can never be interrupted by another transaction. SPI Transfer The whole process of an SPI master exchanging data with a slave. One SPI transfer consists of one or more SPI transactions. Single Transfer An SPI transfer that consists of only one transaction. CPU-Controlled Transfer A data transfer that happens between CPU buffer SPI_W0_REG SPI_W15_REG and SPI peripheral. DMA-Controlled Transfer A data transfer that happens between DMA and SPI peripheral, controlled by the DMA engine. Configurable Segmented Transfer A data transfer controlled by DMA in SPI master mode. Such trans- fer consists of multiple transactions (segments), and each transac- tion can be configured independently. Slave Segmented Transfer A data transfer controlled by DMA in SPI slave mode. Such transfer consists of multiple transactions (segments). Espressif Systems 918 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Full-duplex The sending line and receiving line between the master and the slave are independent. Sending data and receiving data happen at the same time. Half-duplex Only one side, the master or the slave, sends data, and the other side receives data. Sending data and receiving data can not happen simultaneously on one side. 4-line full-duplex 4-line here means: clock line, CS line, and two data lines. The two data lines can be used to send or receive data simultaneously. 4-line half-duplex 4-line here means: clock line, CS line, and two data lines. The two data lines can not be used simultaneously. 3-line half-duplex 3-line here means: clock line, CS line, and one data line. The data line is used to transmit or receive data. 1-bit SPI In one clock cycle, one bit can be transferred. (2-bit) Dual SPI In one clock cycle, two bits can be transferred. Dual Output Read A data mode of Dual SPI. In one clock cycle, one bit of a command, or one bit of an address, or two bits of data can be transferred. Dual I/O Read Another data mode of Dual SPI. In one clock cycle, one bit of a command, or two bits of an address, or two bits of data can be transferred. (4-bit) Quad SPI In one clock cycle, four bits can be transferred. Quad Output Read A data mode of Quad SPI. In one clock cycle, one bit of a command, or one bit of an address, or four bits of data can be transferred. Quad I/O Read Another data mode of Quad SPI. In one clock cycle, one bit of a command, or four bits of an address, or four bits of data can be transferred. QPI In one clock cycle, four bits of a command, or four bits of an ad- dress, or four bits of data can be transferred. FSPI Fast SPI. The prefix of the signals for GP-SPI2. FSPI bus signals are routed to GPIO pins via either GPIO matrix or IO MUX. 29.3 Features GP-SPI2 has the following features: • Works as master or as slave • Half- and full-duplex communications • CPU- and DMA-controlled transfers • Various data modes – 1-bit SPI mode – 2-bit Dual SPI mode – 4-bit Quad SPI mode – QPI mode • Configurable module clock frequency Espressif Systems 919 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) – Master: up to 80 MHz – Slave: up to 40 MHz • Configurable data length – CPU-controlled transfer as master or as slave: 1∼64 bytes – DMA-controlled single transfer as master: 1∼32 KB – DMA-controlled configurable segmented transfer as master: data length is unlimited – DMA-controlled single transfer or segmented transfer as slave: data length is unlimited • Configurable bit read/write order • Independent interrupts for CPU-controlled transfer and DMA-controlled transfer • Configurable clock polarity and phase • Four SPI clock modes: mode 0∼mode 3 • Multiple CS lines as master: CS0∼CS5 • Able to communicate with SPI devices, such as a sensor, a screen controller, as well as a flash or RAM chip 29.4 Architectural Overview Figure 29.4-1. SPI Module Overview Figure 29.4-1 shows an overview of this SPI module. GP-SPI2 exchanges data with SPI devices in the following ways: • CPU-controlled transfer: CPU <-> GP-SPI2 <-> SPI devices • DMA-controlled transfer: GDMA <-> GP-SPI2 <-> SPI devices The signals for GP-SPI2 are prefixed with “FSPI” (Fast SPI). FSPI bus signals are routed to GPIO pins via either the GPIO matrix or the IO MUX. For more information, see Chapter 6 GPIO Matrix and IO MUX. 29.5 Functional Description Espressif Systems 920 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) 29.5.1 Data Modes GP-SPI2 can be configured as either a master or a slave to communicate with other SPI devices in the following data modes. See Table 29.5-1. Table 29.5-1. Data Modes Supported by GP-SPI2 Data Mode CMD State Address State Data State 1-bit SPI 1-bit 1-bit 1-bit Dual SPI Dual Output Read 1-bit 1-bit 2-bit Dual I/O Read 1-bit 2-bit 2-bit Quad SPI Quad Output Read 1-bit 1-bit 4-bit Quad I/O Read 1-bit 4-bit 4-bit QPI 4-bit 4-bit 4-bit For more information about the states used when GP-SPI2 works as a master or a slave, see Section 29.5.9 and Section 29.5.10, respectively. 29.5.2 FSPI Bus Signals Table 29.5-2 describes the functions of FSPI bus signals. Table 29.5-3 lists the signals used in various SPI modes. Table 29.5-2. Functional Description of FSPI Bus Signals FSPI Bus Signal Function FSPID MOSI/SIO0 (serial data input and output, bit0) FSPIQ MISO/SIO1 (serial data input and output, bit1) FSPIWP SIO2 (serial data input and output, bit2) FSPIHD SIO3 (serial data input and output, bit3) FSPICLK Input and output clock as master/slave FSPICS0 Input and output CS signal as master/slave FSPICS1∼5 Output CS signal as master Espressif Systems 921 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Table 29.5-3. FSPI Bus Signals Used in Various SPI Modes Master Slave 1-bit SPI 1-bit SPIFSPI Bus Signal FD 1 3-line HD 2 4-line HD 2-bit Dual SPI 4-bit Quad SPI QPI FD 3-line HD 4-line HD 2-bit Dual SPI 4-bit Quad SPI QPI FSPICLK Y Y Y Y Y Y Y Y Y Y Y Y FSPICS0 Y Y Y Y Y Y Y Y Y Y Y Y FSPICS1 Y Y Y Y Y Y FSPICS2 Y Y Y Y Y Y FSPICS3 Y Y Y Y Y Y FSPICS4 Y Y Y Y Y Y FSPICS5 Y Y Y Y Y Y FSPID Y Y (Y) 3 Y 4 Y 5 Y Y Y (Y) 6 Y 7 Y 8 Y FSPIQ Y (Y) 3 Y 4 Y 5 Y Y (Y) 6 Y 7 Y 8 Y FSPIWP Y 5 Y Y 8 Y FSPIHD Y 5 Y Y 8 Y 1 FD: full-duplex 2 HD: half-duplex 3 Only one of the two signals is used at a time. 4 The two signals are used in parallel. 5 The four signals are used in parallel. 6 Only one of the two signals is used at a time. 7 The two signals are used in parallel. 8 The four signals are used in parallel. Espressif Systems 922 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) 29.5.3 Bit Read/Write Order Control • When operating as a master: – The bit order of the command, address, and data sent by the GP-SPI master is controlled by SPI_WR_BIT_ORDER. – The bit order of the data received by the master is controlled by SPI_RD_BIT_ORDER. • When operating as a slave: – The bit order of the data sent by the GP-SPI slave is controlled by SPI_WR_BIT_ORDER. – The bit order of the command, address, and data received by the slave is controlled by SPI_RD_BIT_ORDER. Table 29.5-4 shows the functions of SPI_RD/WR_BIT_ORDER. Espressif Systems 923 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Table 29.5-4. Bit Order Control in GP-SPI2 Bit Mode FSPI Bus Data SPI_RD/WR_BIT_ORDER = 0 (MSB) SPI_RD/WR_BIT_ORDER = 2 (MSB) SPI_RD/WR_BIT_ORDER = 1 (LSB) SPI_RD/WR_BIT_ORDER = 3 (LSB) 1-bit mode FSPID or FSPIQ B7->B6->B5->B4->B3->B2->B1->B0 B7->B6->B5->B4->B3->B2->B1->B0 B0->B1->B2->B3->B4->B5->B6->B7 B0->B1->B2->B3->B4->B5->B6->B7 2-bit mode FSPIQ B7->B5->B3->B1 B6->B4->B2->B0 B1->B3->B5->B7 B0->B2->B4->B6 FSPID B6->B4->B2->B0 B7->B5->B3->B1 B0->B2->B4->B6 B1->B3->B5->B7 4-bit mode FSPIHD B7->B3 B4->B0 B3->B7 B0->B4 FSPIWP B6->B2 B5->B1 B2->B6 B1->B5 FSPIQ B5->B1 B6->B2 B1->B5 B2->B6 FSPID B4->B0 B7->B3 B0->B4 B3->B7 Espressif Systems 924 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) 29.5.4 Unaligned Byte Transfer • When operating as a master, GP-SPI2 sends and receives data in bits. The bit length is equal to SPI_MS_DATA_BITLEN + 1, a multiple of 1/2/4/8 in 1/2/4/8-bit mode. – When sending data whose length is not an integer multiple of 8 bits, the software needs to fill the last part of the data less than 8 bits into a full 1-byte data. – When receiving data whose length is not an integer multiple of 8 bits, the part less than 1 byte is still received as 1 byte. • When operating as slave, GP-SPI2 sends and receives data in bits. The bit length is a multiple of 1/2/4/8 in 1/2/4/8-bit mode. – When sending data whose length is not an integer multiple of 8 bits, the software needs to fill the last part of the data less than 8 bits into a full 1-byte data. – When receiving data whose length is not an integer multiple of 8 bits, the part less than 1 byte is still received as 1 byte. The total bit length received can be read from SPI_SLV_DATA_BITLEN. The valid bits in the last 1 byte is indicated by SPI_SLV_LAST_BYTE_STRB. Note: No matter working as master or slave, GP-SPI2 sends and receives the data parts less than 1 byte following the same bit order as the other data bits as configured. 29.5.5 Transfer Types The transfer types supported by GP-SPI2 working as a master or a slave are shown in Table 29.5-5. Table 29.5-5. Supported Transfer Types as Master or Slave Mode CPU- Controlled Single Transfer DMA- Controlled Single Transfer DMA-Controlled Configurable Segmented Transfer DMA-Controlled Slave Segmented Transfer Master Full-Duplex Y Y Y – Half-Duplex Y Y Y – Slave Full-Duplex Y Y – Y Half-Duplex Y Y – Y The following sections provide detailed information about the transfer types listed in the table above. 29.5.6 CPU-Controlled Data Transfer GP-SPI2 provides 16 x 32-bit data buffers: SPI_W0_REG∼SPI_W15_REG. Figure 29.5-1 shows the buffer’s structure. CPU-controlled transfer indicates the transfer in which the data to send is from GP-SPI2 data buffer and the received data is stored to GP-SPI2 data buffer. In such transfer, every single transaction needs to be triggered by the CPU, after its related registers are configured. For such reason, the CPU-controlled transfer is Espressif Systems 925 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) always single transfer (consisting of only one transaction). CPU-controlled transfer supports full-duplex communication and half-duplex communication. Figure 29.5-1. Data Buffer Used in CPU-Controlled Transfer 29.5.6.1 CPU-Controlled Master Transfer In a CPU-controlled master full-duplex or half-duplex transfer, the RX or TX data is saved to or sent from SPI_W0_REG∼SPI_W15_REG. The bits SPI_USR_MOSI_HIGHPART and SPI_USR_MISO_HIGHPART control which buffers are used. See the description below. • TX data – When SPI_USR_MOSI_HIGHPART is cleared, i.e., high part mode is disabled, TX data is read from SPI_W0_REG∼SPI_W15_REG and the data address is incremented by 1 on each byte transferred. If the data byte length is larger than 64, the data in SPI_W0_REG∼SPI_W15_REG may be sent more than once. Take each 256 bytes as a cycle: * The first 64 bytes (Byte 0∼Byte 63) are read from SPI_W0_REG∼SPI_W15_REG, sequentially. * Byte 64∼Byte 255 are read from SPI_W15_REG[31:24] repeatedly. * Byte 256∼Byte 319 (the first 64 bytes in another 256 bytes) are read from SPI_W0_REG∼SPI_W15_REG again, sequentially, same as the behaviors described above. For instance: to send 258 bytes (Byte 0∼Byte 257), the data is read from the registers as follows: * The first 64 bytes (Byte 0∼Byte 63) are read from SPI_W0_REG∼SPI_W15_REG, sequentially. * Byte 64∼Byte 255 are read from SPI_W15_REG[31:24] repeatedly. * The other bytes (Byte 256 and Byte 257) are read from SPI_W0_REG[7:0] and SPI_W0_REG[15:8] again, sequentially. The logic is: · The address to read data for Byte 256 is the result of (256 % 64 = 0), i.e., SPI_W0_REG[7:0]. · The address to read data for Byte 257 is the result of (257 % 64 = 1), i.e., SPI_W0_REG[15:8]. – When SPI_USR_MOSI_HIGHPART is set, i.e., high part mode is enabled, TX data is read from SPI_W8_REG∼SPI_W15_REG and the data address is incremented by 1 on each byte transferred. If the data byte length is larger than 32, the data in SPI_W8_REG∼SPI_W15_REG may be sent more than once. Take each 256 bytes as a cycle: Espressif Systems 926 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) * The first 32 bytes (Byte 0∼Byte 31) are read from SPI_W8_REG∼SPI_W15_REG, sequentially. * Byte 32∼Byte 255 are read from SPI_W15_REG[31:24] repeatedly. * Byte 256∼Byte 287 (the first 32 bytes in the another 256 bytes) are read from SPI_W8_REG∼SPI_W15_REG again, sequentially, same as the behaviors described above. For instance: to send 258 bytes (Byte 0∼Byte 257), the data is read from the registers as follows: * The first 32 bytes (Byte 0∼Byte 31) are read from SPI_W8_REG∼SPI_W15_REG, sequentially. * Byte 32∼Byte 255 are read from SPI_W15_REG[31:24] repeatedly. * The other bytes (Byte 256 and Byte 257) are read from SPI_W8_REG[7:0] and SPI_W8_REG[15:8] again, sequentially. The logic is: · The address to read data for Byte 256 is the result of (256 % 32 = 0), i.e., SPI_W8_REG[7:0]. · The address to read data for Byte 257 is the result of (257 % 32 = 1), i.e., SPI_W8_REG[15:8]. • RX data – When SPI_USR_MISO_HIGHPART is cleared, i.e., high part mode is disabled, RX data is saved to SPI_W0_REG∼SPI_W15_REG, and the data address is incremented by 1 on each byte transferred. If the data byte length is larger than 64, the data in SPI_W0_REG∼SPI_W15_REG may be overwritten. Take each 256 bytes as a cycle: * The first 64 bytes (Byte 0∼Byte 63) are saved to SPI_W0_REG∼SPI_W15_REG, sequentially. * Byte 64∼Byte 255 are saved to SPI_W15_REG[31:24] repeatedly. * Byte 255∼Byte 319 (the first 64 bytes in the another 256 bytes) are saved to SPI_W0_REG∼SPI_W15_REG again, sequentially, same as the behaviors described above. For instance: to receive 258 bytes (Byte 0∼Byte 257), the data is saved to the registers as follows: * The first 64 bytes (Byte 0∼Byte 63) are saved to SPI_W0_REG∼SPI_W15_REG, sequentially. * Byte 64∼Byte 255 are saved to SPI_W15_REG[31:24] repeatedly. * The other bytes (Byte 256 and Byte 257) are saved to SPI_W0_REG[7:0] and SPI_W0_REG[15:8] again, sequentially. The logic is: · The address to save Byte 256 is the result of (256 % 64 = 0), i.e., SPI_W0_REG[7:0]. · The address to save Byte 257 is the result of (257 % 64 = 1), i.e., SPI_W0_REG[15:8]. – When SPI_USR_MISO_HIGHPART is set, i.e., high part mode is enabled, the RX data is saved to SPI_W8_REG∼SPI_W15_REG, and the data address is incremented by 1 on each byte transferred. If the data byte length is larger than 32, the content of SPI_W8_REG∼SPI_W15_REG may be overwritten. Take each 256 bytes as a cycle: * Byte 0∼Byte 31 are saved to SPI_W8_REG∼SPI_W15_REG, sequentially. * Byte 32∼Byte 255 are saved to SPI_W15_REG[31:24] repeatedly. * Byte 256∼Byte 287 (the first 32 bytes in the another 256 bytes) are saved to SPI_W8_REG∼SPI_W15_REG again, sequentially. Espressif Systems 927 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) For instance: to receive 258 bytes (Byte 0∼Byte 257), the data is saved to the registers as follows: * The first 32 bytes (Byte 0∼Byte 31) are saved to SPI_W8_REG∼SPI_W15_REG, sequentially. * Byte 32∼Byte 255 are saved to SPI_W15_REG[31:24] repeatedly. * The other bytes (Byte 256 and Byte 257) are saved to SPI_W8_REG[7:0] and SPI_W8_REG[15:8] again, sequentially. The logic is: · The address to save Byte 256 is the result of (256 % 32 = 0), i.e., SPI_W8_REG[7:0]. · The address to save Byte 257 is the result of (257 % 32 = 1), i.e., SPI_W8_REG[15:8]. Note: • TX/RX data address mentioned above both are byte-addressable. – If high part mode is disabled, Address 0 stands for SPI_W0_REG[7:0], and Address 1 for SPI_W0_REG[15:8], and so on. – If high part mode is enabled, Address 0 stands for SPI_W8_REG[7:0], and Address 1 for SPI_W8_REG[15:8], and so on. The largest address points to SPI_W15_REG[31:24]. • To avoid any possible error in TX/RX data, such as TX data being sent more than once or RX data being overwritten, please make sure the registers are configured correctly. 29.5.6.2 CPU-Controlled Slave Transfer In a CPU-controlled slave full-duplex or half-duplex transfer, the RX or TX data is saved to or sent from SPI_W0_REG∼SPI_W15_REG, which are byte-addressable. • In full-duplex communication, the address of SPI_W0_REG∼SPI_W15_REG starts from 0 and is incremented by 1 on each byte transferred. If the data address is larger than 63, the data in SPI_W0_REG∼SPI_W15_REG will be overwritten, same as the behaviors described in the master transfer when high part mode is disabled. • In half-duplex communication, the ADDR value in transmission format is the start address of the RX or TX data, corresponding to the registers SPI_W0_REG∼SPI_W15_REG. The RX or TX address is incremented by 1 on each byte transferred. If the address is larger than 63 (the highest byte address, i.e., SPI_W15_REG[31:24]), the data in SPI_W8_REG∼SPI_W15_REG will be overwritten, same as the behaviors described in the master transfer when high part mode is enabled. According to your applications, the registers SPI_W0_REG∼SPI_W15_REG can be used as: • data buffers only • data buffers and status buffers • status buffers only 29.5.7 DMA-Controlled Data Transfer DMA-controlled transfer refers to the transfer in which the GDMA RX module receives data and the GDMA TX module sends data. This transfer is supported when the GP-SPI2 works as master or as slave. A DMA-controlled transfer can be: Espressif Systems 928 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) • a single transfer, consisting of only one transaction. GP-SPI2 supports this transfer when it works as master or as slave. • a configurable segmented transfer, consisting of several transactions (segments). GP-SPI2 supports this transfer only when works as a master. For more information, see Section 29.5.9.5. • a slave segmented transfer, consisting of several transactions (segments). GP-SPI2 supports this transfer only when works as a slave. For more information, see Section 29.5.10.3. A DMA-controlled transfer only needs to be triggered once by CPU. When such a transfer is triggered, data is transferred by the DMA engine from or to the DMA-linked memory, without CPU operation. DMA-controlled transfer supports full-duplex communication, half-duplex communication, and functions described in Section 29.5.9 and Section 29.5.10. Meanwhile, the GDMA RX module is independent from the GDMA TX module, which means that there are four kinds of full-duplex communications: • Data is received in DMA-controlled mode and sent in DMA-controlled mode. • Data is received in DMA-controlled mode but sent in CPU-controlled mode. • Data is received in CPU-controlled mode but sent in DMA-controlled mode. • Data is received in CPU-controlled mode and sent in CPU-controlled mode. 29.5.7.1 DMA Configuration • Select a GDMA channel n and configure GDMA TX/RX descriptor. See Chapter 3 GDMA Controller (GDMA). • Set AHB_DMA_INLINK_START_CHn or AHB_DMA_OUTLINK_START_CHn to start DMA RX or TX engine, respectively. • Before all the GDMA TX buffer is used or the GDMA TX engine is reset, if AHB_DMA_OUTLINK_RESTART_CHn is set, a new TX buffer will be added to the end of the last TX buffer in use. • GDMA RX buffer is linked in the same way as the GDMA TX buffer, by setting AHB_DMA_INLINK_START_CHn or AHB_DMA_INLINK_RESTART_CHn. • The TX and RX data lengths are determined by the configured GDMA TX and RX buffer respectively, both of which are 0∼32 KB. • Initialize GDMA inlink and outlink before GDMA starts. The bits SPI_DMA_RX_ENA and SPI_DMA_TX_ENA in register SPI_DMA_CONF_REG should be set, otherwise the read/write data will be stored to/sent from the registers SPI_W0_REG∼SPI_W15_REG. When GP-SPI2 operates as master, if AHB_DMA_IN_SUC_EOF_CHn_INT_ENA is set, then the interrupt AHB_DMA_IN_SUC_EOF_CHn_INT will be triggered when one single transfer or one configurable segmented transfer is finished. When GP-SPI2 operates as slave, if AHB_DMA_IN_SUC_EOF_CHn_INT_ENA is set, then the interrupt AHB_DMA_IN_SUC_EOF_CHn_INT will be triggered when one of the following conditions are met. Table 29.5-6. Interrupt Trigger Condition on GP-SPI2 Data Transfer as Slave Transfer Type Control Bit 1 Control Bit 2 Condition Slave Single Transfer 0 0 A single transfer is done. Espressif Systems 929 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) 1 0 A single transfer is done. Or the length of the received data is equal to ( SPI_MS_DATA_BITLEN + 1). Slave Segmented Transfer 0 1 CMD7 or End_SEG_TRANS is received correctly. 1 1 CMD7 or End_SEG_TRANS is received correctly. Or the length of the received data is equal to (SPI_MS_DATA_BITLEN + 1). 1 SPI_RX_EOF_EN 2 SPI_DMA_SLV_SEG_TRANS_EN 29.5.7.2 GDMA TX/RX Buffer Length Control It is recommended that the length of the configured DMA TX/RX buffer is equal to the length of actual data transferred. • If the length of the configured GDMA TX buffer is shorter than that of the actual data transferred, the extra data will be the same as the last transferred data. SPI_OUTFIFO_EMPTY_ERR_INT and AHB_DMA_OUT_EOF_CHn_INT are triggered. • If the length of the configured GDMA TX buffer is longer than that of the actual data transferred, the TX buffer is not fully used, and the remaining buffer will be used for the following transaction even if a new TX buffer is linked later. Please keep it in mind. Or save the unused data and reset the GDMA. • If the length of the configured GDMA RX buffer is shorter than that of the actual data transferred, the extra data will be lost. SPI_INFIFO_FULL_ERR_INT and SPI_TRANS_DONE_INT are triggered. But AHB_DMA_IN_SUC_EOF_CHn_INT is not triggered. • If the length of the configured GDMA RX buffer is longer than that of the actual data transferred, the RX buffer is not fully used, and the remaining buffer is discarded. In the following transaction, a new linked buffer will be used directly. 29.5.8 Data Flow Control CPU-controlled and DMA-controlled transfers are supported in GP-SPI2 both as master and as slave. CPU-controlled transfer means that data is transferred between registers SPI_W0_REG∼SPI_W15_REG and the SPI device. DMA-controlled transfer means that data is transferred between the configured GDMA TX/RX buffer and the SPI device. To select between the two transfer types, configure SPI_DMA_RX_ENA and SPI_DMA_TX_ENA before the transfer starts. Espressif Systems 930 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) 29.5.8.1 GP-SPI2 Functional Blocks Figure 29.5-2. GP-SPI2 Functional Blocks Figure 29.5-2 shows the main functional blocks in GP-SPI2, including: • Master FSM: all the features supported in GP-SPI2 as master are controlled by this state machine together with register configuration. • SPI Buffer: SPI_W0_REG∼SPI_W15_REG. See Figure 29.5-1. The data in CPU-controlled transfer is prepared in this buffer. • Timing Module: captures data on FSPI bus. • spi_mst/slv_din_ctrl and spi_mst/slv_dout_ctrl: converts the TX/RX data into bytes. • spi_rx_afifo: stores the received data. • buf_tx_afifo: stores the data to send. • dma_tx_afifo: stores the data from GDMA. • clk_spi_mst: this clock is divided from PLL_CLK and works as the module clock of GP-SPI2, to generate SPI_CLK signal for data transfer and for slaves, when GP-SPI2 works as master. • SPI_CLK Generator: generates SPI_CLK by dividing clk_spi_mst. The divider is determined by SPI_CLKCNT_N and SPI_CLKDIV_PRE. • SPI_CLK_out Mode Control: outputs the SPI_CLK signal for data transfer and for slaves. • SPI_CLK_in Mode Control: captures the SPI_CLK signal from SPI master when GP-SPI2 works as slave. Espressif Systems 931 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) 29.5.8.2 Data Flow Control When GP-SPI2 Works as Master Figure 29.5-3. Data Flow Control When GP-SPI2 Works as Master Figure 29.5-3 shows the data flow when GP-SPI2 works as master. Its control logic is as follows: • RX data: data bits on FSPI bus are captured by Timing Module, converted into bytes by spi_mst_din_ctrl module, then buffered in spi_rx_afifo, and finally stored in corresponding addresses according to the transfer types. – CPU-controlled transfer: the data is stored to registers SPI_W0_REG ∼SPI_W15_REG. – DMA-controlled transfer: the data is stored to GDMA RX buffer. • TX data: the TX data is from corresponding addresses according to transfer modes and is saved to buf_tx_afifo. – CPU-controlled transfer: TX data is from SPI_W0_REG∼SPI_W15_REG. – DMA-controlled transfer: TX data is from GDMA TX buffer. The data in buf_tx_afifo is sent out to Timing Module in 1/2/4-bit modes, controlled by GP-SPI2 state machine. The Timing Module can be used for timing compensation. For more information, see Section 29.8. 29.5.8.3 Data Flow Control When GP-SPI2 Works as Slave Figure 29.5-4. Data Flow Control When GP-SPI2 Works as Slave Figure 29.5-4 shows the data flow when GP-SPI2 works as slave. Its control logic is as follows: Espressif Systems 932 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) • In CPU/DMA-controlled full-/half-duplex transfer, when an external SPI master starts the SPI transfer, data on the FSPI bus is captured, converted into bytes by the spi_slv_din_ctrl module, and then is stored in spi_rx_afifo. – In CPU-controlled full-duplex transfer, the received data in spi_rx_afifo will be later stored into registers SPI_W0_REG∼SPI_W15_REG, successively. – In half-duplex Wr_BUF transfer, when the value of address (SLV_ADDR[7:0]) is received, the received data in spi_rx_afifo will be stored in the related address of registers SPI_W0_REG ∼SPI_W15_REG. – In DMA-controlled full-duplex transfer or in half-duplex Wr_DMA transfer, the received data in spi_rx_afifo will be stored in the configured GDMA RX buffer. • In CPU-controlled full-/half-duplex transfer, the data to send is stored in buf_tx_afifo. In DMA-controlled full-/half-duplex transfer, the data to send is stored in dma_tx_afifo. Therefore, Rd_BUF transaction controlled by CPU and Rd_DMA transaction controlled by DMA can be done in one slave segmented transfer. – In CPU-controlled full-duplex transfer, when SPI_SLAVE_MODE and SPI_DOUTDIN are set and SPI_DMA_TX_ENA is cleared, the data in SPI_W0_REG∼SPI_W15_REG will be stored into buf_tx_afifo. – In CPU-controlled half-duplex transfer, when SPI_SLAVE_MODE is set, SPI_DOUTDIN is cleared, Rd_BUF command and SLV_ADDR[7:0] are received, the data started from the related address of SPI_W0_REG∼SPI_W15_REG will be stored into buf_tx_afifo. – In DMA-controlled full-duplex transfer, when SPI_SLAVE_MODE, SPI_DOUTDIN, and SPI_DMA_TX_ENA are set, the data in the configured GDMA TX buffer will be stored into dma_tx_afifo. – In DMA-controlled half-duplex transfer, when SPI_SLAVE_MODE is set, SPI_DOUTDIN is cleared, and Rd_DMA command is received, the data in the configured DMA TX buffer will be stored into dma_tx_afifo. The data in buf_tx_afifo or dma_tx_afifo is sent out by spi_slv_dout_ctrl module in 1/2/4-bit modes. 29.5.9 GP-SPI2 Works as Master GP-SPI2 can be configured as an SPI master by clearing the bit SPI_SLAVE_MODE in SPI_SLAVE_REG. In this operation mode, GP-SPI2 provides clock signal (the divided clock from GP-SPI module clock) and CS signal (CS0∼CS5). 29.5.9.1 State Machine When GP-SPI2 works as master, the state machine controls GP-SPI2’s various states during data transfer, including configuration (CONF), preparation (PREP), command (CMD), address (ADDR), dummy (DUMMY), data out (DOUT), and data in (DIN) states. GP-SPI2 is mainly used to access 1/2/4-bit SPI devices, such as flash and external RAM, thus the naming of GP-SPI2 states keeps consistent with the sequence naming of flash and external RAM. The meaning of each state is described as follows and Figure 29.5-5 shows the workflow of GP-SPI2 state machine. 1. IDLE: GP-SPI2 is not active or is operating as a slave. Espressif Systems 933 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) 2. CONF: only used in DMA-controlled configurable segmented transfer. Set SPI_USR and SPI_USR_CONF to enable this state. If this state is not enabled, it means the current transfer is a single transfer. 3. PREP: prepare an SPI transaction and control SPI CS setup time. Set SPI_USR and SPI_CS_SETUP to enable this state. 4. CMD: send command sequence. Set SPI_USR and SPI_USR_COMMAND to enable this state. 5. ADDR: send address sequence. Set SPI_USR and SPI_USR_ADDR to enable this state. 6. DUMMY (wait cycle): send dummy sequence. Set SPI_USR and SPI_USR_DUMMY to enable this state. 7. DATA: transfer data. • DOUT: send data sequence. Set SPI_USR and SPI_USR_MOSI to enable this state. • DIN: receive data sequence. Set SPI_USR and SPI_USR_MISO to enable this state. 8. DONE: control SPI CS hold time. Set SPI_USR to enable this state. Note: To start this state machine, set SPI_USR first. SPI_MST_FD_WAIT_DMA_TX_DATA controls when SPI_USR takes effect: • 0: the configured state takes effect immediately after SPI_USR and other control registers are configured. • 1: if DOUT state is configured, the SPI_USR and other control registers will take effect, and the state machine will start, only when the data is ready in buf_tx_afifo. Espressif Systems 934 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Figure 29.5-5. GP-SPI2 State Machine Espressif Systems 935 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Legend to state flow: • —: indicates corresponding state condition is not satisfied; repeats current state. • —: corresponding registers are set and conditions are satisfied; goes to next state. • —: state registers are not set; skips one or more following states, depending on whether the registers of the following states are set or not. Explanation of the conditions listed in the figure above: • CONF condition: gpc[17:0] >= SPI_CONF_BITLEN[17:0] • PREP condition: gpc[4:0] >= SPI_CS_SETUP_TIME[4:0] • CMD condition: gpc[3:0] >= SPI_USR_COMMAND_BITLEN[3:0] • ADDR condition: gpc[4:0] >= SPI_USR_ADDR_BITLEN[4:0] • DUMMY condition: gpc[7:0] >= SPI_USR_DUMMY_CYCLELEN[7:0] • DOUT condition: gpc[17:0] >= SPI_MS_DATA_BITLEN[17:0] • DIN condition: gpc[17:0] >= SPI_MS_DATA_BITLEN[17:0] • DONE condition: (gpc[4:0] >= SPI_CS_HOLD_TIME[4:0] || SPI_CS_HOLD == 1’b0) A counter (gpc[17:0]) is used in the state machine to control the cycle length of each state. The states CONF, PREP, CMD, ADDR, DUMMY, DOUT, and DIN can be enabled or disabled independently. The cycle length of each state can also be configured independently. 29.5.9.2 Register Configuration for State and Bit Mode Control Introduction The registers, related to GP-SPI2 state control, are listed in Table 29.5-7. Users can enable QPI mode for GP-SPI2 by setting the bit SPI_QPI_MODE in register SPI_USER_REG. Espressif Systems 936 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Table 29.5-7. Registers Used for State Control in 1/2/4-bit Modes State Control Registers for 1-bit Mode FSPI Bus Control Registers for 2-bit Mode FSPI Bus Control Registers for 4-bit Mode FSPI Bus CMD SPI_USR_COMMAND_VALUE SPI_USR_COMMAND_BITLEN SPI_USR_COMMAND SPI_USR_COMMAND_VALUE SPI_USR_COMMAND_BITLEN SPI_FCMD_DUAL SPI_USR_COMMAND SPI_USR_COMMAND_VALUE SPI_USR_COMMAND_BITLEN SPI_FCMD_QUAD SPI_USR_COMMAND ADDR SPI_USR_ADDR_VALUE SPI_USR_ADDR_BITLEN SPI_USR_ADDR SPI_USR_ADDR_VALUE SPI_USR_ADDR_BITLEN SPI_USR_ADDR SPI_FADDR_DUAL SPI_USR_ADDR_VALUE SPI_USR_ADDR_BITLEN SPI_USR_ADDR SPI_FADDR_QUAD DUMMY SPI_USR_DUMMY_CYCLELEN SPI_USR_DUMMY SPI_USR_DUMMY_CYCLELEN SPI_USR_DUMMY SPI_USR_DUMMY_CYCLELEN SPI_USR_DUMMY DIN SPI_USR_MISO SPI_MS_DATA_BITLEN SPI_USR_MISO SPI_MS_DATA_BITLEN SPI_FREAD_DUAL SPI_USR_MISO SPI_MS_DATA_BITLEN SPI_FREAD_QUAD DOUT SPI_USR_MOSI SPI_MS_DATA_BITLEN SPI_USR_MOSI SPI_MS_DATA_BITLEN SPI_FWRITE_DUAL SPI_USR_MOSI SPI_MS_DATA_BITLEN SPI_FWRITE_QUAD Espressif Systems 937 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) As shown in Table 29.5-7, the registers in each cell should be configured to set the FSPI bus to corresponding bit mode, i.e., the mode shown in the table header, at a specific state (corresponding to the first column). Configuration For instance, when GP-SPI2 reads data, and • CMD is in 1-bit mode • ADDR is in 2-bit mode • DUMMY lasts for 8 clock cycles • DIN is in 4-bit mode The register configuration can be as follows: 1. Configure CMD state related registers. • Configure the required command value in SPI_USR_COMMAND_VALUE. • Configure command bit length in SPI_USR_COMMAND_BITLEN. SPI_USR_COMMAND_BITLEN = expected bit length - 1. • Set SPI_USR_COMMAND. • Clear SPI_FCMD_DUAL AND SPI_FCMD_QUAD. 2. Configure ADDR state related registers. • Configure the required address value in SPI_USR_ADDR_VALUE. • Configure address bit length in SPI_USR_ADDR_BITLEN. SPI_USR_ADDR_BITLEN = expected bit length - 1. • Set SPI_USR_ADDR and SPI_FADDR_DUAL. • Clear SPI_FADDR_QUAD. 3. Configure DUMMY state related registers. • Configure DUMMY cycles in SPI_USR_DUMMY_CYCLELEN. SPI_USR_DUMMY_CYCLELEN = expected clock cycles - 1. • Set SPI_USR_DUMMY. 4. Configure DIN state related registers. • Configure read data bit length in SPI_MS_DATA_BITLEN. SPI_MS_DATA_BITLEN = expected bit length - 1. • Set SPI_FREAD_QUAD and SPI_USR_MISO. • Clear SPI_FREAD_DUAL. • Configure GDMA for DMA-controlled transfer. For CPU controlled transfer, no action is needed. 5. Clear SPI_USR_MOSI. 6. Set SPI_DMA_AFIFO_RST, SPI_BUF_AFIFO_RST, and SPI_RX_AFIFO_RST to reset these buffers. 7. Set SPI_USR to start GP-SPI2 transfer. Espressif Systems 938 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Note: Updating the configuration when the GP-SPI2 works as master described in this and subsequent sections requires setting SPI_UPDATE accordingly to synchronize the configuration from AHB_CLK domain to clk_spi_mst domain. For more detailed configuration, see the sections above. No operation is required when the GP-SPI2 works as slave. When writing data (DOUT state), SPI_USR_MOSI should be configured instead, while SPI_USR_MISO should be cleared. The output data bit length is the value of SPI_MS_DATA_BITLEN + 1. Output data should be configured in GP-SPI2 data buffer (SPI_W0_REG∼SPI_W15_REG) for CPU-controlled transfer, or GDMA TX buffer for DMA-controlled transfer. Pay special attention to the command value in SPI_USR_COMMAND_VALUE and the address value in SPI_USR_ADDR_VALUE. The configuration of command value is as follows: Table 29.5-8. Sending Sequence of Command Value COMMAND_BITLEN 1 COMMAND_VALUE 2 BIT_ORDER 3 Sending Sequence of Command Value 0∼7 [7:0] 1 COMMAND_VALUE[COMMAND_BITLEN:0] is sent first. 0 COMMAND_VALUE[7:7−COMMAND_BITLEN] is sent first. 8∼15 [15:0] 1 COMMAND_VALUE[7:0] is sent first, and then COMMAND_VALUE[COMMAND_BITLEN:8]. 0 COMMAND_VALUE[7:0] is sent first, and then COM- MAND_VALUE[15:15−COMMAND_BITLEN]. 1 SPI_USR_COMMAND_BITLEN: this field is used to configure the bit length of the command. 2 SPI_USR_COMMAND_VALUE: command value is written into this field. For which part of this field is used, see the table above. 3 SPI_WR_BIT_ORDER: For the detailed configuration, see Table 29.5-4. The configuration of address value is as follows: Table 29.5-9. Sending Sequence of Address Value ADDR_BITLEN 1 ADDR_VALUE 2 BIT_ORDER 3 Sending Sequence of Address Value 0∼7 [31:24] 1 COMMAND_VALUE[ADDR_BITLEN + 24:24] is sent first. 0 ADDR_VALUE[31:31−ADDR_BITLEN] is sent first. 8∼15 [31:16] 1 ADDR_VALUE[31:24] is sent first, and then ADDR_VALUE[ADDR_BITLEN + 8:16]. 0 ADDR_VALUE[31:24] is sent first, and then ADDR_VALUE[23:31−ADDR_BITLEN]. 16∼23 [31:8] 1 ADDR_VALUE[31:16] is sent first, and then ADDR_VALUE[ADDR_BITLEN−8:8]. Espressif Systems 939 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) 0 ADDR_VALUE[31:16] is sent first, and then ADDR_VALUE[15:31−ADDR_BITLEN]. 24∼31 [31:0] 1 ADDR_VALUE[31:8] is sent first, and then ADDR_VALUE[ADDR_BITLEN−24:0]. 0 ADDR_VALUE[31:8] is sent first, and then ADDR_VALUE[7:31−ADDR_BITLEN]. 1 SPI_USR_ADDR_BITLEN: this field is used to configure the bit length of the address. 2 SPI_USR_ADDR_VALUE: address value is written into this field. For which part of this field is used, see the table above. 3 SPI_WR_BIT_ORDER: For the detailed configuration, see Table 29.5-4. 29.5.9.3 Full-Duplex Communication (1-bit Mode Only) Introduction GP-SPI2 supports SPI full-duplex communication. In this mode, SPI master provides CLK and CS signals, exchanging data with SPI slave in 1-bit mode via MOSI (FSPID, sending) and MISO (FSPIQ, receiving) at the same time. To enable this communication mode, set the bit SPI_DOUTDIN in register SPI_USER_REG. Figure 29.5-6 illustrates the connection of GP-SPI2 with its slave in full-duplex communication. Figure 29.5-6. Full-Duplex Communication Between GP-SPI2 Master and a Slave In full-duplex communication, the behavior of states CMD, ADDR, DUMMY, DOUT, and DIN are configurable. Usually, the states CMD, ADDR and DUMMY are not used in this communication. The bit length of transferred data is configured in SPI_MS_DATA_BITLEN. The actual bit length used in communication equals to (SPI_MS_DATA_BITLEN + 1). Configuration To start a data transfer, follow the steps below: • Configure the IO path via IO MUX or GPIO matrix between GP-SPI2 and an external SPI device. • Configure AHB_CLK and APB_CLK (See Chapter 7 Reset and Clock) and module clock (clk_spi_mst) for the GP-SPI2 module. • Set SPI_DOUTDIN and clear SPI_SLAVE_MODE, to enable master full-duplex communication. • Configure GP-SPI2 registers listed in Table 29.5-7. • Configure SPI CS setup time and hold time according to Section 29.6. • Set the polarity of FSPICLK according to Section 29.7. Espressif Systems 940 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) • Prepare data according to the selected transfer type: – In CPU-controlled MOSI transfer, prepare data in registers SPI_W0_REG∼SPI_W15_REG. – In DMA-controlled transfer, * configure SPI_DMA_TX_ENA/SPI_DMA_RX_ENA, * configure GDMA TX/RX link, * and start GDMA TX/RX engine, as described in Section 29.5.7 and Section 29.5.8. • Configure interrupts and wait for SPI slave to get ready for transfer. • Set SPI_DMA_AFIFO_RST, SPI_BUF_AFIFO_RST, and SPI_RX_AFIFO_RST to reset these buffers. • Set SPI_USR in register SPI_CMD_REG to start the transfer and wait for the configured interrupts. 29.5.9.4 Half-Duplex Communication (1/2/4-bit Mode) Introduction In this mode, GP-SPI2 provides CLK and CS signals. Only one side (SPI master or slave) can send data at a time, while the other side receives the data. To enable this communication mode, clear the bit SPI_DOUTDIN in register SPI_USER_REG. The standard format of SPI half-duplex communication is CMD + [ADDR +] [DUMMY +] [DOUT or DIN]. The states ADDR, DUMMY, DOUT, and DIN are optional, and can be disabled or enabled independently. As described in Section 29.5.9.2, the properties of GP-SPI2 states: CMD, ADDR, DUMMY, DOUT and DIN, such as cycle length, value, and parallel bus bit mode, can be set independently. For the register configuration, see Table 29.5-7. The detailed properties of half-duplex GP-SPI2 are as follows: 1. CMD: 0∼16 bits, MOSI (master output, slave input). 2. ADDR: 0∼32 bits, MOSI (master output, slave input). 3. DUMMY: 0∼256 FSPICLK cycles, MOSI (master output, slave input). 4. DOUT: 0∼512 bits (64 bytes) in CPU-controlled transfer, 0∼256 Kbits (32 KB) in DMA-controlled single transfer, and unlimited length in DMA-controlled configurable segmented transfer, MOSI (master output, slave input). 5. DIN: 0∼512 bits (64 bytes) in CPU-controlled transfer, 0∼256 Kbits (32 KB) in DMA-controlled single transfer, and unlimited length in DMA-controlled configurable segmented transfer, MISO (slave output, master input). Configuration The register configuration can be as follows: 1. Configure the IO path via IO MUX or GPIO matrix between GP-SPI2 and an external SPI device. 2. Configure AHB_CLK, APB_CLK, and module clock (clk_spi_mst) for the GP-SPI2 module. 3. Clear SPI_DOUTDIN and SPI_SLAVE_MODE, to enable master half-duplex communication. 4. Configure GP-SPI2 registers listed in Table 29.5-7. 5. Configure SPI CS setup time and hold time according to Section 29.6. Espressif Systems 941 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) 6. Set the polarity of FSPICLK according to Section 29.7. 7. Prepare data according to the selected transfer type: • In CPU-controlled MOSI transfer, prepare data in registers SPI_W0_REG∼SPI_W15_REG. • In DMA-controlled transfer, – configure SPI_DMA_TX_ENA/SPI_DMA_RX_ENA, – configure GDMA TX/RX link, – and start GDMA TX/RX engine, as described in Section 29.5.7 and Section 29.5.8. 8. Configure interrupts and wait for SPI slave to get ready for transfer. 9. Set SPI_DMA_AFIFO_RST, SPI_BUF_AFIFO_RST, and SPI_RX_AFIFO_RST to reset these buffers. 10. Set SPI_USR in register SPI_CMD_REG to start the transfer and wait for the configured interrupts. Application Example The following example shows how GP-SPI2 accesses flash and external RAM in master half-duplex communication. Figure 29.5-7. Connection of GP-SPI2 to Flash and External RAM in 4-bit Mode Figure 29.5-8 indicates GP-SPI2 Quad I/O Read sequence according to standard flash specification. Other GP-SPI2 command sequences are implemented in accordance with the requirements of SPI slaves. Espressif Systems 942 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Figure 29.5-8. SPI Quad I/O Read Command Sequence Sent by GP-SPI2 to Flash 29.5.9.5 DMA-Controlled Configurable Segmented Transfer Note: Users can simply skip the CONF state of a configurable segmented transfer to implement a single transfer, so there is no separate section on how to configure a single transfer as master. Introduction When GP-SPI2 works as a master, it provides a feature named configurable segmented transfer controlled by DMA. A DMA-controlled transfer as master can be: • a single transfer, consisting of only one transaction; • or a configurable segmented transfer, consisting of several transactions (segments). In a configurable segmented transfer, the registers of each single transaction (segment) are configurable. This feature enables GP-SPI2 to do as many transactions (segments) as configured after such transfer is triggered once by the CPU. Figure 29.5-9 shows how this feature works. Figure 29.5-9. Configurable Segmented Transfer As shown in Figure 29.5-9, the registers for one transaction (segment n) can be reconfigured by GP-SPI2 hardware according to the content in its Conf_bufn during the CONF state, before this segment starts. It is recommended to provide separate GDMA CONF links and CONF buffers (Conf_bufi in Figure 29.5-9) for each CONF state. A GDMA TX link is used to connect all the CONF buffers and TX data buffers (Tx_bufi in Figure Espressif Systems 943 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) 29.5-9) into a chain. Hence, the behavior of the FSPI bus in each segment can be controlled independently. For example, in a configurable segmented transfer, its segment i, segment j, and segment k can be configured to full-duplex, half-duplex MISO, and half-duplex MOSI, respectively. i, j, and k represent different segment numbers. Meanwhile, the state of GP-SPI2, the data length and cycle length of the FSPI bus, and the behavior of the GDMA, can be configured independently for each segment. When this whole DMA-controlled transfer (consisting of several segments) has finished, a GP-SPI2 interrupt, SPI_DMA_SEG_TRANS_DONE_INT, is triggered. Configuration 1. Configure the IO path via IO MUX or GPIO matrix between GP-SPI2 and an external SPI device. 2. Configure AHB_CLK, APB_CLK, and module clock (clk_spi_mst) for the GP-SPI2 module. 3. Clear SPI_DOUTDIN and SPI_SLAVE_MODE, to enable master half-duplex communication. 4. Configure GP-SPI2 registers listed in Table 29.5-7. 5. Configure SPI CS setup time and hold time according to Section 29.6. 6. Set the polarity of FSPICLK according to Section 29.7. 7. Prepare descriptors for GDMA CONF buffer and TX data (optional) for each segment. Chain the descriptors of CONF buffer and TX buffers of several segments into one linked list. 8. Similarly, prepare descriptors for RX buffers for each segment and chain them into one linked list. 9. Configure all the needed CONF buffers, TX buffers and RX buffers, respectively for each segment before this DMA-controlled transfer begins. 10. Point AHB_DMA_OUTLINK_ADDR_CHn to the head address of the CONF and TX buffer descriptor linked list, and then set AHB_DMA_OUTLINK_START_CHn to start the TX GDMA. 11. Clear the bit SPI_RX_EOF_EN in register SPI_DMA_CONF_REG. Point AHB_DMA_INLINK_ADDR_CHn to the head address of the CONF and RX buffer descriptor linked list, and then set AHB_DMA_INLINK_START_CHn to start the RX GDMA. 12. Set SPI_USR_CONF to enable CONF state. 13. Set SPI_DMA_SEG_TRANS_DONE_INT_ENA to enable the SPI_DMA_SEG_TRANS_DONE_INT interrupt. Configure other interrupts if needed according to Section 29.9. 14. Wait for all the slaves to get ready for transfer. 15. Set SPI_DMA_AFIFO_RST, SPI_BUF_AFIFO_RST, and SPI_RX_AFIFO_RST to reset these buffers. 16. Set SPI_USR to start this DMA-controlled transfer. 17. Wait for SPI_DMA_SEG_TRANS_DONE_INT interrupt, which means this transfer has finished and the data has been stored into corresponding memory. Note: Prepare the data to send for each segment in its PREP state. Shall ensure that: (SP I_CS_SET U P _T IM E + 1) × T SP I _CLK >= 4 × (T AHB_CLK + T clk_spi_mst) Espressif Systems 944 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Configuration of CONF Buffer and Magic Value In a configurable segmented transfer, only registers which change from the last transaction (segment) need to be re-configured to new values in CONF state. The configuration of other registers can be skipped (i.e., kept the same) to save time and chip resources. The first word in GDMA CONF bufferi, called SPI_BIT_MAP_WORD, defines whether given GP-SPI2 register is to be updated or not in segment i. The relation of SPI_BIT_MAP_WORD and GP-SPI2 registers to update can be seen in Table 29.5-10 Bitmap (BM) Table. If a bit in the BM table is set to 1, its corresponding register value will be updated in this segment. Otherwise, if some registers should be kept from being changed, the related bits should be set to 0. Table 29.5-10. BM Table for CONF State BM Bit Register BM Bit Register 0 SPI_ADDR_REG 7 SPI_MISC_REG 1 SPI_CTRL_REG 8 SPI_DIN_MODE_REG 2 SPI_CLOCK_REG 9 SPI_DIN_NUM_REG 3 SPI_USER_REG 10 SPI_DOUT_MODE_REG 4 SPI_USER1_REG 11 SPI_DMA_CONF_REG 5 SPI_USER2_REG 12 SPI_DMA_INT_ENA_REG 6 SPI_MS_DLEN_REG 13 SPI_DMA_INT_CLR_REG Then new values of all the registers to be modified should be placed right after SPI_BIT_MAP_WORD, in consecutive words in the CONF buffer. To ensure the correctness of the content in each CONF buffer, the value in SPI_BIT_MAP_WORD[31:28] is used as a “magic value”, and will be compared with SPI_DMA_SEG_MAGIC_VALUE in register SPI_SLAVE_REG. The value of SPI_DMA_SEG_MAGIC_VALUE should be configured before this DMA-controlled transfer starts, and can not be changed during these segments. • If SPI_BIT_MAP_WORD[31:28] == SPI_DMA_SEG_MAGIC_VALUE, this DMA-controlled transfer continues normally. SPI_DMA_SEG_TRANS_DONE_INT is triggered at the end of this DMA-controlled transfer. • If SPI_BIT_MAP_WORD[31:28] != SPI_DMA_SEG_MAGIC_VALUE, GP-SPI2 state (spi_st) goes back to IDLE and the transfer is ended immediately. The interrupt SPI_DMA_SEG_TRANS_DONE_INT is still triggered, with SPI_SEG_MAGIC_ERR_INT_RAW bit set to 1. CONF Buffer Configuration Example Table 29.5-11 and Table 29.5-12 provide an example to configure a CONF buffer for a transaction (segmenti) in which SPI_ADDR_REG, SPI_CTRL_REG, SPI_CLOCK_REG, SPI_USER_REG, and SPI_USER1_REG need to be updated. Table 29.5-11. An Example of CONF bufferi in Segment i CONF bufferi Note SPI_BIT_MAP_WORD The first word in this buffer. Its value is 0xA000001F in this example when the SPI_DMA_SEG_MAGIC_VALUE is set to 0xA. As shown in Table 29.5-12, bits 0, 1, 2, 3, and 4 are set, indicating the follow- ing registers will be updated. Espressif Systems 945 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) SPI_ADDR_REG The second word, stores the new value to SPI_ADDR_REG. SPI_CTRL_REG The third word, stores the new value to SPI_CTRL_REG. SPI_CLOCK_REG The fourth word, stores the new value to SPI_CLOCK_REG. SPI_USER_REG The fifth word, stores the new value to SPI_USER_REG. SPI_USER1_REG The sixth word, stores the new value to SPI_USER1_REG. Table 29.5-12. BM Bit Value and Register to Be Updated in This Example BM Bit Value Register BM Bit Value Register 0 1 SPI_ADDR_REG 7 0 SPI_MISC_REG 1 1 SPI_CTRL_REG 8 0 SPI_DIN_MODE_REG 2 1 SPI_CLOCK_REG 9 0 SPI_DIN_NUM_REG 3 1 SPI_USER_REG 10 0 SPI_DOUT_MODE_REG 4 1 SPI_USER1_REG 11 0 SPI_DMA_CONF_REG 5 0 SPI_USER2_REG 12 0 SPI_DMA_INT_ENA_REG 6 0 SPI_MS_DLEN_REG 13 0 SPI_DMA_INT_CLR_REG Notes In a DMA-controlled configurable segmented transfer, please pay special attention to the following bits: • SPI_USR_CONF: set SPI_USR_CONF before SPI_USR is set, to enable this transfer. • SPI_USR_CONF_NXT: if segment i is not the final transaction of this whole DMA-controlled transfer, its SPI_USR_CONF_NXT bit should be set to 1. • SPI_CONF_BITLEN: GP-SPI2 CS setup time and hold time are programmable independently in each segment, see Section 29.6 for detailed configuration. The CS high time in each segment is about: (SP I_CON F _BIT LEN + 5) × T AHB_CLK The CS high time in CONF state can be set from 62.5 ns∼3.2768 ms when f AHB_CLK is 80 MHz. (SPI_CONF_BITLEN + 5) will overflow from (0x40000 - SPI_CONF_BITLEN - 5) if SPI_CONF_BITLEN is larger than 0x3FFFA. 29.5.10 GP-SPI2 Works as Slave GP-SPI2 can be used as a slave to communicate with an SPI master. As a slave, GP-SPI2 supports 1-bit SPI, 2-bit dual SPI, 4-bit quad SPI, and QPI modes, with specific communication formats. To enable this mode, set SPI_SLAVE_MODE in register SPI_SLAVE_REG. The CS signal must be held low during the transfer, and its falling and rising edges indicate the start and end of a single or segmented transfer. Take CS low-level effective as an example, when GP-SPI is used as a slave, the CS invalid duration (high-level) between each SPI transfer should not be less than 8 T AHB_CLK to ensure that each transfer can end normally. Espressif Systems 946 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) 29.5.10.1 Configurable Communication Formats When GP-SPI2 works as slave, full-duplex and half-duplex communications are available. To select from the two communications, configure SPI_DOUTDIN in register SPI_USER_REG. Full-duplex communication means that input data and output data are transmitted simultaneously throughout the entire transaction. All bits are treated as input or output data, which means no command, address or dummy states are expected. The interrupt SPI_TRANS_DONE_INT is triggered once the transaction ends. In half-duplex communication, the format is CMD+ADDR+DUMMY+DATA (DIN or DOUT). • “DIN” means that an SPI master reads data from GP-SPI2. • “DOUT” means that an SPI master writes data to GP-SPI2. The detailed properties of each state are as follows: 1. CMD: • Indicate the function of SPI slave. • One byte from master to slave. • Only the values in Table 29.5-13 and Table 29.5-14 are valid. • Can be sent in 1-bit SPI mode or 4-bit QPI mode. 2. ADDR: • The address for Wr_BUF and Rd_BUF commands in CPU-controlled transfer, or placeholder bits in other transfers and can be defined by application. • One byte from master to slave. • Can be sent in 1-bit, 2-bit, or 4-bit modes according to the command. 3. DUMMY: • Its value is meaningless. SPI slave prepares data in this state. • Bit mode of FSPI bus is also meaningless here. • Last for eight SPI_CLK cycles. 4. DIN or DOUT: • Data length can be 0∼64 bytes in CPU-controlled transfer and unlimited in DMA-controlled transfer. • Can be sent in 1-bit, 2-bit or 4-bit modes according to the CMD value. Note: The states of ADDR and DUMMY can never be skipped in any half-duplex communications. When a half-duplex transaction is complete, the transferred CMD and ADDR values are latched into SPI_SLV_LAST_COMMAND and SPI_SLV_LAST_ADDR, respectively. SPI_SLV_CMD_ERR_INT_RAW will be set if the transferred CMD value is not supported by GP-SPI2 as slave. SPI_SLV_CMD_ERR_INT_RAW can only be cleared by software. Espressif Systems 947 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) 29.5.10.2 CMD Values Supported in Half-Duplex Communication In half-duplex communication, the defined values of CMD determine the transfer types. Unsupported CMD values are disregarded, meanwhile the related transfer is ignored and SPI_SLV_CMD_ERR_INT_RAW is set. The transfer format is CMD (8 bits) + ADDR (8 bits) + DUMMY (8 SPI_CLK cycles) + DATA (unit in bytes). The detailed description of CMD[3:0] is as follows: • 0x1 (Wr_BUF): CPU-controlled write operation. Master sends data and GP-SPI2 receives data. The data is stored in the related address of SPI_W0_REG∼SPI_W15_REG. • 0x2 (Rd_BUF): CPU-controlled read operation. Master receives the data sent by GP-SPI2. The data comes from the related address of SPI_W0_REG∼SPI_W15_REG. • 0x3 (Wr_DMA): DMA-controlled write operation. Master sends data and GP-SPI2 receives data. The data is stored in GP-SPI2 GDMA RX buffer. • 0x4 (Rd_DMA): DMA-controlled read operation. Master receives the data sent by GP-SPI2. The data comes from GP-SPI2 GDMA TX buffer. • 0x7 (CMD7): used to generate an SPI_SLV_CMD7_INT interrupt. It can also generate a AHB_DMA_IN_SUC_EOF_CHn_INT interrupt in a slave segmented transfer when GDMA RX link is used. But it will not end GP-SPI2’s slave segmented transfer. • 0x8 (CMD8): only used to generate an SPI_SLV_CMD8_INT interrupt, which will not end GP-SPI2’s slave segmented transfer. • 0x9 (CMD9): only used to generate an SPI_SLV_CMD9_INT interrupt, which will not end GP-SPI2’s slave segmented transfer. • 0xA (CMDA): only used to generate an SPI_SLV_CMDA_INT interrupt, which will not end GP-SPI2’s slave segmented transfer. CMD7, CMD8, CMD9, and CMDA commands are reserved for user definition. These commands can be used as handshake signals, as passwords of some specific functions, as trigger signals of some user defined actions, and so on. 1/2/4-bit modes in states of CMD, ADDR, DATA are supported, which are determined by value of CMD[7:4]. The DUMMY state is always in 1-bit mode and lasts for eight SPI_CLK cycles. The definition of CMD[7:4] is as follows: • 0x0: CMD, ADDR, and DATA states are all in 1-bit mode. • 0x1: CMD and ADDR are in 1-bit mode. DATA is in 2-bit mode. • 0x2: CMD and ADDR are in 1-bit mode. DATA is in 4-bit mode. • 0x5: CMD is in 1-bit mode. ADDR and DATA are in 2-bit mode. • 0xA: CMD is in 1-bit mode, ADDR and DATA are in 4-bit mode or in QPI mode. In addition, if the value of CMD[7:0] is 0x05, 0xA5, 0x06, or 0xDD, DUMMY and DATA states are skipped. The definition of CMD[7:0] is as follows: • 0x05 (End_SEG_TRANS): master sends this command to end slave segmented transfer in SPI mode. • 0xA5 (End_SEG_TRANS): master sends this command to end slave segmented transfer in QPI mode. Espressif Systems 948 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) • 0x06 (En_QPI): GP-SPI2 enters QPI mode when receiving this command and the bit SPI_QPI_MODE in register SPI_USER_REG is set. • 0xDD (Ex_QPI): GP-SPI2 exits QPI mode when receiving this command and the bit SPI_QPI_MODE is cleared. All the CMD values supported by GP-SPI2 are listed in Table 29.5-13 and Table 29.5-14. Note that the DUMMY state is always in 1-bit mode and lasts for eight SPI_CLK cycles. Table 29.5-13. CMD Values Supported in SPI Mode Transfer Type CMD[7:0] CMD State ADDR State DATA State Wr_BUF 0x01 1-bit mode 1-bit mode 1-bit mode 0x11 1-bit mode 1-bit mode 2-bit mode 0x21 1-bit mode 1-bit mode 4-bit mode 0x51 1-bit mode 2-bit mode 2-bit mode 0xA1 1-bit mode 4-bit mode 4-bit mode Rd_BUF 0x02 1-bit mode 1-bit mode 1-bit mode 0x12 1-bit mode 1-bit mode 2-bit mode 0x22 1-bit mode 1-bit mode 4-bit mode 0x52 1-bit mode 2-bit mode 2-bit mode 0xA2 1-bit mode 4-bit mode 4-bit mode Wr_DMA 0x03 1-bit mode 1-bit mode 1-bit mode 0x13 1-bit mode 1-bit mode 2-bit mode 0x23 1-bit mode 1-bit mode 4-bit mode 0x53 1-bit mode 2-bit mode 2-bit mode 0xA3 1-bit mode 4-bit mode 4-bit mode Rd_DMA 0x04 1-bit mode 1-bit mode 1-bit mode 0x14 1-bit mode 1-bit mode 2-bit mode 0x24 1-bit mode 1-bit mode 4-bit mode 0x54 1-bit mode 2-bit mode 2-bit mode 0xA4 1-bit mode 4-bit mode 4-bit mode CMD7 0x07 1-bit mode 1-bit mode - 0x17 1-bit mode 1-bit mode - 0x27 1-bit mode 1-bit mode - 0x57 1-bit mode 2-bit mode - 0xA7 1-bit mode 4-bit mode - CMD8 0x08 1-bit mode 1-bit mode - 0x18 1-bit mode 1-bit mode - 0x28 1-bit mode 1-bit mode - 0x58 1-bit mode 2-bit mode - 0xA8 1-bit mode 4-bit mode - CMD9 0x09 1-bit mode 1-bit mode - 0x19 1-bit mode 1-bit mode - 0x29 1-bit mode 1-bit mode - 0x59 1-bit mode 2-bit mode - 0xA9 1-bit mode 4-bit mode - CMDA 0x0A 1-bit mode 1-bit mode - Espressif Systems 949 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Table 29.5-13. CMD Values Supported in SPI Mode Transfer Type CMD[7:0] CMD State ADDR State DATA State 0x1A 1-bit mode 1-bit mode - 0x2A 1-bit mode 1-bit mode - 0x5A 1-bit mode 2-bit mode - 0xAA 1-bit mode 4-bit mode - End_SEG_TRANS 0x05 1-bit mode - - En_QPI 0x06 1-bit mode - - Table 29.5-14. CMD Values Supported in QPI Mode Transfer Type CMD[7:0] CMD State ADDR State DATA State Wr_BUF 0xA1 4-bit mode 4-bit mode 4-bit mode Rd_BUF 0xA2 4-bit mode 4-bit mode 4-bit mode Wr_DMA 0xA3 4-bit mode 4-bit mode 4-bit mode Rd_DMA 0xA4 4-bit mode 4-bit mode 4-bit mode CMD7 0xA7 4-bit mode 4-bit mode - CMD8 0xA8 4-bit mode 4-bit mode - CMD9 0xA9 4-bit mode 4-bit mode - CMDA 0xAA 4-bit mode 4-bit mode - End_SEG_TRANS 0xA5 4-bit mode 4-bit mode - Ex_QPI 0xDD 4-bit mode 4-bit mode - Master sends 0x06 CMD (En_QPI) to set GP-SPI2 slave to QPI mode and all the states of supported transfer will be in 4-bit mode afterwards. If 0xDD CMD (Ex_QPI) is received, GP-SPI2 slave will be back to SPI mode. Other transfer types than these described in Table 29.5-13 and Table 29.5-14 are ignored. If the CS low-level duration is longer than two APB_CLK cycles, SPI_TRANS_DONE_INT will be triggered. For more information on interrupts triggered at the end of transmissions, please refer to Section 29.9. 29.5.10.3 Slave Single Transfer and Slave Segmented Transfer When GP-SPI2 works as slave, it supports full-duplex and half-duplex communications controlled by DMA and by CPU. DMA-controlled transfer can be a single transfer, or a slave segmented transfer consisting of several transactions (segments). The CPU-controlled transfer can only be one single transfer, since each CPU-controlled transaction needs to be triggered by CPU. In a slave segmented transfer, all transfer types listed in Table 29.5-13 and Table 29.5-14 are supported in a single transaction (segment). It means that CPU-controlled transactions and DMA-controlled transactions can be mixed in one slave segmented transfer. It is recommended that in a slave segmented transfer: • CPU-controlled transaction is used for handshake communication and short data transfers. • DMA-controlled transaction is used for large data transfers. Espressif Systems 950 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) 29.5.10.4 Configuration of Slave Single Transfer When operating as slave, GP-SPI2 supports CPU/DMA-controlled full-duplex/half-duplex single transfers. The register configuration procedure is as follows: 1. Configure the IO path via IO MUX or GPIO matrix between GP-SPI2 and an external SPI device. 2. Configure AHB_CLK and APB_CLK. 3. Set SPI_SLAVE_MODE to enable slave mode. 4. Configure SPI_DOUTDIN: • 1: enable full-duplex communication. • 0: enable half-duplex communication. 5. Prepare data: • if CPU-controlled transfer is selected and GP-SPI2 is used to send data, then prepare data in registers SPI_W0_REG∼SPI_W15_REG. • if DMA-controlled transfer is selected, – configure SPI_DMA_TX_ENA/SPI_DMA_RX_ENA and SPI_RX_EOF_EN. – configure GDMA TX/RX link, – and start GDMA TX/RX engine, as described in Section 29.5.7 and Section 29.5.8. 6. Set SPI_DMA_AFIFO_RST, SPI_BUF_AFIFO_RST, and SPI_RX_AFIFO_RST to reset these buffers. 7. Clear SPI_DMA_SLV_SEG_TRANS_EN in register SPI_DMA_CONF_REG to enable slave single transfer. 8. Set SPI_TRANS_DONE_INT_ENA in register SPI_DMA_INT_ENA_REG and wait for the interrupt SPI_TRANS_DONE_INT. In DMA-controlled mode, it is recommended to wait for the interrupt AHB_DMA_IN_SUC_EOF_CHn_INT when DMA RX buffer is used, which means that data has been stored in the related memory. Other interrupts described in Section 29.9 are optional. 29.5.10.5 Configuration of Slave Segmented Transfer in Half-Duplex GDMA must be used in this mode. The register configuration procedure is as follows: 1. Configure the IO path via IO MUX or GPIO matrix between GP-SPI2 and an external SPI device. 2. Configure AHB_CLK and APB_CLK. 3. Set SPI_SLAVE_MODE to enable slave mode. 4. Clear SPI_DOUTDIN to enable half-duplex communication. 5. Prepare data in registers SPI_W0_REG∼ SPI_W15_REG, if needed. 6. Set SPI_DMA_AFIFO_RST, SPI_BUF_AFIFO_RST, and SPI_RX_AFIFO_RST to reset these buffers. 7. Set bits SPI_DMA_RX_ENA and SPI_DMA_TX_ENA. Clear the bit SPI_RX_EOF_EN. Configure GDMA TX/RX link and start GDMA TX/RX engine, as shown in Section 29.5.7 and Section 29.5.8. 8. Set SPI_DMA_SLV_SEG_TRANS_EN in register SPI_DMA_CONF_REG to enable slave segmented transfer. Espressif Systems 951 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) 9. Set SPI_DMA_SEG_TRANS_DONE_INT_ENA in register SPI_DMA_INT_ENA_REG and wait for the interrupt SPI_DMA_SEG_TRANS_DONE_INT, which means that the segmented transfer has finished and data has been put into the related memory. Other interrupts described in Section 29.9 are optional. When End_SEG_TRANS (0x05 in SPI mode, 0xA5 in QPI mode) is received by GP-SPI2, this slave segmented transfer is ended and the interrupt SPI_DMA_SEG_TRANS_DONE_INT is triggered. 29.5.10.6 Configuration of Slave Segmented Transfer in Full-Duplex GDMA must be used in this mode. In such transfer, the data is transferred from and to the GDMA buffer. The interrupt AHB_DMA_IN_SUC_EOF_CHn_INT is triggered when the transfer ends. The register configuration procedure is as follows: 1. Configure the IO path via IO MUX or GPIO matrix between GP-SPI2 and an external SPI device. 2. Configure AHB_CLK and APB_CLK. 3. Set SPI_SLAVE_MODE and SPI_DOUTDIN, to enable slave full-duplex communication. 4. Set SPI_DMA_AFIFO_RST, SPI_BUF_AFIFO_RST, and SPI_RX_AFIFO_RST to reset these buffers. 5. Set SPI_DMA_TX_ENA and SPI_DMA_RX_ENA. Configure GDMA TX/RX link and start GDMA TX/RX engine, as shown in Section 29.5.7 and Section 29.5.8. 6. Set SPI_RX_EOF_EN in register SPI_DMA_CONF_REG. Configure SPI_MS_DATA_BITLEN[17:0] in register SPI_MS_DLEN_REG to the bit length of the received GDMA data in unit of byte. 7. Set SPI_DMA_SLV_SEG_TRANS_EN in register SPI_DMA_CONF_REG to enable slave segmented transfer. 8. Set AHB_DMA_IN_SUC_EOF_CHn_INT_ENA and wait for the interrupt AHB_DMA_IN_SUC_EOF_CHn_INT. 29.6 CS Setup Time and Hold Time Control SPI bus CS (SPI_CS) setup time and hold time are very important to meet the timing requirements of various SPI devices (e.g., flash or PSRAM). CS setup time is the time between the CS falling edge and the first latch edge of SPI bus CLK (SPI_CLK). The first latch edge for mode 0 and mode 3 is rising edge, and falling edge for mode 1 and mode 2. CS hold time is the time between the last latch edge of SPI_CLK and the CS rising edge. When operating as slave, the CS setup time and hold time should be longer than 0.5 x T_SPI_CLK, otherwise the SPI transfer may be incorrect. T_SPI_CLK is one cycle of SPI_CLK. When operating as master, set the CS setup time by specifying SPI_CS_SETUP in register SPI_USER_REG and SPI_CS_SETUP_TIME in register SPI_USER1_REG. • If SPI_CS_SETUP is cleared, the SPI CS setup time is 0.5 x T_SPI_CLK. • If SPI_CS_SETUP is set, the SPI CS setup time is (SPI_CS_SETUP_TIME + 1.5) x T_SPI_CLK. Set the CS hold time by specifying SPI_CS_HOLD in register SPI_USER_REG and SPI_CS_HOLD_TIME in register SPI_USER1_REG. • If SPI_CS_HOLD is cleared, the SPI CS hold time is 0.5 x T_SPI_CLK. Espressif Systems 952 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) • If SPI_CS_HOLD is set, the SPI CS hold time is (SPI_CS_HOLD_TIME + 1.5) x T_SPI_CLK. Figure 29.6-1 and Figure 29.6-2 show the recommended CS timing and register configuration to access external RAM and flash. Figure 29.6-1. Recommended CS Timing and Settings When Accessing External RAM Figure 29.6-2. Recommended CS Timing and Settings When Accessing Flash 29.7 GP-SPI2 Clock Control GP-SPI2 has the following clocks: • clk_spi_mst: module clock of GP-SPI2. When GP-SPI2 works as master, this clk_spi_mst is used to generate SPI_CLK signal for data transfer and for slaves. • clk_hclk: module timing compensation clock of GP-SPI2, which is a frequency-doubled clock derived from the same source as clk_spi_mst. Espressif Systems 953 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) • SPI_CLK: the output clock when the GP-SPI2 works as master. • AHB_CLK: clock for register configuration. clk_spi_mst is enabled by PCR_SPI2_CLK_EN and its clock source is controlled by PCR_SPI2_CLKMST_SEL: • 0: XTAL_CLK • 1: PLL_F160M_CLK • 2: FOSC_CLK • 1: PLL_F120M_CLK When operating as master, the maximum output clock frequency of GP-SPI2 is f clk_spi_mst . To have slower frequencies, the output clock frequency can be divided as follows: f SPI_CLK = f clk_spi_mst (SPI_CLKCNT_N + 1)(SPI_CLKDIV_PRE + 1) The divider is configured by SPI_CLKCNT_N and SPI_CLKDIV_PRE in register SPI_CLOCK_REG. When the bit SPI_CLK_EQU_SYSCLK in register SPI_CLOCK_REG is set, the output clock frequency of GP-SPI2 will be f clk_spi_mst . For other integral clock divisions, SPI_CLK_EQU_SYSCLK should be cleared. When operating as slave, the supported input clock frequency (f SPI_CLK ) of GP-SPI2 is f SPI_CLK <= f AHB_CLK . 29.7.1 Clock Phase and Polarity SPI protocol has four clock modes, i.e., modes 0∼3. See Figure 29.7-1 and Figure 29.7-2. Note: The images are sourced from the SPI protocol. In the two images, the black SAMPLE signal represents the standard sampling edge, while the red represents the default sampling edge of GP-SPI2. Espressif Systems 954 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Figure 29.7-1. SPI Clock Mode 0 or 2 Figure 29.7-2. SPI Clock Mode 1 or 3 1. Mode 0: CPOL = 0, CPHA = 0; SCK is 0 when the SPI is in idle state; data is changed on the falling edge of SCK and sampled on the rising edge. The first data is shifted out before the first falling edge of SCK. 2. Mode 1: CPOL = 0, CPHA = 1; SCK is 0 when the SPI is in idle state; data is changed on the rising edge of Espressif Systems 955 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) SCK and sampled on the falling edge. 3. Mode 2: CPOL = 1, CPHA = 0; SCK is 1 when the SPI is in idle state; data is changed on the rising edge of SCK and sampled on the falling edge. The first data is shifted out before the first rising edge of SCK. 4. Mode 3: CPOL = 1, CPHA = 1; SCK is 1 when the SPI is in idle state; data is changed on the falling edge of SCK and sampled on the rising edge. 29.7.2 Clock Control When GP-SPI2 Works as Master The four clock modes 0∼3 are supported in GP-SPI2 when it works as master. The polarity and phase of GP-SPI2 clock are controlled by the bit SPI_CK_IDLE_EDGE in register SPI_MISC_REG and the bit SPI_CK_OUT_EDGE in register SPI_USER_REG. The register configuration for SPI clock modes 0∼3 is provided in Table 29.7-1, and can be changed according to the path delay in the application. Table 29.7-1. Clock Phase and Polarity Configuration as Master Control Bit Mode 0 Mode 1 Mode 2 Mode 3 SPI_CK_IDLE_EDGE 0 0 1 1 SPI_CK_OUT_EDGE 0 1 1 0 SPI_CLK_MODE is used to select the number of rising edges of SPI_CLK when SPI_CS raises high to be 0, 1, 2 or SPI_CLK always on. Note: When SPI_CLK_MODE is configured to 1 or 2, the bit SPI_CS_HOLD must be set and the value of SPI_CS_HOLD_TIME should be larger than 1. 29.7.3 Clock Control When GP-SPI2 Works as Slave GP-SPI2 as slave also supports clock modes 0∼3. The polarity and phase are configured by the bits SPI_TSCK_I_EDGE and SPI_RSCK_I_EDGE in register SPI_USER_REG. The output edge of data is controlled by SPI_CLK_MODE_13 in register SPI_SLAVE_REG. The detailed register configuration is shown in Table 29.7-2: Table 29.7-2. Clock Phase and Polarity Configuration as Slave Control Bit Mode 0 Mode 1 Mode 2 Mode 3 SPI_TSCK_I_EDGE 0 1 1 0 SPI_RSCK_I_EDGE 0 1 1 0 SPI_CLK_MODE_13 0 1 0 1 29.8 GP-SPI2 Timing Compensation Introduction Based on the role of GP-SPI2 in a user-defined SPI transmission system (whether GP-SPI2 works as master or slave), GP-SPI2 provides the following timing compensation schemes: Espressif Systems 956 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) • In master mode, the default compensation scheme delays SPI_CLK by half a cycle. Refer to Figure 29.7-1 and Figure 29.7-2. You can also switch to standard sampling via register configuration. • If the series register compensation scheme is used, it further improves timing compensation for high-speed transmissions on top of the default half-cycle delay. • When working as slave, GP-SPI2 follows the standard SPI protocol for data transmission by default. You can also advance data transmission by half a cycle via register configuration. When GP-SPI2 works as master, it delays the sampling of data returned by the slave by half an SPI clock cycle. You can switch to the standard SPI protocol sampling scheme by setting SPI_CLK_EDGE_SEL high. Note that when SPI_CLK_EQU_SYSCLK is set to 1, the data sampling from slave is always delayed by half an SPI clock cycle, and at this point, you can use other methods to adjust the IO timing. The I/O lines are mapped via GPIO matrix or IO MUX. But there is no timing adjustment in IO MUX. The input data and output data can be delayed for 1 or 2 IO MUX operating clock cycles at the rising or falling edge in GPIO matrix. For detailed register configuration, see Chapter 6 GPIO Matrix and IO MUX. Figure 29.8-1 shows the timing compensation control for GP-SPI2 as master, including the following paths: • “CLK”: the output path of GP-SPI2 bus clock. The clock is sent out by SPI_CLK out control module, passes through GPIO matrix or IO MUX and then goes to an external SPI device. • “IN”: data input path of GP-SPI2 (see line 3 path in color purple in Figure 29.8-1). The input data from an external SPI device passes through GPIO matrix or IO MUX, then is adjusted by the Timing Module (see Figure 29.5-2) and finally is stored into spi_rx_afifo. • “OUT”: data output path of GP-SPI2 (see line 2 path in color rose-red in Figure 29.8-1). The output data is sent out to the Timing Module, passes through GPIO matrix or IO MUX and is then captured by an external SPI device. Figure 29.8-1. Timing Compensation Control Diagram in GP-SPI as Master Espressif Systems 957 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Every input and output data is passing through the Timing Module and the module can be used to apply delay in units of T clk_spi_mst (one cycle of clk_spi_mst) on rising or falling edge. Key Registers • SPI_DIN_MODE_REG: select the latch edge of input data • SPI_DIN_NUM_REG: select the delay cycles of input data • SPI_DOUT_MODE_REG: select the latch edge of output data Timing Compensation Example Figure 29.8-2 shows a timing compensation example when GP-SPI2 works as master. Note that DUMMY cycle length is configurable to compensate the delay in I/O lines, so as to enhance the performance of GP-SPI2. Figure 29.8-2. Timing Compensation Example in GP-SPI2 In Figure 29.8-2, “p1” is the point of input data of Timing Module, “p2” is the point of output data of Timing Module. Since the input data FSPIQ is unaligned to FSPID, the read data of GP-SPI2 will be wrong without the timing compensation. To get the correct read data, follow the settings below. Assuming f clk_spi_mst equals to f SP I_CLK : • Delay FSPID for two cycles at the falling edge of clk_spi_mst. • Delay FSPIQ for one cycle at the falling edge of clk_spi_mst. • Add one extra dummy cycle. When GP-SPI2 works as slave, if the bit SPI_RSCK_DATA_OUT in register SPI_SLAVE_REG is set to 1, the output data is sent at latch edge, which is half an SPI clock cycle earlier. This can be used for slave mode timing Espressif Systems 958 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) compensation. 29.9 Interrupt 29.9.1 Interrupt Description GP-SPI2 can generate the following external interrupt signal: • SPI_INTR SPI_INTR can be mapped to the CPU through the Interrupt Matrix. The interrupt signal is generated by internal interrupt sources. Table 29.9-1 lists the internal interrupt sources, interrupt trigger conditions, and generated interrupt signals. Table 29.9-1. Internal Interrupt Sources of GP-SPI2 Internal Interrupt Source Trigger Condition Interrupt Signal SPI_DMA_INFIFO_FULL_ERR_INT The length of GDMA RX FIFO is shorter than that of actual data transferred SPI_INTR SPI_DMA_OUTFIFO_EMPTY_ERR_INT The length of GDMA TX FIFO is shorter than that of actual data transferred SPI_INTR SPI_SLV_EX_QPI_INT Ex_QPI is received correctly when GP-SPI2 works as slave and the SPI transfer ends SPI_INTR SPI_SLV_EN_QPI_INT En_QPI is received correctly when GP-SPI2 works as slave and the SPI transfer ends SPI_INTR SPI_SLV_CMD7_INT CMD7 is received correctly when GP-SPI2 works as slave and the SPI transfer ends SPI_INTR SPI_SLV_CMD8_INT CMD8 is received correctly when GP-SPI2 works as slave and the SPI transfer ends SPI_INTR SPI_SLV_CMD9_INT CMD9 is received correctly when GP-SPI2 works as slave and the SPI transfer ends SPI_INTR SPI_SLV_CMDA_INT CMDA is received correctly when GP-SPI2 works as slave and the SPI transfer ends SPI_INTR SPI_SLV_RD_DMA_DONE_INT At the end of Rd_DMA transfer when GP-SPI2 works as slave SPI_INTR SPI_SLV_WR_DMA_DONE_INT At the end of Wr_DMA transfer when GP-SPI2 works as slave SPI_INTR SPI_SLV_RD_BUF_DONE_INT At the end of Rd_BUF transfer when GP-SPI2 works as slave SPI_INTR SPI_SLV_WR_BUF_DONE_INT At the end of Wr_BUF transfer when GP-SPI2 works as slave SPI_INTR SPI_TRANS_DONE_INT At the end of SPI bus transfer when GP-SPI2 works as master or as slave SPI_INTR SPI_DMA_SEG_TRANS_DONE_INT At the end of End_SEG_TRANS transfer in GP-SPI2 slave segmented transfer mode or at the end of master configurable segmented transfer mode SPI_INTR Cont’d on next page Espressif Systems 959 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Table 29.9-1 – cont’d from previous page Internal Interrupt Source Trigger Condition Interrupt Signal SPI_SEG_MAGIC_ERR_INT A Magic error occurs in CONF buffer during configurable segmented transfer when GP-SPI2 works as master SPI_INTR SPI_MST_RX_AFIFO_WFULL_ERR_INT RX AFIFO write-full error when GP-SPI2 works as master SPI_INTR SPI_MST_TX_AFIFO_REMPTY_ERR_INT TX AFIFO read-empty error when GP-SPI2 works as master SPI_INTR SPI_SLV_CMD_ERR_INT A received command value is not supported when GP-SPI2 works as slave SPI_INTR SPI_APP2_INT Set SPI_APP2_INT_SET (Only used for user defined function) SPI_INTR SPI_APP1_INT Set SPI_APP1_INT_SET (Only used for user defined function) SPI_INTR 29.9.2 Interrupts Used in Master and in Slave Table 29.9-2 and Table 29.9-3 show the interrupts used in GP-SPI2 master and slave modes. Set the interrupt enable bit SPI_*_INT_ENA in SPI_DMA_INT_ENA_REG and wait for the interrupt. When the transfer ends, the related interrupt is triggered and should be cleared by software before the next transfer. Table 29.9-2. GP-SPI2 Master Mode Interrupts Transfer Type Communication Mode Controlled by Interrupt Single Transfer Full-duplex DMA AHB_DMA_IN_SUC_EOF_CHn_INT 1 CPU SPI_TRANS_DONE_INT 2 Half-duplex MOSI Mode DMA SPI_TRANS_DONE_INT CPU SPI_TRANS_DONE_INT Half-duplex MISO Mode DMA AHB_DMA_IN_SUC_EOF_CHn_INT CPU SPI_TRANS_DONE_INT Configurable Segmented Transfer Full-duplex DMA SPI_DMA_SEG_TRANS_DONE_INT 3 CPU Not supported Half-duplex MOSI Mode DMA SPI_DMA_SEG_TRANS_DONE_INT CPU Not supported Half-duplex MISO DMA SPI_DMA_SEG_TRANS_DONE_INT CPU Not supported 1 If AHB_DMA_IN_SUC_EOF_CHn_INT is triggered, it means all the RX data of GP-SPI2 has been stored in the RX buffer, and the TX data has been transferred to the slave. 2 SPI_TRANS_DONE_INT is triggered when CS is high, which indicates that master has completed the data exchange in SPI_W0_REG∼SPI_W15_REG with slave in this mode. 3 If SPI_DMA_SEG_TRANS_DONE_INT is triggered, it means that the whole configurable segmented transfer (consisting of several segments) has finished, i.e., the RX data has been stored in the RX buffer completely and all the TX data has been sent out. Espressif Systems 960 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Table 29.9-3. GP-SPI2 Slave Mode Interrupts Transfer Type Communication Mode Controlled by Interrupt Single Transfer Full-duplex DMA AHB_DMA_IN_SUC_EOF_CHn_INT 1 CPU SPI_TRANS_DONE_INT 2 Half-duplex MOSI Mode DMA (Wr_DMA) AHB_DMA_IN_SUC_EOF_CHn_INT 3 CPU (Wr_BUF) SPI_TRANS_DONE_INT 4 Half-duplex MISO Mode DMA (Rd_DMA) SPI_TRANS_DONE_INT 5 CPU (Rd_BUF) SPI_TRANS_DONE_INT 6 Slave Segmented Transfer Full-duplex DMA AHB_DMA_IN_SUC_EOF_CHn_INT 7 CPU Not supported 8 Half-duplex MOSI Mode DMA (Wr_DMA) SPI_DMA_SEG_TRANS_DONE_INT 9 CPU (Wr_BUF) Not supported 10 Half-duplex MISO Mode DMA (Rd_DMA) SPI_DMA_SEG_TRANS_DONE_INT 11 CPU (Rd_BUF) Not supported 12 1 If AHB_DMA_IN_SUC_EOF_CHn_INT is triggered, it means all the RX data has been stored in the RX buffer, and the TX data has been sent to the slave. 2 SPI_TRANS_DONE_INT is triggered when CS is high, which indicates that master has completed the data ex- change in SPI_W0_REG∼SPI_W15_REG with slave in this mode. 3 SPI_SLV_WR_DMA_DONE_INT just means that the transmission on the SPI bus is done, but can not ensure that all the push data has been stored in the RX buffer. For this reason, AHB_DMA_IN_SUC_EOF_CHn_INT is recommended. 4 Or wait for SPI_SLV_WR_BUF_DONE_INT. 5 Or wait for SPI_SLV_RD_DMA_DONE_INT. 6 Or wait for SPI_SLV_RD_BUF_DONE_INT. 7 Slave should set the total read data byte length in SPI_MS_DATA_BITLEN before the transfer begins. Set SPI_RX_EOF_EN to 1 before the end of the interrupt program. 8 Master and slave should define a method to end the segmented transfer, such as via GPIO interrupt. 9 Master sends End_SEG_TRAN to end the segmented transfer or slave sets the total read data byte length in SPI_MS_DATA_BITLEN and waits for AHB_DMA_IN_SUC_EOF_CHn_INT. 10 Half-duplex Wr_BUF single transfer can be used in a slave segmented transfer. 11 Master sends End_SEG_TRAN to end the segmented transfer. 12 Half-duplex Rd_BUF single transfer can be used in a slave segmented transfer. 29.10 Register Summary The addresses in this section are relative to GP-SPI2 base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access User-defined control registers SPI_CMD_REG Command control register 0x0000 varies SPI_ADDR_REG Address value register 0x0004 R/W Espressif Systems 961 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Name Description Address Access SPI_USER_REG SPI USER control register 0x0010 varies SPI_USER1_REG SPI USER control register 1 0x0014 R/W SPI_USER2_REG SPI USER control register 2 0x0018 R/W Control and configuration registers SPI_CTRL_REG SPI control register 0x0008 varies SPI_MS_DLEN_REG SPI data bit length control register 0x001C R/W SPI_MISC_REG SPI misc register 0x0020 varies SPI_DMA_CONF_REG SPI DMA control register 0x0030 varies SPI_SLAVE_REG SPI slave control register 0x00E0 varies SPI_SLAVE1_REG SPI slave control register 1 0x00E4 R/W/SS Clock control registers SPI_CLOCK_REG SPI clock control register 0x000C R/W SPI_CLK_GATE_REG SPI module clock and register clock control 0x00E8 R/W Timing registers SPI_DIN_MODE_REG SPI input delay mode configuration 0x0024 varies SPI_DIN_NUM_REG SPI input delay number configuration 0x0028 varies SPI_DOUT_MODE_REG SPI output delay mode configuration 0x002C varies Interrupt registers SPI_DMA_INT_ENA_REG SPI interrupt enable register 0x0034 R/W SPI_DMA_INT_CLR_REG SPI interrupt clear register 0x0038 WT SPI_DMA_INT_RAW_REG SPI interrupt raw register 0x003C R/WTC/SS SPI_DMA_INT_ST_REG SPI interrupt status register 0x0040 RO SPI_DMA_INT_SET_REG SPI interrupt software set register 0x0044 WT CPU-controlled data buffer SPI_W0_REG SPI CPU-controlled buffer 0 0x0098 R/W/SS SPI_W1_REG SPI CPU-controlled buffer 1 0x009C R/W/SS SPI_W2_REG SPI CPU-controlled buffer 2 0x00A0 R/W/SS SPI_W3_REG SPI CPU-controlled buffer 3 0x00A4 R/W/SS SPI_W4_REG SPI CPU-controlled buffer 4 0x00A8 R/W/SS SPI_W5_REG SPI CPU-controlled buffer 5 0x00AC R/W/SS SPI_W6_REG SPI CPU-controlled buffer 6 0x00B0 R/W/SS SPI_W7_REG SPI CPU-controlled buffer 7 0x00B4 R/W/SS SPI_W8_REG SPI CPU-controlled buffer 8 0x00B8 R/W/SS SPI_W9_REG SPI CPU-controlled buffer 9 0x00BC R/W/SS SPI_W10_REG SPI CPU-controlled buffer 10 0x00C0 R/W/SS SPI_W11_REG SPI CPU-controlled buffer 11 0x00C4 R/W/SS SPI_W12_REG SPI CPU-controlled buffer 12 0x00C8 R/W/SS SPI_W13_REG SPI CPU-controlled buffer 13 0x00CC R/W/SS SPI_W14_REG SPI CPU-controlled buffer 14 0x00D0 R/W/SS SPI_W15_REG SPI CPU-controlled buffer 15 0x00D4 R/W/SS Version register SPI_DATE_REG Version control 0x00F0 R/W Espressif Systems 962 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) 29.11 Register Notice: ESP32-C5 does not currently support the functions associated with the fields marked with HRO access in this section. The addresses in this section are relative to GP-SPI2 base address provided in Table 4.3-2 in Chapter 4 System and Memory. For how to program reserved fields, please refer to Section Programming Reserved Register Field. Register 29.1. SPI_CMD_REG (0x0000) (reserved) 0 0 0 0 0 0 0 31 25 SPI_USR 0 24 SPI_UPDATE 0 23 (reserved) 0 0 0 0 0 22 18 SPI_CONF_BITLEN 0 17 0 Reset SPI_CONF_BITLEN Configures the SPI_CLK cycles of SPI CONF state. Measurement unit: SPI_CLK clock cycle. Can be configured in CONF state. (R/W) SPI_UPDATE Configures whether or not to synchronize SPI registers from APB clock domain into SPI module clock domain. 0: Not synchronize 1: Synchronize This bit is only used in SPI master transfer. (WT) SPI_USR Configures whether or not to enable user-defined command. 0: Not enable 1: Enable An SPI operation will be triggered when the bit is set. This bit will be cleared once the operation is done. Can not be changed by CONF_buf. (R/W/SC) Espressif Systems 963 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Register 29.2. SPI_ADDR_REG (0x0004) SPI_USR_ADDR_VALUE 0 31 0 Reset SPI_USR_ADDR_VALUE Configures the address to slave. Can be configured in CONF state. (R/W) Espressif Systems 964 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Register 29.3. SPI_USER_REG (0x0010) SPI_USR_COMMAND 1 31 SPI_USR_ADDR 0 30 SPI_USR_DUMMY 0 29 SPI_USR_MISO 0 28 SPI_USR_MOSI 0 27 SPI_USR_DUMMY_IDLE 0 26 SPI_USR_MOSI_HIGHPART 0 25 SPI_USR_MISO_HIGHPART 0 24 (reserved) 0 0 0 0 0 0 23 18 SPI_SIO 0 17 (reserved) 0 16 SPI_USR_CONF_NXT 0 15 SPI_FWRITE_OCT 0 14 SPI_FWRITE_QUAD 0 13 SPI_FWRITE_DUAL 0 12 (reserved) 0 0 11 10 SPI_CK_OUT_EDGE 0 9 SPI_RSCK_I_EDGE 0 8 SPI_CS_SETUP 1 7 SPI_CS_HOLD 1 6 SPI_TSCK_I_EDGE 0 5 SPI_OPI_MODE 0 4 SPI_QPI_MODE 0 3 (reserved) 0 0 2 1 SPI_DOUTDIN 0 0 Reset SPI_DOUTDIN Configures whether or not to enable full-duplex communication. 0: Disable 1: Enable Can be configured in CONF state. (R/W) SPI_QPI_MODE Configures whether or not to enable QPI mode. 0: Disable 1: Enable This configuration is applicable when the SPI controller works as master or slave. Can be configured in CONF state. (R/W/SS/SC) SPI_OPI_MODE Reserved (HRO) SPI_TSCK_I_EDGE Configures whether or not to change the polarity of TSCK in slave transfer. 0: TSCK = SPI_CK_I 1: TSCK = !SPI_CK_I (R/W) SPI_CS_HOLD Configures whether or not to keep SPI CS low when SPI is in DONE state. 0: Not keep low 1: Keep low Can be configured in CONF state. (R/W) SPI_CS_SETUP Configures whether or not to enable SPI CS when SPI is in prepare (PREP) state. 0: Disable 1: Enable Can be configured in CONF state. (R/W) Continued on the next page... Espressif Systems 965 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Register 29.3. SPI_USER_REG (0x0010) Continued from the previous page... SPI_RSCK_I_EDGE Configures whether or not to change the polarity of RSCK in slave transfer. 0: RSCK = !SPI_CK_I 1: RSCK = SPI_CK_I (R/W) SPI_CK_OUT_EDGE Configures SPI clock mode together with SPI_CK_IDLE_EDGE. Can be configured in CONF state. For more information, see Section 29.7.2. (R/W) SPI_FWRITE_DUAL Configures whether or not to enable the 2-bit mode of read-data phase in write operations. 0: Not enable 1: Enable Can be configured in CONF state. (R/W) SPI_FWRITE_QUAD Configures whether or not to enable the 4-bit mode of read-data phase in write operations. 0: Not enable 1: Enable Can be configured in CONF state. (R/W) SPI_FWRITE_OCT Reserved (HRO) SPI_USR_CONF_NXT Configures whether or not to enable the CONF state for the next transaction (segment) in a configurable segmented transfer. 0: this transfer will end after the current transaction (segment) is finished. Or this is not a config- urable segmented transfer. 1: this configurable segmented transfer will continue its next transaction (segment). Can be configured in CONF state. (R/W) Continued on the next page... Espressif Systems 966 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Register 29.3. SPI_USER_REG (0x0010) Continued from the previous page... SPI_SIO Configures whether or not to enable 3-line half-duplex communication, where MOSI and MISO signals share the same pin. 0: Disable 1: Enable Can be configured in CONF state. (R/W) SPI_USR_MISO_HIGHPART Configures whether or not to enable high part mode, i.e., only access to high part of the buffers: SPI_W8_REG∼SPI_W15_REG in read-data phase. 0: Disable 1: Enable Can be configured in CONF state. (R/W) SPI_USR_MOSI_HIGHPART Configures whether or not to enable high part mode, i.e., only access to high part of the buffers: SPI_W8_REG∼SPI_W15_REG in write-data phase. 0: Disable 1: Enable Can be configured in CONF state. (R/W) SPI_USR_DUMMY_IDLE Configures whether or not to disable SPI clock in DUMMY state. 0: Not disable 1: Disable Can be configured in CONF state. (R/W) SPI_USR_MOSI Configures whether or not to enable the write-data (DOUT) state of an operation. 0: Disable 1: Enable Can be configured in CONF state. (R/W) SPI_USR_MISO Configures whether or not to enable the read-data (DIN) state of an operation. 0: Disable 1: Enable Can be configured in CONF state. (R/W) SPI_USR_DUMMY Configures whether or not to enable the DUMMY state of an operation. 0: Disable 1: Enable Can be configured in CONF state. (R/W) Continued on the next page... Espressif Systems 967 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Register 29.3. SPI_USER_REG (0x0010) Continued from the previous page... SPI_USR_ADDR Configures whether or not to enable the address (ADDR) state of an operation. 0: Disable 1: Enable Can be configured in CONF state. (R/W) SPI_USR_COMMAND Configures whether or not to enable the command (CMD) state of an opera- tion. 0: Disable 1: Enable Can be configured in CONF state. (R/W) Espressif Systems 968 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Register 29.4. SPI_USER1_REG (0x0014) SPI_USR_ADDR_BITLEN 23 31 27 SPI_CS_HOLD_TIME 0x1 26 22 SPI_CS_SETUP_TIME 0 21 17 SPI_MST_WFULL_ERR_END_EN 1 16 (reserved) 0 0 0 0 0 0 0 0 15 8 SPI_USR_DUMMY_CYCLELEN 7 7 0 Reset SPI_USR_DUMMY_CYCLELEN Configures the length of DUMMY state. Measurement unit: SPI_CLK clock cycles. This value is (the expected cycle number - 1). Can be configured in CONF state. (R/W) SPI_MST_WFULL_ERR_END_EN Configures whether or not to end the SPI transfer when SPI RX AFIFO wfull error occurs in master full-/half-duplex transfers. 0: Not end 1: End (R/W) SPI_CS_SETUP_TIME Configures the length of prepare (PREP) state. Measurement unit: SPI_CLK clock cycles. This value is equal to the expected cycles - 1. This field is used together with SPI_CS_SETUP. Can be configured in CONF state. (R/W) SPI_CS_HOLD_TIME Configures the delay cycles of CS pin. Measurement unit: SPI_CLK clock cycles. This field is used together with SPI_CS_HOLD. Can be configured in CONF state. (R/W) SPI_USR_ADDR_BITLEN Configures the bit length in address state. This value is (expected bit number - 1). Can be configured in CONF state. (R/W) Espressif Systems 969 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Register 29.5. SPI_USER2_REG (0x0018) SPI_USR_COMMAND_BITLEN 7 31 28 SPI_MST_REMPTY_ERR_END_EN 1 27 (reserved) 0 0 0 0 0 0 0 0 0 0 0 26 16 SPI_USR_COMMAND_VALUE 0 15 0 Reset SPI_USR_COMMAND_VALUE Configures the command value. Can be configured in CONF state. (R/W) SPI_MST_REMPTY_ERR_END_EN Configures whether or not to end the SPI transfer when SPI TX AFIFO read empty error occurs in master full-/half-duplex transfers. 0: Not end 1: End (R/W) SPI_USR_COMMAND_BITLEN Configures the bit length of command state. This value is (expected bit number - 1). Can be configured in CONF state. (R/W) Espressif Systems 970 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Register 29.6. SPI_CTRL_REG (0x0008) (reserved) 0 0 0 0 0 31 27 SPI_WR_BIT_ORDER 0 26 25 SPI_RD_BIT_ORDER 0 24 23 (reserved) 0 22 SPI_WP_POL 1 21 SPI_HOLD_POL 1 20 SPI_D_POL 1 19 SPI_Q_POL 1 18 (reserved) 0 17 SPI_FREAD_OCT 0 16 SPI_FREAD_QUAD 0 15 SPI_FREAD_DUAL 0 14 (reserved) 0 0 0 13 11 SPI_FCMD_OCT 0 10 SPI_FCMD_QUAD 0 9 SPI_FCMD_DUAL 0 8 SPI_FADDR_OCT 0 7 SPI_FADDR_QUAD 0 6 SPI_FADDR_DUAL 0 5 (reserved) 0 4 SPI_DUMMY_OUT 0 3 (reserved) 0 0 0 2 0 Reset SPI_DUMMY_OUT Configures whether or not to output the FSPI bus signals in DUMMY state. 0: Not output 1: Output Can be configured in CONF state. (R/W) SPI_FADDR_DUAL Configures whether or not to enable 2-bit mode during address (ADDR) state. 0: Disable 1: Enable Can be configured in CONF state. (R/W) SPI_FADDR_QUAD Configures whether or not to enable 4-bit mode during address (ADDR) state. 0: Disable 1: Enable Can be configured in CONF state. (R/W) SPI_FADDR_OCT Reserved (HRO) SPI_FCMD_DUAL Configures whether or not to enable 2-bit mode during command (CMD) state. 0: Disable 1: Enable Can be configured in CONF state. (R/W) SPI_FCMD_QUAD Configures whether or not to enable 4-bit mode during command (CMD) state. 0: Disable 1: Enable Can be configured in CONF state. (R/W) Continued on the next page... Espressif Systems 971 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Register 29.6. SPI_CTRL_REG (0x0008) Continued from the previous page... SPI_FCMD_OCT Reserved (HRO) SPI_FREAD_DUAL Configures whether or not to enable the 2-bit mode of read-data (DIN) state in read operations. 0: Disable 1: Enable Can be configured in CONF state. (R/W) SPI_FREAD_QUAD Configures whether or not to enable the 4-bit mode of read-data (DIN) state in read operations. 0: Disable 1: Enable Can be configured in CONF state. (R/W) SPI_FREAD_OCT Reserved (HRO) SPI_Q_POL Configures MISO line polarity. 0: Low 1: High Can be configured in CONF state. (R/W) Continued on the next page... Espressif Systems 972 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Register 29.6. SPI_CTRL_REG (0x0008) Continued from the previous page... SPI_D_POL Configures MOSI line polarity. 0: Low 1: High Can be configured in CONF state. (R/W) SPI_HOLD_POL Configures SPI_HOLD output value when SPI is in idle. 0: Output low 1: Output high Can be configured in CONF state. (R/W) SPI_WP_POL Configures the output value of write-protect signal when SPI is in idle. 0: Output low 1: Output high Can be configured in CONF state. (R/W) SPI_RD_BIT_ORDER Configures the bit order in read-data (MISO) state. 0: MSB first 1: LSB first Can be configured in CONF state. (R/W) SPI_WR_BIT_ORDER Configures the bit order in command (CMD), address (ADDR), and write-data (MOSI) states. 0: MSB first 1: LSB first Can be configured in CONF state. (R/W) Espressif Systems 973 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Register 29.7. SPI_MS_DLEN_REG (0x001C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 18 SPI_MS_DATA_BITLEN 0 17 0 Reset SPI_MS_DATA_BITLEN Configures the data bit length of SPI transfer in DMA-controlled master trans- fer or in CPU-controlled master transfer. Or configures the bit length of SPI RX transfer in DMA- controlled slave transfer. This value shall be (expected bit_num - 1). Can be configured in CONF state. (R/W) Espressif Systems 974 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Register 29.8. SPI_MISC_REG (0x0020) SPI_QUAD_DIN_PIN_SWAP 0 31 SPI_CS_KEEP_ACTIVE 0 30 SPI_CK_IDLE_EDGE 0 29 (reserved) 0 0 0 0 28 25 SPI_DQS_IDLE_EDGE 0 24 SPI_SLAVE_CS_POL 0 23 (reserved) 0 0 0 22 20 SPI_CMD_DTR_EN 0 19 SPI_ADDR_DTR_EN 0 18 SPI_DATA_DTR_EN 0 17 SPI_CLK_DATA_DTR_EN 0 16 (reserved) 0 0 0 15 13 SPI_MASTER_CS_POL 0 12 7 SPI_CK_DIS 0 6 SPI_CS5_DIS 1 5 SPI_CS4_DIS 1 4 SPI_CS3_DIS 1 3 SPI_CS2_DIS 1 2 SPI_CS1_DIS 1 1 SPI_CS0_DIS 0 0 Reset SPI_CS0_DIS Configures whether or not to disable SPI_CS0 pin. 0: SPI_CS0 signal is from/to SPI_CS0 pin. 1: Disable SPI_CS0 pin. Can be configured in CONF state. (R/W) SPI_CS1_DIS Configures whether or not to disable SPI_CS1 pin. 0: SPI_CS1 signal is from/to SPI_CS1 pin. 1: Disable SPI_CS1 pin. Can be configured in CONF state. (R/W) SPI_CS2_DIS Configures whether or not to disable SPI_CS2 pin. 0: SPI_CS2 signal is from/to SPI_CS2 pin. 1: Disable SPI_CS2 pin. Can be configured in CONF state. (R/W) SPI_CS3_DIS Configures whether or not to disable SPI_CS3 pin. 0: SPI_CS3 signal is from/to SPI_CSn pin. 1: Disable SPI_CS3 pin. Can be configured in CONF state. (R/W) SPI_CS4_DIS Configures whether or not to disable SPI_CS4 pin. 0: SPI_CS4 signal is from/to SPI_CS4 pin. 1: Disable SPI_CS4 pin. Can be configured in CONF state. (R/W) SPI_CS5_DIS Configures whether or not to disable SPI_CS5 pin. 0: SPI_CS5 signal is from/to SPI_CS5 pin. 1: Disable SPI_CS5 pin. Can be configured in CONF state. (R/W) Continued on the next page... Espressif Systems 975 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Register 29.8. SPI_MISC_REG (0x0020) Continued from the previous page... SPI_CK_DIS Configures whether or not to disable SPI_CLK output. 0: Enable 1: Disable Can be configured in CONF state. (R/W) SPI_MASTER_CS_POL Configures the polarity of SPI_CSn (n = 0-5) line in master transfer. 0: SPI_CSn is low active. 1: SPI_CSn is high active. Can be configured in CONF state. (R/W) SPI_CLK_DATA_DTR_EN Reserved (HRO) SPI_DATA_DTR_EN Reserved (HRO) SPI_ADDR_DTR_EN Reserved (HRO) SPI_CMD_DTR_EN Reserved (HRO) SPI_SLAVE_CS_POL Configures whether or not invert SPI slave input CS polarity. 0: Not change 1: Invert Can be configured in CONF state. (R/W) Continued on the next page... Espressif Systems 976 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Register 29.8. SPI_MISC_REG (0x0020) Continued from the previous page... SPI_DQS_IDLE_EDGE Reserved (HRO) SPI_CK_IDLE_EDGE Configures the level of SPI_CLK line when GP-SPI2 is in idle. 0: Low 1: High Can be configured in CONF state. (R/W) SPI_CS_KEEP_ACTIVE Configures whether or not to keep the SPI_CS line low. 0: Not keep low 1: Keep low Can be configured in CONF state. (R/W) SPI_QUAD_DIN_PIN_SWAP Configures whether or not to swap SPI Quad input pins. 0: Not swap 1: Swap FSPID with FSPIQ, and FSPIWP with FSPIHD Can be configured in CONF state. (R/W) Espressif Systems 977 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Register 29.9. SPI_DMA_CONF_REG (0x0030) SPI_DMA_AFIFO_RST 0 31 SPI_BUF_AFIFO_RST 0 30 SPI_RX_AFIFO_RST 0 29 SPI_DMA_TX_ENA 0 28 SPI_DMA_RX_ENA 0 27 (reserved) 0 0 0 0 0 26 22 SPI_RX_EOF_EN 0 21 SPI_SLV_TX_SEG_TRANS_CLR_EN 0 20 SPI_SLV_RX_SEG_TRANS_CLR_EN 0 19 SPI_DMA_SLV_SEG_TRANS_EN 0 18 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 2 SPI_DMA_INFIFO_FULL 1 1 SPI_DMA_OUTFIFO_EMPTY 1 0 Reset SPI_DMA_OUTFIFO_EMPTY Represents whether or not the DMA TX FIFO is ready for sending data. 0: Ready 1: Not ready (RO) SPI_DMA_INFIFO_FULL Represents whether or not the DMA RX FIFO is ready for receiving data. 0: Ready 1: Not ready (RO) SPI_DMA_SLV_SEG_TRANS_EN Configures whether or not to enable DMA-controlled segmented transfer in slave half-duplex communication. 0: Disable 1: Enable (R/W) SPI_SLV_RX_SEG_TRANS_CLR_EN In slave segmented transfer, if the size of the DMA RX buffer is smaller than the size of the received data, 1: the data in all the following Wr_DMA transactions will not be received 0: the data in this Wr_DMA transaction will not be received, but in the following transactions, - if the size of DMA RX buffer is not 0, the data in following Wr_DMA transactions will be received. - if the size of DMA RX buffer is 0, the data in following Wr_DMA transactions will not be received. (R/W) SPI_SLV_TX_SEG_TRANS_CLR_EN In slave segmented transfer, if the size of the DMA TX buffer is smaller than the size of the transmitted data, 1: the data in the following transactions will not be updated, i.e. the old data is transmitted repeat- edly. 0: the data in this transaction will not be updated. But in the following transactions, - if new data is filled in DMA TX FIFO, new data will be transmitted. - if no new data is filled in DMA TX FIFO, no new data will be transmitted. (R/W) Continued on the next page... Espressif Systems 978 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Register 29.9. SPI_DMA_CONF_REG (0x0030) Continued from the previous page... SPI_RX_EOF_EN Configures the trigger source of AHB_DMA_IN_SUC_EOF_CHn_INT_RAW. 0: AHB_DMA_IN_SUC_EOF_CHn_INT_RAW is set by SPI_TRANS_DONE_INT event in a single transfer, or by an SPI_DMA_SEG_TRANS_DONE_INT event in a segmented transfer. 1: In a DAM-controlled transfer, if the bit number of transferred data is equal to (SPI_MS_DATA_BITLEN + 1), then AHB_DMA_IN_SUC_EOF_CHn_INT_RAW will be set by hard- ware. (R/W) SPI_DMA_RX_ENA Configures whether or not to enable DMA-controlled receive data transfer. 0: Disable 1: Enable (R/W) SPI_DMA_TX_ENA Configures whether or not to enable DMA-controlled send data transfer. 0: Disable 1: Enable (R/W) SPI_RX_AFIFO_RST Configures whether or not to reset spi_rx_afifo as shown in Figure 29.5-3 and in Figure 29.5-4. 0: Not reset 1: Reset spi_rx_afifo is used to receive data in SPI master and slave transfer. (WT) SPI_BUF_AFIFO_RST Configures whether or not to reset buf_tx_afifo as shown in Figure 29.5-3 and in Figure 29.5-4. 0: Not reset 1: Reset buf_tx_afifo is used to send data out in CPU-controlled master and slave transfer. (WT) SPI_DMA_AFIFO_RST Configures whether or not to reset dma_tx_afifo as shown in Figure 29.5-3 and in Figure 29.5-4. 0: Not reset 1: Reset dma_tx_afifo is used to send data out in DMA-controlled slave transfer. (WT) Espressif Systems 979 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Register 29.10. SPI_SLAVE_REG (0x00E0) (reserved) 0 0 31 30 SPI_MST_FD_WAIT_DMA_TX_DATA 0 29 SPI_USR_CONF 0 28 SPI_SOFT_RESET 0 27 SPI_SLAVE_MODE 0 26 SPI_DMA_SEG_MAGIC_VALUE 10 25 22 (reserved) 0 0 21 20 SPI_SLV_LAST_BYTE_STRB 0 19 12 SPI_SLV_WRBUF_BITLEN_EN 0 11 SPI_SLV_RDBUF_BITLEN_EN 0 10 SPI_SLV_WRDMA_BITLEN_EN 0 9 SPI_SLV_RDDMA_BITLEN_EN 0 8 (reserved) 0 0 0 0 7 4 SPI_RSCK_DATA_OUT 0 3 SPI_CLK_MODE_13 0 2 SPI_CLK_MODE 0 1 0 Reset SPI_CLK_MODE Configures SPI clock mode. 0: SPI clock is off when CS becomes inactive. 1: SPI clock is delayed one cycle after CS becomes inactive. 2: SPI clock is delayed two cycles after CS becomes inactive. 3: SPI clock is always on. Can be configured in CONF state. (R/W) SPI_CLK_MODE_13 Configure clock mode. 0: Support SPI clock mode 0 or 2. See Table 29.7-2. 1: Support SPI clock mode 1 or 3. See Table 29.7-2. (R/W) SPI_RSCK_DATA_OUT Configures the edge of output data. 0: Output data at TSCK rising edge. 1: Output data at RSCK rising edge. (R/W) SPI_SLV_RDDMA_BITLEN_EN Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length of Rd_DMA transfer. 0: Not use 1: Use (R/W) SPI_SLV_WRDMA_BITLEN_EN Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length of Wr_DMA transfer. 0: Not use 1: Use (R/W) SPI_SLV_RDBUF_BITLEN_EN Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length of Rd_BUF transfer. 0: Not use 1: Use (R/W) Continued on the next page... Espressif Systems 980 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Register 29.10. SPI_SLAVE_REG (0x00E0) Continued from the previous page... SPI_SLV_WRBUF_BITLEN_EN Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length of Wr_BUF transfer. 0: Not use 1: Use (R/W) SPI_SLV_LAST_BYTE_STRB Represents the effective bit of the last received data byte in SPI slave FD and HD mode. (R/SS) SPI_DMA_SEG_MAGIC_VALUE Configures the magic value of BM table in DMA-controlled config- urable segmented transfer. (R/W) SPI_SLAVE_MODE Configures SPI work mode. 0: Master 1: Slave (R/W) SPI_SOFT_RESET Configures whether to reset the SPI clock line, CS line, and data line via software. 0: Not reset 1: Reset Can be configured in CONF state. (WT) SPI_USR_CONF Configures whether or not to enable the CONF state of current DMA-controlled configurable segmented transfer. 0: No effect, which means the current transfer is not a configurable segmented transfer. 1: Enable, which means a configurable segmented transfer is started. (R/W) SPI_MST_FD_WAIT_DMA_TX_DATA Configures whether or not to wait DMA TX data gets ready before starting SPI transfer in master full-duplex transfer. 0: Not wait 1: Wait (R/W) Espressif Systems 981 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Register 29.11. SPI_SLAVE1_REG (0x00E4) SPI_SLV_LAST_ADDR 0 31 26 SPI_SLV_LAST_COMMAND 0 25 18 SPI_SLV_DATA_BITLEN 0 17 0 Reset SPI_SLV_DATA_BITLEN Configures the transferred data bit length in SPI slave full-/half-duplex modes. (R/W/SS) SPI_SLV_LAST_COMMAND Configures the command value in slave mode. (R/W/SS) SPI_SLV_LAST_ADDR Configures the address value in slave mode. (R/W/SS) Espressif Systems 982 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Register 29.12. SPI_CLOCK_REG (0x000C) SPI_CLK_EQU_SYSCLK 1 31 SPI_CLK_EDGE_SEL 0 30 (reserved) 0 0 0 0 0 0 0 0 29 22 SPI_CLKDIV_PRE 0 21 18 SPI_CLKCNT_N 0x3 17 12 SPI_CLKCNT_H 0x1 11 6 SPI_CLKCNT_L 0x3 5 0 Reset SPI_CLKCNT_L Configures clock duty cycles, together with SPI_CLKCNT_H and SPI_CLKCNT_N. In master transfer, this field must be equal to SPI_CLKCNT_N. In slave mode, it must be 0. Can be configured in CONF state. (R/W) SPI_CLKCNT_H Configures the duty cycle of SPI_CLK (high level) in master transfer. It’s recommended to configure this value to floor((SPI_CLKCNT_N + 1)/2 - 1). floor() here is to round a number down, e.g., floor(2.2) = 2. In slave mode, it must be 0. Can be configured in CONF state. (R/W) SPI_CLKCNT_N Configures the divider of SPI_CLK in master transfer. SPI_CLK frequency is f clk_spi_mst /(SPI_CLKDIV_PRE + 1)/(SPI_CLKCNT_N + 1) Can be configured in CONF state. (R/W) SPI_CLKDIV_PRE Configures the pre-divider of SPI_CLK in master transfer. Can be configured in CONF state. (R/W) SPI_CLK_EDGE_SEL Configures to use standard clock sampling edge or delay the sampling edge by half a cycle in master transfer. 0: clock sampling edge is delayed by half a cycle. 1: clock sampling edge is standard. Can be configured in CONF state. (R/W) SPI_CLK_EQU_SYSCLK Configures whether or not the SPI_CLK is equal to clk_spi_mst in master transfer. 0: SPI_CLK is divided from clk_spi_mst. 1: SPI_CLK is equal to clk_spi_mst. Can be configured in CONF state. (R/W) Espressif Systems 983 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Register 29.13. SPI_CLK_GATE_REG (0x00E8) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 (reserved) 0 2 (reserved) 0 1 SPI_CLK_EN 0 0 Reset SPI_CLK_EN Configures whether or not to enable clock gate. 0: Disable 1: Enable (R/W) Espressif Systems 984 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Register 29.14. SPI_DIN_MODE_REG (0x0024) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 17 SPI_TIMING_HCLK_ACTIVE 0 16 SPI_DIN7_MODE 0 15 14 SPI_DIN6_MODE 0 13 12 SPI_DIN5_MODE 0 11 10 SPI_DIN4_MODE 0 9 8 SPI_DIN3_MODE 0 7 6 SPI_DIN2_MODE 0 5 4 SPI_DIN1_MODE 0 3 2 SPI_DIN0_MODE 0 1 0 Reset SPI_DIN0_MODE Configures the input mode for FSPID signal. 0: Input without delay 1: Input at the (SPI_DIN0_NUM + 1)th falling edge of clk_spi_mst 2: Input at the (SPI_DIN0_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle 3: Input at the (SPI_DIN0_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst falling edge cycle Can be configured in CONF state. (R/W) SPI_DIN1_MODE Configures the input mode for FSPIQ signal. 0: Input without delay 1: Input at the (SPI_DIN1_NUM+1)th falling edge of clk_spi_mst 2: Input at the (SPI_DIN1_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle 3: Input at the (SPI_DIN1_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst falling edge cycle Can be configured in CONF state. (R/W) SPI_DIN2_MODE Configures the input mode for FSPIWP signal. 0: Input without delay 1: Input at the (SPI_DIN2_NUM + 1)th falling edge of clk_spi_mst 2: Input at the (SPI_DIN2_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle 3: Input at the (SPI_DIN2_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst falling edge cycle Can be configured in CONF state. (R/W) SPI_DIN3_MODE Configures the input mode for FSPIHD signal. 0: Input without delay 1: Input at the (SPI_DIN3_NUM + 1)th falling edge of clk_spi_mst 2: Input at the (SPI_DIN3_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle 3: Input at the (SPI_DIN3_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst falling edge cycle Can be configured in CONF state. (R/W) Continued on the next page... Espressif Systems 985 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Register 29.14. SPI_DIN_MODE_REG (0x0024) Continued from the previous page... SPI_DIN4_MODE Reserved (HRO) SPI_DIN5_MODE Reserved (HRO) SPI_DIN6_MODE Reserved (HRO) SPI_DIN7_MODE Reserved (HRO) SPI_TIMING_HCLK_ACTIVE Configures whether or not to enable HCLK (high-frequency clock) in SPI input timing module. 0: Disable 1: Enable Can be configured in CONF state. (R/W) Espressif Systems 986 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Register 29.15. SPI_DIN_NUM_REG (0x0028) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 SPI_DIN7_NUM 0 15 14 SPI_DIN6_NUM 0 13 12 SPI_DIN5_NUM 0 11 10 SPI_DIN4_NUM 0 9 8 SPI_DIN3_NUM 0 7 6 SPI_DIN2_NUM 0 5 4 SPI_DIN1_NUM 0 3 2 SPI_DIN0_NUM 0 1 0 Reset SPI_DIN0_NUM Configures the delays to input signal FSPID based on the setting of SPI_DIN0_MODE. 0: Delayed by 1 clock cycle 1: Delayed by 2 clock cycles 2: Delayed by 3 clock cycles 3: Delayed by 4 clock cycles Can be configured in CONF state. (R/W) SPI_DIN1_NUM Configures the delays to input signal FSPIQ based on the setting of SPI_DIN1_MODE. 0: Delayed by 1 clock cycle 1: Delayed by 2 clock cycles 2: Delayed by 3 clock cycles 3: Delayed by 4 clock cycles Can be configured in CONF state. (R/W) SPI_DIN2_NUM Configures the delays to input signal FSPIWP based on the setting of SPI_DIN2_MODE. 0: Delayed by 1 clock cycle 1: Delayed by 2 clock cycles 2: Delayed by 3 clock cycles 3: Delayed by 4 clock cycles Can be configured in CONF state. (R/W) SPI_DIN3_NUM Configures the delays to input signal FSPIHD based on the setting of SPI_DIN3_MODE. 0: Delayed by 1 clock cycle 1: Delayed by 2 clock cycles 2: Delayed by 3 clock cycles 3: Delayed by 4 clock cycles Can be configured in CONF state. (R/W) SPI_DIN4_NUM Reserved (HRO) SPI_DIN5_NUM Reserved (HRO) SPI_DIN6_NUM Reserved (HRO) SPI_DIN7_NUM Reserved (HRO) Espressif Systems 987 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Register 29.16. SPI_DOUT_MODE_REG (0x002C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 9 SPI_D_DQS_MODE 0 8 SPI_DOUT7_MODE 0 7 SPI_DOUT6_MODE 0 6 SPI_DOUT5_MODE 0 5 SPI_DOUT4_MODE 0 4 SPI_DOUT3_MODE 0 3 SPI_DOUT2_MODE 0 2 SPI_DOUT1_MODE 0 1 SPI_DOUT0_MODE 0 0 Reset SPI_DOUT0_MODE Configures the output mode for FSPID signal. 0: Output without delay 1: Output with a delay of a SPI module clock cycle at its falling edge Can be configured in CONF state. (R/W) SPI_DOUT1_MODE Configures the output mode for FSPIQ signal. 0: Output without delay 1: Output with a delay of a SPI module clock cycle at its falling edge Can be configured in CONF state. (R/W) SPI_DOUT2_MODE Configures the output mode for FSPIWP signal. 0: Output without delay 1: Output with a delay of a SPI module clock cycle at its falling edge Can be configured in CONF state. (R/W) SPI_DOUT3_MODE Configures the output mode for FSPIHD signal. 0: Output without delay 1: Output with a delay of a SPI module clock cycle at its falling edge Can be configured in CONF state. (R/W) SPI_DOUT4_MODE Reserved (HRO) SPI_DOUT5_MODE Reserved (HRO) SPI_DOUT6_MODE Reserved (HRO) SPI_DOUT7_MODE Reserved (HRO) SPI_D_DQS_MODE Reserved (HRO) Espressif Systems 988 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Register 29.17. SPI_DMA_INT_ENA_REG (0x0034) (reserved) 0 0 0 0 0 0 0 0 0 0 0 31 21 SPI_APP1_INT_ENA 0 20 SPI_APP2_INT_ENA 0 19 SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA 0 18 SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA 0 17 SPI_SLV_CMD_ERR_INT_ENA 0 16 SPI_SLV_BUF_ADDR_ERR_INT_ENA 0 15 SPI_SEG_MAGIC_ERR_INT_ENA 0 14 SPI_DMA_SEG_TRANS_DONE_INT_ENA 0 13 SPI_TRANS_DONE_INT_ENA 0 12 SPI_SLV_WR_BUF_DONE_INT_ENA 0 11 SPI_SLV_RD_BUF_DONE_INT_ENA 0 10 SPI_SLV_WR_DMA_DONE_INT_ENA 0 9 SPI_SLV_RD_DMA_DONE_INT_ENA 0 8 SPI_SLV_CMDA_INT_ENA 0 7 SPI_SLV_CMD9_INT_ENA 0 6 SPI_SLV_CMD8_INT_ENA 0 5 SPI_SLV_CMD7_INT_ENA 0 4 SPI_SLV_EN_QPI_INT_ENA 0 3 SPI_SLV_EX_QPI_INT_ENA 0 2 SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA 0 1 SPI_DMA_INFIFO_FULL_ERR_INT_ENA 0 0 Reset SPI_DMA_INFIFO_FULL_ERR_INT_ENA Write 1 to enable the SPI_DMA_INFIFO_FULL_ERR_INT interrupt. (R/W) SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA Write 1 to enable the SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. (R/W) SPI_SLV_EX_QPI_INT_ENA Write 1 to enable the SPI_SLV_EX_QPI_INT interrupt. (R/W) SPI_SLV_EN_QPI_INT_ENA Write 1 to enable the SPI_SLV_EN_QPI_INT interrupt. (R/W) SPI_SLV_CMD7_INT_ENA Write 1 to enable the SPI_SLV_CMD7_INT interrupt. (R/W) SPI_SLV_CMD8_INT_ENA Write 1 to enable the SPI_SLV_CMD8_INT interrupt. (R/W) SPI_SLV_CMD9_INT_ENA Write 1 to enable the SPI_SLV_CMD9_INT interrupt. (R/W) SPI_SLV_CMDA_INT_ENA Write 1 to enable the SPI_SLV_CMDA_INT interrupt. (R/W) SPI_SLV_RD_DMA_DONE_INT_ENA Write 1 to enable the SPI_SLV_RD_DMA_DONE_INT interrupt. (R/W) SPI_SLV_WR_DMA_DONE_INT_ENA Write 1 to enable the SPI_SLV_WR_DMA_DONE_INT inter- rupt. (R/W) SPI_SLV_RD_BUF_DONE_INT_ENA Write 1 to enable the SPI_SLV_RD_BUF_DONE_INT interrupt. (R/W) SPI_SLV_WR_BUF_DONE_INT_ENA Write 1 to enable the SPI_SLV_WR_BUF_DONE_INT interrupt. (R/W) Continued on the next page... Espressif Systems 989 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Register 29.17. SPI_DMA_INT_ENA_REG (0x0034) Continued from the previous page... SPI_TRANS_DONE_INT_ENA Write 1 to enable the SPI_TRANS_DONE_INT interrupt. (R/W) SPI_DMA_SEG_TRANS_DONE_INT_ENA Write 1 to enable the SPI_DMA_SEG_TRANS_DONE_INT interrupt. (R/W) SPI_SEG_MAGIC_ERR_INT_ENA Write 1 to enable the SPI_SEG_MAGIC_ERR_INT interrupt. (R/W) SPI_SLV_BUF_ADDR_ERR_INT_ENA Write 1 to enable the SPI_SLV_BUF_ADDR_ERR_INT inter- rupt. (R/W) SPI_SLV_CMD_ERR_INT_ENA Write 1 to enable the SPI_SLV_CMD_ERR_INT interrupt. (R/W) SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA Write 1 to enable the SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. (R/W) SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA Write 1 to enable the SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. (R/W) SPI_APP2_INT_ENA Write 1 to enable the SPI_APP2_INT interrupt. (R/W) SPI_APP1_INT_ENA Write 1 to enable the SPI_APP1_INT interrupt. (R/W) Espressif Systems 990 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Register 29.18. SPI_DMA_INT_CLR_REG (0x0038) (reserved) 0 0 0 0 0 0 0 0 0 0 0 31 21 SPI_APP1_INT_CLR 0 20 SPI_APP2_INT_CLR 0 19 SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR 0 18 SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR 0 17 SPI_SLV_CMD_ERR_INT_CLR 0 16 SPI_SLV_BUF_ADDR_ERR_INT_CLR 0 15 SPI_SEG_MAGIC_ERR_INT_CLR 0 14 SPI_DMA_SEG_TRANS_DONE_INT_CLR 0 13 SPI_TRANS_DONE_INT_CLR 0 12 SPI_SLV_WR_BUF_DONE_INT_CLR 0 11 SPI_SLV_RD_BUF_DONE_INT_CLR 0 10 SPI_SLV_WR_DMA_DONE_INT_CLR 0 9 SPI_SLV_RD_DMA_DONE_INT_CLR 0 8 SPI_SLV_CMDA_INT_CLR 0 7 SPI_SLV_CMD9_INT_CLR 0 6 SPI_SLV_CMD8_INT_CLR 0 5 SPI_SLV_CMD7_INT_CLR 0 4 SPI_SLV_EN_QPI_INT_CLR 0 3 SPI_SLV_EX_QPI_INT_CLR 0 2 SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR 0 1 SPI_DMA_INFIFO_FULL_ERR_INT_CLR 0 0 Reset SPI_DMA_INFIFO_FULL_ERR_INT_CLR Write 1 to clear the SPI_DMA_INFIFO_FULL_ERR_INT in- terrupt. (WT) SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR Write 1 to clear the SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. (WT) SPI_SLV_EX_QPI_INT_CLR Write 1 to clear the SPI_SLV_EX_QPI_INT interrupt. (WT) SPI_SLV_EN_QPI_INT_CLR Write 1 to clear the SPI_SLV_EN_QPI_INT interrupt. (WT) SPI_SLV_CMD7_INT_CLR Write 1 to clear the SPI_SLV_CMD7_INT interrupt. (WT) SPI_SLV_CMD8_INT_CLR Write 1 to clear the SPI_SLV_CMD8_INT interrupt. (WT) SPI_SLV_CMD9_INT_CLR Write 1 to clear the SPI_SLV_CMD9_INT interrupt. (WT) SPI_SLV_CMDA_INT_CLR Write 1 to clear the SPI_SLV_CMDA_INT interrupt. (WT) SPI_SLV_RD_DMA_DONE_INT_CLR Write 1 to clear the SPI_SLV_RD_DMA_DONE_INT interrupt. (WT) SPI_SLV_WR_DMA_DONE_INT_CLR Write 1 to clear the SPI_SLV_WR_DMA_DONE_INT interrupt. (WT) SPI_SLV_RD_BUF_DONE_INT_CLR Write 1 to clear the SPI_SLV_RD_BUF_DONE_INT interrupt. (WT) SPI_SLV_WR_BUF_DONE_INT_CLR Write 1 to clear the SPI_SLV_WR_BUF_DONE_INT interrupt. (WT) Continued on the next page... Espressif Systems 991 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Register 29.18. SPI_DMA_INT_CLR_REG (0x0038) Continued from the previous page... SPI_TRANS_DONE_INT_CLR Write 1 to clear the SPI_TRANS_DONE_INT interrupt. (WT) SPI_DMA_SEG_TRANS_DONE_INT_CLR Write 1 to clear the SPI_DMA_SEG_TRANS_DONE_INT interrupt. (WT) SPI_SEG_MAGIC_ERR_INT_CLR Write 1 to clear the SPI_SEG_MAGIC_ERR_INT interrupt. (WT) SPI_SLV_BUF_ADDR_ERR_INT_CLR Write 1 to clear the SPI_SLV_BUF_ADDR_ERR_INT interrupt. (WT) SPI_SLV_CMD_ERR_INT_CLR Write 1 to clear the SPI_SLV_CMD_ERR_INT interrupt. (WT) SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR Write 1 to clear the SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. (WT) SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR Write 1 to clear the SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. (WT) SPI_APP2_INT_CLR Write 1 to clear the SPI_APP2_INT interrupt. (WT) SPI_APP1_INT_CLR Write 1 to clear the SPI_APP1_INT interrupt. (WT) Espressif Systems 992 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Register 29.19. SPI_DMA_INT_RAW_REG (0x003C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 31 21 SPI_APP1_INT_RAW 0 20 SPI_APP2_INT_RAW 0 19 SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW 0 18 SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW 0 17 SPI_SLV_CMD_ERR_INT_RAW 0 16 SPI_SLV_BUF_ADDR_ERR_INT_RAW 0 15 SPI_SEG_MAGIC_ERR_INT_RAW 0 14 SPI_DMA_SEG_TRANS_DONE_INT_RAW 0 13 SPI_TRANS_DONE_INT_RAW 0 12 SPI_SLV_WR_BUF_DONE_INT_RAW 0 11 SPI_SLV_RD_BUF_DONE_INT_RAW 0 10 SPI_SLV_WR_DMA_DONE_INT_RAW 0 9 SPI_SLV_RD_DMA_DONE_INT_RAW 0 8 SPI_SLV_CMDA_INT_RAW 0 7 SPI_SLV_CMD9_INT_RAW 0 6 SPI_SLV_CMD8_INT_RAW 0 5 SPI_SLV_CMD7_INT_RAW 0 4 SPI_SLV_EN_QPI_INT_RAW 0 3 SPI_SLV_EX_QPI_INT_RAW 0 2 SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW 0 1 SPI_DMA_INFIFO_FULL_ERR_INT_RAW 0 0 Reset SPI_DMA_INFIFO_FULL_ERR_INT_RAW The raw interrupt status of SPI_DMA_INFIFO_FULL_ERR_INT. (R/WTC/SS) SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW The raw interrupt status of SPI_DMA_OUTFIFO_EMPTY_ERR_INT. SPI_SLV_EX_QPI_INT_RAW The raw interrupt status of SPI_SLV_EX_QPI_INT. (R/WTC/SS) SPI_SLV_EN_QPI_INT_RAW The raw interrupt status of SPI_SLV_EN_QPI_INT. (R/WTC/SS) SPI_SLV_CMD7_INT_RAW The raw interrupt status of SPI_SLV_CMD7_INT. (R/WTC/SS) SPI_SLV_CMD8_INT_RAW The raw interrupt status of SPI_SLV_CMD8_INT. (R/WTC/SS) SPI_SLV_CMD9_INT_RAW The raw interrupt status of SPI_SLV_CMD9_INT. (R/WTC/SS) SPI_SLV_CMDA_INT_RAW The raw interrupt status of SPI_SLV_CMDA_INT. (R/WTC/SS) SPI_SLV_RD_DMA_DONE_INT_RAW The raw interrupt status of SPI_SLV_RD_DMA_DONE_INT. (R/WTC/SS) SPI_SLV_WR_DMA_DONE_INT_RAW The raw interrupt status of SPI_SLV_WR_DMA_DONE_INT. (R/WTC/SS) SPI_SLV_RD_BUF_DONE_INT_RAW The raw interrupt status of SPI_SLV_RD_BUF_DONE_INT. (R/WTC/SS) Continued on the next page... Espressif Systems 993 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Register 29.19. SPI_DMA_INT_RAW_REG (0x003C) Continued from the previous page... SPI_SLV_WR_BUF_DONE_INT_RAW The raw interrupt status of SPI_SLV_WR_BUF_DONE_INT. (R/WTC/SS) SPI_TRANS_DONE_INT_RAW The raw interrupt status of SPI_TRANS_DONE_INT. (R/WTC/SS) SPI_DMA_SEG_TRANS_DONE_INT_RAW The raw interrupt status of SPI_DMA_SEG_TRANS_DONE_INT. (R/WTC/SS) SPI_SEG_MAGIC_ERR_INT_RAW The raw interrupt status of SPI_SEG_MAGIC_ERR_INT. (R/WTC/SS) SPI_SLV_BUF_ADDR_ERR_INT_RAW The raw interrupt status of SPI_SLV_BUF_ADDR_ERR_INT. (R/WTC/SS) SPI_SLV_CMD_ERR_INT_RAW The raw interrupt status of SPI_SLV_CMD_ERR_INT. (R/WTC/SS) SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW The raw interrupt status of SPI_MST_RX_AFIFO_WFULL_ERR_INT. (R/WTC/SS) SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW The raw interrupt status of SPI_MST_TX_AFIFO_REMPTY_ERR_INT. (R/WTC/SS) SPI_APP2_INT_RAW The raw interrupt status of SPI_APP2_INT. The value is only controlled by the application. (R/WTC/SS) SPI_APP1_INT_RAW The raw interrupt status of SPI_APP1_INT. The value is only controlled by the application. (R/WTC/SS) Espressif Systems 994 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Register 29.20. SPI_DMA_INT_ST_REG (0x0040) (reserved) 0 0 0 0 0 0 0 0 0 0 0 31 21 SPI_APP1_INT_ST 0 20 SPI_APP2_INT_ST 0 19 SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST 0 18 SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST 0 17 SPI_SLV_CMD_ERR_INT_ST 0 16 SPI_SLV_BUF_ADDR_ERR_INT_ST 0 15 SPI_SEG_MAGIC_ERR_INT_ST 0 14 SPI_DMA_SEG_TRANS_DONE_INT_ST 0 13 SPI_TRANS_DONE_INT_ST 0 12 SPI_SLV_WR_BUF_DONE_INT_ST 0 11 SPI_SLV_RD_BUF_DONE_INT_ST 0 10 SPI_SLV_WR_DMA_DONE_INT_ST 0 9 SPI_SLV_RD_DMA_DONE_INT_ST 0 8 SPI_SLV_CMDA_INT_ST 0 7 SPI_SLV_CMD9_INT_ST 0 6 SPI_SLV_CMD8_INT_ST 0 5 SPI_SLV_CMD7_INT_ST 0 4 SPI_SLV_EN_QPI_INT_ST 0 3 SPI_SLV_EX_QPI_INT_ST 0 2 SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST 0 1 SPI_DMA_INFIFO_FULL_ERR_INT_ST 0 0 Reset SPI_DMA_INFIFO_FULL_ERR_INT_ST The interrupt status of SPI_DMA_INFIFO_FULL_ERR_INT. (RO) SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST The interrupt status of SPI_DMA_OUTFIFO_EMPTY_ERR_INT. (RO) SPI_SLV_EX_QPI_INT_ST The interrupt status of SPI_SLV_EX_QPI_INT. (RO) SPI_SLV_EN_QPI_INT_ST The interrupt status of SPI_SLV_EN_QPI_INT. (RO) SPI_SLV_CMD7_INT_ST The interrupt status of SPI_SLV_CMD7_INT. (RO) SPI_SLV_CMD8_INT_ST The interrupt status of SPI_SLV_CMD8_INT. (RO) SPI_SLV_CMD9_INT_ST The interrupt status of SPI_SLV_CMD9_INT. (RO) SPI_SLV_CMDA_INT_ST The interrupt status of SPI_SLV_CMDA_INT. (RO) SPI_SLV_RD_DMA_DONE_INT_ST The interrupt status of SPI_SLV_RD_DMA_DONE_INT. (RO) SPI_SLV_WR_DMA_DONE_INT_ST The interrupt status of SPI_SLV_WR_DMA_DONE_INT. (RO) SPI_SLV_RD_BUF_DONE_INT_ST The interrupt status of SPI_SLV_RD_BUF_DONE_INT. (RO) SPI_SLV_WR_BUF_DONE_INT_ST The interrupt status of SPI_SLV_WR_BUF_DONE_INT. (RO) Continued on the next page... Espressif Systems 995 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Register 29.20. SPI_DMA_INT_ST_REG (0x0040) Continued from the previous page... SPI_TRANS_DONE_INT_ST The interrupt status of SPI_TRANS_DONE_INT. (RO) SPI_DMA_SEG_TRANS_DONE_INT_ST The interrupt status of SPI_DMA_SEG_TRANS_DONE_INT. (RO) SPI_SEG_MAGIC_ERR_INT_ST The interrupt status of SPI_SEG_MAGIC_ERR_INT. (RO) SPI_SLV_BUF_ADDR_ERR_INT_ST The interrupt status of SPI_SLV_BUF_ADDR_ERR_INT. (RO) SPI_SLV_CMD_ERR_INT_ST The interrupt status of SPI_SLV_CMD_ERR_INT. (RO) SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST The interrupt status of SPI_MST_RX_AFIFO_WFULL_ERR_INT. (RO) SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST The interrupt status of SPI_MST_TX_AFIFO_REMPTY_ERR_INT. (RO) SPI_APP2_INT_ST The interrupt status of SPI_APP2_INT. (RO) SPI_APP1_INT_ST The interrupt status of SPI_APP1_INT. (RO) Espressif Systems 996 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Register 29.21. SPI_DMA_INT_SET_REG (0x0044) (reserved) 0 0 0 0 0 0 0 0 0 0 0 31 21 SPI_APP1_INT_SET 0 20 SPI_APP2_INT_SET 0 19 SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET 0 18 SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET 0 17 SPI_SLV_CMD_ERR_INT_SET 0 16 SPI_SLV_BUF_ADDR_ERR_INT_SET 0 15 SPI_SEG_MAGIC_ERR_INT_SET 0 14 SPI_DMA_SEG_TRANS_DONE_INT_SET 0 13 SPI_TRANS_DONE_INT_SET 0 12 SPI_SLV_WR_BUF_DONE_INT_SET 0 11 SPI_SLV_RD_BUF_DONE_INT_SET 0 10 SPI_SLV_WR_DMA_DONE_INT_SET 0 9 SPI_SLV_RD_DMA_DONE_INT_SET 0 8 SPI_SLV_CMDA_INT_SET 0 7 SPI_SLV_CMD9_INT_SET 0 6 SPI_SLV_CMD8_INT_SET 0 5 SPI_SLV_CMD7_INT_SET 0 4 SPI_SLV_EN_QPI_INT_SET 0 3 SPI_SLV_EX_QPI_INT_SET 0 2 SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET 0 1 SPI_DMA_INFIFO_FULL_ERR_INT_SET 0 0 Reset SPI_DMA_INFIFO_FULL_ERR_INT_SET Write 1 to set the SPI_DMA_INFIFO_FULL_ERR_INT inter- rupt. (WT) SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET Write 1 to set the SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. (WT) SPI_SLV_EX_QPI_INT_SET Write 1 to set the SPI_SLV_EX_QPI_INT interrupt. (WT) SPI_SLV_EN_QPI_INT_SET Write 1 to set the SPI_SLV_EN_QPI_INT interrupt. (WT) SPI_SLV_CMD7_INT_SET Write 1 to set the SPI_SLV_CMD7_INT interrupt. (WT) SPI_SLV_CMD8_INT_SET Write 1 to set the SPI_SLV_CMD8_INT interrupt. (WT) SPI_SLV_CMD9_INT_SET Write 1 to set the SPI_SLV_CMD9_INT interrupt. (WT) SPI_SLV_CMDA_INT_SET Write 1 to set the SPI_SLV_CMDA_INT interrupt. (WT) SPI_SLV_RD_DMA_DONE_INT_SET Write 1 to set the SPI_SLV_RD_DMA_DONE_INT interrupt. (WT) SPI_SLV_WR_DMA_DONE_INT_SET Write 1 to set the SPI_SLV_WR_DMA_DONE_INT interrupt. (WT) SPI_SLV_RD_BUF_DONE_INT_SET Write 1 to set the SPI_SLV_RD_BUF_DONE_INT interrupt. (WT) SPI_SLV_WR_BUF_DONE_INT_SET Write 1 to set the SPI_SLV_WR_BUF_DONE_INT interrupt. (WT) SPI_TRANS_DONE_INT_SET Write 1 to set the SPI_TRANS_DONE_INT interrupt. (WT) Continued on the next page... Espressif Systems 997 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Register 29.21. SPI_DMA_INT_SET_REG (0x0044) Continued from the previous page... SPI_DMA_SEG_TRANS_DONE_INT_SET Write 1 to set the SPI_DMA_SEG_TRANS_DONE_INT in- terrupt. (WT) SPI_SEG_MAGIC_ERR_INT_SET Write 1 to set the SPI_SEG_MAGIC_ERR_INT interrupt. (WT) SPI_SLV_BUF_ADDR_ERR_INT_SET Write 1 to set the SPI_SLV_BUF_ADDR_ERR_INT interrupt. (WT) SPI_SLV_CMD_ERR_INT_SET Write 1 to set the SPI_SLV_CMD_ERR_INT interrupt. (WT) SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET Write 1 to set the SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. (WT) SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET Write 1 to set the SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. (WT) SPI_APP2_INT_SET Write 1 to set the SPI_APP2_INT interrupt. (WT) SPI_APP1_INT_SET Write 1 to set the SPI_APP1_INT interrupt. (WT) Register 29.22. SPI_W0_REG (0x0098) SPI_BUF0 0 31 0 Reset SPI_BUF0 32-bit data buffer 1. (R/W/SS) Espressif Systems 998 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Register 29.23. SPI_W1_REG (0x009C) SPI_BUF1 0 31 0 Reset SPI_BUF1 32-bit data buffer 1. (R/W/SS) Register 29.24. SPI_W2_REG (0x00A0) SPI_BUF2 0 31 0 Reset SPI_BUF2 32-bit data buffer 2. (R/W/SS) Register 29.25. SPI_W3_REG (0x00A4) SPI_BUF3 0 31 0 Reset SPI_BUF3 32-bit data buffer 3. (R/W/SS) Register 29.26. SPI_W4_REG (0x00A8) SPI_BUF4 0 31 0 Reset SPI_BUF4 32-bit data buffer 4. (R/W/SS) Espressif Systems 999 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Register 29.27. SPI_W5_REG (0x00AC) SPI_BUF5 0 31 0 Reset SPI_BUF5 32-bit data buffer 5. (R/W/SS) Register 29.28. SPI_W6_REG (0x00B0) SPI_BUF6 0 31 0 Reset SPI_BUF6 32-bit data buffer 6. (R/W/SS) Register 29.29. SPI_W7_REG (0x00B4) SPI_BUF7 0 31 0 Reset SPI_BUF7 32-bit data buffer 7. (R/W/SS) Register 29.30. SPI_W8_REG (0x00B8) SPI_BUF8 0 31 0 Reset SPI_BUF8 32-bit data buffer 8. (R/W/SS) Espressif Systems 1000 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Register 29.31. SPI_W9_REG (0x00BC) SPI_BUF9 0 31 0 Reset SPI_BUF9 32-bit data buffer 9. (R/W/SS) Register 29.32. SPI_W10_REG (0x00C0) SPI_BUF10 0 31 0 Reset SPI_BUF10 32-bit data buffer 10. (R/W/SS) Register 29.33. SPI_W11_REG (0x00C4) SPI_BUF11 0 31 0 Reset SPI_BUF11 32-bit data buffer 11. (R/W/SS) Register 29.34. SPI_W12_REG (0x00C8) SPI_BUF12 0 31 0 Reset SPI_BUF12 32-bit data buffer 12. (R/W/SS) Espressif Systems 1001 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 29 SPI Controller (SPI) Register 29.35. SPI_W13_REG (0x00CC) SPI_BUF13 0 31 0 Reset SPI_BUF13 32-bit data buffer 13. (R/W/SS) Register 29.36. SPI_W14_REG (0x00D0) SPI_BUF14 0 31 0 Reset SPI_BUF14 32-bit data buffer 14. (R/W/SS) Register 29.37. SPI_W15_REG (0x00D4) SPI_BUF15 0 31 0 Reset SPI_BUF15 32-bit data buffer 15. (R/W/SS) Register 29.38. SPI_DATE_REG (0x00F0) (reserved) 0 0 0 0 31 28 SPI_DATE 0x2304183 27 0 Reset SPI_DATE Version control register. (R/W) Espressif Systems 1002 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Chapter 30 I2C Controller (I2C) The I2C (Inter-Integrated Circuit) bus allows ESP32-C5 to communicate with multiple external devices. These external devices can share one I2C bus. ESP32-C5 has two I2C controllers: one in the main system and one in the low-power system. The I2C controller in the main system can act as a master or a slave (referred to as I2C below), while the one in the low-power system can only act as a master (referred to as LP_I2C below), which can still work when the main system sleeps. 30.1 Overview The I2C bus has two lines, namely a serial data line (SDA) and a serial clock line (SCL). Both SDA and SCL lines are open-drain. The I2C bus can be connected to a single or multiple master devices and a single or multiple slave devices. However, only one master device can access a slave at a time via the bus. The master initiates communication by generating a START condition: pulling the SDA line low while SCL is high. Then it issues nine clock pulses via SCL. The first eight pulses are used to transmit a 7-bit address followed by a read/write (R/W ) bit. If the address of an I2C slave matches the 7-bit address transmitted, this matching slave can respond by pulling SDA low on the ninth clock pulse. The master and the slave can send or receive data according to the R/W bit. Whether to terminate the data transfer or not is determined by the logic level of the acknowledge (ACK) bit. During data transfer, SDA changes only when SCL is low. Once the communication has finished, the master sends a STOP condition: pulling SDA up while SCL is high. If a master both reads and writes data in one transfer, then it should send a RSTART condition, a slave address, and a R/W bit before changing its operation. The RSTART condition is used to change the transfer direction and the mode of the devices (master mode or slave mode). 30.2 Feature List The I2C controller of ESP32-C5 has the following features: • Master mode and slave mode • Communication between multiple masters and slaves • Standard mode (100 Kbit/s) • Fast mode (400 Kbit/s) • 7-bit addressing and 10-bit addressing • Continuous data transfer achieved by pulling SCL low in slave mode • Programmable digital noise filtering Espressif Systems 1003 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) • Dual address mode, which uses slave address and slave memory or register address 30.3 Architecture Overview Figure 30.3-1. I2C Master Architecture Figure 30.3-2. I2C Slave Architecture The I2C controller runs either in master mode or slave mode, which is determined by I2C_MS_MODE. Figure 30.3-1 shows the architecture of a master, while Figure 30.3-2 shows that of a slave. The I2C controller has the following main parts: • Transmit and receive memory (TX/RX RAM): stores data to be transmitted and data received respectively. Espressif Systems 1004 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) • Command controller (CMD_Controller): generates RSTART, STOP, WRITE, READ, and END commands • SCL clock controller (SCL_FSM): generates the timing sequence conforming to the I2C protocol. Figure 30.3-3 and Table 30.3-1 are the timing diagram and corresponding parameters of the I2C protocol. • SDA data controller (SCL_MAIN_FSM): controls the execution of I2C commands and the data sequence of the SDA line. It also controls the ACK_deal module to generate the ACK bit and detect the level of the ACK bit on the SDA line. • Serial/parallel data converter (DATA_Shifter): shift data between serial and parallel form • Filter for SCL (SCL_Filter): remove noises on SCL input signals • Filter for SDA (SDA_Filter): remove noises on SDA input signals • ACK bit controller (ack_deal): generate the ACK bit and detect the level of the ACK bit on the SDA line under the control of SCL_MAIN_FSM. Besides, the I2C controller also has a clock module that generates I2C clocks, and a synchronization module that synchronizes the APB bus and the I2C controller. The clock module is used to select clock sources, turn on and off clocks, and divide clocks. The synchronization module synchronizes signal transfer between different clock domains. Figure 30.3-3. I2C Protocol Timing (Cited from Fig.31 in The I2C-bus specification Version 2.1) Espressif Systems 1005 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Table 30.3-1. I2C Timing Parameters (Cited from Table 5 in The I2C-bus specification Version 2.1) 30.4 Functional Description As mentioned above, one or more masters and one or more slaves can be connected on the I2C bus. The following sections describe the operations of the ESP32-C5 I2C controllers. Note that operations may differ between the I2C controllers in ESP32-C5 and other masters or slaves on the bus. Please refer to datasheets of individual I2C devices for specific information. 30.4.1 Clock Configuration Registers, TX RAM, and RX RAM are configured and accessed in the APB_CLK clock domain. The main logic of the I2C controller, including SCL_FSM, SCL_MAIN_FSM, SCL_FILTER, SDA_FILTER, and DATA_SHIFTER, are in the I2C_SCLK clock domain. You can configure the clock source for I2C_SCLK of I2C in the main system (HP) to XTAL_CLK or RC_FAST_CLK via PCR_I2C_SCLK_SEL. For the clock source for I2C_SCLK of LP_I2C in the low-power system (LP), you can configure it to CLK_XTALD2 or CLK_ROOT_FAST via LP_CLKRST_LP_I2C_CLK_SEL. The steps to configure the clock source for I2C are as follows: • Enable the clock source for I2C_SCLK of I2C by configuring PCR_I2C_SCLK_EN to 1. • When PCR_I2C_SCLK_SEL is 0, the clock source is XTAL_CLK. • When PCR_I2C_SCLK_SEL is 1, the clock source is RC_FAST_CLK. The steps to configure the clock source for LP_I2C are as follows: • Enable the clock source for I2C_SCLK of LP_I2C by configuring LPPERI_LP_EXT_I2C_CK_EN to 1. • When LP_CLKRST_LP_I2C_CLK_SEL is 0, the clock source is CLK_ROOT_FAST. • When LP_CLKRST_LP_I2C_CLK_SEL is 1, the clock source is CLK_XTALD2. Espressif Systems 1006 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) The clock source then passes through a fractional divider to generate I2C_SCLK of I2C according to the following formula: I2C_SCLK_DIV _N UM + 1 + I2C_SCLK_DIV _A I2C_SCLK_DIV _B In the formula, I2C_SCLK_DIV_NUM represents the integer part of the divisor, I2C_SCLK_DIV_A represents the numerator of the fractional part of the divisor, and I2C_SCLK_DIV_B represents the denominator of the fractional part of the divisor. Limited by timing parameters, the derived clock I2C_SCLK should operate at a frequency 20 times larger than SCL’s frequency. For I2C: • Configure I2C_SCLK_DIV_NUM via PCR_I2C_SCLK_DIV_NUM. • Configure I2C_SCLK_DIV_A via PCR_I2C_SCLK_DIV_A. • Configure I2C_SCLK_DIV_B via PCR_I2C_SCLK_DIV_B. 30.4.2 SCL and SDA Noise Filtering SCL_Filter and SDA_Filter modules are identical and are used to filter signal noise on SCL and SDA, respectively. These filters can be enabled or disabled by configuring I2C_SCL_FILTER_EN and I2C_SDA_FILTER_EN. Take SCL_Filter as an example. When enabled, SCL_Filter samples input signals on the SCL line continuously. These input signals are valid only if they remain unchanged for consecutive I2C_SCL_FILTER_THRES I2C_SCLK clock cycles. Given that only valid input signals can pass through the filter, SCL_Filter can remove glitches whose pulse width is shorter than I2C_SCL_FILTER_THRES I2C_SCLK clock cycles, while SDA_Filter can remove glitches whose pulse width is shorter than I2C_SDA_FILTER_THRES I2C_SCLK clock cycles. 30.4.3 SCL Clock Stretching The I2C controller operating in slave mode (i.e., as a slave) can perform clock stretching by holding the SCL line low. This action suspends data transmission, providing more time to process data. This function is enabled by setting the I2C_SLAVE_SCL_STRETCH_EN bit. The time period for releasing the SCL line from stretching is configured by setting the I2C_STRETCH_PROTECT_NUM field to avoid timing sequence errors. The slave can activate clock stretching by pulling the SCL line low in response to one of four specific events. 1. Address match: The address of the slave matches the address sent by the master via the SDA line, and the R/W bit is 1. 2. RAM being full: RX RAM of the slave is full. Note that when the slave receives less than the FIFO depth, which is 32 bytes in ESP32-C5 I2C, it is not necessary to enable clock stretching; when the slave receives FIFO depth bytes or more, you may interrupt data transmission to wrapped around RAM via the FIFO threshold, or enable clock stretching for more time to process data. When clock stretching is enabled, I2C_RX_FULL_ACK_LEVEL must be cleared, otherwise there will be unpredictable consequences. 3. RAM being empty: The slave is sending data, but its TX RAM is empty. 4. Sending an ACK: If I2C_SLAVE_BYTE_ACK_CTL_EN is set, the slave pulls SCL low when sending an ACK bit. At this stage, software validates data and configures I2C_SLAVE_BYTE_ACK_LVL to control the level of the ACK bit. Note that when RX RAM of the slave is full, the level of the ACK bit to be sent is determined by Espressif Systems 1007 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) I2C_RX_FULL_ACK_LEVEL, instead of I2C_SLAVE_BYTE_ACK_LVL. In this case, I2C_RX_FULL_ACK_LEVEL should also be cleared to ensure proper functioning of clock stretching. When clock stretching occurs, the cause of stretching can be read from the I2C_STRETCH_CAUSE bit. Clock stretching can be disabled by setting the I2C_SLAVE_SCL_STRETCH_CLR bit. 30.4.4 Generating SCL Pulses in Idle State Usually, when the I2C bus is idle, the SCL line is held high. The I2C controller in ESP32-C5 can be programmed to generate SCL pulses in an idle state. This function only works when the I2C controller is configured as master. If the I2C_SCL_RST_SLV_EN bit is set, hardware will send I2C_SCL_RST_SLV_NUM SCL pulses, and then automatically clear the I2C_SCL_RST_SLV_EN bit. 30.4.5 Synchronization I2C registers are configured in the APB_CLK domain, whereas the I2C controller is configured in the asynchronous I2C_SCLK domain. Therefore, before being used by the I2C controller, register values should be synchronized by first writing configuration registers and then writing 1 to I2C_CONF_UPGATE. Registers that need synchronization are listed in Table 30.4-1. Espressif Systems 1008 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Table 30.4-1. I2C Synchronous Registers Register Field Address I2C_CTR_REG I2C_SLV_TX_AUTO_START_EN 0x0004 I2C_ADDR_10BIT_RW_CHECK_EN I2C_ADDR_BROADCASTING_EN I2C_SDA_FORCE_OUT I2C_SCL_FORCE_OUT I2C_SAMPLE_SCL_LEVEL I2C_RX_FULL_ACK_LEVEL I2C_MS_MODE I2C_TX_LSB_FIRST I2C_RX_LSB_FIRST I2C_ARBITRATION_EN I2C_TO_REG I2C_TIME_OUT_EN 0x000C I2C_TIME_OUT_VALUE I2C_SLAVE_ADDR_REG I2C_ADDR_10BIT_EN 0x0010 I2C_SLAVE_ADDR I2C_FIFO_CONF_REG I2C_FIFO_ADDR_CFG_EN 0x0018 I2C_SCL_SP_CONF_REG I2C_SDA_PD_EN 0x0080 I2C_SCL_PD_EN I2C_SCL_RST_SLV_NUM I2C_SCL_RST_SLV_EN I2C_SCL_STRETCH_CONF_REG I2C_SLAVE_BYTE_ACK_CTL_EN 0x0084 I2C_SLAVE_BYTE_ACK_LVL I2C_SLAVE_SCL_STRETCH_EN I2C_STRETCH_PROTECT_NUM I2C_SCL_LOW_PERIOD_REG I2C_SCL_LOW_PERIOD 0x0000 I2C_SCL_HIGH_PERIOD_REG I2C_WAIT_HIGH_PERIOD 0x0038 I2C_HIGH_PERIOD I2C_SDA_HOLD_REG I2C_SDA_HOLD_TIME 0x0030 I2C_SDA_SAMPLE_REG I2C_SDA_SAMPLE_TIME 0x0034 I2C_SCL_START_HOLD_REG I2C_SCL_START_HOLD_TIME 0x0040 I2C_SCL_RSTART_SETUP_REG I2C_SCL_RSTART_SETUP_TIME 0x0044 I2C_SCL_STOP_HOLD_REG I2C_SCL_STOP_HOLD_TIME 0x0048 I2C_SCL_STOP_SETUP_REG I2C_SCL_STOP_SETUP_TIME 0x004C I2C_SCL_ST_TIME_OUT_REG I2C_SCL_ST_TO_I2C 0x0078 I2C_SCL_MAIN_ST_TIME_OUT_REG I2C_SCL_MAIN_ST_TO_I2C 0x007C I2C_FILTER_CFG_REG I2C_SCL_FILTER_EN 0x0050 I2C_SCL_FILTER_THRES I2C_SDA_FILTER_EN I2C_SDA_FILTER_THRES 30.4.6 Open-Drain Output SCL and SDA output drivers must be configured as open-drain. There are two ways to achieve this: Espressif Systems 1009 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) 1. Set I2C_SCL_FORCE_OUT and I2C_SDA_FORCE_OUT, and configure GPIO_PINn_PAD_DRIVER for corresponding SCL and SDA pads as open-drain. 2. Clear I2C_SCL_FORCE_OUT and I2C_SDA_FORCE_OUT. Because these lines are configured as open-drain, the low-to-high transition time of each line is longer, determined together by the pull-up resistor and line capacitance. The output duty cycle of I2C is limited by the SDA and SCL line’s pull-up speed, mainly SCL’s speed. In addition, when I2C_SCL_FORCE_OUT and I2C_SCL_PD_EN are set to 1, SCL can be forced low; when I2C_SDA_FORCE_OUT and I2C_SDA_PD_EN are set to 1, SDA can be forced low. 30.4.7 Timing Parameters Configuration Figure 30.4-1. I2C Timing Diagram Figure 30.4-1 shows the timing diagram of an I2C master. This figure also specifies registers used to configure the START bit, STOP bit, data hold time, data sample time, waiting time on the rising SCL edge, etc. Timing parameters are calculated as follows in I2C_SCLK clock cycles: 1. t LOW = (I2C_SCL_LOW _P ERIO D + 1) · T I2C_SCLK 2. t HIGH = (I2C_SCL_HIGH_P ERIOD + 1) · T I2C_SCLK 3. t SU:ST A = (I2C_SCL_RST ART _SET U P _T IM E + 1) · T I2C_SCLK 4. t HD:ST A = (I2C_SCL_ST ART _HOLD_T IME + 1) · T I2C_SCLK 5. t r = (I2C_SCL_W AIT _HIGH_P ERIOD + 1) · T I2C_SCLK 6. t SU:ST O = (I2C_SCL_ST OP _SET UP _T IM E + 1) · T I2C_SCLK 7. t BUF = (I2C_SCL_ST OP _HOLD_T IM E + 1) · T I2C_SCLK 8. t HD:DAT = (I2C_SDA_HOLD_T IME + 1) · T I2C_SCLK 9. t SU:DAT = (I2C_SCL_LOW _P ERIO D − I2C_SDA_HOLD _T IM E) · T I2C_SCLK Timing registers below are divided into two groups, depending on the mode in which these registers are active: • Master mode only: Espressif Systems 1010 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) 1. I2C_SCL_START_HOLD_TIME: Specifies the interval between the moment SDA is pulled low and the moment SCL is pulled low when the master generates a START condition. This interval is (I2C_SCL_START_HOLD_TIME +1) in I2C_SCLK cycles. This register is active only when the I2C controller works in master mode. 2. I2C_SCL_LOW_PERIOD: Specifies the low period of SCL. This period lasts (I2C_SCL_LOW_PERIOD +1) in I2C_SCLK cycles. This register is active only when the I2C controller works in master mode. However, this period could be extended in the following scenarios: – SCL is pulled low by peripheral devices when I2C acts as a master. – SCL is pulled low by an END command executed by the I2C controller. – SCL is pulled low by clock stretching when I2C acts as a slave. 3. I2C_SCL_WAIT_HIGH_PERIOD: Specifies the time for SCL to switch from low to high in I2C_SCLK cycles. Please make sure that SCL can be pulled high within this time period. Otherwise, the high period of SCL may be incorrect. This register is active only when the I2C controller works in master mode. 4. I2C_SCL_HIGH_PERIOD: Specifies the high period of SCL in I2C_SCLK cycles. This register is active only when the I2C controller works in master mode. When SCL goes high within (I2C_SCL_WAIT_HIGH_PERIOD + 1) in I2C_SCLK cycles, its frequency is: f scl = f I2C_SCLK I2C_SCL_LOW_PERIOD + I2C_SCL_HIGH_PERIOD + I2C_SCL_WAIT_HIGH_PERIOD + 3 + I2C_SCL_FILTER_THRES where 3 represents the amount of clock cycles required to synchronize the SCL. If the SCL filtering function is turned on, the delay caused by I2C_SCL_FILTER_THRES needs to be added. As the SCL low-to-high transition time represented by I2C_SCL_WAIT_HIGH_PERIOD + 1 module clock can be affected by the pull-up resistor, IO drive capability, SCL line capacitance, etc., deviation may occur between the actual frequency of the test and the theoretical frequency. At this point, deviations can be reduced by adjusting the value of I2C_SCL_WAIT_HIGH_PERIOD. • Master mode and slave mode: 1. I2C_SDA_SAMPLE_TIME: Specifies the interval between the rising edge of SCL and the level sampling time of SDA. It is advised to set a value in the middle of SCL’s high period, so as to correctly sample the level of SCL. This register is active both in master mode and slave mode. 2. I2C_SDA_HOLD_TIME: Specifies the interval between changing the SDA output level and the falling edge of SCL. This register is active both in master mode and slave mode. Timing parameters limits corresponding register configuration. 1. f I2C_SC LK f SC L > 20 2. 3 × f I2C_SCLK ≤ (I2C_SDA_HOLD_T IME − 4) × f AP B_CLK 3. I2C_SDA_HOLD_TIME + I2C_SCL_START_HOLD_TIME > SDA_FILTER_THRES + 3 4. I2C_SCL_WAIT_HIGH_PERIOD < I2C_SDA_SAMPLE_TIME < I2C_SCL_HIGH_PERIOD 5. I2C_SDA_SAMPLE_TIME < I2C_SCL_WAIT_HIGH_PERIOD + I2C_SCL_START_HOLD_TIME + I2C_SCL_RSTART_SETUP_TIME 6. I2C_STRETCH_PROTECT_NUM + I2C_SDA_HOLD_TIME > I2C_SCL_LOW_PERIOD Espressif Systems 1011 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) 30.4.8 Timeout Control The I2C controller has three types of timeout control, namely timeout control for SCL_FSM, for SCL_MAIN_FSM, and for the SCL line. The first two are always enabled, while the third is configurable. When SCL_FSM remains unchanged for more than 2 I2C_SCL_ST _T O_I2C+1 clock cycles, an I2C_SCL_ST_TO_INT interrupt is triggered, and then SCL_FSM goes to idle state. The value of I2C_SCL_ST_TO_I2C should be less than or equal to 23, which means SCL_FSM could remain unchanged for 2 24 I2C_SCLK clock cycles at most before the interrupt is generated. When SCL_MAIN_FSM remains unchanged for more than 2 I2C_SCL_M AIN _ST _T O_I2C+1 I2C_SCLK clock cycles, an I2C_SCL_MAIN_ST_TO_INT interrupt is triggered, and then SCL_MAIN_FSM goes to idle state. The value of I2C_SCL_MAIN_ST_TO_I2C should be less than or equal to 23, which means SCL_MAIN_FSM could remain unchanged for 2 24 clock cycles at most before the interrupt is generated. Timeout control for SCL is enabled by setting I2C_TIME_OUT_EN. When the level of SCL remains unchanged for more than 2 I2C_T IM E_OUT _V ALU E+1 clock cycles, an I2C_TIME_OUT_INT interrupt is triggered, and then the I2C bus goes to idle state. 30.4.9 Command Configuration When the I2C controller works in master mode, CMD_Controller reads commands from eight sequential command registers and controls SCL_FSM and SCL_MAIN_FSM accordingly. Figure 30.4-2. Structure of I2C Command Registers Command registers, whose structure is illustrated in Figure 30.4-2, are active only when the I2C controller works in master mode. Fields of command registers are: 1. CMD_DONE: Indicates that a command has been executed. After each command has been executed, the CMD_DONE bit in the corresponding command register is set to 1 by hardware. By reading this bit, the software can tell if the command has been executed. When writing new commands, this bit must be cleared by software. 2. op_code: Indicates the command. The I2C controller supports five commands: • WRITE: op_code = 1. The I2C controller sends a slave address, a register address (only in dual address mode), and data to the slave. • STOP: op_code = 2. The I2C controller sends a STOP bit defined by the I2C protocol. This code also indicates that the command sequence has been executed, and the CMD_Controller stops reading commands. After restarted by software, the CMD_Controller resumes reading commands from command register 0. Espressif Systems 1012 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) • READ: op_code = 3. The I2C controller reads data from the slave. • END: op_code = 4. The I2C controller pulls the SCL line down and suspends I2C communication. This code also indicates that the command sequence has been completed, and the CMD_Controller stops executing commands. Once the software refreshes data in command registers and the RAM, the CMD_Controller can be restarted to execute commands from command register 0 again. • RSTART: op_code = 6. The I2C controller sends a START bit or a RSTART bit defined by the I2C protocol. 3. ack_value: Used to configure the level of the ACK bit sent by the I2C controller during a read operation. This bit is ignored in RSTART, STOP, END, and WRITE conditions. 4. ack_exp: Used to configure the level of the ACK bit expected by the I2C controller during a write operation. This bit is ignored during RSTART, STOP, END, and READ conditions. 5. ack_check_en: Used to enable the I2C controller during a write operation to check whether the ACK level sent by the slave matches ack_exp in the command. If this bit is set and the level received does not match ack_exp in the WRITE command, the master will generate an I2C_NACK_INT interrupt and a STOP condition for data transfer. If this bit is cleared, the controller will not check the ACK level sent by the slave. This bit is ignored during RSTART, STOP, END, and READ conditions. 6. byte_num: Specifies the length of data (in bytes) to be read or written. It can range from 1 to 255 bytes. This bit is ignored during RSTART, STOP, and END conditions. Each command sequence is executed starting from command register 0 and terminated by a STOP or an END. Therefore, there must be a STOP or an END command in the eight command registers. A complete data transfer on the I2C bus should be initiated by a START and terminated by a STOP. The transfer process may be completed using multiple sequences, separated by END commands. Each sequence may differ in the direction of data transfer, clock frequency, slave addresses, data length, etc. This allows efficient use of available peripheral RAM and also achieves more flexible I2C communication. 30.4.10 TX/RX RAM Data Storage Both TX RAM and RX RAM are 32 × 8 bits and can be accessed in FIFO or non-FIFO mode. If I2C_NONFIFO_EN bit is cleared, both RAMs are accessed in FIFO mode; if I2C_NONFIFO_EN bit is set, both RAMs are accessed in non-FIFO mode. TX RAM stores data that the I2C controller needs to send. During communication, when the I2C controller needs to send data (except acknowledgment bits), it reads data from TX RAM and sends them sequentially via SDA. When the I2C controller works in master mode, all data must be stored in TX RAM in the order they need to be sent to slaves. The data stored in TX RAM include slave addresses, read/write bits, register addresses (only in dual address mode) and data to be sent. When the I2C controller works in slave mode, TX RAM only stores data to be sent. TX RAM can be read and written by the CPU. The CPU writes to TX RAM either in FIFO mode or in non-FIFO mode (direct address). In FIFO mode, the CPU writes to TX RAM via the fixed address I2C_DATA_REG, with addresses for writing in TX RAM incremented automatically by hardware. In non-FIFO mode, the CPU accesses TX RAM directly via address fields (I2C Base Address + 0x100) ~(I2C Base Address + 0x17C). Each byte in TX RAM occupies an entire word in the address space. Therefore, the address of the first byte is I2C Base Address + 0x100, the second byte is I2C Base Address + 0x104, the third byte is I2C Base Address + 0x108, and so on. Espressif Systems 1013 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) The CPU can only read TX RAM via direct addresses. Bytes written to the TX RAM can be read back by the CPU, via the direct addresses. Addresses for reading TX RAM are the same as addresses for writing TX RAM. RX RAM stores data the I2C controller receives during communication. When the I2C controller works in slave mode, neither slave addresses sent by the master nor register addresses (only in dual address mode) will be stored in RX RAM. Values of RX RAM can be read by software after I2C communication is completed. RX RAM can only be read by the CPU. The CPU reads RX RAM either in FIFO mode or in non-FIFO mode (direct address). In FIFO mode, the CPU reads RX RAM via the fixed address I2C_DATA_REG, with addresses for reading RX RAM incremented automatically by hardware. In non-FIFO mode, the CPU accesses TX RAM directly via address fields (I2C Base Address + 0x180) ~(I2C Base Address + 0x1FC). Each byte in RX RAM occupies an entire word in the address space. Therefore, the address of the first byte is I2C Base Address + 0x180, the second byte is I2C Base Address + 0x184, the third byte is I2C Base Address + 0x188 and so on. In FIFO mode, the TX RAM of a master may wrap around to send data larger than the FIFO depth. Set I2C_FIFO_PRT_EN. If the size of data to be sent is smaller than I2C_TXFIFO_WM_THRHD (master), an I2C_TXFIFO_WM_INT (master) interrupt is generated. After receiving the interrupt, the software continues writing to I2C_DATA_REG (master). Please ensure that software writes to or refreshes TX RAM before the master sends data, otherwise it may result in unpredictable consequences. In FIFO mode, the RX RAM of a slave may also wrap around to receive data larger than the FIFO depth. Set I2C_FIFO_PRT_EN and clear I2C_RX_FULL_ACK_LEVEL. If data already received (to be overwritten) is larger than I2C_RXFIFO_WM_THRHD (slave), an I2C_RXFIFO_WM_INT (slave) interrupt is generated. After receiving the interrupt, the software continues reading from I2C_DATA_REG (slave). 30.4.11 Data Conversion DATA_Shifter is used for serial/parallel conversion, converting byte data in TX RAM to an outgoing serial bitstream or an incoming serial bitstream to byte data in RX RAM. I2C_RX_LSB_FIRST and I2C_TX_LSB_FIRST can be used to select LSB- or MSB-first storage and transmission of data. 30.4.12 Addressing Mode The ESP32-C5 I2C controller supports 7-bit and 10-bit addressing. 10-bit addressing can be mixed with 7-bit addressing. Besides, the ESP32-C5 I2C controller also supports dual address mode. Define the slave address as SLV_ADDR. In 7-bit addressing mode, the slave address is SLV_ADDR[6:0]; in 10-bit addressing mode, the slave address is SLV_ADDR[9:0]. In 7-bit addressing mode, the master only needs to send one byte of the address, which comprises SLV_ADDR[6:0] and a R /W bit. In the 7-bit addressing mode, there is a special case called general call addressing (broadcast). It is enabled by setting I2C_ADDR_BROADCASTING_EN in a slave. When the slave receives the general call address (0x00) from the master and the R/W bit followed is 0, it responds to the master regardless of its own address. In 10-bit addressing mode, the master needs to send two bytes of address. The first byte is slave_addr_first_7bits followed by a R/W bit, and slave_addr_first_7bits should be configured as (0x78 | SLV_ADDR[9:8]). The second byte is slave_addr_second_byte, which should be configured as SLV_ADDR[7:0]. The slave can enable 10-bit addressing by configuring I2C_ADDR_10BIT_EN. I2C_SLAVE_ADDR is used to Espressif Systems 1014 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) configure I2C slave address. Specifically, I2C_SLAVE_ADDR[14:7] should be configured as SLV_ADDR[7:0], and I2C_SLAVE_ADDR[6:0] should be configured as (0x78 | SLV_ADDR[9:8]). Since a 10-bit slave address has one more byte than a 7-bit address, byte_num of the WRITE command and the number of bytes in the RAM increase by one. Please refer to Programming Example for detailed descriptions. When working in slave mode, the I2C controller supports dual address mode, where the first address is the address of an I2C slave, and the second one is the slave’s memory address. When using dual address mode, RAM must be accessed in non-FIFO mode. Dual address mode is enabled by setting I2C_FIFO_ADDR_CFG_EN. When the slave address received by the slave is inconsistent with the internally configured slave address, the I2C_SLAVE_ADDR_UNMATCH interrupt will be generated. 30.4.13 R/W Bit Check in 10-bit Addressing Mode In 10-bit addressing mode, when I2C_ADDR_10BIT_RW_CHECK_EN is set to 1, the I2C controller performs a check on the first byte, which consists of slave_addr_first_7bits and a R/W bit. When the R/W bit does not indicate a WRITE operation, i.e., not in line with the I2C protocol, the data transfer ends. If the check feature is not enabled, when the R/W bit does not indicate a WRITE, the data transfer still continues, but transfer failure may occur. 30.4.14 Start the I2C Controller To start the I2C controller in master mode, after configuring the controller to master mode and command registers, write 1 to I2C_TRANS_START in order to let the master start to parse and execute command sequences. The master always executes a command sequence starting from the command register 0 to a STOP or an END. To execute another command sequence starting from command register 0, refresh commands by writing 1 again to I2C_TRANS_START. To start the I2C controller slave mode, after configuring the controller to slave mode and setting the relevant registers, write 1 to I2C_TRANS_START. The slave will respond to the master when the received address matches. For the slave device, please note: • Always set I2C_TRANS_START before accepting any transfer. Otherwise, even if the address matches, the slave will not respond to the master. • If the master initiates a STOP condition and prematurely terminates the transmission with the slave, the slave must first set I2C_SLV_TX_AUTO_START_EN, then set I2C_TRANS_START, and finally clear I2C_SLV_TX_AUTO_START_EN before the next transfer. Otherwise, an abnormal TX FIFO pointer issue will occur in the slave. 30.5 Functional Differences Between LP_I2C and I2C LP_I2C can be used as a master to communicate with external devices when the main system sleeps. LP_I2C includes all the functions of the ESP32-C5 I2C master , but doesn’t include any functions of ESP32-C5 I2C slave . It does not contain any registers related to the I2C slave . For detailed register list, see 30.8.2 LP_I2C Register Summary. Espressif Systems 1015 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) The design differences between LP_I2C and I2C master are as follows: • The size of TX/RX RAM in LP_I2C is 16x8 bit, which means the TX�RX FIFO depth is 16 bytes. • The clock source of APB_CLK in LP_I2C is CLK_AON_FAST. The clock source for I2C_SCLK is configured via LP_CLKRST_LP_I2C_CLK_SEL. The corresponding bits are: – 0: CLK_ROOT_FAST – 1: CLK_XTALD2 Configuring LPPERI_LP_EXT_I2C_CK_EN to 1 enables the clock source of I2C_SCLK. Adjust the timing registers accordingly when the clock frequency changes. See the programming examples of ESP32-C5 I2C slave in Section 30.7 for that of LP_I2C. 30.6 Interrupts ESP32-C5’s I2Cn can generate the I2Cn_INTR interrupt signal that will be sent to the Interrupt Matrix. There are several internal interrupt sources from I2Cn that can generate the above interrupt signal(s) as follows: • I2C_SLAVE_STRETCH_INT: Triggered when one of the four stretching events occurs in slave mode. • I2C_DET_START_INT: Triggered when the master or the slave detects a START signal. • I2C_SCL_MAIN_ST_TO_INT: Triggered when the main state machine SCL_MAIN_FSM remains unchanged for over 2 I2C_SCL_M AIN _ST _T O_I2C+1 clock cycles. • I2C_SCL_ST_TO_INT: Triggered when the state machine SCL_FSM remains unchanged for over 2 I2C_SCL_ST _T O_I2C+1 clock cycles. • I2C_RXFIFO_UDF_INT: Triggered when the I2C controller reads RX FIFO via the APB bus, but RX FIFO is empty. • I2C_TXFIFO_OVF_INT: Triggered when the I2C controller writes TX FIFO via the APB bus, but TX FIFO is full. • I2C_NACK_INT: Triggered when the ACK value received by the master is not as expected, or when the ACK value received by the slave is 1. • I2C_TRANS_START_INT: Triggered when the I2C controller sends a START bit. • I2C_TIME_OUT_INT: Triggered when SCL stays high or low for more than 2 I2C_T IM E_OUT _V ALU E+1 clock cycles during data transfer. • I2C_TRANS_COMPLETE_INT: Triggered when the I2C controller detects a STOP bit. • I2C_MST_TXFIFO_UDF_INT: Triggered when TX FIFO of the master underflows. • I2C_ARBITRATION_LOST_INT: Triggered when the SDA’s output value does not match its input value while the master’s SCL is high. • I2C_BYTE_TRANS_DONE_INT: Triggered when the I2C controller sends or receives a byte. • I2C_END_DETECT_INT: Triggered when op_code of the master indicates an END command and an END condition is detected. • I2C_RXFIFO_OVF_INT: Triggered when RX FIFO of the I2C controller overflows. Espressif Systems 1016 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) • I2C_TXFIFO_WM_INT: I2C TX FIFO watermark interrupt. Triggered when I2C_FIFO_PRT_EN is 1 and the pointers of TX FIFO are less than I2C_TXFIFO_WM_THRHD[4:0]. • I2C_RXFIFO_WM_INT: I2C RX FIFO watermark interrupt. Triggered when I2C_FIFO_PRT_EN is 1 and the pointers of RX FIFO are greater than I2C_RXFIFO_WM_THRHD[4:0]. • I2C_GENERAL_CALL_INT: Triggered when the general call address is received in slave mode. • I2C_SLAVE_ADDR_UNMATCH_INT: Triggered when the received slave address is inconsistent with the internally configured slave address in slave mode. Note: For definitions of interrupt, interrupt signal, interrupt source, and their correlations, please refer to Chapter 9 Interrupt Matrix > Section 9.2 Terminology. Each interrupt source can be configured by a common set of registers that are described in Section Interrupt Configuration Registers. The specific registers can be found in Section 30.8.1 I2C Register Summary. 30.7 Programming Procedures This section provides programming examples for typical communication scenarios. ESP32-C5 has two I2C controllers. For the convenience of description, I2C masters and slaves in all subsequent figures are ESP32-C5 I2C controllers. I2C master is referred to as I2C master , and I2C slave is referred to as I2C slave . 30.7.1 I2C master Writes to I2C slave with a 7-bit Address in One Command Sequence 30.7.1.1 Introduction Figure 30.7-1. I2C master Writing to I2C slave with a 7-bit Address Espressif Systems 1017 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Figure 30.7-1 shows how I2C master writes N bytes of data to I2C slave registers or RAM using 7-bit addressing. As shown in Figure 30.7-1, the first byte in the RAM of I2C master is a 7-bit I2C slave address followed by a R/W bit. When the R/W bit is 0, it indicates a WRITE operation. The remaining bytes are used to store data ready for transfer. The cmd box contains related command sequences. After the command sequence is configured and data in RAM is ready, I2C master enables the controller and initiates data transfer by setting the I2C_TRANS_START bit. The controller has four steps to take: 1. Wait for SCL to go high, to avoid SCL being used by other masters or slaves. 2. Execute a RSTART command by sending a START bit. 3. Execute a WRITE command by taking N+1 bytes from the RAM in order and sending them to I2C slave in the same order. The first byte is the address of I2C slave . 4. Execute a STOP command. Once the I2C master transfers a STOP bit, an I2C_TRANS_COMPLETE_INT interrupt is generated. 30.7.1.2 Configuration Example 1. Configure the timing parameter registers of I2C master and I2C slave according to Section 30.4.7. 2. Set I2C_MS_MODE (master) to 1, and I2C_MS_MODE (slave) to 0. 3. Write 1 to I2C_CONF_UPGATE (master) and I2C_CONF_UPGATE (slave) to synchronize registers. 4. Configure command registers of I2C master . Command register op_code ack_value ack_exp ack_check_en byte_num I2C_COMMAND0 (master) RSTART — — — — I2C_COMMAND1 (master) WRITE ack_value ack_exp 1 N+1 I2C_COMMAND2 (master) STOP — — — — 5. Write the address of I2C slave and data to be sent to TX RAM of I2C master in either FIFO mode or non-FIFO mode according to Section 30.4.10. 6. Write the address of I2C slave to I2C_SLAVE_ADDR (slave) in I2C_SLAVE_ADDR_REG (slave) register. 7. Write 1 to I2C_CONF_UPGATE (master) and I2C_CONF_UPGATE (slave) to synchronize registers. 8. Write 1 to I2C_TRANS_START (master) and I2C_TRANS_START (slave) to start transfer. 9. I2C slave compares the slave address sent by I2C master with its own address in I2C_SLAVE_ADDR (slave). When ack_check_en (master) in I2C master ’s WRITE command is 1, I2C master checks ACK value each time it sends a byte. When ack_check_en (master) is 0, I2C master does not check the ACK value and take I2C slave as a matching slave by default. • Match: If the received ACK value matches ack_exp (master) (the expected ACK value) in the WRITE command, I2C master continues data transfer. • Not match: If the received ACK value does not match ack_exp in the WRITE command, I2C master generates an I2C_NACK_INT (master) interrupt and stops data transfer. 10. I2C master sends data, and determines whether to check ACK value according to ack_check_en (master). 11. If data to be sent (N) is larger than TX FIFO depth, TX RAM of I2C master may wrap around in FIFO mode. For details, please refer to Section 30.4.10. Espressif Systems 1018 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) 12. If data to be received (N) is larger than RX FIFO depth, RX RAM of I2C slave may wrap around in FIFO mode. For details, please refer to Section 30.4.10. If data to be received (N) is larger than RX FIFO depth, the other way is to enable clock stretching by setting the I2C_SLAVE_SCL_STRETCH_EN (slave), and clearing I2C_RX_FULL_ACK_LEVEL. When RX RAM is full, an I2C_SLAVE_STRETCH_INT (slave) interrupt is generated. In this way, I2C slave can hold SCL low, in exchange for more time to read data. After the software has finished reading, you can set I2C_SLAVE_STRETCH_INT_CLR (slave) to 1 to clear interrupt, and set I2C_SLAVE_SCL_STRETCH_CLR (slave) to release the SCL line. 13. After data transfer completes, I2C master executes the STOP command, and generates an I2C_TRANS_COMPLETE_INT (master) interrupt. 30.7.2 I2C master Writes to I2C slave with a 10-bit Address in One Command Sequence 30.7.2.1 Introduction Figure 30.7-2. I2C master Writing to a Slave with a 10-bit Address Figure 30.7-2 shows how I2C master writes N bytes of data using 10-bit addressing to an I2C slave. The configuration and transfer process is similar to what is described in 30.7.1, except that a 10-bit I2C slave address is formed from two bytes. Since a 10-bit I2C slave address has one more byte than a 7-bit I2C slave address, byte_num and length of data in TX RAM increase by 1 accordingly. 30.7.2.2 Configuration Example 1. Set I2C_MS_MODE (master) to 1, and I2C_MS_MODE (slave) to 0. 2. Write 1 to I2C_CONF_UPGATE (master) and I2C_CONF_UPGATE (slave) to synchronize registers. 3. Configure command registers of I2C master . Espressif Systems 1019 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Command registers op_code ack_value ack_exp ack_check_en byte_num I2C_COMMAND0 (master) RSTART — — — — I2C_COMMAND1 (master) WRITE ack_value ack_exp 1 N+2 I2C_COMMAND2 (master) STOP — — — — 4. Configure I2C_SLAVE_ADDR (slave) in I2C_SLAVE_ADDR_REG (slave) as I2C slave ’s 10-bit address, and set I2C_ADDR_10BIT_EN (slave) to 1 to enable 10-bit addressing. 5. Write the address of I2C slave and data to be sent to TX RAM of I2C master . The first byte of the address of I2C slave comprises ((0x78 | I2C_SLAVE_ADDR[9:8])«1) and a R/W bit. The second byte of the address of I2C slave is I2C_SLAVE_ADDR[7:0]. These two bytes are followed by data to be sent in FIFO or non-FIFO mode. 6. Write 1 to I2C_CONF_UPGATE (master) and I2C_CONF_UPGATE (slave) to synchronize registers. 7. Write 1 to I2C_TRANS_START (master) and I2C_TRANS_START (slave) to start transfer. 8. I2C slave compares the slave address sent by I2C master with its own address in I2C_SLAVE_ADDR (slave). When ack_check_en (master) in I2C master ’s WRITE command is 1, I2C master checks ACK value each time it sends a byte. When ack_check_en (master) is 0, I2C master does not check the ACK value and take I2C slave as a matching slave by default. • Match: If the received ACK value matches ack_exp (master) (the expected ACK value), I2C master continues data transfer. • Not match: If the received ACK value does not match ack_exp, I2C master generates an I2C_NACK_INT (master) interrupt and stops data transfer. 9. I2C master sends data, and determines whether to check ACK value according to ack_check_en (master). 10. If data to be sent is larger than TX FIFO depth, TX RAM of I2C master may wrap around in FIFO mode. For details, please refer to Section 30.4.10. 11. If data to be received is larger than RX FIFO depth, RX RAM of I2C slave may wrap around in FIFO mode. For details, please refer to Section 30.4.10. If data to be received is larger than RX FIFO depth, the other way is to enable clock stretching by setting I2C_SLAVE_SCL_STRETCH_EN (slave), and clearing I2C_RX_FULL_ACK_LEVEL to 0. When RX RAM is full, an I2C_SLAVE_STRETCH_INT (slave) interrupt is generated. In this way, I2C slave can hold SCL low, in exchange for more time to read data. After the software has finished reading, you can set I2C_SLAVE_STRETCH_INT_CLR (slave) to 1 to clear interrupt, and set I2C_SLAVE_SCL_STRETCH_CLR (slave) to release the SCL line. 12. After data transfer completes, I2C master executes the STOP command, and generates an I2C_TRANS_COMPLETE_INT (master) interrupt. 30.7.3 I2C master Writes to I2C slave with Two 7-bit Addresses in One Com- mand Sequence Espressif Systems 1020 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) 30.7.3.1 Introduction Figure 30.7-3. I2C master Writing to I2C slave with Two 7-bit Addresses Figure 30.7-3 shows how I2C master writes N bytes of data to I2C slave registers or RAM using 7-bit double addressing. The configuration and transfer process is similar to what is described in Section 30.7.1, except that in 7-bit dual address mode I2C master sends two 7-bit addresses. The first address is the address of an I2C slave, and the second one is I2C slave ’s memory address (i.e., addrM in Figure 30.7-3). When using double addressing, RAM must be accessed in non-FIFO mode. The I2C slave puts received byte0 byte (N-1) into its RAM in an order starting from addrM. The RAM is overwritten every 32 bytes. 30.7.3.2 Configuration Example 1. Set I2C_MS_MODE (master) to 1, and I2C_MS_MODE (slave) to 0. 2. Set I2C_FIFO_ADDR_CFG_EN (slave) to 1 to enable dual address mode. 3. Write 1 to I2C_CONF_UPGATE (master) and I2C_CONF_UPGATE (slave) to synchronize registers. 4. Configure command registers of I2C master . Command registers op_code ack_value ack_exp ack_check_en byte_num I2C_COMMAND0 (master) RSTART — — — — I2C_COMMAND1 (master) WRITE ack_value ack_exp 1 N+2 I2C_COMMAND2 (master) STOP — — — — 5. Write the address of I2C slave and data to be sent to TX RAM of I2C master in FIFO or non-FIFO mode. 6. Write the address of I2C slave to I2C_SLAVE_ADDR (slave) in I2C_SLAVE_ADDR_REG (slave) register. 7. Write 1 to I2C_CONF_UPGATE (master) and I2C_CONF_UPGATE (slave) to synchronize registers. 8. Write 1 to I2C_TRANS_START (master) and I2C_TRANS_START (slave) to start transfer. 9. I2C slave compares the slave address sent by I2C master with its own address in I2C_SLAVE_ADDR (slave). When ack_check_en (master) in I2C master ’s WRITE command is 1, I2C master checks ACK value each time it Espressif Systems 1021 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) sends a byte. When ack_check_en (master) is 0, I2C master does not check ACK value and take I2C slave as a matching slave by default. • Match: If the received ACK value matches ack_exp (master) (the expected ACK value), I2C master continues data transfer. • Not match: If the received ACK value does not match ack_exp, I2C master generates an I2C_NACK_INT (master) interrupt and stops data transfer. 10. I2C slave receives the RX RAM address sent by I2C master and adds the offset. 11. I2C master sends data, and determines whether to check ACK value according to ack_check_en (master). 12. If data to be sent is larger than TX FIFO depth, TX RAM of I2C master may wrap around in FIFO mode. For details, please refer to Section 30.4.10. 13. If data to be received is larger than RX FIFO depth, you may enable clock stretching by setting I2C_SLAVE_SCL_STRETCH_EN (slave), and clearing I2C_RX_FULL_ACK_LEVEL to 0. When RX RAM is full, an I2C_SLAVE_STRETCH_INT (slave) interrupt is generated. In this way, I2C slave can hold SCL low, in exchange for more time to read data. After the software has finished reading, you can set I2C_SLAVE_STRETCH_INT_CLR (slave) to 1 to clear interrupt, and set I2C_SLAVE_SCL_STRETCH_CLR (slave) to release the SCL line. 14. After data transfer completes, I2C master executes the STOP command, and generates an I2C_TRANS_COMPLETE_INT (master) interrupt. 30.7.4 I2C master Writes to I2C slave with a 7-bit Address in Multiple Com- mand Sequences Espressif Systems 1022 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) 30.7.4.1 Introduction Figure 30.7-4. I2C master Writing to I2C slave with a 7-bit Address in Multiple Sequences Given that the I2C Controller RAM holds only the size of TX/RX FIFO depth, when data are too large to be processed, it is advised to transmit them in multiple command sequences. Each command sequence ends with an END command. When the controller executes this END command, SCL will be pulled low, and the software can refresh command sequence registers and the RAM for the next transfer. Figure 30.7-4 shows how I2C master writes to an I2C slave in two or three segments as an example. For the first segment, the CMD_Controller registers are configured as shown in Segment0. Once data in I2C master ’s RAM is ready and I2C_TRANS_START is set, I2C master initiates data transfer. After executing the END command, I2C master turns off the SCL clock and pulls SCL low to reserve the bus. Meanwhile, the controller generates an I2C_END_DETECT_INT interrupt. For the second segment, after detecting the I2C_END_DETECT_INT interrupt, the software refreshes the CMD_Controller registers, reloads the RAM, and clears this interrupt, as shown in Segment1. If cmd1 in the second segment is a STOP, then data is transmitted to I2C slave in two segments. I2C master resumes data transfer after I2C_TRANS_START is set, and terminates the transfer by sending a STOP bit. For the third segment, after the second data transfer finishes and an I2C_END_DETECT_INT is detected, the Espressif Systems 1023 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) CMD_Controller registers of I2C master are configured as shown in Segment2. Once I2C_TRANS_START is set, I2C master generates a STOP bit and terminates the transfer. Note that other I2C master s will not transact on the bus between two segments. The bus is only released after a STOP command is sent. The I2C controller can be reset by setting I2C_FSM_RST field at any time. This field will later be cleared automatically by hardware. 30.7.4.2 Configuration Example 1. Set I2C_MS_MODE (master) to 1, and I2C_MS_MODE (slave) to 0. 2. Write 1 to I2C_CONF_UPGATE (master) and I2C_CONF_UPGATE (slave) to synchronize registers. 3. Configure command registers of I2C master . Command registers op_code ack_value ack_exp ack_check_en byte_num I2C_COMMAND0 (master) RSTART — — — — I2C_COMMAND1 (master) WRITE ack_value ack_exp 1 N+1 I2C_COMMAND2 (master) END — — — — 4. Write the address of I2C slave and data to be sent to TX RAM of I2C master in either FIFO mode or non-FIFO mode according to Section 30.4.10. 5. Write the address of I2C slave to I2C_SLAVE_ADDR (slave) in I2C_SLAVE_ADDR_REG (slave) register. 6. Write 1 to I2C_CONF_UPGATE (master) and I2C_CONF_UPGATE (slave) to synchronize registers. 7. Write 1 to I2C_TRANS_START (master) and I2C_TRANS_START (slave) to start transfer. 8. I2C slave compares the slave address sent by I2C master with its own address in I2C_SLAVE_ADDR (slave). When ack_check_en (master) in I2C master ’s WRITE command is 1, I2C master checks ACK value each time it sends a byte. When ack_check_en (master) is 0, I2C master does not check ACK value and take I2C slave as a matching slave by default. • Match: If the received ACK value matches ack_exp (master) (the expected ACK value), I2C master continues data transfer. • Not match: If the received ACK value does not match ack_exp, I2C master generates an I2C_NACK_INT (master) interrupt and stops data transfer. 9. I2C master sends data, and checks ACK value or not according to ack_check_en (master). 10. After the I2C_END_DETECT_INT (master) interrupt is generated, set I2C_END_DETECT_INT_CLR (master) to 1 to clear this interrupt. 11. Update I2C master ’s command registers. Command registers op_code ack_value ack_exp ack_check_en byte_num I2C_COMMAND0 (master) WRITE ack_value ack_exp 1 M I2C_COMMAND1 (master) END/STOP — — — — 12. Write M bytes of data to be sent to TX RAM of I2C master in FIFO or non-FIFO mode. 13. Write 1 to I2C_TRANS_START (master) bit to start the transfer and repeat step 9. Espressif Systems 1024 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) 14. If the command is a STOP, I2C stops the transfer and generates an I2C_TRANS_COMPLETE_INT (master) interrupt. 15. If the command is an END, repeat step 10. 16. Update I2C master ’s command registers. Command registers of I2C master op_code ack_value ack_exp ack_check_en byte_num I2C_COMMAND1 (master) STOP — — — — 17. Write 1 to I2C_TRANS_START (master) bit to start transfer. 18. I2C master executes the STOP command and generates an I2C_TRANS_COMPLETE_INT (master) interrupt. 30.7.5 I2C master Reads I2C slave with a 7-bit Address in One Command Se- quence 30.7.5.1 Introduction Figure 30.7-5. I2C master Reading I2C slave with a 7-bit Address Figure 30.7-5 shows how I2C master reads N bytes of data from an I2C slave using 7-bit addressing. cmd1 is a WRITE command, and when this command is executed I2C master sends the address of I2C slave . The byte sent comprises a 7-bit I2C slave address and a R/W bit. When the R/W bit is 1, it indicates a READ operation. If the address of an I2C slave matches the sent address, this matching slave starts sending data to I2C master . I2C master generates acknowledgments according to ack_value defined in the READ command upon receiving a byte. As illustrated in Figure 30.7-5, I2C master executes two READ commands: it generates ACKs for (N-1) bytes of data in cmd2, and a NACK for the last byte of data in cmd 3. This configuration may be changed as required. Espressif Systems 1025 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) I2C master writes received data into the controller RAM from addr0, whose original content (the address of I2C slave and a R/W bit) is overwritten by byte0 marked red in Figure 30.7-5. 30.7.5.2 Configuration Example 1. Set I2C_MS_MODE (master) to 1, and I2C_MS_MODE (slave) to 0. 2. We recommend setting I2C_SLAVE_SCL_STRETCH_EN (slave) to 1, so that SCL can be held low for more processing time when I2C slave needs to send data. If this bit is not set, the software should write data to be sent to I2C slave ’s TX RAM before I2C master initiates the transfer. The configuration below is applicable to the scenario where I2C_SLAVE_SCL_STRETCH_EN (slave) is 1. 3. Write 1 to I2C_CONF_UPGATE (master) and I2C_CONF_UPGATE (slave) to synchronize registers. 4. Configure command registers of I2C master . Command registers of I2C master op_code ack_value ack_exp ack_check_en byte_num I2C_COMMAND0 (master) RSTART — — — — I2C_COMMAND1 (master) WRITE 0 0 1 1 I2C_COMMAND2 (master) READ 0 0 1 N-1 I2C_COMMAND3 (master) READ 1 0 1 1 I2C_COMMAND4 (master) STOP — — — — 5. Write the address of I2C slave to TX RAM of I2C master in either FIFO mode or non-FIFO mode according to Section 30.4.10. 6. Write the address of I2C slave to I2C_SLAVE_ADDR (slave) in I2C_SLAVE_ADDR_REG (slave) register. 7. Write 1 to I2C_CONF_UPGATE (master) and I2C_CONF_UPGATE (slave) to synchronize registers. 8. Write 1 to I2C_TRANS_START (master) bit to start I2C master ’s transfer. 9. Start I2C slave ’s transfer according to Section 30.4.14. 10. I2C slave compares the slave address sent by I2C master with its own address in I2C_SLAVE_ADDR (slave). When ack_check_en (master) in I2C master ’s WRITE command is 1, I2C master checks ACK value each time it sends a byte. When ack_check_en (master) is 0, I2C master does not check ACK value and take I2C slave as a matching slave by default. • Match: If the received ACK value matches ack_exp (master) (the expected ACK value), I2C master continues data transfer. • Not match: If the received ACK value does not match ack_exp, I2C master generates an I2C_NACK_INT (master) interrupt and stops data transfer. 11. After I2C_SLAVE_STRETCH_INT (slave) is generated, the I2C_STRETCH_CAUSE bit is 0. The address of I2C slave matches the address sent over SDA, and I2C slave needs to send data. 12. Write data to be sent to TX RAM of I2C slave in either FIFO mode or non-FIFO mode according to Section 30.4.10. 13. Set I2C_SLAVE_SCL_STRETCH_CLR (slave) to 1 to release SCL. 14. I2C slave sends data, and I2C master checks ACK value or not according to ack_check_en (master) in the READ command. Espressif Systems 1026 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) 15. If data to be read by I2C master is larger than the TX FIFO depth of I2C slave , an I2C_SLAVE_STRETCH_INT (slave) interrupt will be generated when TX RAM of I2C slave becomes empty. In this way, I2C slave can hold SCL low, so that software has more time to pad data in TX RAM of I2C slave and read data in RX RAM of I2C master . After software has finished reading, you can set I2C_SLAVE_STRETCH_INT_CLR (slave) to 1 to clear interrupt, and set I2C_SLAVE_SCL_STRETCH_CLR (slave) to release the SCL line. 16. After I2C master has received the last byte of data, set ack_value (master) to 1. I2C slave will stop the transfer once receiving the I2C_NACK_INT interrupt. 17. After data transfer completes, I2C master executes the STOP command, and generates an I2C_TRANS_COMPLETE_INT (master) interrupt. 30.7.6 I2C master Reads I2C slave with a 10-bit Address in One Command Sequence 30.7.6.1 Introduction Figure 30.7-6. I2C master Reading I2C slave with a 10-bit Address Figure 30.7-6 shows how I2C master reads data from an I2C slave using 10-bit addressing. Unlike 7-bit addressing, in 10-bit addressing the WRITE command of the I2C master is formed from two bytes, and correspondingly TX RAM of this master stores a 10-bit address of two bytes. The R/W bit in the first byte is 0, which indicates a WRITE operation. After a RSTART condition, I2C master sends the first byte of address again to read data from I2C slave , but the R/W bit is 1, which indicates a READ operation. The two address bytes can be configured as described in Section 30.7.2. 30.7.6.2 Configuration Example 1. Set I2C_MS_MODE (master) to 1, and I2C_MS_MODE (slave) to 0. Espressif Systems 1027 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) 2. We recommend setting I2C_SLAVE_SCL_STRETCH_EN (slave) to 1, so that SCL can be held low for more processing time when I2C slave needs to send data. If this bit is not set, the software should write data to be sent to I2C slave ’s TX RAM before I2C master initiates the transfer. The configuration below is applicable to a scenario where I2C_SLAVE_SCL_STRETCH_EN (slave) is 1. 3. Write 1 to I2C_CONF_UPGATE (master) and I2C_CONF_UPGATE (slave) to synchronize registers. 4. Configure command registers of I2C master . Command registers of I2C master op_code ack_value ack_exp ack_check_en byte_num I2C_COMMAND0 (master) RSTART — — — — I2C_COMMAND1 (master) WRITE 0 0 1 2 I2C_COMMAND2 (master) RSTART — — — — I2C_COMMAND3 (master) WRITE 0 0 1 1 I2C_COMMAND4 (master) READ 0 0 1 N-1 I2C_COMMAND5 (master) READ 1 0 1 1 I2C_COMMAND6 (master) STOP — — — — 5. Configure I2C_SLAVE_ADDR (slave) in I2C_SLAVE_ADDR_REG (slave) as I2C slave ’s 10-bit address, and set I2C_ADDR_10BIT_EN (slave) to 1 to enable 10-bit addressing. 6. Write the address of I2C slave and data to be sent to TX RAM of I2C master in either FIFO or non-FIFO mode. The first byte of address comprises ((0x78 | I2C_SLAVE_ADDR[9:8])«1) and a R/W bit, which is 1 and indicates a WRITE operation. The second byte of address is I2C_SLAVE_ADDR[7:0]. The third byte is ((0x78 | I2C_SLAVE_ADDR[9:8])«1) and a R/W bit, which is 1 and indicates a READ operation. 7. Write 1 to I2C_CONF_UPGATE (master) and I2C_CONF_UPGATE (slave) to synchronize registers. 8. Write 1 to I2C_TRANS_START (master) to start I2C master ’s transfer. 9. Start I2C slave ’s transfer according to Section 30.4.14. 10. I2C slave compares the slave address sent by I2C master with its own address in I2C_SLAVE_ADDR (slave). When ack_check_en (master) in I2C master ’s WRITE command is 1, I2C master checks ACK value each time it sends a byte. When ack_check_en (master) is 0, I2C master does not check ACK value and take I2C slave as a matching slave by default. • Match: If the received ACK value matches ack_exp (master) (the expected ACK value), I2C master continues data transfer. • Not match: If the received ACK value does not match ack_exp, I2C master generates an I2C_NACK_INT (master) interrupt and stops data transfer. 11. I2C master sends a RSTART and the third byte in TX RAM, which is ((0x78 | I2C_SLAVE_ADDR[9:8])«1) and a R/W bit that indicates READ. 12. I2C slave repeats step 10. If its address matches the address sent by I2C master , I2C slave proceed on to the next steps. 13. After I2C_SLAVE_STRETCH_INT (slave) is generated, the I2C_STRETCH_CAUSE bit is 0. The address of I2C slave matches the address sent over SDA, and I2C slave needs to send data. 14. Write data to be sent to TX RAM of I2C slave in either FIFO mode or non-FIFO mode according to Section 30.4.10. Espressif Systems 1028 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) 15. Set I2C_SLAVE_SCL_STRETCH_CLR (slave) to 1 to release SCL. 16. I2C slave sends data, and I2C master checks ACK value or not according to ack_check_en (master) in the READ command. 17. If data to be read by I2C master is larger than the TX FIFO depth of I2C slave , an I2C_SLAVE_STRETCH_INT (slave) interrupt will be generated when TX RAM of I2C slave becomes empty. In this way, I2C slave can hold SCL low, so that software has more time to pad data in TX RAM of I2C slave and read data in RX RAM of I2C master . After the software has finished reading, you can set I2C_SLAVE_STRETCH_INT_CLR (slave) to 1 to clear interrupt, and set I2C_SLAVE_SCL_STRETCH_CLR (slave) to release the SCL line. 18. After I2C master has received the last byte of data, set ack_value (master) to 1. I2C slave will stop transfer once receiving the I2C_NACK_INT interrupt. 19. After data transfer completes, I2C master executes the STOP command, and generates an I2C_TRANS_COMPLETE_INT (master) interrupt. 30.7.7 I2C master Reads I2C slave with Two 7-bit Addresses in One Com- mand Sequence 30.7.7.1 Introduction Figure 30.7-7. I2C master Reading N Bytes of Data from addrM of I2C slave with a 7-bit Address Figure 30.7-7 shows how I2C master reads data from specified addresses in an I2C slave. I2C master sends two bytes of addresses: the first byte is a 7-bit I2C slave address followed by a R/W bit, which is 0 and indicates a WRITE; the second byte is I2C slave ’s memory address. After a RSTART condition, I2C master sends the first byte of address again, but the R/W bit is 1 which indicates a READ. Then, I2C master reads data starting from addrM. Espressif Systems 1029 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) 30.7.7.2 Configuration Example 1. Set I2C_MS_MODE (master) to 1, and I2C_MS_MODE (slave) to 0. 2. We recommend setting I2C_SLAVE_SCL_STRETCH_EN (slave) to 1, so that SCL can be held low for more processing time when I2C slave needs to send data. If this bit is not set, the software should write data to be sent to I2C slave ’s TX RAM before I2C master initiates the transfer. The configuration below is applicable to the scenario where I2C_SLAVE_SCL_STRETCH_EN (slave) is 1. 3. Set I2C_FIFO_ADDR_CFG_EN (slave) to 1 to enable dual address mode. 4. Write 1 to I2C_CONF_UPGATE (master) and I2C_CONF_UPGATE (slave) to synchronize registers. 5. Configure command registers of I2C master . Command registers of I2C master op_code ack_value ack_exp ack_check_en byte_num I2C_COMMAND0 (master) RSTART — — — — I2C_COMMAND1 (master) WRITE 0 0 1 2 I2C_COMMAND2 (master) RSTART — — — — I2C_COMMAND3 (master) WRITE 0 0 1 1 I2C_COMMAND4 (master) READ 0 0 1 N-1 I2C_COMMAND5 (master) READ 1 0 1 1 I2C_COMMAND6 (master) STOP — — — — 6. Configure I2C_SLAVE_ADDR (slave) in I2C_SLAVE_ADDR_REG (slave) register as I2C slave ’s 7-bit address, and set I2C_ADDR_10BIT_EN (slave) to 0 to enable 7-bit addressing. 7. Write the address of I2C slave and data to be sent to TX RAM of I2C master in either FIFO or non-FIFO mode according to Section 30.4.10. The first byte of address comprises ( I2C_SLAVE_ADDR[6:0])«1) and a R/W bit, which is 0 and indicates a WRITE. The second byte of the address is memory address M of I2C slave . The third byte is ( I2C_SLAVE_ADDR[6:0])«1) and a R/W bit, which is 1 and indicates a READ. 8. Write 1 to I2C_CONF_UPGATE (master) and I2C_CONF_UPGATE (slave) to synchronize registers. 9. Write 1 to I2C_TRANS_START (master) to start I2C master ’s transfer. 10. Start I2C slave ’s transfer according to Section 30.4.14. 11. I2C slave compares the slave address sent by I2C master with its own address in I2C_SLAVE_ADDR (slave). When ack_check_en (master) in I2C master ’s WRITE command is 1, I2C master checks ACK value each time it sends a byte. When ack_check_en (master) is 0, I2C master does not check ACK value and takes I2C slave as a matching slave by default. • Match: If the received ACK value matches ack_exp (master) (the expected ACK value), I2C master continues data transfer. • Not match: If the received ACK value does not match ack_exp, I2C master generates an I2C_NACK_INT (master) interrupt and stops data transfer. 12. I2C slave receives memory address sent by I2C master and adds the offset. 13. I2C master sends a RSTART and the third byte in TX RAM, which is ((0x78 | I2C_SLAVE_ADDR[9:8])«1) and a R bit. Espressif Systems 1030 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) 14. I2C slave repeats step 11. If its address matches the address sent by I2C master , I2C slave proceed on to the next steps. 15. After I2C_SLAVE_STRETCH_INT (slave) is generated, the I2C_STRETCH_CAUSE bit is 0. The address of I2C slave matches the address sent over SDA, and I2C slave needs to send data. 16. Write data to be sent to TX RAM of I2C slave in either FIFO mode or non-FIFO mode according to Section 30.4.10. 17. Set I2C_SLAVE_SCL_STRETCH_CLR (slave) to 1 to release SCL. 18. I2C slave sends data, and I2C master checks ACK value or not according to ack_check_en (master) in the READ command. 19. If data to be read by I2C master is larger than the TX FIFO depth of I2C slave , an I2C_SLAVE_STRETCH_INT (slave) interrupt will be generated when TX RAM of I2C slave becomes empty. In this way, I2C slave can hold SCL low, so that software has more time to pad data in TX RAM of I2C slave and read data in RX RAM of I2C master . After software has finished reading, you can set I2C_SLAVE_STRETCH_INT_CLR (slave) to 1 to clear interrupt, and set I2C_SLAVE_SCL_STRETCH_CLR (slave) to release the SCL line. 20. After I2C master has received the last byte of data, set ack_value (master) to 1. I2C slave will stop transfer once receiving the I2C_NACK_INT interrupt. 21. After data transfer completes, I2C master executes the STOP command, and generates an I2C_TRANS_COMPLETE_INT (master) interrupt. 30.7.8 I2C master Reads I2C slave with a 7-bit Address in Multiple Command Sequences Espressif Systems 1031 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) 30.7.8.1 Introduction Figure 30.7-8. I2C master Reading I2C slave with a 7-bit Address in Segments Figure 30.7-8 shows how I2C master reads (N+M) bytes of data from an I2C slave in two/three segments separated by END commands. Configuration procedures are described as follows: 1. The procedures for Segment0 is similar to 30.7-5, except that the last command is an END. 2. Prepare data in the TX RAM of I2C slave , and set I2C_TRANS_START to start data transfer. After executing the END command, I2C master refreshes command registers and the RAM as shown in Segment1, and clears the corresponding I2C_END_DETECT_INT interrupt. If cmd2 in Segment1 is a STOP, then data is read from I2C slave in two segments. I2C master resumes data transfer by setting I2C_TRANS_START and terminates the transfer by sending a STOP bit. 3. If cmd2 in Segment1 is an END, then data is read from I2C slave in three segments. After the second data Espressif Systems 1032 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) transfer finishes and an I2C_END_DETECT_INT interrupt is detected, the cmd box is configured as shown in Segment2. Once I2C_TRANS_START is set, I2C master terminates the transfer by sending a STOP bit. 30.7.8.2 Configuration Example 1. Set I2C_MS_MODE (master) to 1, and I2C_MS_MODE (slave) to 0. 2. We recommend setting I2C_SLAVE_SCL_STRETCH_EN (slave) to 1, so that SCL can be held low for more processing time when I2C slave needs to send data. If this bit is not set, the software should write data to be sent to I2C slave ’s TX RAM before I2C master initiates the transfer. The configuration below is applicable to a scenario where I2C_SLAVE_SCL_STRETCH_EN (slave) is 1. 3. Write 1 to I2C_CONF_UPGATE (master) and I2C_CONF_UPGATE (slave) to synchronize registers. 4. Configure command registers of I2C master . Command registers of I2C master op_code ack_value ack_exp ack_check_en byte_num I2C_COMMAND0 (master) RSTART — — — — I2C_COMMAND1 (master) WRITE 0 0 1 1 I2C_COMMAND2 (master) READ 0 0 1 N I2C_COMMAND3 (master) END — — — — 5. Write the address of I2C slave to TX RAM of I2C master in FIFO or non-FIFO mode. 6. Write the address of I2C slave to I2C_SLAVE_ADDR (slave) in I2C_SLAVE_ADDR_REG (slave) register. 7. Write 1 to I2C_CONF_UPGATE (master) and I2C_CONF_UPGATE (slave) to synchronize registers. 8. Write 1 to I2C_TRANS_START (master) to start I2C master ’s transfer. 9. Start I2C slave ’s transfer according to Section 30.4.14. 10. I2C slave compares the slave address sent by I2C master with its own address in I2C_SLAVE_ADDR (slave). When ack_check_en (master) in I2C master ’s WRITE command is 1, I2C master checks ACK value each time it sends a byte. When ack_check_en (master) is 0, I2C master does not check the ACK value and takes I2C slave as a matching slave by default. • Match: If the received ACK value matches ack_exp (master) (the expected ACK value), I2C master continues data transfer. • Not match: If the received ACK value does not match ack_exp, I2C master generates an I2C_NACK_INT (master) interrupt and stops data transfer. 11. After I2C_SLAVE_STRETCH_INT (slave) is generated, the I2C_STRETCH_CAUSE bit is 0. The address of I2C slave matches the address sent over SDA, and I2C slave needs to send data. 12. Write data to be sent to TX RAM of I2C slave in either FIFO mode or non-FIFO mode according to Section 30.4.10. 13. Set I2C_SLAVE_SCL_STRETCH_CLR (slave) to 1 to release SCL. 14. I2C slave sends data, and I2C master checks ACK value or not according to ack_check_en (master) in the READ command. 15. If data to be read by I2C master in one READ command (N or M) is larger than the TX FIFO depth of I2C slave , an I2C_SLAVE_STRETCH_INT (slave) interrupt will be generated when TX RAM of I2C slave becomes empty. Espressif Systems 1033 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) In this way, I2C slave can hold SCL low so that software has more time to pad data in TX RAM of I2C slave and read data in RX RAM of I2C master . After the software has finished reading, you can set I2C_SLAVE_STRETCH_INT_CLR (slave) to 1 to clear interrupt, and set I2C_SLAVE_SCL_STRETCH_CLR (slave) to release the SCL line. 16. Once finishing reading data in the first READ command, I2C master executes the END command and triggers an I2C_END_DETECT_INT (master) interrupt, which is cleared by setting I2C_END_DETECT_INT_CLR (master) to 1. 17. Update I2C master ’s command registers using one of the following two methods: Command registers of I2C master op_code ack_value ack_exp ack_check_en byte_num I2C_COMMAND0 (master) READ ack_value ack_exp 1 M I2C_COMMAND1 (master) END — — — — Or Command registers of I2C master op_code ack_value ack_exp ack_check_en byte_num I2C_COMMAND0 (master) READ 0 0 1 M-1 I2C_COMMAND0 (master) READ 1 0 1 1 I2C_COMMAND1 (master) STOP — — — — 18. Write M bytes of data to be sent to TX RAM of I2C slave . If M is larger than the TX FIFO depth, then repeat step 12 in FIFO or non-FIFO mode. 19. Write 1 to I2C_TRANS_START (master) bit to start the transfer and repeat step 14. 20. If the last command is a STOP, then set ack_value (master) to 1 after I2C master has received the last byte of data. I2C slave stops transfer upon the I2C_NACK_INT interrupt. I2C master executes the STOP command to stop the transfer and generates an I2C_TRANS_COMPLETE_INT (master) interrupt. 21. If the last command is an END, then repeat step 16 and proceed on to the next steps. 22. Update I2C master ’s command registers. Command registers of I2C master op_code ack_value ack_exp ack_check_en byte_num I2C_COMMAND1 (master) STOP — — — — 23. Write 1 to I2C_TRANS_START (master) bit to start transfer. 24. I2C master executes the STOP command to stop transfer, and generates an I2C_TRANS_COMPLETE_INT (master) interrupt. Espressif Systems 1034 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) 30.8 Register Summary 30.8.1 I2C Register Summary The addresses in this section are relative to the I2C Controller base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Timing registers I2C_SCL_LOW_PERIOD_REG Configures the low level width of the SCL Clock 0x0000 R/W I2C_SDA_HOLD_REG Configures the hold time after a negative SCL edge 0x0030 R/W I2C_SDA_SAMPLE_REG Configures the sample time after a positive SCL edge 0x0034 R/W I2C_SCL_HIGH_PERIOD_REG Configures the high level width of SCL 0x0038 R/W I2C_SCL_START_HOLD_REG Configures the delay between the SDA and SCL negative edge for a start condition 0x0040 R/W I2C_SCL_RSTART_SETUP_REG Configures the delay between the positive edge of SCL and the negative edge of SDA 0x0044 R/W I2C_SCL_STOP_HOLD_REG Configures the delay after the SCL clock edge for a stop condition 0x0048 R/W I2C_SCL_STOP_SETUP_REG Configures the delay between the SDA and SCL rising edge for a stop condition Measure- ment unit: i2c_sclk 0x004C R/W I2C_SCL_ST_TIME_OUT_REG SCL status time out register 0x0078 R/W I2C_SCL_MAIN_ST_TIME_OUT_REG SCL main status time out register 0x007C R/W Configuration registers I2C_CTR_REG Transmission setting 0x0004 varies I2C_TO_REG Setting time out control for receiving data 0x000C R/W I2C_SLAVE_ADDR_REG Local slave address setting 0x0010 R/W I2C_FIFO_CONF_REG FIFO configuration register 0x0018 R/W I2C_FILTER_CFG_REG SCL and SDA filter configuration register 0x0050 R/W I2C_SCL_SP_CONF_REG Power configuration register 0x0080 varies I2C_SCL_STRETCH_CONF_REG Set SCL stretch of I2C slave 0x0084 varies Status registers I2C_SR_REG Describe I2C work status 0x0008 RO I2C_FIFO_ST_REG FIFO status register 0x0014 RO I2C_DATA_REG Rx FIFO read data 0x001C HRO Interrupt registers I2C_INT_RAW_REG Raw interrupt status 0x0020 R/SS WTC I2C_INT_CLR_REG Interrupt clear bits 0x0024 WT I2C_INT_ENA_REG Interrupt enable bits 0x0028 R/W Espressif Systems 1035 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Name Description Address Access I2C_INT_STATUS_REG Status of captured I2C communication events 0x002C RO Command registers I2C_COMD0_REG I2C command register 0 0x0058 varies I2C_COMD1_REG I2C command register 1 0x005C varies I2C_COMD2_REG I2C command register 2 0x0060 varies I2C_COMD3_REG I2C command register 3 0x0064 varies I2C_COMD4_REG I2C command register 4 0x0068 varies I2C_COMD5_REG I2C command register 5 0x006C varies I2C_COMD6_REG I2C command register 6 0x0070 varies I2C_COMD7_REG I2C command register 7 0x0074 varies Version register I2C_DATE_REG Version register 0x00F8 R/W Address register I2C_TXFIFO_START_ADDR_REG I2C TX FIFO base address register 0x0100 HRO I2C_RXFIFO_START_ADDR_REG I2C RX FIFO base address register 0x0180 HRO 30.8.2 LP_I2C Register Summary The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Timing Registers LP_I2C_SCL_LOW_PERIOD_REG Configures the low level width of the SCL Clock 0x0000 R/W LP_I2C_SDA_HOLD_REG Configures the hold time after a negative SCL edge 0x0030 R/W LP_I2C_SDA_SAMPLE_REG Configures the sample time after a positive SCL edge 0x0034 R/W LP_I2C_SCL_HIGH_PERIOD_REG Configures the high level width of SCL 0x0038 R/W LP_I2C_SCL_START_HOLD_REG Configures the delay between the SDA and SCL negative edge for a start condition 0x0040 R/W LP_I2C_SCL_RSTART_SETUP_REG Configures the delay between the positive edge of SCL and the negative edge of SDA 0x0044 R/W LP_I2C_SCL_STOP_HOLD_REG Configures the delay after the SCL clock edge for a stop condition 0x0048 R/W LP_I2C_SCL_STOP_SETUP_REG Configures the delay between the SDA and SCL positive edge for a stop condition 0x004C R/W LP_I2C_SCL_ST_TIME_OUT_REG SCL status time out register 0x0078 R/W LP_I2C_SCL_MAIN_ST_TIME_OUT_REG SCL main status time out register 0x007C R/W Configuration Registers LP_I2C_CTR_REG Transmission setting 0x0004 varies LP_I2C_TO_REG Setting time out control for receiving data 0x000C R/W LP_I2C_FIFO_CONF_REG FIFO configuration register 0x0018 R/W LP_I2C_FILTER_CFG_REG SCL and SDA filter configuration register 0x0050 R/W LP_I2C_SCL_SP_CONF_REG Power configuration register 0x0080 varies Espressif Systems 1036 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Name Description Address Access Status Registers LP_I2C_SR_REG Describe I2C work status 0x0008 RO LP_I2C_FIFO_ST_REG FIFO status register 0x0014 RO LP_I2C_DATA_REG Rx FIFO read data 0x001C RO Interrupt Registers LP_I2C_INT_RAW_REG Raw interrupt status 0x0020 R/SS WTC LP_I2C_INT_CLR_REG Interrupt clear bits 0x0024 WT LP_I2C_INT_ENA_REG Interrupt enable bits 0x0028 R/W LP_I2C_INT_STATUS_REG Status of captured I2C communication events 0x002C RO Command Registers LP_I2C_COMD0_REG I2C command register 0 0x0058 varies LP_I2C_COMD1_REG I2C command register 1 0x005C varies LP_I2C_COMD2_REG I2C command register 2 0x0060 varies LP_I2C_COMD3_REG I2C command register 3 0x0064 varies LP_I2C_COMD4_REG I2C command register 4 0x0068 varies LP_I2C_COMD5_REG I2C command register 5 0x006C varies LP_I2C_COMD6_REG I2C command register 6 0x0070 varies LP_I2C_COMD7_REG I2C command register 7 0x0074 varies Version Register LP_I2C_DATE_REG Version register 0x00F8 R/W Address Registers LP_I2C_TXFIFO_START_ADDR_REG I2C TXFIFO base address register 0x0100 HRO LP_I2C_RXFIFO_START_ADDR_REG I2C RXFIFO base address register 0x0180 HRO Espressif Systems 1037 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) 30.9 Registers 30.9.1 I2C Registers The addresses in this section are relative to the I2C Controller base address provided in Table 4.3-2 in Chapter 4 System and Memory. For how to program reserved fields, please refer to Section Programming Reserved Register Field. Register 30.1. I2C_SCL_LOW_PERIOD_REG (0x0000) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 9 I2C_SCL_LOW_PERIOD 0 8 0 Reset I2C_SCL_LOW_PERIOD Configures the low level width of the SCL clock in master mode. Measurement unit: I2C_SCLK clock cycles (R/W) Register 30.2. I2C_SDA_HOLD_REG (0x0030) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 9 I2C_SDA_HOLD_TIME 0 8 0 Reset I2C_SDA_HOLD_TIME Configures the time to hold the data after the falling edge of SCL. Measurement unit: I2C_SCLK clock cycles (R/W) Espressif Systems 1038 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.3. I2C_SDA_SAMPLE_REG (0x0034) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 9 I2C_SDA_SAMPLE_TIME 0 8 0 Reset I2C_SDA_SAMPLE_TIME Configures the time for sampling SDA. Measurement unit: I2C_SCLK clock cycles (R/W) Register 30.4. I2C_SCL_HIGH_PERIOD_REG (0x0038) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 I2C_SCL_WAIT_HIGH_PERIOD 0 15 9 I2C_SCL_HIGH_PERIOD 0 8 0 Reset I2C_SCL_HIGH_PERIOD Configures for how long SCL remains high in master mode. Measurement unit: I2C_SCLK clock cycles (R/W) I2C_SCL_WAIT_HIGH_PERIOD Configures the SCL_FSM’s waiting period for SCL high level in mas- ter mode. Measurement unit: I2C_SCLK clock cycles (R/W) Espressif Systems 1039 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.5. I2C_SCL_START_HOLD_REG (0x0040) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 9 I2C_SCL_START_HOLD_TIME 8 8 0 Reset I2C_SCL_START_HOLD_TIME Configures the time between the falling edge of SDA and the falling edge of SCL for a START condition. Measurement unit: I2C_SCLK clock cycles (R/W) Register 30.6. I2C_SCL_RSTART_SETUP_REG (0x0044) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 9 I2C_SCL_RSTART_SETUP_TIME 8 8 0 Reset I2C_SCL_RSTART_SETUP_TIME Configures the time between the rising edge of SCL and the neg- ative edge of SDA for a RESTART condition. Measurement unit: I2C_SCLK clock cycles (R/W) Register 30.7. I2C_SCL_STOP_HOLD_REG (0x0048) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 9 I2C_SCL_STOP_HOLD_TIME 8 8 0 Reset I2C_SCL_STOP_HOLD_TIME Configures the delay after the STOP condition. Measurement unit: I2C_SCLK clock cycles (R/W) Espressif Systems 1040 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.8. I2C_SCL_STOP_SETUP_REG (0x004C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 9 I2C_SCL_STOP_SETUP_TIME 8 8 0 Reset I2C_SCL_STOP_SETUP_TIME Configures the time between the rising edge of SCL and the rising edge of SDA. Measurement unit: I2C_SCLK clock cycles (R/W) Register 30.9. I2C_SCL_ST_TIME_OUT_REG (0x0078) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 5 I2C_SCL_ST_TO_I2C 0x10 4 0 Reset I2C_SCL_ST_TO_I2C Configures the threshold value of SCL_FSM state unchanged period. It should be no more than 23. The actual period is 2^(reg_time_out_value+1). Measurement unit: I2C_SCLK clock cycles (R/W) Register 30.10. I2C_SCL_MAIN_ST_TIME_OUT_REG (0x007C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 5 I2C_SCL_MAIN_ST_TO_I2C 0x10 4 0 Reset I2C_SCL_MAIN_ST_TO_I2C Configures the threshold value of SCL_MAIN_FSM state unchanged period. It should be no more than 23. The actual period is 2^(I2C_SCL_MAIN_ST_TO_I2C+1). Measurement unit: I2C_SCLK clock cycles (R/W) Espressif Systems 1041 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.11. I2C_CTR_REG (0x0004) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 15 I2C_ADDR_BROADCASTING_EN 0 14 I2C_ADDR_10BIT_RW_CHECK_EN 0 13 I2C_SLV_TX_AUTO_START_EN 0 12 I2C_CONF_UPGATE 0 11 I2C_FSM_RST 0 10 I2C_ARBITRATION_EN 1 9 I2C_CLK_EN 0 8 I2C_RX_LSB_FIRST 0 7 I2C_TX_LSB_FIRST 0 6 I2C_TRANS_START 0 5 I2C_MS_MODE 0 4 I2C_RX_FULL_ACK_LEVEL 1 3 I2C_SAMPLE_SCL_LEVEL 0 2 I2C_SCL_FORCE_OUT 0 1 I2C_SDA_FORCE_OUT 0 0 Reset I2C_SDA_FORCE_OUT Configures the SDA output mode. 0: Open drain output 1: Direct output (R/W) I2C_SCL_FORCE_OUT Configures the SCL output mode. 0: Open drain output 1: Direct output (R/W) I2C_SAMPLE_SCL_LEVEL Configures the sample mode for SDA. 0: Sample SDA data on the SCL high level 1: Sample SDA data on the SCL low level (R/W) I2C_RX_FULL_ACK_LEVEL Configures the ACK value that needs to be sent by the master when the received RX RAM has reached the threshold. (R/W) I2C_MS_MODE Configures the module as an I2C Master or Slave. 0: Slave 1: Master (R/W) I2C_TRANS_START Configures whether the slave starts sending the data in TX FIFO. 0: No effect 1: Start (WT) I2C_TX_LSB_FIRST Configures to control the sending order for data needing to be sent. 0: send data from the most significant bit 1: send data from the least significant bit (R/W) I2C_RX_LSB_FIRST Configures to control the storage order for received data. 0: receive data from the most significant bit 1: receive data from the least significant bit (R/W) Continued on the next page... Espressif Systems 1042 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.11. I2C_CTR_REG (0x0004) Continued from the previous page... I2C_CLK_EN Configures whether to gate clock signal for registers. 0: Support clock only when registers are read or written to by software 1: Force clock on for registers (R/W) I2C_ARBITRATION_EN Configures to enable I2C bus arbitration detection. 0: No effect 1: Enable (R/W) I2C_FSM_RST Configures to reset the SCL_FSM. 0: No effect 1: Reset (WT) I2C_CONF_UPGATE Configures this bit for synchronization. 0: No effect 1: Synchronize (WT) I2C_SLV_TX_AUTO_START_EN Configures to enable slave to send data automatically 0: Disable 1: Enable (R/W) I2C_ADDR_10BIT_RW_CHECK_EN Configures to check if the R/W bit of 10-bit addressing consists with I2C protocol. 0: Not check 1: Check (R/W) I2C_ADDR_BROADCASTING_EN Configures to support the 7-bit general call function. 0: Not support 1: Support (R/W) Espressif Systems 1043 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.12. I2C_TO_REG (0x000C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 6 I2C_TIME_OUT_EN 0 5 I2C_TIME_OUT_VALUE 0x10 4 0 Reset I2C_TIME_OUT_VALUE Configures the timeout threshold period for SCL stuck at high or low level. The actual period is 2^(I2C_TIME_OUT_VALUE+1). Measurement unit: I2C_SCLK clock cycles (R/W) I2C_TIME_OUT_EN Configures to enable time out control. 0: No effect 1: Enable (R/W) Register 30.13. I2C_SLAVE_ADDR_REG (0x0010) I2C_ADDR_10BIT_EN 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 15 I2C_SLAVE_ADDR 0 14 0 Reset I2C_SLAVE_ADDR Configure the slave address of I2C Slave. (R/W) I2C_ADDR_10BIT_EN Configures to enable the slave 10-bit addressing mode in master mode. 0: No effect 1: Enable (R/W) Espressif Systems 1044 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.14. I2C_FIFO_CONF_REG (0x0018) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 15 I2C_FIFO_PRT_EN 1 14 I2C_TX_FIFO_RST 0 13 I2C_RX_FIFO_RST 0 12 I2C_FIFO_ADDR_CFG_EN 0 11 I2C_NONFIFO_EN 0 10 I2C_TXFIFO_WM_THRHD 0x4 9 5 I2C_RXFIFO_WM_THRHD 0xb 4 0 Reset I2C_RXFIFO_WM_THRHD Configures the watermark threshold of RX FIFO in non-FIFO ac- cess mode. When I2C_FIFO_PRT_EN is 1 and RX FIFO counter is bigger than I2C_RXFIFO_WM_THRHD[4:0], I2C_RXFIFO_WM_INT_RAW bit will be valid. (R/W) I2C_TXFIFO_WM_THRHD Configures the watermark threshold of TX FIFO in non-FIFO access mode. When I2C_FIFO_PRT_EN is 1 and TC FIFO counter is bigger than I2C_TXFIFO_WM_THRHD[4:0], I2C_TXFIFO_WM_INT_RAW bit will be valid. (R/W) I2C_NONFIFO_EN Configures to enable APB non-FIFO access. (R/W) I2C_FIFO_ADDR_CFG_EN Configures the slave to enable dual address mode. When this mode is enabled, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM. 0: Disable 1: Enable (R/W) I2C_RX_FIFO_RST Configures to reset RX FIFO. 0: No effect 1: Reset (R/W) I2C_TX_FIFO_RST Configures to reset TX FIFO. 0: No effect 1: Reset (R/W) I2C_FIFO_PRT_EN Configures to enable FIFO pointer in non-FIFO access mode. This bit controls the valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts. 0: No effect 1: Enable (R/W) Espressif Systems 1045 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.15. I2C_FILTER_CFG_REG (0x0050) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 10 I2C_SDA_FILTER_EN 1 9 I2C_SCL_FILTER_EN 1 8 I2C_SDA_FILTER_THRES 0 7 4 I2C_SCL_FILTER_THRES 0 3 0 Reset I2C_SCL_FILTER_THRES Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL input has smaller width than this register value, the I2C controller will ignore that pulse. Measurement unit: I2C_SCLK clock cycles (R/W) I2C_SDA_FILTER_THRES Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA input has smaller width than this register value, the I2C controller will ignore that pulse. Measurement unit: I2C_SCLK clock cycles (R/W) I2C_SCL_FILTER_EN Configures to enable the filter function for SCL. 0: No effect 1: Enable (R/W) I2C_SDA_FILTER_EN Configures to enable the filter function for SDA. 0: No effect 1: Enable (R/W) Espressif Systems 1046 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.16. I2C_SCL_SP_CONF_REG (0x0080) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 I2C_SDA_PD_EN 0 7 I2C_SCL_PD_EN 0 6 I2C_SCL_RST_SLV_NUM 0 5 1 I2C_SCL_RST_SLV_EN 0 0 Reset I2C_SCL_RST_SLV_EN Configures to send out SCL pulses when I2C master is IDLE. The number of pulses equals to I2C_SCL_RST_SLV_NUM. 0: Invalid 1: Send out SCL pulses (R/W/SC) I2C_SCL_RST_SLV_NUM Configure the pulses of SCL generated in I2C master mode. Valid when I2C_SCL_RST_SLV_EN is 1. Measurement unit: I2C_SCLK clock cycles (R/W) I2C_SCL_PD_EN Configures to power down the I2C output SCL line. 0: Not power down. 1: Not work and power down. Valid only when I2C_SCL_FORCE_OUT is 1. (R/W) I2C_SDA_PD_EN Configures to power down the I2C output SDA line. 0: Not power down. 1: Not work and power down. Valid only when I2C_SDA_FORCE_OUT is 1. (R/W) Espressif Systems 1047 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.17. I2C_SCL_STRETCH_CONF_REG (0x0084) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 14 I2C_SLAVE_BYTE_ACK_LVL 0 13 I2C_SLAVE_BYTE_ACK_CTL_EN 0 12 I2C_SLAVE_SCL_STRETCH_CLR 0 11 I2C_SLAVE_SCL_STRETCH_EN 0 10 I2C_STRETCH_PROTECT_NUM 0 9 0 Reset I2C_STRETCH_PROTECT_NUM Configures the time period to release the SCL line from stretching to avoid timing violation. Usually it should be larger than the SDA setup time. Measurement unit: I2C_SCLK clock cycles (R/W) I2C_SLAVE_SCL_STRETCH_EN Configures to enable slave SCL stretch function. The SCL output line will be stretched low when I2C_SLAVE_SCL_STRETCH_EN is 1 and a stretch event happens. The stretch cause can be seen in I2C_STRETCH_CAUSE. 0: Disable 1: Enable (R/W) I2C_SLAVE_SCL_STRETCH_CLR Configures to clear the I2C slave SCL stretch function. 0: No effect 1: Clear (WT) I2C_SLAVE_BYTE_ACK_CTL_EN Configures to enable the function for the slave to control ACK level. 0: Disable 1: Enable (R/W) I2C_SLAVE_BYTE_ACK_LVL Configures the ACK level when slave controlling ACK level function is enabled. 0: Low level 1: High level (R/W) Espressif Systems 1048 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.18. I2C_SR_REG (0x0008) (reserved) 0 31 I2C_SCL_STATE_LAST 0 30 28 (reserved) 0 27 I2C_SCL_MAIN_STATE_LAST 0 26 24 I2C_TXFIFO_CNT 0 23 18 (reserved) 0 0 17 16 I2C_STRETCH_CAUSE 0x3 15 14 I2C_RXFIFO_CNT 0 13 8 (reserved) 0 0 7 6 I2C_SLAVE_ADDRESSED 0 5 I2C_BUS_BUSY 0 4 I2C_ARB_LOST 0 3 (reserved) 0 2 I2C_SLAVE_RW 0 1 I2C_RESP_REC 0 0 Reset I2C_RESP_REC Represents the received ACK value in master mode or slave mode. 0: ACK 1: NACK (RO) I2C_SLAVE_RW Represents the transfer direction in slave mode. 0: Master writes to slave 1: Master reads from slave (RO) I2C_ARB_LOST Represents whether the I2C controller loses control of SCL line. 0: No arbitration lost 1: Arbitration lost (RO) I2C_BUS_BUSY Represents the I2C bus state. 0: The I2C bus is in an idle state. 1: The I2C bus is busy transferring data (RO) I2C_SLAVE_ADDRESSED Represents whether the address sent by the master is equal to the ad- dress of the slave. Valid only when the module is configured as an I2C Slave. 0: Not equal 1: Equal (RO) I2C_RXFIFO_CNT Represents the number of data bytes received in RAM. (RO) I2C_STRETCH_CAUSE Represents the cause of SCL clocking stretching in slave mode. 0: Stretching SCL low when the master starts to read data. 1: Stretching SCL low when I2C TX FIFO is empty in slave mode. 2: Stretching SCL low when I2C RX FIFO is full in slave mode. 3: Invalid (RO) I2C_TXFIFO_CNT Represents the number of data bytes to be sent. (RO) Continued on the next page... Espressif Systems 1049 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.18. I2C_SR_REG (0x0008) Continued from the previous page... I2C_SCL_MAIN_STATE_LAST Represents the states of the I2C module state machine. 0: Idle 1: Address shift 2: ACK address 3: Rx data 4: Tx data 5: Send ACK 6: Wait ACK 7: Invalid (RO) I2C_SCL_STATE_LAST Represents the states of the state machine used to produce SCL. 0: Idle 1: Start 2: Negative edge 3: Low 4: rising edge 5: High 6: Stop 7: Invalid (RO) Register 30.19. I2C_FIFO_ST_REG (0x0014) (reserved) 0 0 31 30 I2C_SLAVE_RW_POINT 0 29 22 (reserved) 0 0 21 20 I2C_TXFIFO_WADDR 0 19 15 I2C_TXFIFO_RADDR 0 14 10 I2C_RXFIFO_WADDR 0 9 5 I2C_RXFIFO_RADDR 0 4 0 Reset I2C_RXFIFO_RADDR Represents the offset address of the APB reading from RX FIFO. (RO) I2C_RXFIFO_WADDR Represents the offset address of the I2C module receiving data and writing to RX FIFO. (RO) I2C_TXFIFO_RADDR Represents the offset address of the I2C module reading from TX FIFO. (RO) I2C_TXFIFO_WADDR Represents the offset address of the APB bus writing to TX FIFO. (RO) I2C_SLAVE_RW_POINT Represents the offset address in the I2C Slave RAM addressed by I2C Mas- ter when in I2C slave mode. (RO) Espressif Systems 1050 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.20. I2C_DATA_REG (0x001C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 I2C_FIFO_RDATA 0 7 0 Reset I2C_FIFO_RDATA Represents the value of RX FIFO read data. (RO) Register 30.21. I2C_INT_RAW_REG (0x0020) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 31 19 I2C_SLAVE_ADDR_UNMATCH_INT_RAW 0 18 I2C_GENERAL_CALL_INT_RAW 0 17 I2C_SLAVE_STRETCH_INT_RAW 0 16 I2C_DET_START_INT_RAW 0 15 I2C_SCL_MAIN_ST_TO_INT_RAW 0 14 I2C_SCL_ST_TO_INT_RAW 0 13 I2C_RXFIFO_UDF_INT_RAW 0 12 I2C_TXFIFO_OVF_INT_RAW 0 11 I2C_NACK_INT_RAW 0 10 I2C_TRANS_START_INT_RAW 0 9 I2C_TIME_OUT_INT_RAW 0 8 I2C_TRANS_COMPLETE_INT_RAW 0 7 I2C_MST_TXFIFO_UDF_INT_RAW 0 6 I2C_ARBITRATION_LOST_INT_RAW 0 5 I2C_BYTE_TRANS_DONE_INT_RAW 0 4 I2C_END_DETECT_INT_RAW 0 3 I2C_RXFIFO_OVF_INT_RAW 0 2 I2C_TXFIFO_WM_INT_RAW 1 1 I2C_RXFIFO_WM_INT_RAW 0 0 Reset I2C_RXFIFO_WM_INT_RAW The raw interrupt status of I2C_RXFIFO_WM_INT interrupt. (R/SS/WTC) I2C_TXFIFO_WM_INT_RAW The raw interrupt status of I2C_TXFIFO_WM_INT interrupt. (R/SS/WTC) I2C_RXFIFO_OVF_INT_RAW The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt. (R/SS/WTC) I2C_END_DETECT_INT_RAW The raw interrupt status of the I2C_END_DETECT_INT interrupt. (R/SS/WTC) I2C_BYTE_TRANS_DONE_INT_RAW The raw interrupt status of the I2C_BYTE_TRANS_DONE_INT interrupt. (R/SS/WTC) I2C_ARBITRATION_LOST_INT_RAW The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt. (R/SS/WTC) I2C_MST_TXFIFO_UDF_INT_RAW The raw interrupt status of I2C_MST_TXFIFO_UDF_INT inter- rupt. (R/SS/WTC) I2C_TRANS_COMPLETE_INT_RAW The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt. (R/SS/WTC) Continued on the next page... Espressif Systems 1051 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.21. I2C_INT_RAW_REG (0x0020) Continued from the previous page... I2C_TIME_OUT_INT_RAW The raw interrupt status of the I2C_TIME_OUT_INT interrupt. (R/SS/WTC) I2C_TRANS_START_INT_RAW The raw interrupt status of the I2C_TRANS_START_INT interrupt. (R/SS/WTC) I2C_NACK_INT_RAW The raw interrupt status of I2C_NACK_INT interrupt. (R/SS/WTC) I2C_TXFIFO_OVF_INT_RAW The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt. (R/SS/WTC) I2C_RXFIFO_UDF_INT_RAW The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt. (R/SS/WTC) I2C_SCL_ST_TO_INT_RAW The raw interrupt status of I2C_SCL_ST_TO_INT interrupt. (R/SS/WTC) I2C_SCL_MAIN_ST_TO_INT_RAW The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT inter- rupt. (R/SS/WTC) I2C_DET_START_INT_RAW The raw interrupt status of I2C_DET_START_INT interrupt. (R/SS/WTC) I2C_SLAVE_STRETCH_INT_RAW The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. (R/SS/WTC) I2C_GENERAL_CALL_INT_RAW The raw interrupt status of I2C_GENARAL_CALL_INT interrupt. (R/SS/WTC) I2C_SLAVE_ADDR_UNMATCH_INT_RAW The raw interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT interrupt. (R/SS/WTC) Espressif Systems 1052 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.22. I2C_INT_CLR_REG (0x0024) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 31 19 I2C_SLAVE_ADDR_UNMATCH_INT_CLR 0 18 I2C_GENERAL_CALL_INT_CLR 0 17 I2C_SLAVE_STRETCH_INT_CLR 0 16 I2C_DET_START_INT_CLR 0 15 I2C_SCL_MAIN_ST_TO_INT_CLR 0 14 I2C_SCL_ST_TO_INT_CLR 0 13 I2C_RXFIFO_UDF_INT_CLR 0 12 I2C_TXFIFO_OVF_INT_CLR 0 11 I2C_NACK_INT_CLR 0 10 I2C_TRANS_START_INT_CLR 0 9 I2C_TIME_OUT_INT_CLR 0 8 I2C_TRANS_COMPLETE_INT_CLR 0 7 I2C_MST_TXFIFO_UDF_INT_CLR 0 6 I2C_ARBITRATION_LOST_INT_CLR 0 5 I2C_BYTE_TRANS_DONE_INT_CLR 0 4 I2C_END_DETECT_INT_CLR 0 3 I2C_RXFIFO_OVF_INT_CLR 0 2 I2C_TXFIFO_WM_INT_CLR 0 1 I2C_RXFIFO_WM_INT_CLR 0 0 Reset I2C_RXFIFO_WM_INT_CLR Write 1 to clear I2C_RXFIFO_WM_INT interrupt. (WT) I2C_TXFIFO_WM_INT_CLR Write 1 to clear I2C_TXFIFO_WM_INT interrupt. (WT) I2C_RXFIFO_OVF_INT_CLR Write 1 to clear I2C_RXFIFO_OVF_INT interrupt. (WT) I2C_END_DETECT_INT_CLR Write 1 to clear the I2C_END_DETECT_INT interrupt. (WT) I2C_BYTE_TRANS_DONE_INT_CLR Write 1 to clear the I2C_BYTE_TRANS_DONE_INT interrupt. (WT) I2C_ARBITRATION_LOST_INT_CLR Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt. (WT) I2C_MST_TXFIFO_UDF_INT_CLR Write 1 to clear I2C_MST_TXFIFO_UDF_INT interrupt. (WT) I2C_TRANS_COMPLETE_INT_CLR Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt. (WT) I2C_TIME_OUT_INT_CLR Write 1 to clear the I2C_TIME_OUT_INT interrupt. (WT) I2C_TRANS_START_INT_CLR Write 1 to clear the I2C_TRANS_START_INT interrupt. (WT) I2C_NACK_INT_CLR Write 1 to clear I2C_NACK_INT interrupt. (WT) I2C_TXFIFO_OVF_INT_CLR Write 1 to clear I2C_TXFIFO_OVF_INT interrupt. (WT) I2C_RXFIFO_UDF_INT_CLR Write 1 to clear I2C_RXFIFO_UDF_INT interrupt. (WT) I2C_SCL_ST_TO_INT_CLR Write 1 to clear I2C_SCL_ST_TO_INT interrupt. (WT) I2C_SCL_MAIN_ST_TO_INT_CLR Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt. (WT) I2C_DET_START_INT_CLR Write 1 to clear I2C_DET_START_INT interrupt. (WT) I2C_SLAVE_STRETCH_INT_CLR Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. (WT) I2C_GENERAL_CALL_INT_CLR Write 1 to clear I2C_GENARAL_CALL_INT interrupt. (WT) I2C_SLAVE_ADDR_UNMATCH_INT_CLR Write 1 to clear I2C_SLAVE_ADDR_UNMATCH_INT inter- rupt. (WT) Espressif Systems 1053 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.23. I2C_INT_ENA_REG (0x0028) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 31 19 I2C_SLAVE_ADDR_UNMATCH_INT_ENA 0 18 I2C_GENERAL_CALL_INT_ENA 0 17 I2C_SLAVE_STRETCH_INT_ENA 0 16 I2C_DET_START_INT_ENA 0 15 I2C_SCL_MAIN_ST_TO_INT_ENA 0 14 I2C_SCL_ST_TO_INT_ENA 0 13 I2C_RXFIFO_UDF_INT_ENA 0 12 I2C_TXFIFO_OVF_INT_ENA 0 11 I2C_NACK_INT_ENA 0 10 I2C_TRANS_START_INT_ENA 0 9 I2C_TIME_OUT_INT_ENA 0 8 I2C_TRANS_COMPLETE_INT_ENA 0 7 I2C_MST_TXFIFO_UDF_INT_ENA 0 6 I2C_ARBITRATION_LOST_INT_ENA 0 5 I2C_BYTE_TRANS_DONE_INT_ENA 0 4 I2C_END_DETECT_INT_ENA 0 3 I2C_RXFIFO_OVF_INT_ENA 0 2 I2C_TXFIFO_WM_INT_ENA 0 1 I2C_RXFIFO_WM_INT_ENA 0 0 Reset I2C_RXFIFO_WM_INT_ENA Write 1 to enable I2C_RXFIFO_WM_INT interrupt. (R/W) I2C_TXFIFO_WM_INT_ENA Write 1 to enable I2C_TXFIFO_WM_INT interrupt. (R/W) I2C_RXFIFO_OVF_INT_ENA Write 1 to enable I2C_RXFIFO_OVF_INT interrupt. (R/W) I2C_END_DETECT_INT_ENA Write 1 to enable the I2C_END_DETECT_INT interrupt. (R/W) I2C_BYTE_TRANS_DONE_INT_ENA Write 1 to enable the I2C_BYTE_TRANS_DONE_INT interrupt. (R/W) I2C_ARBITRATION_LOST_INT_ENA Write 1 to enable the I2C_ARBITRATION_LOST_INT interrupt. (R/W) I2C_MST_TXFIFO_UDF_INT_ENA Write 1 to enable I2C_MST_TXFIFO_UDF_INT interrupt. (R/W) I2C_TRANS_COMPLETE_INT_ENA Write 1 to enable the I2C_TRANS_COMPLETE_INT interrupt. (R/W) I2C_TIME_OUT_INT_ENA Write 1 to enable the I2C_TIME_OUT_INT interrupt. (R/W) I2C_TRANS_START_INT_ENA Write 1 to enable the I2C_TRANS_START_INT interrupt. (R/W) I2C_NACK_INT_ENA Write 1 to enable I2C_NACK_INT interrupt. (R/W) I2C_TXFIFO_OVF_INT_ENA Write 1 to enable I2C_TXFIFO_OVF_INT interrupt. (R/W) I2C_RXFIFO_UDF_INT_ENA Write 1 to enable I2C_RXFIFO_UDF_INT interrupt. (R/W) I2C_SCL_ST_TO_INT_ENA Write 1 to enable I2C_SCL_ST_TO_INT interrupt. (R/W) I2C_SCL_MAIN_ST_TO_INT_ENA Write 1 to enable I2C_SCL_MAIN_ST_TO_INT interrupt. (R/W) I2C_DET_START_INT_ENA Write 1 to enable I2C_DET_START_INT interrupt. (R/W) I2C_SLAVE_STRETCH_INT_ENA Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt. (R/W) I2C_GENERAL_CALL_INT_ENA Write 1 to enable I2C_GENARAL_CALL_INT interrupt. (R/W) I2C_SLAVE_ADDR_UNMATCH_INT_ENA Write 1 to enable I2C_SLAVE_ADDR_UNMATCH_INT in- terrupt. (R/W) Espressif Systems 1054 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.24. I2C_INT_STATUS_REG (0x002C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 31 19 I2C_SLAVE_ADDR_UNMATCH_INT_ST 0 18 I2C_GENERAL_CALL_INT_ST 0 17 I2C_SLAVE_STRETCH_INT_ST 0 16 I2C_DET_START_INT_ST 0 15 I2C_SCL_MAIN_ST_TO_INT_ST 0 14 I2C_SCL_ST_TO_INT_ST 0 13 I2C_RXFIFO_UDF_INT_ST 0 12 I2C_TXFIFO_OVF_INT_ST 0 11 I2C_NACK_INT_ST 0 10 I2C_TRANS_START_INT_ST 0 9 I2C_TIME_OUT_INT_ST 0 8 I2C_TRANS_COMPLETE_INT_ST 0 7 I2C_MST_TXFIFO_UDF_INT_ST 0 6 I2C_ARBITRATION_LOST_INT_ST 0 5 I2C_BYTE_TRANS_DONE_INT_ST 0 4 I2C_END_DETECT_INT_ST 0 3 I2C_RXFIFO_OVF_INT_ST 0 2 I2C_TXFIFO_WM_INT_ST 0 1 I2C_RXFIFO_WM_INT_ST 0 0 Reset I2C_RXFIFO_WM_INT_ST The masked interrupt status of I2C_RXFIFO_WM_INT interrupt. (RO) I2C_TXFIFO_WM_INT_ST The masked interrupt status of I2C_TXFIFO_WM_INT interrupt. (RO) I2C_RXFIFO_OVF_INT_ST The masked interrupt status of I2C_RXFIFO_OVF_INT interrupt. (RO) I2C_END_DETECT_INT_ST The masked interrupt status of the I2C_END_DETECT_INT interrupt. (RO) I2C_BYTE_TRANS_DONE_INT_ST The masked interrupt status of the I2C_BYTE_TRANS_DONE_INT interrupt. (RO) I2C_ARBITRATION_LOST_INT_ST The masked interrupt status of the I2C_ARBITRATION_LOST_INT interrupt. (RO) I2C_MST_TXFIFO_UDF_INT_ST The masked interrupt status of I2C_MST_TXFIFO_UDF_INT inter- rupt. (RO) I2C_TRANS_COMPLETE_INT_ST The masked interrupt status of the I2C_TRANS_COMPLETE_INT interrupt. (RO) I2C_TIME_OUT_INT_ST The masked interrupt status of the I2C_TIME_OUT_INT interrupt. (RO) I2C_TRANS_START_INT_ST The masked interrupt status of the I2C_TRANS_START_INT interrupt. (RO) I2C_NACK_INT_ST The masked interrupt status of I2C_NACK_INT interrupt. (RO) I2C_TXFIFO_OVF_INT_ST The masked interrupt status of I2C_TXFIFO_OVF_INT interrupt. (RO) Continued on the next page... Espressif Systems 1055 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.24. I2C_INT_STATUS_REG (0x002C) Continued from the previous page... I2C_RXFIFO_UDF_INT_ST The masked interrupt status of I2C_RXFIFO_UDF_INT interrupt. (RO) I2C_SCL_ST_TO_INT_ST The masked interrupt status of I2C_SCL_ST_TO_INT interrupt. (RO) I2C_SCL_MAIN_ST_TO_INT_ST The masked interrupt status of I2C_SCL_MAIN_ST_TO_INT inter- rupt. (RO) I2C_DET_START_INT_ST The masked interrupt status of I2C_DET_START_INT interrupt. (RO) I2C_SLAVE_STRETCH_INT_ST The masked interrupt status of I2C_SLAVE_STRETCH_INT inter- rupt. (RO) I2C_GENERAL_CALL_INT_ST The masked interrupt status of I2C_GENARAL_CALL_INT interrupt. (RO) I2C_SLAVE_ADDR_UNMATCH_INT_ST The masked interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT interrupt. (RO) Espressif Systems 1056 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.25. I2C_COMD0_REG (0x0058) I2C_COMMAND0_DONE 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 14 I2C_COMMAND0 0 13 0 Reset I2C_COMMAND0 Configures command 0. It consists of three parts: op_code is the command 1: WRITE 2: STOP 3: READ 4: END 6: RSTART Byte_num represents the number of bytes that need to be sent or received. ack_check_en, ack_exp, and ack are used to control the ACK bit. See I2C cmd structure 30.4-2 for more information. (R/W) I2C_COMMAND0_DONE Represents whether command 0 is done in I2C Master mode. 0: Not done 1: Done (R/W/SS) Register 30.26. I2C_COMD1_REG (0x005C) I2C_COMMAND1_DONE 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 14 I2C_COMMAND1 0 13 0 Reset I2C_COMMAND1 Configures command 1. See details in I2C_COMMAND0. (R/W) I2C_COMMAND1_DONE Represents whether command 1 is done in I2C Master mode. 0: Not done 1: Done (R/W/SS) Espressif Systems 1057 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.27. I2C_COMD2_REG (0x0060) I2C_COMMAND2_DONE 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 14 I2C_COMMAND2 0 13 0 Reset I2C_COMMAND2 Configures command 2. See details in I2C_COMMAND0. (R/W) I2C_COMMAND2_DONE Represents whether command 2 is done in I2C Master mode. 0: Not done 1: Done (R/W/SS) Register 30.28. I2C_COMD3_REG (0x0064) I2C_COMMAND3_DONE 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 14 I2C_COMMAND3 0 13 0 Reset I2C_COMMAND3 Configures command 3. See details in I2C_COMMAND0. (R/W) I2C_COMMAND3_DONE Represents whether command 3 is done in I2C Master mode. 0: Not done 1: Done (R/W/SS) Espressif Systems 1058 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.29. I2C_COMD4_REG (0x0068) I2C_COMMAND4_DONE 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 14 I2C_COMMAND4 0 13 0 Reset I2C_COMMAND4 Configures command 4. See details in I2C_COMMAND0. (R/W) I2C_COMMAND4_DONE Represents whether command 4 is done in I2C Master mode. 0: Not done 1: Done (R/W/SS) Register 30.30. I2C_COMD5_REG (0x006C) I2C_COMMAND5_DONE 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 14 I2C_COMMAND5 0 13 0 Reset I2C_COMMAND5 Configures command 5. See details in I2C_COMMAND0. (R/W) I2C_COMMAND5_DONE Represents whether command 5 is done in I2C Master mode. 0: Not done 1: Done (R/W/SS) Espressif Systems 1059 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.31. I2C_COMD6_REG (0x0070) I2C_COMMAND6_DONE 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 14 I2C_COMMAND6 0 13 0 Reset I2C_COMMAND6 Configures command 6. See details in I2C_COMMAND0. (R/W) I2C_COMMAND6_DONE Represents whether command 6 is done in I2C Master mode. 0: Not done 1: Done (R/W/SS) Register 30.32. I2C_COMD7_REG (0x0074) I2C_COMMAND7_DONE 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 14 I2C_COMMAND7 0 13 0 Reset I2C_COMMAND7 Configures command 7. See details in I2C_COMMAND0. (R/W) I2C_COMMAND7_DONE Represents whether command 7 is done in I2C Master mode. 0: Not done 1: Done (R/W/SS) Register 30.33. I2C_DATE_REG (0x00F8) I2C_DATE 0x2401040 31 0 Reset I2C_DATE Version control register. (R/W) Espressif Systems 1060 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.34. I2C_TXFIFO_START_ADDR_REG (0x0100) I2C_TXFIFO_START_ADDR 0 31 0 Reset I2C_TXFIFO_START_ADDR Represents the I2C TX FIFO first address. (HRO) Register 30.35. I2C_RXFIFO_START_ADDR_REG (0x0180) I2C_RXFIFO_START_ADDR 0 31 0 Reset I2C_RXFIFO_START_ADDR Represents the I2C RX FIFO first address. (HRO) 30.9.2 LP_I2C Registers Register 30.36. LP_I2C_SCL_LOW_PERIOD_REG (0x0000) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 9 LP_I2C_SCL_LOW_PERIOD 0 8 0 Reset LP_I2C_SCL_LOW_PERIOD Configures the low level width of the SCL Clock in master mode. Measurement unit: I2C_SCLK clock cycles (R/W) Espressif Systems 1061 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.37. LP_I2C_SDA_HOLD_REG (0x0030) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 9 LP_I2C_SDA_HOLD_TIME 0 8 0 Reset LP_I2C_SDA_HOLD_TIME Configures the time to hold the data after the falling edge of SCL. Measurement unit: I2C_SCLK clock cycles (R/W) Register 30.38. LP_I2C_SDA_SAMPLE_REG (0x0034) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 9 LP_I2C_SDA_SAMPLE_TIME 0 8 0 Reset LP_I2C_SDA_SAMPLE_TIME Configures the time for sampling SDA. Measurement unit: I2C_SCLK clock cycles (R/W) Espressif Systems 1062 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.39. LP_I2C_SCL_HIGH_PERIOD_REG (0x0038) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 LP_I2C_SCL_WAIT_HIGH_PERIOD 0 15 9 LP_I2C_SCL_HIGH_PERIOD 0 8 0 Reset LP_I2C_SCL_HIGH_PERIOD Configures for how long SCL remains high in master mode. Measurement unit: I2C_SCLK clock cycles (R/W) LP_I2C_SCL_WAIT_HIGH_PERIOD Configures the SCL_FSM’s waiting period for SCL high level in master mode. Measurement unit: I2C_SCLK clock cycles (R/W) Register 30.40. LP_I2C_SCL_START_HOLD_REG (0x0040) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 9 LP_I2C_SCL_START_HOLD_TIME 8 8 0 Reset LP_I2C_SCL_START_HOLD_TIME Configures the time between the falling edge of SDA and the falling edge of SCL for a START condition. Measurement unit: I2C_SCLK clock cycles (R/W) Espressif Systems 1063 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.41. LP_I2C_SCL_RSTART_SETUP_REG (0x0044) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 9 LP_I2C_SCL_RSTART_SETUP_TIME 8 8 0 Reset LP_I2C_SCL_RSTART_SETUP_TIME Configures the time between the rising edge of SCL and the negative edge of SDA for a RESTART condition. Measurement unit: I2C_SCLK clock cycles (R/W) Register 30.42. LP_I2C_SCL_STOP_HOLD_REG (0x0048) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 9 LP_I2C_SCL_STOP_HOLD_TIME 8 8 0 Reset LP_I2C_SCL_STOP_HOLD_TIME Configures the delay after the STOP condition. Measurement unit: I2C_SCLK clock cycles (R/W) Espressif Systems 1064 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.43. LP_I2C_SCL_STOP_SETUP_REG (0x004C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 9 LP_I2C_SCL_STOP_SETUP_TIME 8 8 0 Reset LP_I2C_SCL_STOP_SETUP_TIME Configures the time between the rising edge of SCL and the ris- ing edge of SDA. Measurement unit: I2C_SCLK clock cycles (R/W) Register 30.44. LP_I2C_SCL_ST_TIME_OUT_REG (0x0078) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 5 LP_I2C_SCL_ST_TO_I2C 0x10 4 0 Reset LP_I2C_SCL_ST_TO_I2C Configures the threshold value of SCL_FSM state unchanged period. It should be no more than 23. Measurement unit: I2C_SCLK clock cycles (R/W) Register 30.45. LP_I2C_SCL_MAIN_ST_TIME_OUT_REG (0x007C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 5 LP_I2C_SCL_MAIN_ST_TO_I2C 0x10 4 0 Reset LP_I2C_SCL_MAIN_ST_TO_I2C Configures the threshold value of SCL_MAIN_FSM state un- changed period. It should be no more than 23. Measurement unit: I2C_SCLK clock cycles (R/W) Espressif Systems 1065 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.46. LP_I2C_CTR_REG (0x0004) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 12 LP_I2C_CONF_UPGATE 0 11 LP_I2C_FSM_RST 0 10 LP_I2C_ARBITRATION_EN 1 9 LP_I2C_CLK_EN 0 8 LP_I2C_RX_LSB_FIRST 0 7 LP_I2C_TX_LSB_FIRST 0 6 LP_I2C_TRANS_START 0 5 (reserved) 0 4 LP_I2C_RX_FULL_ACK_LEVEL 1 3 LP_I2C_SAMPLE_SCL_LEVEL 0 2 (reserved) 0 0 1 0 Reset LP_I2C_SAMPLE_SCL_LEVEL Configures the sample mode for SDA. 1: Sample SDA data on the SCL low level. 0: Sample SDA data on the SCL high level. (R/W) LP_I2C_RX_FULL_ACK_LEVEL Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has reached the threshold. (R/W) LP_I2C_TRANS_START Configures to start sending the data in TX FIFO for slave. 0: No effect 1: Start (WT) LP_I2C_TX_LSB_FIRST Configures to control the sending order for data to be sent. 1: send data from the least significant bit 0: send data from the most significant bit (R/W) LP_I2C_RX_LSB_FIRST Configures to control the storage order for received data. 1: receive data from the least significant bit 0: receive data from the most significant bit (R/W) LP_I2C_CLK_EN Configures whether to gate clock signal for registers. 0: Support clock only when registers are read or written to by software 1: Force clock on for registers. (R/W) LP_I2C_ARBITRATION_EN Configures to enable I2C bus arbitration detection. 0: No effect 1: Enable (R/W) LP_I2C_FSM_RST Configures to reset the SCL_FSM. 0: No effect 1: Reset (WT) LP_I2C_CONF_UPGATE Configures this bit for synchronization. 0: No effect 1: Synchronize (WT) Espressif Systems 1066 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.47. LP_I2C_TO_REG (0x000C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 6 LP_I2C_TIME_OUT_EN 0 5 LP_I2C_TIME_OUT_VALUE 0x10 4 0 Reset LP_I2C_TIME_OUT_VALUE Configures the timeout threshold period for SCL stucking at high or low level. The actual period is 2^(LP_I2C_TIME_OUT_VALUE+1). Measurement unit: I2C_SCLK clock cycles. (R/W) LP_I2C_TIME_OUT_EN Configures to enable time out control. 0: No effect 1: Enable (R/W) Espressif Systems 1067 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.48. LP_I2C_FIFO_CONF_REG (0x0018) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 15 LP_I2C_FIFO_PRT_EN 1 14 LP_I2C_TX_FIFO_RST 0 13 LP_I2C_RX_FIFO_RST 0 12 (reserved) 0 11 LP_I2C_NONFIFO_EN 0 10 (reserved) 0 9 LP_I2C_TXFIFO_WM_THRHD 0x2 8 5 (reserved) 0 4 LP_I2C_RXFIFO_WM_THRHD 0x6 3 0 Reset LP_I2C_RXFIFO_WM_THRHD Configures the watermark threshold of RX FIFO in nonfifo ac- cess mode. When LP_I2C_FIFO_PRT_EN is 1 and RX FIFO counter is bigger than LP_I2C_RXFIFO_WM_THRHD[3:0], LP_I2C_RXFIFO_WM_INT_RAW bit will be valid. (R/W) LP_I2C_TXFIFO_WM_THRHD Configures the watermark threshold of TX FIFO in nonfifo ac- cess mode. When LP_I2C_FIFO_PRT_EN is 1 and RX FIFO counter is bigger than LP_I2C_TXFIFO_WM_THRHD, LP_I2C_TXFIFO_WM_INT_RAW bit will be valid. (R/W) LP_I2C_NONFIFO_EN Configures to enable APB nonfifo access. (R/W) LP_I2C_RX_FIFO_RST Configures to reset RX FIFO. 0: No effect 1: Reset (R/W) LP_I2C_TX_FIFO_RST Configures to reset TX FIFO. 0: No effect 1: Reset (R/W) LP_I2C_FIFO_PRT_EN Configures to enable FIFO pointer in non-fifo access mode. This bit controls the valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts. 0: No effect 1: Enable (R/W) Espressif Systems 1068 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.49. LP_I2C_FILTER_CFG_REG (0x0050) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 10 LP_I2C_SDA_FILTER_EN 1 9 LP_I2C_SCL_FILTER_EN 1 8 LP_I2C_SDA_FILTER_THRES 0 7 4 LP_I2C_SCL_FILTER_THRES 0 3 0 Reset LP_I2C_SCL_FILTER_THRES Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL input has smaller width than this value, the I2C controller will ignore that pulse. Measurement unit: I2C_SCLK clock cycles (R/W) LP_I2C_SDA_FILTER_THRES Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA input has smaller width than this value, the I2C controller will ignore that pulse. Measurement unit: I2C_SCLK clock cycles (R/W) LP_I2C_SCL_FILTER_EN Configures to enable the filter function for SCL. 0: No effect 1: Enable (R/W) LP_I2C_SDA_FILTER_EN Configures to enable the filter function for SDA. 0: No effect 1: Enable (R/W) Espressif Systems 1069 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.50. LP_I2C_SCL_SP_CONF_REG (0x0080) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 LP_I2C_SDA_PD_EN 0 7 LP_I2C_SCL_PD_EN 0 6 LP_I2C_SCL_RST_SLV_NUM 0 5 1 LP_I2C_SCL_RST_SLV_EN 0 0 Reset LP_I2C_SCL_RST_SLV_EN Configures to send out SCL pulses when I2C master is IDLE. The num- ber of pulses equals to LP_I2C_SCL_RST_SLV_NUM. (R/W/SC) LP_I2C_SCL_RST_SLV_NUM Configure the pulses of SCL generated in I2C master mode. Valid when LP_I2C_SCL_RST_SLV_EN is 1. Measurement unit: I2C_SCLK clock cycles (R/W) LP_I2C_SCL_PD_EN Configures to power down the I2C output SCL line. 0: Not power down 1: Not work and power down Valid only when LP_I2C_SCL_FORCE_OUT is 1 (R/W) LP_I2C_SDA_PD_EN Configures to power down the I2C output SDA line. 0: Not power down. 1: Not work and power down. Valid only when LP_I2C_SDA_FORCE_OUT is 1. (R/W) Espressif Systems 1070 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.51. LP_I2C_SR_REG (0x0008) (reserved) 0 31 LP_I2C_SCL_STATE_LAST 0 30 28 (reserved) 0 27 LP_I2C_SCL_MAIN_STATE_LAST 0 26 24 (reserved) 0 23 LP_I2C_TXFIFO_CNT 0 22 18 (reserved) 0 0 0 0 0 17 13 LP_I2C_RXFIFO_CNT 0 12 8 (reserved) 0 0 0 7 5 LP_I2C_BUS_BUSY 0 4 LP_I2C_ARB_LOST 0 3 (reserved) 0 0 2 1 LP_I2C_RESP_REC 0 0 Reset LP_I2C_RESP_REC Represents the received ACK value in master mode or slave mode. 0: ACK 1: NACK (RO) LP_I2C_ARB_LOST Represents whether the I2C controller loses control of SCL line. 0: No arbitration lost 1: Arbitration lost (RO) LP_I2C_BUS_BUSY Represents the I2C bus state. 1: The I2C bus is busy transferring data 0: The I2C bus is in idle state (RO) LP_I2C_RXFIFO_CNT Represents the number of data bytes received in RAM. (RO) LP_I2C_TXFIFO_CNT Represents the number of data bytes to be sent. (RO) LP_I2C_SCL_MAIN_STATE_LAST Represents the states of the I2C module state machine. 0: Idle 1: Address shift 2: ACK address 3: Rx data 4: Tx data 5: Send ACK 6: Wait ACK (RO) LP_I2C_SCL_STATE_LAST Represents the states of the state machine used to produce SCL. 0: Idle 1: Start 2: Negative edge 3: Low 4: rising edge 5: High 6: Stop (RO) Espressif Systems 1071 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.52. LP_I2C_FIFO_ST_REG (0x0014) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 31 19 LP_I2C_TXFIFO_WADDR 0 18 15 (reserved) 0 14 LP_I2C_TXFIFO_RADDR 0 13 10 (reserved) 0 9 LP_I2C_RXFIFO_WADDR 0 8 5 (reserved) 0 4 LP_I2C_RXFIFO_RADDR 0 3 0 Reset LP_I2C_RXFIFO_RADDR Represents the offset address of the APB reading from RX FIFO (RO) LP_I2C_RXFIFO_WADDR Represents the offset address of i2c module receiving data and writing to RX FIFO. (RO) LP_I2C_TXFIFO_RADDR Represents the offset address of i2c module reading from TX FIFO. (RO) LP_I2C_TXFIFO_WADDR Represents the offset address of APB bus writing to TX FIFO. (RO) Register 30.53. LP_I2C_DATA_REG (0x001C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 LP_I2C_FIFO_RDATA 0 7 0 Reset LP_I2C_FIFO_RDATA Represents the value of RX FIFO read data. (RO) Espressif Systems 1072 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.54. LP_I2C_INT_RAW_REG (0x0020) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 LP_I2C_DET_START_INT_RAW 0 15 LP_I2C_SCL_MAIN_ST_TO_INT_RAW 0 14 LP_I2C_SCL_ST_TO_INT_RAW 0 13 LP_I2C_RXFIFO_UDF_INT_RAW 0 12 LP_I2C_TXFIFO_OVF_INT_RAW 0 11 LP_I2C_NACK_INT_RAW 0 10 LP_I2C_TRANS_START_INT_RAW 0 9 LP_I2C_TIME_OUT_INT_RAW 0 8 LP_I2C_TRANS_COMPLETE_INT_RAW 0 7 LP_I2C_MST_TXFIFO_UDF_INT_RAW 0 6 LP_I2C_ARBITRATION_LOST_INT_RAW 0 5 LP_I2C_BYTE_TRANS_DONE_INT_RAW 0 4 LP_I2C_END_DETECT_INT_RAW 0 3 LP_I2C_RXFIFO_OVF_INT_RAW 0 2 LP_I2C_TXFIFO_WM_INT_RAW 1 1 LP_I2C_RXFIFO_WM_INT_RAW 0 0 Reset LP_I2C_RXFIFO_WM_INT_RAW The raw interrupt status of LP_I2C_RXFIFO_WM_INT interrupt. (R/SS/WTC) LP_I2C_TXFIFO_WM_INT_RAW The raw interrupt status of LP_I2C_TXFIFO_WM_INT interrupt. (R/SS/WTC) LP_I2C_RXFIFO_OVF_INT_RAW The raw interrupt status of LP_I2C_RXFIFO_OVF_INT interrupt. (R/SS/WTC) LP_I2C_END_DETECT_INT_RAW The raw interrupt status of the LP_I2C_END_DETECT_INT inter- rupt. (R/SS/WTC) LP_I2C_BYTE_TRANS_DONE_INT_RAW The raw interrupt status of the LP_I2C_BYTE_TRANS_DONE_INT interrupt. (R/SS/WTC) LP_I2C_ARBITRATION_LOST_INT_RAW The raw interrupt status of the LP_I2C_ARBITRATION_LOST_INT interrupt. (R/SS/WTC) LP_I2C_MST_TXFIFO_UDF_INT_RAW The raw interrupt status of LP_I2C_MST_TXFIFO_UDF_INT interrupt. (R/SS/WTC) LP_I2C_TRANS_COMPLETE_INT_RAW The raw interrupt status of the LP_I2C_TRANS_COMPLETE_INT interrupt. (R/SS/WTC) LP_I2C_TIME_OUT_INT_RAW The raw interrupt status of the LP_I2C_TIME_OUT_INT interrupt. (R/SS/WTC) LP_I2C_TRANS_START_INT_RAW The raw interrupt status of the LP_I2C_TRANS_START_INT in- terrupt. (R/SS/WTC) LP_I2C_NACK_INT_RAW The raw interrupt status of LP_I2C_NACK_INT interrupt. (R/SS/WTC) LP_I2C_TXFIFO_OVF_INT_RAW The raw interrupt status of LP_I2C_TXFIFO_OVF_INT interrupt. (R/SS/WTC) LP_I2C_RXFIFO_UDF_INT_RAW The raw interrupt status of LP_I2C_RXFIFO_UDF_INT interrupt. (R/SS/WTC) LP_I2C_SCL_ST_TO_INT_RAW The raw interrupt status of LP_I2C_SCL_ST_TO_INT interrupt. (R/SS/WTC) Continued on the next page... Espressif Systems 1073 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.54. LP_I2C_INT_RAW_REG (0x0020) Continued from the previous page... LP_I2C_SCL_MAIN_ST_TO_INT_RAW The raw interrupt status of LP_I2C_SCL_MAIN_ST_TO_INT interrupt. (R/SS/WTC) LP_I2C_DET_START_INT_RAW The raw interrupt status of LP_I2C_DET_START_INT interrupt. (R/SS/WTC) Espressif Systems 1074 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.55. LP_I2C_INT_CLR_REG (0x0024) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 LP_I2C_DET_START_INT_CLR 0 15 LP_I2C_SCL_MAIN_ST_TO_INT_CLR 0 14 LP_I2C_SCL_ST_TO_INT_CLR 0 13 LP_I2C_RXFIFO_UDF_INT_CLR 0 12 LP_I2C_TXFIFO_OVF_INT_CLR 0 11 LP_I2C_NACK_INT_CLR 0 10 LP_I2C_TRANS_START_INT_CLR 0 9 LP_I2C_TIME_OUT_INT_CLR 0 8 LP_I2C_TRANS_COMPLETE_INT_CLR 0 7 LP_I2C_MST_TXFIFO_UDF_INT_CLR 0 6 LP_I2C_ARBITRATION_LOST_INT_CLR 0 5 LP_I2C_BYTE_TRANS_DONE_INT_CLR 0 4 LP_I2C_END_DETECT_INT_CLR 0 3 LP_I2C_RXFIFO_OVF_INT_CLR 0 2 LP_I2C_TXFIFO_WM_INT_CLR 0 1 LP_I2C_RXFIFO_WM_INT_CLR 0 0 Reset LP_I2C_RXFIFO_WM_INT_CLR Write 1 to clear LP_I2C_RXFIFO_WM_INT interrupt. (WT) LP_I2C_TXFIFO_WM_INT_CLR Write 1 to clear LP_I2C_TXFIFO_WM_INT interrupt. (WT) LP_I2C_RXFIFO_OVF_INT_CLR Write 1 to clear LP_I2C_RXFIFO_OVF_INT interrupt. (WT) LP_I2C_END_DETECT_INT_CLR Write 1 to clear the LP_I2C_END_DETECT_INT interrupt. (WT) LP_I2C_BYTE_TRANS_DONE_INT_CLR Write 1 to clear the LP_I2C_BYTE_TRANS_DONE_INT in- terrupt. (WT) LP_I2C_ARBITRATION_LOST_INT_CLR Write 1 to clear the LP_I2C_ARBITRATION_LOST_INT in- terrupt. (WT) LP_I2C_MST_TXFIFO_UDF_INT_CLR Write 1 to clear LP_I2C_MST_TXFIFO_UDF_INT interrupt. (WT) LP_I2C_TRANS_COMPLETE_INT_CLR Write 1 to clear the LP_I2C_TRANS_COMPLETE_INT inter- rupt. (WT) LP_I2C_TIME_OUT_INT_CLR Write 1 to clear the LP_I2C_TIME_OUT_INT interrupt. (WT) LP_I2C_TRANS_START_INT_CLR Write 1 to clear the LP_I2C_TRANS_START_INT interrupt. (WT) LP_I2C_NACK_INT_CLR Write 1 to clear LP_I2C_NACK_INT interrupt. (WT) LP_I2C_TXFIFO_OVF_INT_CLR Write 1 to clear LP_I2C_TXFIFO_OVF_INT interrupt. (WT) LP_I2C_RXFIFO_UDF_INT_CLR Write 1 to clear LP_I2C_RXFIFO_UDF_INT interrupt. (WT) LP_I2C_SCL_ST_TO_INT_CLR Write 1 to clear LP_I2C_SCL_ST_TO_INT interrupt. (WT) LP_I2C_SCL_MAIN_ST_TO_INT_CLR Write 1 to clear LP_I2C_SCL_MAIN_ST_TO_INT interrupt. (WT) LP_I2C_DET_START_INT_CLR Write 1 to clear LP_I2C_DET_START_INT interrupt. (WT) Espressif Systems 1075 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.56. LP_I2C_INT_ENA_REG (0x0028) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 LP_I2C_DET_START_INT_ENA 0 15 LP_I2C_SCL_MAIN_ST_TO_INT_ENA 0 14 LP_I2C_SCL_ST_TO_INT_ENA 0 13 LP_I2C_RXFIFO_UDF_INT_ENA 0 12 LP_I2C_TXFIFO_OVF_INT_ENA 0 11 LP_I2C_NACK_INT_ENA 0 10 LP_I2C_TRANS_START_INT_ENA 0 9 LP_I2C_TIME_OUT_INT_ENA 0 8 LP_I2C_TRANS_COMPLETE_INT_ENA 0 7 LP_I2C_MST_TXFIFO_UDF_INT_ENA 0 6 LP_I2C_ARBITRATION_LOST_INT_ENA 0 5 LP_I2C_BYTE_TRANS_DONE_INT_ENA 0 4 LP_I2C_END_DETECT_INT_ENA 0 3 LP_I2C_RXFIFO_OVF_INT_ENA 0 2 LP_I2C_TXFIFO_WM_INT_ENA 0 1 LP_I2C_RXFIFO_WM_INT_ENA 0 0 Reset LP_I2C_RXFIFO_WM_INT_ENA Write 1 to enable LP_I2C_RXFIFO_WM_INT interrupt. (R/W) LP_I2C_TXFIFO_WM_INT_ENA Write 1 to enable LP_I2C_TXFIFO_WM_INT interrupt. (R/W) LP_I2C_RXFIFO_OVF_INT_ENA Write 1 to enable LP_I2C_RXFIFO_OVF_INT interrupt. (R/W) LP_I2C_END_DETECT_INT_ENA Write 1 to enable the LP_I2C_END_DETECT_INT interrupt. (R/W) LP_I2C_BYTE_TRANS_DONE_INT_ENA Write 1 to enable the LP_I2C_BYTE_TRANS_DONE_INT interrupt. (R/W) LP_I2C_ARBITRATION_LOST_INT_ENA Write 1 to enable the LP_I2C_ARBITRATION_LOST_INT interrupt. (R/W) LP_I2C_MST_TXFIFO_UDF_INT_ENA Write 1 to enable LP_I2C_MST_TXFIFO_UDF_INT interrupt. (R/W) LP_I2C_TRANS_COMPLETE_INT_ENA Write 1 to enable the LP_I2C_TRANS_COMPLETE_INT in- terrupt. (R/W) LP_I2C_TIME_OUT_INT_ENA Write 1 to enable the LP_I2C_TIME_OUT_INT interrupt. (R/W) LP_I2C_TRANS_START_INT_ENA Write 1 to enable the LP_I2C_TRANS_START_INT interrupt. (R/W) LP_I2C_NACK_INT_ENA Write 1 to enable LP_I2C_NACK_INT interrupt. (R/W) LP_I2C_TXFIFO_OVF_INT_ENA Write 1 to enable LP_I2C_TXFIFO_OVF_INT interrupt. (R/W) LP_I2C_RXFIFO_UDF_INT_ENA Write 1 to enable LP_I2C_RXFIFO_UDF_INT interrupt. (R/W) LP_I2C_SCL_ST_TO_INT_ENA Write 1 to enable LP_I2C_SCL_ST_TO_INT interrupt. (R/W) LP_I2C_SCL_MAIN_ST_TO_INT_ENA Write 1 to enable LP_I2C_SCL_MAIN_ST_TO_INT interrupt. (R/W) LP_I2C_DET_START_INT_ENA Write 1 to enable LP_I2C_DET_START_INT interrupt. (R/W) Espressif Systems 1076 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.57. LP_I2C_INT_STATUS_REG (0x002C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 LP_I2C_DET_START_INT_ST 0 15 LP_I2C_SCL_MAIN_ST_TO_INT_ST 0 14 LP_I2C_SCL_ST_TO_INT_ST 0 13 LP_I2C_RXFIFO_UDF_INT_ST 0 12 LP_I2C_TXFIFO_OVF_INT_ST 0 11 LP_I2C_NACK_INT_ST 0 10 LP_I2C_TRANS_START_INT_ST 0 9 LP_I2C_TIME_OUT_INT_ST 0 8 LP_I2C_TRANS_COMPLETE_INT_ST 0 7 LP_I2C_MST_TXFIFO_UDF_INT_ST 0 6 LP_I2C_ARBITRATION_LOST_INT_ST 0 5 LP_I2C_BYTE_TRANS_DONE_INT_ST 0 4 LP_I2C_END_DETECT_INT_ST 0 3 LP_I2C_RXFIFO_OVF_INT_ST 0 2 LP_I2C_TXFIFO_WM_INT_ST 0 1 LP_I2C_RXFIFO_WM_INT_ST 0 0 Reset LP_I2C_RXFIFO_WM_INT_ST The masked interrupt status of LP_I2C_RXFIFO_WM_INT interrupt. (RO) LP_I2C_TXFIFO_WM_INT_ST The masked interrupt status of LP_I2C_TXFIFO_WM_INT interrupt. (RO) LP_I2C_RXFIFO_OVF_INT_ST The masked interrupt status of LP_I2C_RXFIFO_OVF_INT interrupt. (RO) LP_I2C_END_DETECT_INT_ST The masked interrupt status of the LP_I2C_END_DETECT_INT in- terrupt. (RO) LP_I2C_BYTE_TRANS_DONE_INT_ST The masked interrupt status of the LP_I2C_BYTE_TRANS_DONE_INT interrupt. (RO) LP_I2C_ARBITRATION_LOST_INT_ST The masked interrupt status of the LP_I2C_ARBITRATION_LOST_INT interrupt. (RO) LP_I2C_MST_TXFIFO_UDF_INT_ST The masked interrupt status of LP_I2C_MST_TXFIFO_UDF_INT interrupt. (RO) LP_I2C_TRANS_COMPLETE_INT_ST The masked interrupt status of the LP_I2C_TRANS_COMPLETE_INT interrupt. (RO) LP_I2C_TIME_OUT_INT_ST The masked interrupt status of the LP_I2C_TIME_OUT_INT interrupt. (RO) LP_I2C_TRANS_START_INT_ST The masked interrupt status of the LP_I2C_TRANS_START_INT in- terrupt. (RO) LP_I2C_NACK_INT_ST The masked interrupt status of LP_I2C_NACK_INT interrupt. (RO) LP_I2C_TXFIFO_OVF_INT_ST The masked interrupt status of LP_I2C_TXFIFO_OVF_INT interrupt. (RO) LP_I2C_RXFIFO_UDF_INT_ST The masked interrupt status of LP_I2C_RXFIFO_UDF_INT interrupt. (RO) LP_I2C_SCL_ST_TO_INT_ST The masked interrupt status of LP_I2C_SCL_ST_TO_INT interrupt. (RO) Continued on the next page... Espressif Systems 1077 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.57. LP_I2C_INT_STATUS_REG (0x002C) Continued from the previous page... LP_I2C_SCL_MAIN_ST_TO_INT_ST The masked interrupt status of LP_I2C_SCL_MAIN_ST_TO_INT interrupt. (RO) LP_I2C_DET_START_INT_ST The masked interrupt status of LP_I2C_DET_START_INT interrupt. (RO) Register 30.58. LP_I2C_COMD0_REG (0x0058) LP_I2C_COMMAND0_DONE 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 14 LP_I2C_COMMAND0 0 13 0 Reset LP_I2C_COMMAND0 Configures command 0. It consists of three parts: op_code is the command 1: WRITE 2: STOP 3: READ 4: END 6: RSTART Byte_num represents the number of bytes that need to be sent or received. ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure 30.4-2 for more information. (R/W) LP_I2C_COMMAND0_DONE Represents whether command 0 is done in I2C Master mode. 0: Not done 1: Done (R/W/SS) Espressif Systems 1078 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.59. LP_I2C_COMD1_REG (0x005C) LP_I2C_COMMAND1_DONE 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 14 LP_I2C_COMMAND1 0 13 0 Reset LP_I2C_COMMAND1 Configures command 1. See details in LP_I2C_COMMAND0. (R/W) LP_I2C_COMMAND1_DONE Represents whether command 1 is done in I2C Master mode. 0: Not done 1: Done (R/W/SS) Register 30.60. LP_I2C_COMD2_REG (0x0060) LP_I2C_COMMAND2_DONE 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 14 LP_I2C_COMMAND2 0 13 0 Reset LP_I2C_COMMAND2 Configures command 2. See details in LP_I2C_COMMAND0. (R/W) LP_I2C_COMMAND2_DONE Represents whether command 2 is done in I2C Master mode. 0: Not done 1: Done (R/W/SS) Espressif Systems 1079 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.61. LP_I2C_COMD3_REG (0x0064) LP_I2C_COMMAND3_DONE 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 14 LP_I2C_COMMAND3 0 13 0 Reset LP_I2C_COMMAND3 Configures command 3. See details in LP_I2C_COMMAND0. (R/W) LP_I2C_COMMAND3_DONE Represents whether command 3 is done in I2C Master mode. 0: Not done 1: Done (R/W/SS) Register 30.62. LP_I2C_COMD4_REG (0x0068) LP_I2C_COMMAND4_DONE 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 14 LP_I2C_COMMAND4 0 13 0 Reset LP_I2C_COMMAND4 Configures command 4. See details in LP_I2C_COMMAND0. (R/W) LP_I2C_COMMAND4_DONE Represents whether command 4 is done in I2C Master mode. 0: Not done 1: Done (R/W/SS) Espressif Systems 1080 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.63. LP_I2C_COMD5_REG (0x006C) LP_I2C_COMMAND5_DONE 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 14 LP_I2C_COMMAND5 0 13 0 Reset LP_I2C_COMMAND5 Configures command 5. See details in LP_I2C_COMMAND0. (R/W) LP_I2C_COMMAND5_DONE Represents whether command 5 is done in I2C Master mode. 0: Not done 1: Done (R/W/SS) Register 30.64. LP_I2C_COMD6_REG (0x0070) LP_I2C_COMMAND6_DONE 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 14 LP_I2C_COMMAND6 0 13 0 Reset LP_I2C_COMMAND6 Configures command 6. See details in LP_I2C_COMMAND0. (R/W) LP_I2C_COMMAND6_DONE Represents whether command 6 is done in I2C Master mode. 0: Not done 1: Done (R/W/SS) Espressif Systems 1081 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.65. LP_I2C_COMD7_REG (0x0074) LP_I2C_COMMAND7_DONE 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 14 LP_I2C_COMMAND7 0 13 0 Reset LP_I2C_COMMAND7 Configures command 7. See details in LP_I2C_COMMAND0. (R/W) LP_I2C_COMMAND7_DONE Represents whether command 7 is done in I2C Master mode. 0: Not done 1: Done (R/W/SS) Register 30.66. LP_I2C_DATE_REG (0x00F8) LP_I2C_DATE 0x2401040 31 0 Reset LP_I2C_DATE Version control register. (R/W) Register 30.67. LP_I2C_TXFIFO_START_ADDR_REG (0x0100) LP_I2C_TXFIFO_START_ADDR 0 31 0 Reset LP_I2C_TXFIFO_START_ADDR Represents the I2C TX FIFO first address. (HRO) Espressif Systems 1082 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 30 I2C Controller (I2C) Register 30.68. LP_I2C_RXFIFO_START_ADDR_REG (0x0180) LP_I2C_RXFIFO_START_ADDR 0 31 0 Reset LP_I2C_RXFIFO_START_ADDR Represents the I2C RX FIFO first address. (HRO) Espressif Systems 1083 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) Chapter 31 I2S Controller (I2S) 31.1 Overview ESP32-C5 has a built-in I2S interface, which provide flexible communication interfaces for streaming digital data in multimedia applications, especially digital audio applications. The I2S standard bus defines three signals, namely, a bit clock signal (BCK), a channel/word select signal (WS), and a serial data signal (SD). A basic I2S data bus has one master and one slave. The roles remain unchanged throughout the communication. The I2S module on ESP32-C5 provides separate transmit (TX) and receive (RX) units for high performance. 31.2 Terminology To better illustrate the functionality of I2S, the following terms are used in this chapter. Master mode As a master, I2S drives BCK/WS signals and transmits data to or receives data from a slave. Slave mode As a slave, I2S is driven by BCK/WS signals and receives data from or transmits data to a master. Full-duplex There are two separate data lines. The transmitted and received data is carried simultaneously. Half-duplex Only one side, the master or the slave, transmits data first, and the other side receives data. Data transmission and reception cannot occur simultaneously. A-law and µ-law A-law and µ-law are compression/decompression algorithms in digital pulse code modulated (PCM) non-uniform quantization, which can effectively improve the signal-to-quantization noise ra- tio. TDM RX mode In this mode, pulse code modulated (PCM) data is received utiliz- ing time division multiplexing (TDM). The signal lines include BCK, WS, and SD. Data from 16 channels at most can be received. TDM Philips standard, TDM MSB alignment standard, and TDM PCM standard are supported in this mode, depending on user configu- ration. PDM RX mode In this mode, pulse density modulation (PDM) data is received. Used signals include WS and DATA. PDM standard is supported in this mode by user configuration. Espressif Systems 1084 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) TDM TX mode In this mode, pulse code modulated (PCM) data is sent in a way of time division multiplexing (TDM). The signal lines include BCK, WS, and DATA. Data up to 16 channels can be sent. TDM Philips standard, TDM MSB alignment standard, and TDM PCM standard are supported in this mode, depending on user configuration. PDM TX mode In this mode, pulse density modulation (PDM) data is sent. The signal lines include WS and DATA. PDM standard is supported in this mode by user configuration. PCM-to-PDM Data Format Converter A data format converter that converts PCM data into PDM data (hereinafter referred to as PCM-to-PDM converter), which can be enabled in PDM TX master mode. When the converter is enabled, I2S fetches pulse code modulated (PCM) data from storage via GDMA, converts it to pulse density modulation (PDM) data, and then transmits it. 31.3 Features The I2S module has the following features: • Master mode and slave mode • Full-duplex and half-duplex communications • Separate TX and RX units that can work independently or simultaneously • A variety of audio standards supported: – TDM Philips standard – TDM MSB alignment standard – TDM PCM standard – PDM standard • Various TX/RX modes supported: – TDM TX mode, up to 16 channels supported – TDM RX mode, up to 16 channels supported – PDM TX mode * Raw PDM data transmission * PCM-to-PDM data format conversion, up to 2 channels supported – PDM RX mode * Raw PDM data reception • Configurable clock source with frequencies up to 240 MHz • Configurable high-precision sample clock with a variety of sampling frequencies supported (refer to the note below for more details) • 8/16/24/32-bit data width Espressif Systems 1085 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) • Synchronous counter in TX mode • ETM feature • Direct Memory Access • Standard I2S interface interrupts Note: In slave mode, to ensure the sampling accuracy, the module clock frequency must be greater than or equal to 8 times the BCK clock frequency. Therefore, the maximum sampling frequency of I2S is limited by the data bit width and the number of channels. For example, since the clock source frequency is up to 240 MHz, the module clock can be configured up to 120 MHz, and the BCK clock can be configured up to 15 MHz. Therefore, when transmitting dual-channel 32-bit width data, I2S supports sample frequencies up to 234.375 kHz, e.g., 8 kHz, 16 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 128 kHz, and 192 kHz.Please refer to Section 31.6 I2S TX/RX Clock for detailed information. 31.4 System Architecture Figure 31.4-1 shows the structure of the ESP32-C5 I2S module, consisting of: • Transmit control unit (TX Unit) • Receive control unit (RX Unit) • Input and output timing unit (I/O Sync) • Clock divider (Clock Generator) • 64 x 32-bit TX FIFO • 64 x 32-bit RX FIFO • Compress/Decompress units Espressif Systems 1086 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) CPU GDMA Data and Address Bus A-law/μ-law Decompress Clock Generator BCK I2S_TX/RX_CLK I/O Sync I2S A-law/μ-law Compress RX Unit TDM RX RX FIFO TX FIFO PDM RX I2SO_SD_out I2SI_SD_in I2SO_BCK_in / I2SO_BCK_out I2SO_WS_in / I2SO_WS_out I2S_MCLK_out I2SI_WS_in / I2SI_WS_out I2SI_BCK_in / I2SI_BCK_out RX TX TX Unit TDM TX PDM TX PCM-to-PDM Converter XTAL_CLK PLL_F240M_CLK PLL_F160M_CLK I2S_MCLK_in Figure 31.4-1. ESP32-C5 I2S System Diagram The I2S module supports direct memory access (DMA) to internal memory. For more information, see Chapter 3 GDMA Controller (GDMA). Both the TX unit and the RX unit have a three-line interface that uses a bit clock line (BCK), a word select line (WS), and a serial data line (SD). The SD line of the TX unit is used for data output and the SD line of the RX unit for data input. The BCK and WS signal lines of the TX and RX units are used for data output in master mode, and the BCK and WS signal lines of the TX and RX units are used for data input in slave mode. The signal bus of the I2S module is shown at the right part of Figure 31.4-1. The naming of these signals in RX and TX units follows the pattern of I2SA_B_C such as I2SI_BCK_in. • “A” indicates that the signal belongs to the I2S TX or RX unit, which includes: – “I”: Signal input to/output from the RX unit – “O”: Signal input to/output from the TX unit • “B” represents the signal function, which includes: – BCK – WS – SD • “C” represents the signal direction, which includes: – “in”: Input signal into the I2S module – “out”: Output signal from the I2S module Table 31.4-1 provides a detailed description of I2S signals. Espressif Systems 1087 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) Table 31.4-1. I2S Signal Description Signal Direction Function I2SI_BCK_in Input In I2S slave mode, inputs BCK signal for RX unit. I2SI_BCK_out Output In I2S master mode, outputs BCK signal for RX unit. I2SI_WS_in Input In I2S slave mode, inputs WS signal for RX unit. I2SI_WS_out Output In I2S master mode, outputs WS signal for RX unit. I2SI_SD_in Input Works as the serial input data bus for I2S RX unit. I2SO_SD_out Output Works as the serial output data bus for I2S TX unit. I2SO_BCK_in Input In I2S slave mode, inputs BCK signal for TX unit. I2SO_BCK_out Output In I2S master mode, outputs BCK signal for TX unit. I2SO_WS_in Input In I2S slave mode, inputs WS signal for TX unit. I2SO_WS_out Output In I2S master mode, outputs WS signal for TX unit. I2S_MCLK_in Input In I2S slave mode, works as a clock source from the external master. I2S_MCLK_out Output In I2S master mode, works as a clock source for the external slave. I2SO_SD1_out Output When the PCM-to-PDM converter is enabled, works as the serial out- put data line for TX unit. * Any required signals of I2S must be mapped to the chip’s pins via GPIO matrix, see Chapter 6 GPIO Matrix and IO MUX. 31.5 Supported Audio Standards ESP32-C5 I2S supports multiple audio standards, including TDM Philips standard, TDM MSB alignment standard, TDM PCM standard, and PDM standard. Select the needed standard by configuring the following bits: • I2S_TX/RX_TDM_EN – 0: Disable TDM mode – 1: Enable TDM mode • I2S_TX/RX_PDM_EN – 0: Disable PDM mode – 1: Enable PDM mode • I2S_TX/RX_MSB_SHIFT – 0: WS and SD signals change simultaneously, i.e., enable MSB alignment standard – 1: WS signal changes one BCK clock cycle earlier than SD signal, i.e., enable Philips standard or select PCM standard Note: I2S_TX/RX_TDM_EN and I2S_TX/RX_PDM_EN must not be configured to 1 or 0 at the same time, otherwise ESP32-C5 I2S will transmit data incorrectly in a mode that is neither TDM nor PDM. Espressif Systems 1088 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) 31.5.1 TDM Philips Standard Philips standards require that WS signal changes one BCK clock cycle earlier than SD signal on BCK falling edge, which means that WS signal is valid from one clock cycle before transmitting the first bit of channel data and changes one clock before the end of channel data transfer. SD signal line transmits the most significant bit of audio data first. Compared with the basic Philips standard, TDM Philips standard supports multiple channels. See Figure 31.5-1. Figure 31.5-1. TDM Philips Standard Timing Diagram 31.5.2 TDM MSB Alignment Standard MSB alignment standards require that WS and SD signals change simultaneously on the falling edge of BCK. The WS signal is valid until the end of the channel data transfer. The SD signal line transmits the most significant bit of audio data first. Compared with the basic MSB alignment standard, TDM MSB alignment standard supports multiple channels. See Figure 31.5-2. Figure 31.5-2. TDM MSB Alignment Standard Timing Diagram Espressif Systems 1089 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) 31.5.3 TDM PCM Standard Short frame synchronization under the PCM standards requires that the WS signal changes one BCK clock cycle earlier than the SD signal on the falling edge of BCK, which means that the WS signal becomes valid one clock cycle before transferring the first bit of channel data and remains unchanged in this BCK clock cycle. SD signal line first transmits the most significant bit of audio data. Compared with the basic PCM standard, TDM PCM standard supports multiple channels. See Figure 31.5-3. Figure 31.5-3. TDM PCM Standard Timing Diagram 31.5.4 PDM Standard Under PDM standard, WS signal changes continuously during data transmission. The low-level and high-level of this signal indicates the left channel and right channel respectively. WS and SD signals change simultaneously. See Figure 31.5-4. Left Right Left Right WS(LRCK) SD(SDOUT) Left Right Left Right RightLeft Left Right RightLeft Left Right RightLeft Left Right Figure 31.5-4. PDM Standard Timing Diagram 31.6 I2S TX/RX Clock I2S_TX/RX_CLK is the master clock of I2S TX/RX unit, divided from: Espressif Systems 1090 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) • 40 MHz XTAL_CLK • 240 MHz PLL_F240M_CLK • 160 MHz PLL_F160M_CLK • I2S_MCLK_in (external input clock) The serial clock (BCK) of the I2S TX/RX unit is divided from I2S_TX/RX_CLK, as shown in Figure 31.6-1. PCR_I2S_TX/RX_CLKM_SEL is used to select clock source for TX/RX unit, and PCR_I2S_TX/RX_CLKM_EN to enable or disable the clock source. XTAL_CLK I2SO_BCK_out I2S_TX_CLK PCR_I2S_TX_CLKM_SEL[1:0] 0 1 N + b a 1 MO PLL_F240M_CLK 1 PLL_F160M_CLK 2 I2S_MCLK_in 3 I2SI_BCK_out I2S_RX_CLK PCR_I2S_RX_CLKM_SEL[1:0] 0 1 N + b a 1 MI 1 2 3 0 1 PCR_I2S_MCLK_SEL I2S_MCLK_out XTAL_CLK PLL_F240M_CLK PLL_F160M_CLK I2S_MCLK_in Figure 31.6-1. I2S Clock Generator The following formula shows the relation between I2S_TX/RX_CLK frequency f I2S_TX/RX_CLK and the divider clock source frequency f I2S_CLK_S : f I2S_TX/RX_CLK = f I2S_CLK_S N + b a N is an integer value between 2 and 256. The value of N is mapped to that of PCR_I2S_TX/RX_CLKM_DIV_NUM as follows: • When PCR_I2S_TX/RX_CLKM_DIV_NUM = 0, N = 256; • When PCR_I2S_TX/RX_CLKM_DIV_NUM = 1, N = 2; • When PCR_I2S_TX/RX_CLKM_DIV_NUM has any other value, N = PCR_I2S_TX/RX_CLKM_DIV_NUM. The values of “a” and “b” in fractional divider depend only on x, y, z, and yn1. The corresponding formulas are as follows: • When b <= a 2 , yn1 = 0, x = floor([ a b ]) − 1, y = a%b, z = b; • When b > a 2 , yn1 = 1, x = floor([ a a - b ]) − 1, y = a%(a - b), z = a - b. The values of x, y, z, and yn1 are configured in PCR_I2S_TX/RX_CLKM_DIV_X, PCR_I2S_TX/RX_CLKM_DIV_Y, PCR_I2S_TX/RX_CLKM_DIV_Z, and PCR_I2S_TX/RX_CLKM_DIV_YN1. Espressif Systems 1091 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) To configure the integer divider, clear PCR_I2S_TX/RX_CLKM_DIV_X and PCR_I2S_TX/RX_CLKM_DIV_Z, then set PCR_I2S_TX/RX_CLKM_DIV_Y to 1. Note: Using fractional divider may introduce some clock jitter. In master TX mode, the serial clock BCK for I2S TX unit is I2SO_BCK_out divided from I2S_TX_CLK which is: f I2SO_BCK_out = f I2S_TX_CLK MO “MO” is an integer value: MO = I2S_TX_BCK_DIV_NUM + 1 Note: Note that I2S_TX_BCK_DIV_NUM must not be configured as 1. In master RX mode, the serial clock BCK for I2S RX unit is I2SI_BCK_out divided from I2S_RX_CLK, which is: f I2SI_BCK_out = f I2S_RX_CLK MI “MI” is an integer value: MI = I2S_RX_BCK_DIV_NUM + 1 Note: • I2S_RX_BCK_DIV_NUM must not be configured as 1. • In I2S slave mode, make sure f I2S_TX/RX_CLK >= 8 * f BCK . The I2S module can output I2S_MCLK_out as the master clock for peripherals. 31.7 I2S Reset The units and FIFOs in the I2S module are reset by the following bits. • I2S TX/RX units: Reset by I2S_TX_RESET and I2S_RX_RESET; • I2S TX/RX FIFO: Reset by I2S_TX_FIFO_RESET and I2S_RX_FIFO_RESET. Note: The I2S module clock must be configured first before the module and FIFO are reset. Espressif Systems 1092 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) 31.8 I2S Master/Slave Mode The ESP32-C5 I2S module can operate as a master or a slave in half-duplex and full-duplex communications, depending on the configuration of I2S_RX_SLAVE_MOD and I2S_TX_SLAVE_MOD. • I2S_TX_SLAVE_MOD – 0: Master TX mode – 1: Slave TX mode • I2S_RX_SLAVE_MOD – 0: Master RX mode – 1: Slave RX mode 31.8.1 Master/Slave TX Mode • I2S works as a master transmitter: – Set I2S_TX_START to start transmitting data. When this bit is set, the TX unit keeps driving the clock signal and serial data. – If I2S_TX_STOP_EN is set and all the data in FIFO is transmitted, the master stops transmitting data and clock signals. – If I2S_TX_STOP_EN is cleared and all the data in FIFO is transmitted, meanwhile no new data is filled into FIFO, the TX unit keeps transmitting the last data frame and clock signal. – Master stops transmitting data when I2S_TX_START is cleared. • I2S works as a slave transmitter: – Set I2S_TX_START. Wait for the master BCK clock to enable a transmit operation. – If I2S_TX_STOP_EN is set and all the data in FIFO is transmitted, then the slave keeps transmitting zeros, till the master stops providing BCK signal. – If I2S_TX_STOP_EN is cleared and all the data in FIFO is transmitted, meanwhile no new data is filled into FIFO, the TX unit keeps transmitting the last data frame. – If I2S_TX_START is cleared, slave keeps transmitting zeros till the master stops providing BCK clock signal. 31.8.2 Master/Slave RX Mode • I2S works as a master receiver: – Set I2S_RX_START to start receiving data. When this bit is set, the RX unit keeps outputting clock signal and sampling input data. – Configure I2S_RX_STOP_MODE to control the suspension of data reception: * 0: The RX unit only suspends data reception when I2S_RX_START is cleared. Espressif Systems 1093 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) * 1: The RX unit suspends data reception when I2S_RX_START is cleared or the number of received bytes is greater than the value configured in I2S_RX_EOF_NUM_REG. When I2S_RX_START is not cleared, data reception can be restarted by setting I2S_RX_RESET to 1. * 2: The RX unit suspends data reception when I2S_RX_START is cleared or GDMA RX FIFO is full. When I2S_RX_START is not cleared and the GDMA RX FIFO is no longer full, data reception can be restarted by setting I2S_RX_RESET to 1. – RX unit stops receiving data when I2S_RX_START is cleared. • I2S works as a slave receiver: – Set I2S_RX_START. Wait for the master BCK signal to start receiving data. – Configure I2S_RX_STOP_MODE to control data reception suspension: * 0: The RX unit only suspends data reception when I2S_RX_START is cleared. * 1: The RX unit suspends data reception when the number of received bytes is greater than the value configured in I2S_RX_EOF_NUM_REG. When I2S_RX_START is not cleared, data reception can be restarted by setting I2S_RX_RESET to 1. * 2: The RX unit suspends data reception when I2S_RX_START is cleared or GDMA RX FIFO is full. When I2S_RX_START is not cleared and the GDMA RX FIFO is no longer full, data reception can be restarted by setting I2S_RX_RESET to 1. – The RX unit stops receiving data when I2S_RX_START is cleared. 31.9 Transmitting Data Note: Updating the configuration described in this and subsequent sections requires to set I2S_TX_UPDATE accordingly to synchronize registers from APB clock domain to TX clock domain. For more detailed configurations, see Section 31.13.1. In TX mode, I2S first reads data through GDMA and transmits these data out via output signals according to the configured data mode and channel mode. 31.9.1 Data Format Control Data format is controlled in the following phases: • Phase I: Read data from memory and write it to TX FIFO; • Phase II: Read the TX data from TX FIFO and convert the data according to the output data mode; • Phase III: Clock out the TX data serially. 31.9.1.1 Bit Width Control of Channel Valid Data The bit width of the valid data in each channel is determined by I2S_TX_BITS_MOD and I2S_TX_24_FILL_EN. For details, see the table below. Espressif Systems 1094 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) Table 31.9-1. Bit Width of Channel Valid Data Channel Valid Data Width I2S_TX_BITS_MOD I2S_TX_24_FILL_EN 32 31 x * 23 1 24 23 0 16 15 x 8 7 x * “x” represents that this value is ignored (applies to all tables in this chapter). 31.9.1.2 Endian Control of Channel Valid Data When I2S reads data through GDMA, the data endian under various data width is controlled by I2S_TX_BIG_ENDIAN. Table 31.9-2 shows how I2S_TX_BIG_ENDIAN controls the reading of the data with different valid data widths of the channel. Table 31.9-2. Endian of Channel Valid Data Channel Valid Data Width Original Data Endian of Processed Data I2S_TX_BIG_ENDIAN 32 {B3, B2, B1, B0} {B3, B2, B1, B0} 0 {B0, B1, B2, B3} 1 24 {B2, B1, B0} {B2, B1, B0} 0 {B0, B1, B2} 1 16 {B1, B0} {B1, B0} 0 {B0, B1} 1 8 {B0} {B0} x Note: B0, B1, B2, B3 each represents an 8-bit data, and the symbol {} indicates that the bytes are combined together. For example, {B3, B2, B1, B0} represents a 32-bit data, wherein B0 represents bit 0-7, B1 represents bit 8-15, B2 represents bit 16-23, and B3 represents bit 24-31. 31.9.1.3 A-law/µ-law Compression and Decompression ESP32-C5 I2S compresses/decompresses the valid data into 32-bit by A-law or by µ-law. If the bit width of valid data is smaller than 32, zeros are filled to the extra high bits of the data to be compressed/decompressed by default. Note: Extra high bits here mean the bits[31: channel valid data width] of the data to be compressed/decompressed. Configure I2S_TX_PCM_BYPASS: • 0: Compress or decompress the data • 1: Do not compress or decompress the data Espressif Systems 1095 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) Configure I2S_TX_PCM_CONF: • 0: Decompress the data using A-law • 1: Compress the data using A-law • 2: Decompress the data using µ-law • 3: Compress the data using µ-law At this point, the first phase of data format control is completed. 31.9.1.4 Bit Width Control of Channel TX Data The TX data width in each channel is determined by I2S_TX_TDM_CHAN_BITS. • If TX data width in each channel is larger than the valid data width, zeros will be filled to these extra bits. Configure I2S_TX_LEFT_ALIGN: – 0: The valid data is at the lower bits of TX data. Zeros are filled into higher bits of TX data; – 1: The valid data is at the higher bits of TX data. Zeros are filled into lower bits of TX data. • If the TX data width in each channel is smaller than the valid data width, only the lower bits of valid data are sent out, and the higher bits are discarded. At this point, the second phase of data format control is completed. 31.9.1.5 Bit Order Control of Channel Data The data bit order in each channel is controlled by I2S_TX_BIT_ORDER: • 0: Not reverse the valid data bit order; • 1: Reverse the valid data bit order. At this point, the data format control is completed. The data after format control will be sent sequentially from high to low. Figure 31.9-1 shows the complete process of TX data format control. Espressif Systems 1096 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) Figure 31.9-1. TX Data Format Control 31.9.2 Channel Mode Control ESP32-C5 I2S supports both TDM TX mode and PDM TX mode. Set I2S_TX_TDM_EN to enable TDM TX mode, or set I2S_TX_PDM_EN to enable PDM TX mode. Note: I2S_TX_TDM_EN and I2S_TX_PDM_EN must not be cleared or set simultaneously. 31.9.2.1 TDM TX Mode In TDM TX mode, I2S supports up to 16 channels to transmit data. The total number of TX channels in use is controlled by I2S_TX_TDM_TOT_CHAN_NUM. For example, If I2S_TX_TDM_TOT_CHAN_NUM is set to 5, six channels in total (channel 0-5) will be used to transmit data. See Figure 31.9-2. Note: Most stereo I2S codecs can be controlled by setting the I2S module into 2-channel mode under TDM standard. In these TX channels, if I2S_TX_TDM_CHANn_EN is set to: • 1: This channel transmits the channel data out; • 0: The TX data to be sent by this channel is controlled by I2S_TX_CHAN_EQUAL: – 1: The data of the previous channel is sent out; – 0: The data stored in I2S_SINGLE_DATA is sent out. In TDM TX master mode, WS signal is controlled by I2S_TX_WS_IDLE_POL and I2S_TX_TDM_WS_WIDTH: • I2S_TX_WS_IDLE_POL: The default level of WS signal; • I2S_TX_TDM_WS_WIDTH: The cycles the WS default level lasts for when transmitting all channel data. Espressif Systems 1097 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) I2S_TX_HALF_SAMPLE_BITS x 2 is equal to the BCK cycles in one WS period. TDM Channel Configuration Example In this example, the register configuration is as follows: • I2S_TX_TDM_CHAN_NUM = 5, i.e., channel 0-5 are used to transmit data. • I2S_TX_CHAN_EQUAL = 1, i.e., data of the previous channel will be transmitted if the I2S_TX_TDM_CHANn_EN (n = 0-5) is cleared. • I2S_TX_TDM_CHAN0/2/5_EN = 1, i.e., these channels transmit their channel data out. • I2S_TX_TDM_CHAN1/3/4_EN = 0, i.e., these channels transmit the previous channel’s data out. Once the configuration is done, data is transmitted as follows. Data_0 Data_0 Data_2 Data_2 Data_2 Data_5 I2S_TX_TDM_CHAN_NUM = 5; I2S_TX_CHAN_EQUAL = 1; I2S_TX_TDM_CHAN0_EN = 1; I2S_TX_TDM_CHAN1_EN = 0; I2S_TX_TDM_CHAN2_EN = 1; I2S_TX_TDM_CHAN3_EN = 0; I2S_TX_TDM_CHAN4_EN = 0; I2S_TX_TDM_CHAN5_EN = 1; Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Figure 31.9-2. TDM Channel Control 31.9.2.2 PDM TX Mode In PDM TX mode, I2S supports both PDM raw data transmission and PCM-to-PDM data format conversion. In PDM TX mode, fetching data through GDMA is controlled by I2S_TX_MONO and I2S_TX_MONO_FST_VLD. See Table 31.9-3. Configure the two bits according to the data stored in memory, be it the single-channel or dual-channel data. Table 31.9-3. Data-Fetching Control in PDM Mode Data-Fetching Control Option Mode I2S_TX_MONO I2S_TX_MONO_FST_VLD Post data-fetching request to GDMA at any edge of WS signal Stereo mode 0 x Post data-fetching request to GDMA only at the second half period of WS signal Mono mode 1 0 Post data-fetching request to GDMA only at the first half period of WS signal Mono mode 1 1 When I2S is in PDM TX master mode, the default level of WS signal is controlled by I2S_TX_WS_IDLE_POL, and the WS signal frequency is half of the BCK signal frequency. The configuration of WS signal is similar to that of BCK signal. Please refer to Section 31.6 and Figure 31.6. When transmitting raw PDM data, the I2S channel mode is controlled by I2S_TX_CHAN_MOD and I2S_TX_WS_IDLE_POL. See the table below. Espressif Systems 1098 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) Table 31.9-4. I2S Channel Control for Raw PDM Data Channel Con- trol Option Left Channel Right Channel Mode Control Field 1 Channel Select Bit 2 Stereo mode Transmit the left channel data Transmit the right channel data 0 x Mono mode Transmit the left channel data Transmit the left channel data 1 0 Transmit the right channel data Transmit the right channel data 1 1 Transmit the right channel data Transmit the right channel data 2 0 Transmit the left channel data Transmit the left channel data 2 1 Transmit the value of “single” 3 Transmit the right channel data 3 0 Transmit the left channel data Transmit the value of “single” 3 1 Transmit the left channel data Transmit the value of “single” 4 0 Transmit the value of “single” Transmit the right channel data 4 1 1 I2S_TX_CHAN_MOD 2 I2S_TX_WS_IDLE_POL 3 The “single” value is equal to the value of I2S_SINGLE_DATA. If the PCM-to-PDM converter is enabled, the PCM data through GDMA is converted to PDM data and then output in PDM signal format. Configure I2S_PCM2PDM_CONV_EN to enable the converter. The register configuration for the PCM-to-PDM converter is as follows: • Configure 1-line PDM output format or 1-/2-line DAC output mode as the table below: Table 31.9-5. I2S PCM-to-PDM Data Output Channel Output Format I2S_TX_PDM_DAC_MODE_EN I2S_TX_PDM_DAC_2OUT_EN 1-line PDM output format 1 0 x 1-line DAC output format 2 1 0 2-line DAC output format 1 1 Note: 1. In PDM output format, SD data of two channels is sent out in one WS period. 2. In DAC output format, SD data of one channel is sent out in one WS period. 3. 1-line PDM/DAC output format uses I2SO_Data_out as the data output line. 4. 2-line DAC output format uses I2SO_Data_out and I2SO_Data1_out as data output lines. 5. In terms of application, the PDM output format is targeted at applications that require clock signals and can decode PDM format codecs, while the DAC output format is targeted at applications that do not rely on clock signals, do not have PDM format codecs, and can recover analog waveforms directly through low-pass filtering. • Configure sampling frequency and upsampling rate as below: When the I2S PCM-to-PDM converter is enabled, PDM clock frequency is equal to BCK frequency. The relation of sampling frequency (f Sampling , the sampling frequency of PCM data) and BCK frequency (the Espressif Systems 1099 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) sampling frequency of PDM data) is as follows: f Sampling = f BCK OSR Upsampling rate (OSR) is related to I2S_TX_PDM_SINC_OSR2 as follows: OSR = I2S_TX_PDM_SINC_OSR2 × 64 Sampling frequency f Sampling is related to I2S_TX_PDM_FS as follows: f Sampling = I2S_TX_PDM_FS × 100 Configure the registers according to the needed sampling frequency, upsampling rate, and PDM clock frequency. PDM Channel Configuration Example In this example of I2S, the register configuration is as follows. • I2S_PCM2PDM_CONV_EN = 0, i.e., transmit the raw PDM data. • I2S_TX_MONO = 0, i.e., data is fetched from memory via GDMA in both the high and low levels of WS. • I2S_TX_CHAN_MOD = 2, i.e., mono mode is selected. • I2S_TX_WS_IDLE_POL = 1, i.e., both the left and right channels transmit the left channel data, and the right channel data will be discarded. Once the configuration is done, assume that the data in memory after data format control is: Left Right Left Right ... Left Right Note: 1. The data above refers to the processed data after data format control instead of the original data. 2. “Left” and “Right” represent channel data, and their bit widths are channel valid data width. Please refer to Section 31.9.1� Then the channel data is transmitted after channel mode control as follows. Left LeftLeft Data (Left) = Data (Right) Left Right WS(LRCK) SD(SDOUT) Left I2S_TX_CHAN_MOD = 2; I2S_TX_WS_IDLE_POL = 1; Figure 31.9-3. PDM Channel Control Example Espressif Systems 1100 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) 31.9.3 Synchronous Counter ESP32-C5 I2S TX unit contains synchronous counters to reflect the current I2S data transmission status. The counters can be used to detect I2S transmit data errors or to synchronize data when multiple devices are using I2S for data transmission. ESP32-C5 I2S contains two types of synchronous counters: • I2S_TX_FIFO_CNT – Each time the I2S TX FIFO reads data, the counter is incremented by 1. – The counter can be reset by setting I2S_TX_FIFO_CNT_RST. – The counter is 31-bit wide and is automatically reset to zero on overflow. • I2S_TX_BCK_CNT – Each time I2S TX transmits a BCK cycle, the counter is incremented by 1. – The counter can be reset by setting I2S_TX_BCK_CNT_RST. – The counter is 31-bit wide and is automatically reset to zero on overflow. Note: • Each time the I2S TX FIFO transmits data, a channel data is sent. Therefore, when I2S transmits the data correctly, I2S_TX_BCK_CNT = I2S_TX_FIFO_CNT * the bit width of channel TX data (see Section 31.9.1.4). • When the I2S TX unit transmits the data, there is some delay between fetching data from the FIFO and transmitting it to the line, so the value of I2S_TX_BCK_CNT might be a little different from that of I2S_TX_FIFO_CNT. Application scenarios 1. I2S TX synchronization for multiple devices When multiple devices transmit data through the I2S TX at the same time, desynchronization may occur after a long period of time due to small frequency differences in the clock sources. In this case, read the I2S_TX_FIFO_CNT value of each device to determine the location of the audio data being sent to perform synchronization. 2. I2S TX stability check When the device is in an application scenario with high GDMA usage, there may be numbers missing in I2S TX occasionally due to multiplexing arbitration. In this case, check the ratio of I2S_TX_BCK_CNT to I2S_TX_FIFO_CNT to confirm the stability of the device when running I2S TX. 31.10 Receiving Data In RX mode, I2S first reads data from the peripheral interface and then stores the data in memory via GDMA according to the configured channel mode and data mode. 31.10.1 Channel Mode Control ESP32-C5 I2S supports both TDM RX mode and PDM RX mode. Set I2S_RX_TDM_EN to enable TDM RX mode, or set I2S_RX_PDM_EN to enable PDM RX mode. Espressif Systems 1101 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) Note: I2S_RX_TDM_EN and I2S_RX_PDM_EN must not be cleared or set simultaneously. 31.10.1.1 TDM RX Mode In TDM RX mode, I2S supports up to 16 channels to input data. The total number of RX channels in use is controlled by I2S_RX_TDM_TOT_CHAN_NUM. For example, if I2S_RX_TDM_TOT_CHAN_NUM is set to 5, channel 0-5 will be used to receive data. In these RX channels, if I2S_RX_TDM_CHANn_EN is set to: • 1: The channel data is valid and will be stored into RX FIFO; • 0: The channel data is invalid and will not be stored into RX FIFO. In TDM master mode, WS signal is controlled by I2S_RX_WS_IDLE_POL and I2S_RX_TDM_WS_WIDTH. • I2S_RX_WS_IDLE_POL: The default level of WS signal; • I2S_RX_TDM_WS_WIDTH: The cycles the WS default level lasts for when receiving all channel data. I2S_RX_HALF_SAMPLE_BITS x 2 is equal to the BCK cycles in one WS period. 31.10.1.2 PDM RX Mode In PDM RX mode, I2S supports PDM raw data reception. It converts the serial data from channels to the data to be entered into memory. In PDM RX master mode, the default level of the WS signal is controlled by I2S_RX_WS_IDLE_POL. WS frequency is half of the BCK frequency. The configuration of the BCK signal is similar to that of WS signal as described in Section 31.6. Note, in PDM RX mode, the value of I2S_RX_HALF_SAMPLE_BITS must be same as that of I2S_RX_BITS_MOD. 31.10.2 Data Format Control The data format of I2S is controlled in the following phases: • Phase I: Serial input data is converted into the data to be saved to RX FIFO; • Phase II: The data is read from RX FIFO and converted according to the input data mode. 31.10.2.1 Bit Order Control of Channel Data The channel data will be stored as the data to be input in order from high to low. The data bit order in each channel is controlled by I2S_RX_BIT_ORDER: • 0: The bit order of the data to be input is not reversed; • 1: The bit order of the data to be input is reversed. At this point, the first phase of data format control is completed. The data to be input after bit order control is stored in the RX FIFO. Espressif Systems 1102 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) 31.10.2.2 Bit Width Control of Channel Storage (Valid) Data The storage data width in each channel is controlled by I2S_RX_BITS_MOD and I2S_RX_24_FILL_EN. See the table below. Table 31.10-1. Channel Storage Data Width Channel Storage Data Width I2S_RX_BITS_MOD I2S_RX_24_FILL_EN 32 31 x 23 1 24 23 0 16 15 x 8 7 x 31.10.2.3 Bit Width Control of Channel RX Data The RX data width in each channel is determined by I2S_RX_TDM_CHAN_BITS. • If the storage data width in each channel is smaller than the received (RX) data width, then only the bits within the storage data width is saved into memory. Configure I2S_RX_LEFT_ALIGN to: – 0: Only the lower bits of the received data within the storage data width is stored to memory; – 1: Only the higher bits of the received data within the storage data width is stored to memory. • If the received data width is smaller than the storage data width in each channel, the higher bits of the received data will be filled with zeros and then the data is saved to memory. 31.10.2.4 Endian Control of Channel Storage Data The received data is then converted into storage data (to be stored to memory) after some processing, such as discarding extra bits or filling zeros in missing bits. The endian of the storage data is controlled by I2S_RX_BIG_ENDIAN under various data width. See the table below. Table 31.10-2. Channel Storage Data Endian Channel Storage Data Width Original Data Endian of Processed Data I2S_RX_BIG_ENDIAN 32 {B3, B2, B1, B0} {B3, B2, B1, B0} 0 {B0, B1, B2, B3} 1 24 {B2, B1, B0} {B2, B1, B0} 0 {B0, B1, B2} 1 16 {B1, B0} {B1, B0} 0 {B0, B1} 1 8 {B0} {B0} x 31.10.2.5 A-law/µ-law Compression and Decompression ESP32-C5 I2S compresses/decompresses the storage data in 32-bit by A-law or by µ-law. By default, zeros are filled into high bits. Configure I2S_RX_PCM_BYPASS: Espressif Systems 1103 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) • 0: Compress or decompress the data • 1: Do not compress or decompress the data Configure I2S_RX_PCM_CONF: • 0: Decompress the data using A-law • 1: Compress the data using A-law • 2: Decompress the data using µ-law • 3: Compress the data using µ-law At this point, the data format control is completed. Data then is stored into memory via GDMA. 31.11 Event Task Matrix Feature ESP32-C5 I2S supports the Event Task Matrix (ETM) function, which allows I2S’s ETM tasks to be triggered by any peripherals’ ETM events, or I2S’s ETM events to trigger any peripherals’ ETM tasks. This section introduces the ETM tasks and events related to I2S. For more information, please refer to Chapter 10 Event Task Matrix (ETM). I2S can receive the following ETM tasks: • I2S0_TASK_START_TX: Enables I2S TX for data transfer. • I2S0_TASK_START_RX: Enables I2S RX for data transfer. • I2S0_TASK_STOP_TX: Stops I2S TX data transfer. • I2S0_TASK_STOP_RX: Stops I2S RX data transfer. I2S can generate the following ETM events: • I2S0_EVT_TX_DONE: Indicates that I2S TX has completed data transmission. Triggered when all data in the TX FIFO has been sent. • I2S0_EVT_RX_DONE: Can be triggered in different ways depending on the configured value of I2S_RX_STOP_MODE: – 0: Will not be triggered; – 1: When triggered, indicates that the number of bytes received by I2S RX is greater than the receive length value configured by I2S_RX_EOF_NUM_REG; – 2: When triggered, indicates that the GDMA RX FIFO is full. • I2S0_EVT_X_WORDS_SENT: Indicates that the word number sent by I2S TX is equal to or larger than the value set by I2S_ETM_TX_SEND_WORD_NUM. • I2S0_EVT_X_WORDS_RECEIVED: Indicates that the word number received by I2S RX is equal to or larger than the value set by I2S_ETM_RX_RECEIVE_WORD_NUM. In practical applications, I2S’s ETM events can trigger its own ETM tasks. For example, the I2S_EVT_X_WORDS_SENT event can trigger the I2S_TASK_STOP_TX task, and in this way stop the I2S operation through ETM. Espressif Systems 1104 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) 31.12 I2S Interrupts ESP32-C5’s I2S can generate the I2S_INTR interrupt signal that will be sent to the Interrupt Matrix. There are several internal interrupt sources from I2S that can generate the above interrupt signal(s) as follows: • I2S_TX_HUNG_INT: Triggered when data transmission is timed out. For example, if the I2S module is configured as TX slave mode, but the master does not provide BCK or WS signals for a long time (specified in I2S_LC_HUNG_CONF_REG), this interrupt will be triggered. • I2S_RX_HUNG_INT: Triggered when the data reception is timed out. For example, if the I2S module is configured as RX slave mode, but the master does not transmit data for a long time (specified in I2S_LC_HUNG_CONF_REG), this interrupt will be triggered. • I2S_TX_DONE_INT: Triggered when sending data is complete, i.e., all data in I2S TX FIFO has been sent. • I2S_RX_DONE_INT: Can be triggered in different ways depending on the configured value of I2S_RX_DONE_MODE: – 0: Triggered when the number of bytes received by I2S RX is greater than the receive length value configured by I2S_RX_EOF_NUM_REG; – 1: Triggered when the GDMA RX FIFO is full. Note: For definitions of interrupt, interrupt signal, interrupt source, and their correlations, please refer to Chapter 9 Interrupt Matrix > Section 9.2 Terminology. Each interrupt source can be configured by a common set of registers that are described in Section Interrupt Configuration Registers. The specific registers can be found in Section 31.14 Register Summary. 31.13 Software Configuration Process 31.13.1 Configure I2S as TX Mode Follow the steps below to configure I2S as TX mode via software: 1. Configure the clock as described in Section 31.6. 2. Configure signal pins according to Table 31.4-1. 3. Select the mode needed by configuring I2S_TX_SLAVE_MOD. • 0: Master TX mode • 1: Slave TX mode 4. Set needed TX data mode and TX channel mode as described in Section 31.9, and then set I2S_TX_UPDATE. 5. Reset TX unit and TX FIFO as described in Section 31.7. 6. Enable corresponding interrupts. See Section 31.12. 7. Configure GDMA outlink. Espressif Systems 1105 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) 8. Set I2S_TX_STOP_EN if needed. For more information, please refer to Section 31.8.1. 9. Start transmitting data: • In master mode, wait till I2S slave gets ready, then set I2S_TX_START to start transmitting data; • In slave mode, set I2S_TX_START. When the I2S master supplies BCK and WS signals, I2S slave starts transmitting data. 10. Wait for the interrupt signals set in Step 6, or check whether the transfer is completed by querying I2S_TX_IDLE: • 0: Transmitter is working; • 1: Transmitter is in idle state. 11. Clear I2S_TX_START to stop data transfer. 31.13.2 Configure I2S as RX Mode Follow the steps below to configure I2S as RX mode via software: 1. Configure the clock as described in Section 31.6. 2. Configure signal pins according to Table 31.4-1. 3. Select the mode needed by configuring I2S_RX_SLAVE_MOD. • 0: Master RX mode • 1: Slave RX mode 4. Set needed RX data mode and RX channel mode as described in Section 31.10, and then set I2S_RX_UPDATE. 5. Reset the RX unit and its FIFO according to Section 31.7. 6. Enable the corresponding interrupts. See Section 31.12. 7. Configure GDMA inlink and set the length of RX data by configuring I2S_RX_EOF_NUM_REG. 8. Start receiving data: • In master mode, when the slave is ready, set I2S_RX_START to start receiving data. • In slave mode, set I2S_RX_START to start receiving data when BCK and WS signals are received from the master. 9. The received data is then stored to the specified memory address according to the configuration of GDMA. Then the corresponding interrupt set in step 6 is generated. Espressif Systems 1106 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) 31.14 Register Summary The addresses in this section are relative to I2S base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Interrupt registers I2S_INT_RAW_REG I2S interrupt raw register 0x000C R/SS/WTC I2S_INT_ST_REG I2S interrupt status register 0x0010 RO I2S_INT_ENA_REG I2S interrupt enable register 0x0014 R/W I2S_INT_CLR_REG I2S interrupt clear register 0x0018 WT RX Control and configuration registers I2S_RX_CONF_REG I2S RX configuration register 0x0020 varies I2S_RX_CONF1_REG I2S RX configuration register 1 0x0028 R/W I2S_RX_TDM_CTRL_REG I2S TX TDM mode control register 0x0050 R/W I2S_RXEOF_NUM_REG I2S RX data number control register 0x0064 R/W TX Control and configuration registers I2S_TX_CONF_REG I2S TX configuration register 0x0024 varies I2S_TX_CONF1_REG I2S TX configuration register 1 0x002C R/W I2S_TX_PCM2PDM_CONF_REG I2S TX PCM-to-PDM configuration register 0x0044 R/W I2S_TX_PCM2PDM_CONF1_REG I2S TX PCM-to-PDM configuration register 0x0048 R/W I2S_TX_TDM_CTRL_REG I2S TX TDM mode control register 0x0054 R/W RX clock and timing registers I2S_RX_TIMING_REG I2S RX timing control register 0x0058 R/W TX clock and timing registers I2S_TX_TIMING_REG I2S TX timing control register 0x005C R/W Control and configuration registers I2S_LC_HUNG_CONF_REG I2S timeout configuration register. 0x0060 R/W I2S_CONF_SIGLE_DATA_REG I2S single data register 0x0068 R/W TX status registers I2S_STATE_REG I2S TX status register 0x006C RO ETM register I2S_ETM_CONF_REG I2S ETM configuration register 0x0070 R/W Sync counter registers I2S_FIFO_CNT_REG I2S sync counter register 0x0074 varies I2S_BCK_CNT_REG I2S sync counter register 0x0078 varies Clock registers I2S_CLK_GATE_REG Clock gate register 0x007C R/W Version register I2S_DATE_REG Version control register 0x0080 R/W Espressif Systems 1107 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) 31.15 Registers The addresses in this section are relative to I2S base address provided in Table 4.3-2 in Chapter 4 System and Memory. For how to program reserved fields, please refer to Section Programming Reserved Register Field. Register 31.1. I2S_INT_RAW_REG (0x000C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 4 I2S_TX_HUNG_INT_RAW 0 3 I2S_RX_HUNG_INT_RAW 0 2 I2S_TX_DONE_INT_RAW 0 1 I2S_RX_DONE_INT_RAW 0 0 Reset I2S_RX_DONE_INT_RAW The raw interrupt status of the I2S_RX_DONE_INT interrupt. (R/SS/WTC) I2S_TX_DONE_INT_RAW The raw interrupt status of the I2S_TX_DONE_INT interrupt. (R/SS/WTC) I2S_RX_HUNG_INT_RAW The raw interrupt status of the I2S_RX_HUNG_INT interrupt. (R/SS/WTC) I2S_TX_HUNG_INT_RAW The raw interrupt status of the I2S_TX_HUNG_INT interrupt. (R/SS/WTC) Register 31.2. I2S_INT_ST_REG (0x0010) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 4 I2S_TX_HUNG_INT_ST 0 3 I2S_RX_HUNG_INT_ST 0 2 I2S_TX_DONE_INT_ST 0 1 I2S_RX_DONE_INT_ST 0 0 Reset I2S_RX_DONE_INT_ST The masked interrupt status of the I2S_RX_DONE_INT interrupt. (RO) I2S_TX_DONE_INT_ST The masked interrupt status of the I2S_TX_DONE_INT interrupt. (RO) I2S_RX_HUNG_INT_ST The masked interrupt status of the I2S_RX_HUNG_INT interrupt. (RO) I2S_TX_HUNG_INT_ST The masked interrupt status of the I2S_TX_HUNG_INT interrupt. (RO) Espressif Systems 1108 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) Register 31.3. I2S_INT_ENA_REG (0x0014) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 4 I2S_TX_HUNG_INT_ENA 0 3 I2S_RX_HUNG_INT_ENA 0 2 I2S_TX_DONE_INT_ENA 0 1 I2S_RX_DONE_INT_ENA 0 0 Reset I2S_RX_DONE_INT_ENA Write 1 to enable the I2S_RX_DONE_INT interrupt. (R/W) I2S_TX_DONE_INT_ENA Write 1 to enable the I2S_TX_DONE_INT interrupt. (R/W) I2S_RX_HUNG_INT_ENA Write 1 to enable the I2S_RX_HUNG_INT interrupt. (R/W) I2S_TX_HUNG_INT_ENA Write 1 to enable the I2S_TX_HUNG_INT interrupt. (R/W) Register 31.4. I2S_INT_CLR_REG (0x0018) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 4 I2S_TX_HUNG_INT_CLR 0 3 I2S_RX_HUNG_INT_CLR 0 2 I2S_TX_DONE_INT_CLR 0 1 I2S_RX_DONE_INT_CLR 0 0 Reset I2S_RX_DONE_INT_CLR Write 1 to clear the I2S_RX_DONE_INT interrupt. (WT) I2S_TX_DONE_INT_CLR Write 1 to clear the I2S_TX_DONE_INT interrupt. (WT) I2S_RX_HUNG_INT_CLR Write 1 to clear the I2S_RX_HUNG_INT interrupt. (WT) I2S_TX_HUNG_INT_CLR Write 1 to clear the I2S_TX_HUNG_INT interrupt. (WT) Espressif Systems 1109 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) Register 31.5. I2S_RX_CONF_REG (0x0020) (reserved) 0 0 0 0 0 31 27 I2S_RX_BCK_DIV_NUM 6 26 21 I2S_RX_PDM_EN 0 20 I2S_RX_TDM_EN 0 19 I2S_RX_BIT_ORDER 0 18 I2S_RX_WS_IDLE_POL 0 17 I2S_RX_24_FILL_EN 0 16 I2S_RX_LEFT_ALIGN 1 15 I2S_RX_DONE_MODE 0 14 I2S_RX_MSB_SHIFT 1 13 I2S_RX_PCM_BYPASS 1 12 I2S_RX_PCM_CONF 0x1 11 10 I2S_RX_MONO_FST_VLD 1 9 I2S_RX_UPDATE 0 8 I2S_RX_BIG_ENDIAN 0 7 I2S_RX_MONO 0 6 I2S_RX_STOP_MODE 0 5 4 I2S_RX_SLAVE_MOD 0 3 I2S_RX_START 0 2 I2S_RX_FIFO_RESET 0 1 I2S_RX_RESET 0 0 Reset I2S_RX_RESET Configures whether to reset RX unit. 0: No effect 1: Reset (WT) I2S_RX_FIFO_RESET Configures whether to reset RX FIFO. 0: No effect 1: Reset (WT) I2S_RX_START Configures whether to start receiving data. 0: No effect 1: Start (R/W/SC) I2S_RX_SLAVE_MOD Configures whether to enable slave RX mode. 0: Enable master mode 1: Enable slave mode (R/W) I2S_RX_STOP_MODE Configures when I2S RX stop data reception. 0: Only stops when I2S_RX_START is cleared 1: Stops when I2S_RX_START is cleared or the number of received bytes is greater than the value configured in I2S_RX_EOF_NUM_REG 2: Stops when I2S_RX_START is cleared or GDMA RX FIFO is full (R/W) I2S_RX_MONO Configures whether to enable RX unit in mono mode. 0: Disable 1: Enable (R/W) I2S_RX_BIG_ENDIAN Configures I2S RX byte endian. 0: Low address data is saved to low address 1: Low address data is saved to high address (R/W) Continued on the next page... Espressif Systems 1110 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) Register 31.5. I2S_RX_CONF_REG (0x0020) Continued from the previous page... I2S_RX_UPDATE Configures whether to update I2S RX registers from APB clock domain to I2S RX clock domain. 0: No effect 1: Update This bit will be cleared by hardware after the register update is done. (R/W/SC) I2S_RX_MONO_FST_VLD Configures the valid data channel in I2S RX mono mode. 0: The second channel data valid 1: The first channel data valid (R/W) I2S_RX_PCM_CONF Configures I2S RX compress/decompress mode. 0 (atol): A-law decompress 1 (ltoa): A-law compress 2 (utol): µ-law decompress 3 (ltou): µ-law compress (R/W) I2S_RX_PCM_BYPASS Configures whether to bypass the Compress/Decompress units for received data. 0: No effect 1: Bypass (R/W) I2S_RX_MSB_SHIFT Configures the timing between the WS signal and the MSB of data. 0: Align at the rising edge 1: The WS signal changes one BCK clock earlier (R/W) I2S_RX_DONE_MODE Configures when to trigger the I2S_RX_DONE_INT interrupt. 0: When RX FIFO is full 1: When IN_SUC_EOF is 1 (R/W) I2S_RX_LEFT_ALIGN Configures I2S RX alignment mode. 0: Right alignment mode 1: Left alignment mode (R/W) I2S_RX_24_FILL_EN Configures the bit number that the 24-bit channel data is stored to. 0: Store 24-bit channel data to 24 bits 1: Store 24-bit channel data to 32 bits (Extra bits are filled with zeros) (R/W) Continued on the next page... Espressif Systems 1111 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) Register 31.5. I2S_RX_CONF_REG (0x0020) Continued from the previous page... I2S_RX_WS_IDLE_POL Configures the relationship between WS level and which channel data to receive. 0: WS remains low when receiving left channel data and high when receiving right channel data 1: WS remains high when receiving left channel data and low when receiving right channel data (R/W) I2S_RX_BIT_ORDER Configures whether to reverse the bit order of the I2S RX data to be received. 0: Not reverse 1: Reverse (R/W) I2S_RX_TDM_EN Configures whether to enable I2S TDM RX mode. 0: Disable 1: Enable (R/W) I2S_RX_PDM_EN Configures whether to enable I2S PDM RX mode. 0: Disable 1: Enable (R/W) I2S_RX_BCK_DIV_NUM Configures the divider of BCK in RX mode. Note this divider must not be configured to 1. (R/W) Espressif Systems 1112 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) Register 31.6. I2S_RX_CONF1_REG (0x0028) I2S_RX_TDM_CHAN_BITS 0xf 31 27 I2S_RX_HALF_SAMPLE_BITS 0xf 26 19 I2S_RX_BITS_MOD 0xf 18 14 (reserved) 0 0 0 0 0 13 9 I2S_RX_TDM_WS_WIDTH 0x0 8 0 Reset I2S_RX_TDM_WS_WIDTH Configures the width of I2SI_WS_out (WS default level) at idle level in TDM mode. Width of I2SI_WS_out at idle level in TDM mode = (I2S_RX_TDM_WS_WIDTH[8:0] +1) x T_BCK. (R/W) I2S_RX_BITS_MOD Configures the valid data bit length of I2S RX channel. 7: All the valid channel data is in 8-bit mode 15: All the valid channel data is in 16-bit mode 23: All the valid channel data is in 24-bit mode 31: All the valid channel data is in 32-bit mode Other values are invalid. (R/W) I2S_RX_HALF_SAMPLE_BITS Configures I2S RX sample bits. BCK cycles in one WS period = I2S_RX_HALF_SAMPLE_BITS x 2. (R/W) I2S_RX_TDM_CHAN_BITS Configures RX bit number for each channel in TDM mode. Bit number expected = I2S_RX_TDM_CHAN_BITS + 1. (R/W) Espressif Systems 1113 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) Register 31.7. I2S_RX_TDM_CTRL_REG (0x0050) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 31 20 I2S_RX_TDM_TOT_CHAN_NUM 0x0 19 16 I2S_RX_TDM_CHAN15_EN 1 15 I2S_RX_TDM_CHAN14_EN 1 14 I2S_RX_TDM_CHAN13_EN 1 13 I2S_RX_TDM_CHAN12_EN 1 12 I2S_RX_TDM_CHAN11_EN 1 11 I2S_RX_TDM_CHAN10_EN 1 10 I2S_RX_TDM_CHAN9_EN 1 9 I2S_RX_TDM_CHAN8_EN 1 8 I2S_RX_TDM_PDM_CHAN7_EN 1 7 I2S_RX_TDM_PDM_CHAN6_EN 1 6 I2S_RX_TDM_PDM_CHAN5_EN 1 5 I2S_RX_TDM_PDM_CHAN4_EN 1 4 I2S_RX_TDM_PDM_CHAN3_EN 1 3 I2S_RX_TDM_PDM_CHAN2_EN 1 2 I2S_RX_TDM_PDM_CHAN1_EN 1 1 I2S_RX_TDM_PDM_CHAN0_EN 1 0 Reset I2S_RX_TDM_PDM_CHANn_EN (n: 0-7) Configures whether to enable the valid data input of I2S RX TDM or PDM channel n. 0: Disable. Channel n only inputs 0 1: Enable (R/W) I2S_RX_TDM_CHANn_EN (n: 8-15) Configures whether to enable the valid data input of I2S RX TDM channel n. 0: Disable. Channel n only inputs 0 1: Enable (R/W) I2S_RX_TDM_TOT_CHAN_NUM Configures the total number of channels in use in I2S RX TDM mode. Total channel number in use = I2S_RX_TDM_TOT_CHAN_NUM + 1. (R/W) Register 31.8. I2S_RXEOF_NUM_REG (0x0064) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 I2S_RX_EOF_NUM 0x40 15 0 Reset I2S_RX_EOF_NUM Configures the bit length of RX data. Bit length of RX data = (I2S_RX_BITS_MOD + 1) x (I2S_RX_EOF_NUM + 1). Once the received data reaches such bit length, an AHB_DMA_IN_SUC_EOF_CHn_INT interrupt is triggered in the configured GDMA RX channel. (R/W) Espressif Systems 1114 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) Register 31.9. I2S_TX_CONF_REG (0x0024) (reserved) 0 31 I2S_SIG_LOOPBACK 0 30 I2S_TX_CHAN_MOD 0 29 27 I2S_TX_BCK_DIV_NUM 6 26 21 I2S_TX_PDM_EN 0 20 I2S_TX_TDM_EN 0 19 I2S_TX_BIT_ORDER 0 18 I2S_TX_WS_IDLE_POL 0 17 I2S_TX_24_FILL_EN 0 16 I2S_TX_LEFT_ALIGN 1 15 I2S_TX_BCK_NO_DLY 1 14 I2S_TX_MSB_SHIFT 1 13 I2S_TX_PCM_BYPASS 1 12 I2S_TX_PCM_CONF 0x0 11 10 I2S_TX_MONO_FST_VLD 1 9 I2S_TX_UPDATE 0 8 I2S_TX_BIG_ENDIAN 0 7 I2S_TX_MONO 0 6 I2S_TX_CHAN_EQUAL 0 5 I2S_TX_STOP_EN 1 4 I2S_TX_SLAVE_MOD 0 3 I2S_TX_START 0 2 I2S_TX_FIFO_RESET 0 1 I2S_TX_RESET 0 0 Reset I2S_TX_RESET Configures whether to reset TX unit. 0: No effect 1: Reset (WT) I2S_TX_FIFO_RESET Configures whether to reset TX FIFO. 0: No effect 1: Reset (WT) I2S_TX_START Configures whether to start transmitting data. 0: No effect 1: Start (R/W/SC) I2S_TX_SLAVE_MOD Configures whether to enable slave TX mode. 0: Enable master mode 1: Enable slave mode (R/W) I2S_TX_STOP_EN Configures whether to stop outputting the BCK signal and the WS signal when TX FIFO is empty. 0: No effect 1: Stop (R/W) I2S_TX_CHAN_EQUAL Configures whether to equalize left channel data and right channel data in I2S TX mono mode or TDM mode. 0: The I2S_SINGLE_DATA is invalid channel data in I2S TX mono mode or TDM mode 1: The left channel data is equal to right channel data in I2S TX mono mode or TDM mode (R/W) I2S_TX_MONO Configures whether to enable TX unit in mono mode. 0: Disable 1: Enable (R/W) Continued on the next page... Espressif Systems 1115 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) Register 31.9. I2S_TX_CONF_REG (0x0024) Continued from the previous page... I2S_TX_BIG_ENDIAN Configures I2S TX byte endian. 0: Low address with low address value 1: Low address value to high address (R/W) I2S_TX_UPDATE Configures whether to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done. This bit will be cleared by hardware after update register done. 0: No effect 1: Update (R/W/SC) I2S_TX_MONO_FST_VLD Configures the valid data channel in I2S TX mono mode. 0: The second channel data valid 1: The first channel data valid (R/W) I2S_TX_PCM_CONF Configures the I2S TX compress/decompress mode. 0 (atol): A-law decompress 1 (ltoa): A-law compress 2 (utol): µ-law decompress 3 (ltou): µ-law compress (R/W) I2S_TX_PCM_BYPASS Configures whether to bypass Compress/Decompress units for transmitted data. 0: No effect 1: Bypass (R/W) I2S_TX_MSB_SHIFT Configures the timing between the WS signal and the MSB of data. 0: Align at the rising edge 1: WS signal changes one BCK clock earlier (R/W) I2S_TX_BCK_NO_DLY Configures the source of the BCK rising and falling edges in master mode. 0: Rising and falling edges are constructed based on the BCK input from I2SO_BCK_in 1: Rising and falling edges are constructed by dividing the clock of I2S TX (R/W) I2S_TX_LEFT_ALIGN Configures I2S TX alignment mode. 0: Right alignment mode 1: Left alignment mode (R/W) Continued on the next page... Espressif Systems 1116 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) Register 31.9. I2S_TX_CONF_REG (0x0024) Continued from the previous page... I2S_TX_24_FILL_EN Configures the bit number that the 24 channel bits are stored to. 0: Store 24-bit channel data to 24 bits 1: Store 24-bit channel data to 32 bits (Extra bits are filled with zeros) (R/W) I2S_TX_WS_IDLE_POL Configures the relationship between WS and which channel data to transmit. 0: WS remains low when transmitting left channel data and high when transmitting right channel data 1: WS remains high when transmitting left channel data and low when transmitting right channel data (R/W) I2S_TX_BIT_ORDER Configures whether to reverse the bit order of valid data to be sent by the I2S TX. 0: Not reverse 1: Reverse (R/W) I2S_TX_TDM_EN Configures whether to enable I2S TDM TX mode. 0: Disable 1: Enable (R/W) I2S_TX_PDM_EN Configures whether to enable I2S PDM TX mode. 0: Disable 1: Enable (R/W) I2S_TX_BCK_DIV_NUM Configures the divider of BCK in TX mode. Note this divider must not be configured to 1. (R/W) I2S_TX_CHAN_MOD Configures I2S TX channel mode. For more information, see Table 31.9-4. (R/W) I2S_SIG_LOOPBACK Configures whether to enable TX unit and RX unit sharing the same WS and BCK signals. 0: Disable 1: Enable (R/W) Espressif Systems 1117 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) Register 31.10. I2S_TX_CONF1_REG (0x002C) I2S_TX_TDM_CHAN_BITS 0xf 31 27 I2S_TX_HALF_SAMPLE_BITS 0xf 26 19 I2S_TX_BITS_MOD 0xf 18 14 (reserved) 0 0 0 0 0 13 9 I2S_TX_TDM_WS_WIDTH 0x0 8 0 Reset I2S_TX_TDM_WS_WIDTH Configures the width of I2SO_WS_out (WS default level) at idle level in TDM mode. The width of I2SO_WS_out at idle level in TDM mode = (I2S_TX_TDM_WS_WIDTH[8:0] +1) x T_BCK. (R/W) I2S_TX_BITS_MOD Configures the valid data bit length of I2S TX channel. 7: All the valid channel data is in 8-bit mode 15: All the valid channel data is in 16-bit mode 23: All the valid channel data is in 24-bit mode 31: All the valid channel data is in 32-bit mode Other values are invalid. (R/W) I2S_TX_HALF_SAMPLE_BITS Configures I2S TX sample bits. BCK cycles in one WS period = I2S_TX_HALF_SAMPLE_BITS x 2. (R/W) I2S_TX_TDM_CHAN_BITS Configures TX bit number for each channel in TDM mode. Bit number expected = I2S_TX_TDM_CHAN_BITS + 1. (R/W) Espressif Systems 1118 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) Register 31.11. I2S_TX_PCM2PDM_CONF_REG (0x0044) (reserved) 0 0 0 0 0 0 31 26 I2S_PCM2PDM_CONV_EN 0 25 I2S_TX_PDM_DAC_MODE_EN 0 24 I2S_TX_PDM_DAC_2OUT_EN 0 23 (reserved) 1 22 (reserved) 0 21 (reserved) 0x1 20 19 (reserved) 0x1 18 17 (reserved) 0x1 16 15 (reserved) 0x1 14 13 (reserved) 0x0 12 5 I2S_TX_PDM_SINC_OSR2 0x2 4 1 (reserved) 0 0 Reset I2S_TX_PDM_SINC_OSR2 Configures I2S TX PDM OSR value. (R/W) I2S_TX_PDM_DAC_2OUT_EN Configures whether to enable I2S TX PDM DAC mode. 0: Enable 1-line DAC output mode 1: Enable 2-line DAC output mode Only valid when I2S_TX_PDM_DAC_MODE_EN is set. (R/W) I2S_TX_PDM_DAC_MODE_EN Configures whether to enable 1-line PDM output mode or DAC out- put mode. 0: Enable 1-line PDM output mode 1: Enable DAC output mode (R/W) I2S_PCM2PDM_CONV_EN Configures whether to enable the I2S TX PCM-to-PDM converter. 0: Disable 1: Enable (R/W) Register 31.12. I2S_TX_PCM2PDM_CONF1_REG (0x0048) (reserved) 0 0 0 0 0 0 31 26 (reserved) 7 25 23 (reserved) 7 22 20 I2S_TX_PDM_FS 480 19 10 (reserved) 960 9 0 Reset I2S_TX_PDM_FS Configures I2S PDM TX upsampling parameter. (R/W) Espressif Systems 1119 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) Register 31.13. I2S_TX_TDM_CTRL_REG (0x0054) (reserved) 0 0 0 0 0 0 0 0 0 0 0 31 21 I2S_TX_TDM_SKIP_MSK_EN 0 20 I2S_TX_TDM_TOT_CHAN_NUM 0x0 19 16 I2S_TX_TDM_CHAN15_EN 1 15 I2S_TX_TDM_CHAN14_EN 1 14 I2S_TX_TDM_CHAN13_EN 1 13 I2S_TX_TDM_CHAN12_EN 1 12 I2S_TX_TDM_CHAN11_EN 1 11 I2S_TX_TDM_CHAN10_EN 1 10 I2S_TX_TDM_CHAN9_EN 1 9 I2S_TX_TDM_CHAN8_EN 1 8 I2S_TX_TDM_CHAN7_EN 1 7 I2S_TX_TDM_CHAN6_EN 1 6 I2S_TX_TDM_CHAN5_EN 1 5 I2S_TX_TDM_CHAN4_EN 1 4 I2S_TX_TDM_CHAN3_EN 1 3 I2S_TX_TDM_CHAN2_EN 1 2 I2S_TX_TDM_CHAN1_EN 1 1 I2S_TX_TDM_CHAN0_EN 1 0 Reset I2S_TX_TDM_CHANn_EN (n: 0-15) Configures whether to enable the valid data output of I2S TX TDM channel n. 0: Channel TX data is controlled by I2S_TX_CHAN_EQUAL and I2S_SINGLE_DATA. See Section 31.9.2.1 1: Enable (R/W) I2S_TX_TDM_TOT_CHAN_NUM Configures the total number of channels in use in I2S TX TDM mode. Total channel number in use = I2S_TX_TDM_TOT_CHAN_NUM + 1. (R/W) I2S_TX_TDM_SKIP_MSK_EN Configures the data to be sent in GDMA TX buffer. 0: Data stored in GDMA TX buffer is used by enabled channels and will not be read by channels that are not enabled 1: Data stored in GDMA TX buffer is read by all channels and will be skipped by channels that are not enabled (R/W) Espressif Systems 1120 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) Register 31.14. I2S_RX_TIMING_REG (0x0058) (reserved) 0 0 31 30 I2S_RX_BCK_IN_DM 0x0 29 28 (reserved) 0 0 27 26 I2S_RX_WS_IN_DM 0x0 25 24 (reserved) 0 0 23 22 I2S_RX_BCK_OUT_DM 0x0 21 20 (reserved) 0 0 19 18 I2S_RX_WS_OUT_DM 0x0 17 16 (reserved) 0 0 15 14 I2S_RX_SD3_IN_DM 0x0 13 12 (reserved) 0 0 11 10 I2S_RX_SD2_IN_DM 0x0 9 8 (reserved) 0 0 7 6 I2S_RX_SD1_IN_DM 0x0 5 4 (reserved) 0 0 3 2 I2S_RX_SD_IN_DM 0x0 1 0 Reset I2S_RX_SD_IN_DM Configures the delay mode of I2S RX SD input signal. 0: Bypass 1: Delay by rising edge 2: Delay by falling edge 3: Invalid (R/W) I2S_RX_SD1_IN_DM Configures the delay mode of I2S RX SD1 input signal. For detailed configura- tion values, please refer to I2S_RX_SD_IN_DM. (R/W) I2S_RX_SD2_IN_DM Configures the delay mode of I2S RX SD2 input signal. For detailed configura- tion values, please refer to I2S_RX_SD_IN_DM. (R/W) I2S_RX_SD3_IN_DM Configures the delay mode of I2S RX SD3 input signal. For detailed configura- tion values, please refer to I2S_RX_SD_IN_DM. (R/W) I2S_RX_WS_OUT_DM Configures the delay mode of I2S RX WS output signal. For detailed config- uration values, please refer to I2S_RX_SD_IN_DM. (R/W) I2S_RX_BCK_OUT_DM Configures the delay mode of I2S RX BCK output signal. For detailed con- figuration values, please refer to I2S_RX_SD_IN_DM. (R/W) I2S_RX_WS_IN_DM Configures the delay mode of I2S RX WS input signal. For detailed configuration values, please refer to I2S_RX_SD_IN_DM. (R/W) I2S_RX_BCK_IN_DM Configures the delay mode of I2S RX BCK input signal. For detailed configu- ration values, please refer to I2S_RX_SD_IN_DM. (R/W) Espressif Systems 1121 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) Register 31.15. I2S_TX_TIMING_REG (0x005C) (reserved) 0 0 31 30 I2S_TX_BCK_IN_DM 0x0 29 28 (reserved) 0 0 27 26 I2S_TX_WS_IN_DM 0x0 25 24 (reserved) 0 0 23 22 I2S_TX_BCK_OUT_DM 0x0 21 20 (reserved) 0 0 19 18 I2S_TX_WS_OUT_DM 0x0 17 16 (reserved) 0 0 0 0 0 0 0 0 0 0 15 6 I2S_TX_SD1_OUT_DM 0x0 5 4 (reserved) 0 0 3 2 I2S_TX_SD_OUT_DM 0x0 1 0 Reset I2S_TX_SD_OUT_DM Configures the delay mode of I2S TX SD output signal. 0: Bypass 1: Delay by rising edge 2: Delay by falling edge 3: Invalid (R/W) I2S_TX_SD1_OUT_DM Configures the delay mode of I2S TX SD1 output signal. For detailed config- uration values, please refer to I2S_TX_SD_OUT_DM. (R/W) I2S_TX_WS_OUT_DM Configures the delay mode of I2S TX WS output signal. For detailed configu- ration values, please refer to I2S_TX_SD_OUT_DM. (R/W) I2S_TX_BCK_OUT_DM Configures the delay mode of I2S TX BCK output signal. For detailed con- figuration values, please refer to I2S_TX_SD_OUT_DM. (R/W) I2S_TX_WS_IN_DM Configures the delay mode of I2S TX WS input signal. For detailed configuration values, please refer to I2S_TX_SD_OUT_DM. (R/W) I2S_TX_BCK_IN_DM Configures the delay mode of I2S TX BCK input signal. For detailed configura- tion values, please refer to I2S_TX_SD_OUT_DM. (R/W) Espressif Systems 1122 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) Register 31.16. I2S_LC_HUNG_CONF_REG (0x0060) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 12 I2S_LC_FIFO_TIMEOUT_ENA 1 11 I2S_LC_FIFO_TIMEOUT_SHIFT 0 10 8 I2S_LC_FIFO_TIMEOUT 0x10 7 0 Reset I2S_LC_FIFO_TIMEOUT Configures the FIFO timeout threshold. The FIFO hung counter is incre- mented by one each time I2S is in an error state and the tick counter reaches its threshold. I2S_TX_HUNG_INT or I2S_RX_HUNG_INT interrupt will be triggered when FIFO hung counter is equal to the FIFO timeout threshold. (R/W) I2S_LC_FIFO_TIMEOUT_SHIFT Configures the tick counter threshold. The tick counter is incre- mented by one each time I2S is in an error state and it is on the rising edge in each system clock (APB). The tick counter is reset when counter value >= 88000/2 I2S_LC_F IF O_T IMEOU T _SHIF T . (R/W) I2S_LC_FIFO_TIMEOUT_ENA Configures whether to enable FIFO timeout. 0: Disable 1: Enable (R/W) Register 31.17. I2S_CONF_SIGLE_DATA_REG (0x0068) I2S_SINGLE_DATA 0 31 0 Reset I2S_SINGLE_DATA Configures constant channel data to be sent out. (R/W) Espressif Systems 1123 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) Register 31.18. I2S_STATE_REG (0x006C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 I2S_TX_IDLE 1 0 Reset I2S_TX_IDLE Represents the TX unit state. 0: I2S TX unit is working 1: I2S TX unit is in idle state (RO) Register 31.19. I2S_ETM_CONF_REG (0x0070) (reserved) 0 0 0 0 31 28 I2S_ETM_RX_RECEIVE_WORD_NUM 0x40 27 14 I2S_ETM_TX_SEND_WORD_NUM 0x40 13 0 Reset I2S_ETM_TX_SEND_WORD_NUM Configures the threshold of triggering ETM I2S_TX_X_WORDS_SENT event. When transmitting word number of I2S_ETM_TX_SEND_WORD_NUM [9:0], I2S will trigger the corresponding ETM event. (R/W) I2S_ETM_RX_RECEIVE_WORD_NUM Configures the threshold of triggering ETM I2S_RX_X_WORDS_RECEIVED event. When receiving word number of I2S_ETM_RX_RECEIVE_WORD_NUM [9:0], I2S will trigger the corresponding ETM event. (R/W) Espressif Systems 1124 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) Register 31.20. I2S_FIFO_CNT_REG (0x0074) I2S_TX_FIFO_CNT_RST 0 31 I2S_TX_FIFO_CNT 0x000000 30 0 Reset I2S_TX_FIFO_CNT Configures the TX FIFO counter value. (RO) I2S_TX_FIFO_CNT_RST Configure whether to reset the TX FIFO counter. 0: No effect 1: Reset (WT) Register 31.21. I2S_BCK_CNT_REG (0x0078) I2S_TX_BCK_CNT_RST 0 31 I2S_TX_BCK_CNT 0x000000 30 0 Reset I2S_TX_BCK_CNT Configures the TX BCK counter value. (RO) I2S_TX_BCK_CNT_RST Configures whether to reset TC BCK counter. 0: No effect 1: Reset (WT) Register 31.22. I2S_CLK_GATE_REG (0x007C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 I2S_CLK_EN 0 0 Reset I2S_CLK_EN Configures whether to enable clock gate. 0: Disable 1: Enable (R/W) Espressif Systems 1125 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 31 I2S Controller (I2S) Register 31.23. I2S_DATE_REG (0x0080) (reserved) 0 0 0 0 31 28 I2S_DATE 0x2307190 27 0 Reset I2S_DATE Version control register. (R/W) Espressif Systems 1126 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 32 Pulse Count Controller (PCNT) Chapter 32 Pulse Count Controller (PCNT) The pulse count controller (PCNT) is designed to count input pulses. It can increment or decrement a pulse counter value by keeping track of rising (positive) or falling (negative) edges of the input pulse signal. The PCNT has four independent pulse counters called units, which have their groups of registers. There is only one clock in PCNT, which is APB_CLK. In this chapter, n denotes the number of a unit from 0 3. Each unit includes two channels (ch0 and ch1) which can independently increment or decrement its pulse counter value. The remainder of the chapter will mostly focus on channel 0 (ch0) as the functionality of the two channels is identical. As shown in Figure 32.0-1, each channel has two input signals: 1. One input pulse signal (e.g. sig_ch0_un, the input pulse signal for ch0 of unit n ch0) 2. One control signal (e.g. ctrl_ch0_un, the control signal for ch0 of unit n ch0) Figure 32.0-1. PCNT Block Diagram Espressif Systems 1127 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 32 Pulse Count Controller (PCNT) 32.1 Features A PCNT has the following features: • Four independent pulse counters (units) that count from 1 to 65535 • Each unit consists of two independent channels sharing one pulse counter • All channels have input pulse signals (e.g. sig_ch0_un) with their corresponding control signals (e.g. ctrl_ch0_un) • Independently filter glitches of input pulse signals (sig_ch0_un and sig_ch1_un) and control signals (ctrl_ch0_un and ctrl_ch1_un) on each unit • Each channel has the following parameters: 1. Selection between counting on positive or negative edges of the input pulse signal 2. Configuration to Increment, Decrement, or Disable counter mode for control signal’s high and low states 3. Step count alert triggered by setting the upcount/downcount step threshold 4. Clearing of the pulse count controller value by setting the clear register or sending a clear signal through GPIO input 5. Generation and recording of a corresponding event signal for each counter mode, with the ability to report it to the interrupt task. • Maximum frequency of input pulses: f AP B_CLK 2 Espressif Systems 1128 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 32 Pulse Count Controller (PCNT) 32.2 Functional Description Figure 32.2-1. PCNT Unit Architecture Figure 32.2-1 shows PCNT’s architecture. As stated above, ctrl_ch0_un is the control signal for ch0 of unit n. Its high and low states can be assigned with different counter modes to count the channel’s input pulse signal sig_ch0_un on negative or positive edges. The available counter modes are as follows: • Increment mode: When a channel detects an active edge of sig_ch0_un (the active edge can be configured by software), the counter value pulse_cnt increases by 1. Upon reaching PCNT_CNT_H_LIM_Un, pulse_cnt is cleared. If the channel’s counter mode is changed or if PCNT_CNT_PAUSE_Un is set to 1 before pulse_cnt reaches PCNT_CNT_H_LIM_Un, then pulse_cnt freezes and its counter mode changes. • Decrement mode: When a channel detects an active edge of sig_ch0_un (the active edge can be configured by software), the counter value pulse_cnt decreases by 1. Upon reaching PCNT_CNT_L_LIM_Un, pulse_cnt is cleared. If the channel’s counter mode is changed or if Espressif Systems 1129 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 32 Pulse Count Controller (PCNT) PCNT_CNT_PAUSE_Un is set to 1 before pulse_cnt reaches PCNT_CNT_L_LIM_Un, then pulse_cnt freezes and its counter mode changes. • Disable mode: Counting is disabled, and the counter value pulse_cnt freezes. Table 32.2-1 to Table 32.2-4 provide information on how to configure the counter mode for channel 0. Table 32.2-1. Counter Mode. Positive Edge of Input Pulse Signal. Control Signal in Low State PCNT_CH0_POS_MODE_Un PCNT_CH0_LCTRL_MODE_Un Counter Mode 1 0 Increment 1 Decrement Others Disable 2 0 Decrement 1 Increment Others Disable Others N/A Disable Table 32.2-2. Counter Mode. Positive Edge of Input Pulse Signal. Control Signal in High State PCNT_CH0_POS_MODE_Un PCNT_CH0_HCTRL_MODE_Un Counter Mode 1 0 Increment 1 Decrement Others Disable 2 0 Decrement 1 Increment Others Disable Others N/A Disable Table 32.2-3. Counter Mode. Negative Edge of Input Pulse Signal. Control Signal in Low State PCNT_CH0_NEG_MODE_Un PCNT_CH0_LCTRL_MODE_Un Counter Mode 1 0 Increment 1 Decrement Others Disable 2 0 Decrement 1 Increment Others Disable Others N/A Disable Espressif Systems 1130 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 32 Pulse Count Controller (PCNT) Table 32.2-4. Counter Mode. Negative Edge of Input Pulse Signal. Control Signal in High State PCNT_CH0_NEG_MODE_Un PCNT_CH0_HCTRL_MODE_Un Counter Mode 1 0 Increment 1 Decrement Others Disable 2 0 Decrement 1 Increment Others Disable Others N/A Disable Each unit has one filter for all its control and input pulse signals. The filter can be enabled with the bit PCNT_FILTER_EN_Un. It monitors the signals and ignores all the noise, i.e. the glitches with pulse widths shorter than PCNT_FILTER_THRES_Un APB clock cycles in length. As shown on Figure 32.2-1, each unit has two channels which process different input pulse signals and increase or decrease values via their respective inc_dec modules, then the two channels send these values to the adder module which has a 16-bit wide signed register. This adder can be suspended by setting PCNT_CNT_PAUSE_Un, and cleared by setting PCNT_PULSE_CNT_RST_Un. The PCNT has seven count event watchpoints that share one interrupt. The interrupt can be enabled or disabled by interrupt enable signals of each individual count event watchpoint. Here are the trigger methods for the count events that can be configured and reported by the PCNT, along with their corresponding interrupt events: • Maximum count value: When pulse_cnt reaches PCNT_CNT_H_LIM_Un, a high limit interrupt is triggered and PCNT_CNT_THR_H_LIM_LAT_Un is high. • Minimum count value: When pulse_cnt reaches PCNT_CNT_L_LIM_Un, a low limit interrupt is triggered and PCNT_CNT_THR_L_LIM_LAT_Un is high. • Two threshold values: When pulse_cnt equals either PCNT_CNT_THRES0_Un or PCNT_CNT_THRES1_Un, an interrupt is triggered and either PCNT_CNT_THR_THRES0_LAT_Un or PCNT_CNT_THR_THRES1_LAT_Un is high respectively. • Zero: When pulse_cnt is 0, an interrupt is triggered and PCNT_CNT_THR_ZERO_LAT_Un is valid. • Upcount Step Threshold: If PCNT_DALTA_CHANGE_EN_Un is set to high, when pulse_cnt exceeds PCNT_CNT_H_STEP_Un during incrementing, an overflow interrupt is generated, and PCNT_CNT_THR_H_STEP_LAT_Un is set to high. For example, if PCNT_CNT_H_STEP_Un is set to 100, an interrupt will be triggered each time the pulse_cnt reaches integer multiples such as 100, 200, 300, and so on. This type of interrupt can be used to periodically monitor whether the number of input pulses has reached a specified multiple, facilitating functions such as quantitative sampling, data statistics, or regular event handling. • Downcount Step Threshold: If PCNT_DALTA_CHANGE_EN_Un is set to high, when pulse_cnt falls below PCNT_CNT_L_STEP_Un during decrementing, an overflow interrupt is generated, and PCNT_CNT_THR_L_STEP_LAT_Un is set to high. For example, if PCNT_DALTA_CHANGE_EN_Un is set to 100, an interrupt will be triggered each time the pulse_cnt decreases to integer multiples such as 100, 200, 300, and so on. This type of interrupt is Espressif Systems 1131 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 32 Pulse Count Controller (PCNT) suitable for periodically monitoring whether the count has decreased by a specified multiple, facilitating quantitative sampling, data statistics, or regular event handling. If PCNT_CNT_H_LIM_Un and/or PCNT_CNT_L_LIM_Un are reconfigured by software when PCNT is working, the new configuration will take effect after pluse_cnt counts to any of the above seven watchpoints; if PCNT_CNT_THRES0_Un, PCNT_CNT_THRES1_Un, PCNT_CNT_H_STEP_Un and/or PCNT_CNT_L_STEP_Un are reconfigured by software, the new configuration will take effect immediately. 32.3 Applications In each unit, channel 0 and channel 1 can be configured to work independently or together. The three subsections below provide details of channel 0 incrementing independently, channel 0 decrementing independently, and channel 0 and channel 1 incrementing together. For other working modes not elaborated in this section (e.g. channel 1 incrementing/decremeting independently, or one channel incrementing while the other decrementing), reference can be made to these three subsections. 32.3.1 Channel 0 Incrementing Independently Figure 32.3-1. Channel 0 Up Counting Diagram Figure 32.3-1 illustrates how channel 0 is configured to increment independently on the positive edge of sig_ch0_un while channel 1 is disabled (see subsection 32.2 for how to disable channel 1). The configuration of channel 0 is shown below. • PCNT_CH0_LCTRL_MODE_Un=0: When ctrl_ch0_un is low, the counter mode specified for the low state turns on, in this case it is Increment mode. • PCNT_CH0_HCTRL_MODE_Un=2: When ctrl_ch0_un is high, the counter mode specified for the low state turns on, in this case it is Disable mode. • PCNT_CH0_POS_MODE_Un=1: The counter increments on the positive edge of sig_ch0_un. • PCNT_CH0_NEG_MODE_Un=0: The counter idles on the negative edge of sig_ch0_un. • PCNT_CNT_H_LIM_Un=5: When pulse_cnt counts up to PCNT_CNT_H_LIM_Un, it is cleared. Espressif Systems 1132 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 32 Pulse Count Controller (PCNT) 32.3.2 Channel 0 Decrementing Independently Figure 32.3-2. Channel 0 Down Counting Diagram Figure 32.3-2 illustrates how channel 0 is configured to decrement independently on the positive edge of sig_ch0_un while channel 1 is disabled. The configuration of channel 0 in this case differs from that in Figure 32.3-1 in the following aspects: • PCNT_CH0_POS_MODE_Un=2: the counter decrements on the positive edge of sig_ch0_un. • PCNT_CNT_L_LIM_Un=-5: when pulse_cnt counts down to PCNT_CNT_L_LIM_Un, it is cleared. 32.3.3 Channel 0 and Channel 1 Incrementing Together Figure 32.3-3. Two Channels Up Counting Diagram Figure 32.3-3 illustrates how channel 0 and channel 1 are configured to increment on the positive edge of sig_ch0_un and sig_ch1_un respectively at the same time. It can be seen in Figure 32.3-3 that control signal ctrl_ch0_un and ctrl_ch1_un have the same waveform, so as input pulse signal sig_ch0_un and sig_ch1_un. The configuration procedure is shown below. • For channel 0: – PCNT_CH0_LCTRL_MODE_Un=0: When ctrl_ch0_un is low, the counter mode specified for the low state turns on, in this case it is Increment mode. – PCNT_CH0_HCTRL_MODE_Un=2: When ctrl_ch0_un is high, the counter mode specified for the low state turns on, in this case it is Disable mode. – PCNT_CH0_POS_MODE_Un=1: The counter increments on the positive edge of sig_ch0_un. – PCNT_CH0_NEG_MODE_Un=0: The counter idles on the negative edge of sig_ch0_un. Espressif Systems 1133 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 32 Pulse Count Controller (PCNT) • For channel 1: – PCNT_CH1_LCTRL_MODE_Un=0: When ctrl_ch1_un is low, the counter mode specified for the low state turns on, in this case it is Increment mode. – PCNT_CH1_HCTRL_MODE_Un=2: When ctrl_ch1_un is high, the counter mode specified for the low state turns on, in this case it is Disable mode. – PCNT_CH1_POS_MODE_Un=1: The counter increments on the positive edge of sig_ch1_un. – PCNT_CH1_NEG_MODE_Un=0: The counter idles on the negative edge of sig_ch1_un. • PCNT_CNT_H_LIM_Un=10: When pulse_cnt counts up to PCNT_CNT_H_LIM_Un, it is cleared. Espressif Systems 1134 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 32 Pulse Count Controller (PCNT) 32.4 Register Summary The addresses in this section are relative to Pulse Count Controller base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Configuration Register PCNT_U0_CONF0_REG Configuration register 0 for unit 0 0x0000 R/W PCNT_U0_CONF1_REG Configuration register 1 for unit 0 0x0004 R/W PCNT_U0_CONF2_REG Configuration register 2 for unit 0 0x0008 R/W PCNT_U0_CONF3_REG Configuration register for unit 0’s step value. 0x000C R/W PCNT_U1_CONF0_REG Configuration register 0 for unit 1 0x0010 R/W PCNT_U1_CONF1_REG Configuration register 1 for unit 1 0x0014 R/W PCNT_U1_CONF2_REG Configuration register 2 for unit 1 0x0018 R/W PCNT_U1_CONF3_REG Configuration register for unit 1’s step value. 0x001C R/W PCNT_U2_CONF0_REG Configuration register 0 for unit 2 0x0020 R/W PCNT_U2_CONF1_REG Configuration register 1 for unit 2 0x0024 R/W PCNT_U2_CONF2_REG Configuration register 2 for unit 2 0x0028 R/W PCNT_U2_CONF3_REG Configuration register for unit 2’s step value. 0x002C R/W PCNT_U3_CONF0_REG Configuration register 0 for unit 3 0x0030 R/W PCNT_U3_CONF1_REG Configuration register 1 for unit 3 0x0034 R/W PCNT_U3_CONF2_REG Configuration register 2 for unit 3 0x0038 R/W PCNT_U3_CONF3_REG Configuration register for unit 3’s step value. 0x003C R/W PCNT_CTRL_REG Control register for all counters 0x0070 R/W Status Register PCNT_U0_CNT_REG Counter value for unit 0 0x0040 RO PCNT_U1_CNT_REG Counter value for unit 1 0x0044 RO PCNT_U2_CNT_REG Counter value for unit 2 0x0048 RO PCNT_U3_CNT_REG Counter value for unit 3 0x004C RO PCNT_U0_STATUS_REG PNCT UNIT0 status register 0x0060 RO PCNT_U1_STATUS_REG PNCT UNIT1 status register 0x0064 RO PCNT_U2_STATUS_REG PNCT UNIT2 status register 0x0068 RO PCNT_U3_STATUS_REG PNCT UNIT3 status register 0x006C RO Interrupt Register PCNT_INT_RAW_REG Interrupt raw status register 0x0050 R/WTC/SS PCNT_INT_ST_REG Interrupt status register 0x0054 RO PCNT_INT_ENA_REG Interrupt enable register 0x0058 R/W PCNT_INT_CLR_REG Interrupt clear register 0x005C WT Version Register PCNT_DATE_REG PCNT version control register 0x00FC R/W Espressif Systems 1135 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 32 Pulse Count Controller (PCNT) 32.5 Registers The addresses in this section are relative to Pulse Count Controller base address provided in Table 4.3-2 in Chapter 4 System and Memory. Espressif Systems 1136 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 32 Pulse Count Controller (PCNT) Register 32.1. PCNT_Un_CONF0_REG (n: 0-3) (0x0000+0x10*n) PCNT_CH1_LCTRL_MODE_Un 0x0 31 30 PCNT_CH1_HCTRL_MODE_Un 0x0 29 28 PCNT_CH1_POS_MODE_Un 0x0 27 26 PCNT_CH1_NEG_MODE_Un 0x0 25 24 PCNT_CH0_LCTRL_MODE_Un 0x0 23 22 PCNT_CH0_HCTRL_MODE_Un 0x0 21 20 PCNT_CH0_POS_MODE_Un 0x0 19 18 PCNT_CH0_NEG_MODE_Un 0x0 17 16 PCNT_THR_THRES1_EN_Un 0 15 PCNT_THR_THRES0_EN_Un 0 14 PCNT_THR_L_LIM_EN_Un 1 13 PCNT_THR_H_LIM_EN_Un 1 12 PCNT_THR_ZERO_EN_Un 1 11 PCNT_FILTER_EN_Un 1 10 PCNT_FILTER_THRES_Un 0x10 9 0 Reset PCNT_FILTER_THRES_Un Configures the maximum threshold for the filter. Any pulses with width less than this will be ignored when the filter is enabled. Measurement unit: APB_CLK cycles. (R/W) PCNT_FILTER_EN_Un This is the enable bit for unit n’s input filter. (R/W) PCNT_THR_ZERO_EN_Un This is the enable bit for unit n’s zero comparator. (R/W) PCNT_THR_H_LIM_EN_Un This is the enable bit for unit n’s thr_h_lim comparator. Configures it to enable the high limit interrupt. (R/W) PCNT_THR_L_LIM_EN_Un This is the enable bit for unit n’s thr_l_lim comparator. Configures it to enable the low limit interrupt. (R/W) PCNT_THR_THRES0_EN_Un This is the enable bit for unit n’s thres0 comparator. (R/W) PCNT_THR_THRES1_EN_Un This is the enable bit for unit n’s thres1 comparator. (R/W) PCNT_CH0_NEG_MODE_Un Configures the behavior when the signal input of channel 0 detects a negative edge. 1: Increment the counter 2: Decrement the counter 0, 3: No effect (R/W) PCNT_CH0_POS_MODE_Un Configures the behavior when the signal input of channel 0 detects a positive edge. 1: Increment the counter 2: Decrement the counter 0, 3: No effect (R/W) PCNT_CH0_HCTRL_MODE_Un Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is high. 0: No modification 1: Invert the behavior (increase -> decrease, decrease -> increase) 2, 3: Inhibit counter modification (R/W) Continued on the next page... Espressif Systems 1137 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 32 Pulse Count Controller (PCNT) Register 32.1. PCNT_Un_CONF0_REG (n: 0-3) (0x0000+0x10*n) Continued from the previous page... PCNT_CH0_LCTRL_MODE_Un Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is low. 0: No modification 1: Invert the behavior (increase -> decrease, decrease -> increase) 2, 3: Inhibit counter modification (R/W) PCNT_CH1_NEG_MODE_Un Configures the behavior when the signal input of channel 1 detects a negative edge. 1: Increment the counter 2: Decrement the counter 0, 3: No effect (R/W) PCNT_CH1_POS_MODE_Un Configures the behavior when the signal input of channel 1 detects a positive edge. 1: Increment the counter 2: Decrement the counter 0, 3: No effect (R/W) PCNT_CH1_HCTRL_MODE_Un Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is high. 0: No modification 1: Invert the behavior (increase -> decrease, decrease -> increase) 2, 3: Inhibit counter modification (R/W) PCNT_CH1_LCTRL_MODE_Un Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is low. 0: No modification 1: Invert the behavior (increase -> decrease, decrease -> increase) 2, 3: Inhibit counter modification (R/W) Espressif Systems 1138 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 32 Pulse Count Controller (PCNT) Register 32.2. PCNT_Un_CONF1_REG (n: 0-3) (0x0004+0x10*n) PCNT_CNT_THRES1_Un 0x00 31 16 PCNT_CNT_THRES0_Un 0x00 15 0 Reset PCNT_CNT_THRES0_Un Configures the thres0 value for unit n. (R/W) PCNT_CNT_THRES1_Un Configures the thres1 value for unit n. (R/W) Register 32.3. PCNT_Un_CONF2_REG (n: 0-3) (0x0008+0x10*n) PCNT_CNT_L_LIM_Un 0x00 31 16 PCNT_CNT_H_LIM_Un 0x00 15 0 Reset PCNT_CNT_H_LIM_Un Configures the thr_h_lim value for unit n. When pulse_cnt reaches this value, the counter will be cleared to 0. (R/W) PCNT_CNT_L_LIM_Un Configures the thr_l_lim value for unit n. When pulse_cnt reaches this value, the counter will be cleared to 0. (R/W) Register 32.4. PCNT_Un_CONF3_REG (n: 0-3) (0x000C+0x10*n) PCNT_CNT_L_STEP_Un 0x00 31 16 PCNT_CNT_H_STEP_Un 0x00 15 0 Reset PCNT_CNT_H_STEP_Un Configures the upcount step threshold value for unit n. (R/W) PCNT_CNT_L_STEP_Un Configures the downcount step threshold for unit n. (R/W) Espressif Systems 1139 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 32 Pulse Count Controller (PCNT) Register 32.5. PCNT_CTRL_REG (0x0070) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 17 PCNT_CLK_EN 0 16 (reserved) 0 0 0 0 15 12 PCNT_DALTA_CHANGE_EN_U3 0 11 PCNT_DALTA_CHANGE_EN_U2 0 10 PCNT_DALTA_CHANGE_EN_U1 0 9 PCNT_DALTA_CHANGE_EN_U0 0 8 PCNT_CNT_PAUSE_U3 0 7 PCNT_PULSE_CNT_RST_U3 1 6 PCNT_CNT_PAUSE_U2 0 5 PCNT_PULSE_CNT_RST_U2 1 4 PCNT_CNT_PAUSE_U1 0 3 PCNT_PULSE_CNT_RST_U1 1 2 PCNT_CNT_PAUSE_U0 0 1 PCNT_PULSE_CNT_RST_U0 1 0 Reset PCNT_PULSE_CNT_RST_Un (n: 0-3) Write 1 to clear unit n’s counter. 0: No effect 1: Clear (R/W) PCNT_CNT_PAUSE_Un (n: 0-3) Write 1 to freeze unit n’s counter. 0: No effect 1: Freeze (R/W) PCNT_DALTA_CHANGE_EN_Un (n: 0-3) Configures this bit to enable unit n’s step comparator. (R/W) PCNT_CLK_EN Configures whether or not to enable the registers clock gate of the PCNT module. 0: The registers can not be read or written by application 1: The registers can be read and written by application (R/W) Register 32.6. PCNT_Un_CNT_REG (n: 0-3) (0x0040+0x4*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 PCNT_PULSE_CNT_Un 0x00 15 0 Reset PCNT_PULSE_CNT_Un Represents the current pulse count value for unit n. (RO) Espressif Systems 1140 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 32 Pulse Count Controller (PCNT) Register 32.7. PCNT_Un_STATUS_REG (n: 0-3) (0x0060+0x4*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 9 PCNT_CNT_THR_L_STEP_LAT_Un 0 8 PCNT_CNT_THR_H_STEP_LAT_Un 0 7 PCNT_CNT_THR_ZERO_LAT_Un 0 6 PCNT_CNT_THR_H_LIM_LAT_Un 0 5 PCNT_CNT_THR_L_LIM_LAT_Un 0 4 PCNT_CNT_THR_THRES0_LAT_Un 0 3 PCNT_CNT_THR_THRES1_LAT_Un 0 2 PCNT_CNT_THR_ZERO_MODE_Un 0x0 1 0 Reset PCNT_CNT_THR_ZERO_MODE_Un Represents the pulse counter status of PCNT_Un correspond- ing to 0. 0: The pulse counter decreases from positive to 0 1: The pulse counter increases from negative to 0 2: The pulse counter is negative 3: The pulse counter is positive (RO) PCNT_CNT_THR_THRES1_LAT_Un Represents the latched value of thres1 event of PCNT_Un when threshold event interrupt is valid. 0: Others 1: The current pulse counter equals to thres1 and the thres1 event is valid (RO) PCNT_CNT_THR_THRES0_LAT_Un Represents the latched value of thres0 event of PCNT_Un when threshold event interrupt is valid. 0: Others 1: The current pulse counter equals to thres0 and the thres0 event is valid (RO) PCNT_CNT_THR_L_LIM_LAT_Un Represents the latched value of the low limit event of PCNT_Un when the threshold event interrupt is valid. 0: Others 1: The current pulse counter equals to thr_l_lim and the low limit event is valid. (RO) PCNT_CNT_THR_H_LIM_LAT_Un Represents the latched value of the high limit event of PCNT_Un when the threshold event interrupt is valid. 0: Others 1: The current pulse counter equals to thr_h_lim and the high limit event is valid. (RO) PCNT_CNT_THR_ZERO_LAT_Un Represents the latched value of the zero threshold event of PCNT_Un when the threshold event interrupt is valid. 0: Others 1: The current pulse counter equals to 0 and the zero threshold event is valid. (RO) Continued on the next page... Espressif Systems 1141 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 32 Pulse Count Controller (PCNT) Register 32.7. PCNT_Un_STATUS_REG (n: 0-3) (0x0060+0x4*n) Continued from the previous page... PCNT_CNT_THR_H_STEP_LAT_Un Represents the latched value of step counter event of PCNT_Un when step counter event interrupt is valid. 1: The current pulse counter decrement equals to reg_cnt_step and step counter event is valid. 0: Others (RO) PCNT_CNT_THR_L_STEP_LAT_Un Represents the latched value of step counter event of PCNT_Un when step counter event interrupt is valid. 1: The current pulse counter increment equals to reg_cnt_step and step counter event is valid. 0: Others (RO) Register 32.8. PCNT_INT_RAW_REG (0x0050) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 4 PCNT_CNT_THR_EVENT_U3_INT_RAW 0 3 PCNT_CNT_THR_EVENT_U2_INT_RAW 0 2 PCNT_CNT_THR_EVENT_U1_INT_RAW 0 1 PCNT_CNT_THR_EVENT_U0_INT_RAW 0 0 Reset PCNT_CNT_THR_EVENT_Un_INT_RAW (n: 0-3) The raw interrupt status bit for the PCNT_CNT_THR_EVENT_Un_INT interrupt. (R/WTC/SS) Register 32.9. PCNT_INT_ST_REG (0x0054) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 4 PCNT_CNT_THR_EVENT_U3_INT_ST 0 3 PCNT_CNT_THR_EVENT_U2_INT_ST 0 2 PCNT_CNT_THR_EVENT_U1_INT_ST 0 1 PCNT_CNT_THR_EVENT_U0_INT_ST 0 0 Reset PCNT_CNT_THR_EVENT_Un_INT_ST (n: 0-3) The masked interrupt status bit for the PCNT_CNT_THR_EVENT_Un_INT interrupt. (RO) Espressif Systems 1142 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 32 Pulse Count Controller (PCNT) Register 32.10. PCNT_INT_ENA_REG (0x0058) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 4 PCNT_CNT_THR_EVENT_U3_INT_ENA 0 3 PCNT_CNT_THR_EVENT_U2_INT_ENA 0 2 PCNT_CNT_THR_EVENT_U1_INT_ENA 0 1 PCNT_CNT_THR_EVENT_U0_INT_ENA 0 0 Reset PCNT_CNT_THR_EVENT_Un_INT_ENA (n: 0-3) The interrupt enable bit for the PCNT_CNT_THR_EVENT_Un_INT interrupt. (R/W) Register 32.11. PCNT_INT_CLR_REG (0x005C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 4 PCNT_CNT_THR_EVENT_U3_INT_CLR 0 3 PCNT_CNT_THR_EVENT_U2_INT_CLR 0 2 PCNT_CNT_THR_EVENT_U1_INT_CLR 0 1 PCNT_CNT_THR_EVENT_U0_INT_CLR 0 0 Reset PCNT_CNT_THR_EVENT_Un_INT_CLR (n: 0-3) Write 1 to clear the PCNT_CNT_THR_EVENT_Un_INT interrupt. (WT) Register 32.12. PCNT_DATE_REG (0x00FC) PCNT_DATE 0x2407310 31 0 Reset PCNT_DATE Version control register. (R/W) Espressif Systems 1143 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 33 USB Serial/JTAG Controller Chapter 33 USB Serial/JTAG Controller ESP32-C5 contains a USB Serial/JTAG Controller. This unit can be used to program the SoC’s flash, read program output, as well as attach a debugger to the running program. All of these are possible for any computer with a USB host (hereafter referred to as ‘host’) without any active external components. 33.1 Overview While programming and debugging an ESP32-C5 project using the UART and JTAG functionality is certainly possible, it has a few downsides. First of all, both UART and JTAG take up IO pins and as such, fewer pins are left usable for controlling external signals in software. Additionally, an external chip or adapter is needed for both UART and JTAG to interface with a host computer, which means it will be necessary to integrate these two functionalities in the form of external chips or debugging adapters. In order to alleviate these issues, ESP32-C5 provides a USB Serial/JTAG Controller, which integrates the functionality of both a USB-to-serial converter as well as a USB-to-JTAG adapter. As this device directly interfaces with an external USB host using only the two data lines required by USB 2.0, only two pins are required to be dedicated to this functionality for debugging ESP32-C5. 33.2 Feature List The USB Serial/JTAG controller has the following features: • USB Full-speed device; Hardwired for CDC-ACM (Communication Device Class - Abstract Control Model) and JTAG adapter functionality • CDC-ACM: – Integrates CDC-ACM adherent serial port emulation (plug-and-play on most modern OSes) – Supports host controllable chip reset and entry into download mode • JTAG adapter functionality: – Allows fast communication with CPU debugging core using a compact representation of JTAG instructions • A control endpoint, a dummy interrupt endpoint, two bulk input endpoints, and two bulk output endpoints; Up to 64-byte data payload size • Internal PHY: very few or no external components needed to connect to a host computer Note: The SDIO Slave controller can be used together with the USB Serial/JTAG controller in single SPI mode, but not in quad Espressif Systems 1144 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 33 USB Serial/JTAG Controller SPI mode. Figure 33.2-1. USB Serial/JTAG High Level Diagram As shown in Figure 33.2-1, the USB Serial/JTAG controller consists of a USB PHY, a USB device interface, a JTAG command processor, a response capture unit, and the CDC-ACM registers. The PHY and device interface are clocked from a 48 MHz clock derived from the baseband PLL (BBPLL); the software-accessible side of the CDC-ACM block is clocked from APB_CLK. The JTAG command processor is connected to the JTAG debugging unit of the main processor; the CDC-ACM registers are connected to the APB bus and as such can be read from and written to by software running on the main CPU. Note that while the USB Serial/JTAG device supports USB 2.0 standard, it only supports Full-speed (12 Mbps) mode but not other modes that the USB 2.0 standard introduced, e.g., the High-speed (480 Mbps) mode. Figure 33.2-2 shows the internal details of the USB Serial/JTAG controller on the USB side. The USB Serial/JTAG controller consists of a USB 2.0 Full-speed device. It contains a control endpoint, a dummy interrupt endpoint, two bulk input endpoints, and two bulk output endpoints. Together, these form a USB composite device, which consists of a CDC-ACM USB class device as well as a vendor-specific device implementing the JTAG interface. On the SoC side, the JTAG interface is directly connected to the RISC-V CPU’s debugging interface, allowing debugging of programs running on that core. Meanwhile, the CDC-ACM device is exposed as a set of registers, allowing a program on the CPU to read and write from it. Additionally, the ROM startup code of the SoC contains code that allows the user to reprogram attached flash memory using this interface. Note: To get specific information about what endpoint numbers are used for what functionality, please parse the relevant USB descriptors as returned by the device. This guarantees compatibility with other devices with the same functionality but a different implementation. Espressif Systems 1145 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 33 USB Serial/JTAG Controller Figure 33.2-2. USB Serial/JTAG Block Diagram 33.3 Functional Description The USB Serial/JTAG controller interfaces with a USB host processor on one side, and with the CPU debugging hardware as well as the software that communicates through the CDC-ACM port on the other side. 33.3.1 CDC-ACM USB Interface Functional Description The CDC-ACM interface adheres to the standard USB CDC-ACM class for serial port emulation. It contains a dummy interrupt endpoint (which will never send any events, as they are not implemented nor needed) and a Bulk IN as well as a Bulk OUT endpoint for the host’s received and sent serial data respectively. These endpoints can handle 64-bytes packet at a time, allowing high throughput. As CDC-ACM is a standard USB device class, a host generally can function without any special installation procedures. That is to say, when the USB debugging device is properly connected to a host, the operating system should show a new serial port moments later. The CDC-ACM interface accepts the following standard CDC-ACM control requests: Table 33.3-1. Standard CDC-ACM Control Requests Command Action SEND_BREAK Accepted but ignored (dummy) SET_LINE_CODING Accepted, value sent is readable in software GET_LINE_CODING By default, returns 9600 baud, no parity, 8 data bits, 1 stop bit (Can be changed through software) SET_CONTROL_LINE_STATE Set the state of the RTS/DTR lines. See Table 33.3-2 Aside from general-purpose communication, the CDC-ACM interface can also be used to reset ESP32-C5 and Espressif Systems 1146 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 33 USB Serial/JTAG Controller optionally make it enter download mode to flash new firmware. This can be realized by setting the RTS and DTR lines on the virtual serial port. Table 33.3-2. CDC-ACM Settings with RTS and DTR RTS DTR Action 0 0 Clear download mode flag 0 1 Set download mode flag 1 0 Reset ESP32-C5 1 1 No action Note that if the download mode flag is set when ESP32-C5 is reset, ESP32-C5 will reboot into download mode. When this flag is cleared and the chip is reset, ESP32-C5 will boot from flash. For specific sequences, please refer to Section 33.5. All these functions can also be disabled by programming various eFuses. Please refer to Chapter 5 eFuse Controller (eFuse) for more details. 33.3.2 CDC-ACM Firmware Interface Functional Description The CPU can interact with the USB Serial/JTAG controller as the module is connected to the internal APB bus of ESP32-C5. This is mainly used to read and write data from and to the virtual serial port on the attached host. USB CDC-ACM serial data is sent to and received from the host in packets of 0 to 64 bytes in size. When enough CDC-ACM data has accumulated in the host, the host sends a packet to the CDC-ACM receive endpoint, and the USB Serial/JTAG controller accepts this packet if it has a free buffer. Conversely, the host checks periodically if the USB Serial/JTAG controller has a packet ready to be sent to the host, and if so, receives this packet. Firmware can get notified of new data from the host in one of the following two ways. First of all, the USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL bit will remain set as long as there still is unread host data in the buffer. Secondly, the availability of data will trigger the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt. When data is available, it can be read by firmware through repeatedly reading bytes from USB_SERIAL_JTAG_EP1_REG. The amount of bytes to read can be determined by checking the USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL bit after reading each byte to see if there is more data to read. After all data is read, the USB device is automatically readied to receive a new data packet from the host. Generally, after sending data, the attached host will block until the data is actually read by firmware in one of the described methods. However, it is possible that a given firmware program does not read data at all. This situation generally is not expected by host programs which are written to talk to a discrete USB-serial converter; the program e.g. stops executing until the data is read. The ESP32-C5 USB-serial-JTAG adapter can simulate the behavior of a discrete USB-serial-JTAG converter: by writing a timeout to USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX and writing an 1 to USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN, any unread data will be automatically flushed after the given timeout. When the firmware has data to send, it can put the data in the send buffer and trigger a flush to allow the host to receive the data in a USB packet. In order to do so, there needs to be space available in the send buffer. Firmware can check this by reading USB_REG_SERIAL_IN_EP_DATA_FREE. A 1 in this register field indicates there is still free room in the buffer, and firmware can fill the buffer by writing bytes to the USB_SERIAL_JTAG_EP1_REG register. Writing the buffer does not immediately trigger sending data to the host Espressif Systems 1147 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 33 USB Serial/JTAG Controller until the buffer is flushed. After the flush, the entire buffer will be ready to be received by the USB host at once. A flush can be triggered in two ways: 1) after the 64th byte is written to the buffer, the USB hardware will automatically flush the buffer to the host; or 2) firmware can trigger a flush by writing 1 to USB_REG_SERIAL_WR_DONE. Regardless of how a flush is triggered, the send buffer will be unavailable for firmware to write into until it has been fully read by the host. As soon as the send buffer has been fully read, the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt will be triggered, indicating that the send buffer can receive another 64 bytes. It is possible to handle some out-of-band serial requests in software, specifically, the host setting DTR and RTS and changing the line state. If the CDC-ACM interface receives a SET_LINE_CODING request, the peripheral can be configured to trigger a USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt, at which point the line coding can be read from the USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG register. Similarly, SET_CONTROL_LINE_STATE requests will trigger USB_SERIAL_JTAG_RTS_CHG_INT and USB_SERIAL_JTAG_DTR_CHG_INT interrupts if they change the state of these lines. Software can then read the specific state through the USB_SERIAL_JTAG_RTS and USB_SERIAL_JTAG_DTR bits. Note that as described earlier, certain RTS/DTR sequences lead to hardware reset of ESP32-C5. Software can disable hardware recognition of these DTR/RTS sequences by setting the USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS bit, allowing software to interpret these signals freely. Finally, the host can read the current line state using GET_LINE_CODING. This event sends back the data in the USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG register and triggers a USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. 33.3.3 USB-to-JTAG Interface: JTAG Command Processor The USB-to-JTAG interface uses a vendor-specific class for its implementation. It consists of two endpoints, one to receive commands and another to send responses. Additionally, some less time-sensitive commands can be given as control requests. Commands from the host to the JTAG interface are interpreted by the JTAG command processor. Internally, the JTAG command processor implements a full four-wire JTAG bus, consisting of the TCK, TMS and TDI output lines to the RISC-V CPU, as well as the TDO line signalling back from the CPU to the JTAG response capture unit. These signals adhere to the IEEE 1149.1 JTAG standards. Additionally, there is an SRST line to reset ESP32-C5. Optionally, software can set USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN in order to redirect these signals to the GPIO matrix instead, where they can be routed to IO pads on ESP32-C5. This also allows external devices to be debugged via the USB Serial/JTAG peripheral. The JTAG command processor parses each received nibble (4-bit value) as a command. As USB data is received in 8-bit bytes, this means each byte contains two commands. The USB command processor will execute high-nibble first and low-nibble second. The commands are used to control the TCK, TMS, TDI, and SRST lines of the internal JTAG bus, as well as to signal the JTAG response capture unit the state of the TDO line (which is driven by the CPU debugging logic) that needs to be captured. In the internal JTAG bus, TCK, TMS, TDI, and TDO are connected directly to the JTAG debugging logic of the RISC-V CPU. SRST is connected to the reset logic of the digital circuitry in ESP32-C5 and a high level on this line will cause a digital system reset. Note that the USB Serial/JTAG controller itself is not affected by SRST. Espressif Systems 1148 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 33 USB Serial/JTAG Controller A nibble can contain the following commands: Table 33.3-3. Commands of a Nibble bit 3 2 1 0 CMD_CLK 0 cap tms tdi CMD_RST 1 0 0 srst CMD_FLUSH 1 0 1 0 CMD_RSV 1 0 1 1 CMD_REP 1 1 R1 R0 • CMD_CLK will set the TDI and TMS as the indicated values and emit one clock pulse on TCK. If the CAP bit is 1, it will instruct the JTAG response capture unit to capture the state of the TDO line. This instruction forms the basis of JTAG communication. • CMD_RST will set the state of the SRST line as the indicated value. This can be used to reset ESP32-C5. • CMD_FLUSH will instruct the JTAG response capture unit to flush the buffer of all bits it collected so the host is able to read them. Note that in some cases, a JTAG transaction will end in an odd number of commands and as such an odd number of nibbles. In this case, it is allowed to repeat the CMD_FLUSH command to get an even number of nibbles fitting an integer number of bytes. • CMD_RSV is reserved in the current implementation. This command will be ignored when received by ESP32-C5. • CMD_REP repeats the last (non-CMD_REP) command for a certain number of times. The purpose is to compress command streams which repeat the CMD_CLK instruction for multiple times. A command such as CMD_CLK can be followed by multiple CMD_REP commands. The number of repetitions done by one CMD_REP can be expressed as repetition_count = (R1 × 2 + R0) × (4 cmd_rep_count ), where cmd_rep_count indicates the number of the CMD_REP instruction that went directly before it. Note that the CMD_REP command is only intended to repeat a CMD_CLK command. Specifically, using it on a CMD_FLUSH command may lead to an unresponsive USB device, and a USB reset will be required to recover it. 33.3.4 USB-to-JTAG Interface: CMD_REP Usage Example Here is a list of commands as an illustration of the usage of CMD_REP. Note that each command is a nibble, and in this example, the bytewise command stream would be 0x0D 0x5E 0xCF. 1. 0x0 (CMD_CLK: cap=0, tdi=0, tms=0) 2. 0xD (CMD_REP: R1=0, R0=1) 3. 0x5 (CMD_CLK: cap=1, tdi=0, tms=1) 4. 0xE (CMD_REP: R1=1, R0=0) 5. 0xC (CMD_REP: R1=0, R0=0) 6. 0xF (CMD_REP: R1=1, R0=1) The following shows what happens at every step: 1. TCK is clocked with the TDI and TMS lines set to 0. No data is captured. Espressif Systems 1149 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 33 USB Serial/JTAG Controller 2. TCK is clocked another (0 × 2 + 1) × (4 0 ) = 1 time with the same settings as step 1. 3. TCK is clocked with the TDI line set to 0 and TMS set to 1. Data on the TDO line is captured. 4. TCK is clocked another (1 × 2 + 0) × (4 0 ) = 2 times with the same settings as step 3. 5. Nothing happens: (0 × 2 + 0) × (4 1 ) = 0. Note that this increases cmd_rep_count in the next step. 6. TCK is clocked another (1 × 2 + 1) × (4 2 ) = 48 times with the same settings as step 3. In other words, this example stream has the same net effect as that of executing command 1 twice, then repeating command 3 for 51 times. 33.3.5 USB-to-JTAG Interface: Response Capture Unit The response capture unit reads the TDO line of the internal JTAG bus and captures its value when the command parser executes a CMD_CLK with cap=1. It puts this bit into an internal shift register, and writes a byte into the USB buffer when 8 bits have been collected. Of these 8 bits, the least significant one is the one that is read from TDO the earliest. As soon as either 64 bytes (512 bits) have been collected or a CMD_FLUSH command is executed, the response capture unit will make the buffer available for the host to receive. Note that the interface to the USB logic is double-buffered. Therefore, as long as the USB throughput is sufficient, the response capture unit can always receive more data. That is to say, while one of the buffers is waiting to be sent to the host, the other can receive more data. When the host has received data from its buffer and the response capture unit flushes its buffer, the two buffers exchange position. This also means that a command stream can cause at most 128 bytes of capture data generated (less if there are flush commands in the stream) without the host acting to receive the generated data. If more data is generated anyway, the command stream will pause and the device will not accept more commands until the generated capture data is read out. Note that in general, the logic of the response capture unit tries not to send zero-byte responses. For instance, sending a series of CMD_FLUSH commands will not cause a series of 0-byte USB responses to be sent. However, in the current implementation, some zero-0 responses may be generated in extraordinary circumstances. It is recommended to ignore these responses. 33.3.6 USB-to-JTAG Interface: Control Transfer Requests Aside from the command processor and the response capture unit, the USB-to-JTAG interface also understands some control requests, as documented in the table below: Table 33.3-4. USB-to-JTAG Control Requests bmRequestType bRequest wValue wIndex wLength Data 01000000b 0 (VEND_JTAG_SETDIV) [divider] interface 0 None 01000000b 1 (VEND_JTAG_SETIO) [iobits] interface 0 None 11000000b 2 (VEND_JTAG_GETTDO) 0 interface 1 [iostate] 10000000b 6 (GET_DESCRIPTOR) 0x2000 0 256 [jtag cap desc] • VEND_JTAG_SETDIV sets the divider used. This directly affects the duration of a TCK clock pulse. The TCK clock pulses are derived from a base clock of 48 MHz, which is divided down using an internal divider. Espressif Systems 1150 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 33 USB Serial/JTAG Controller This control request allows the host to set this divider. Note that on startup, the divider is set to 2, which means the TCK clock rate will generally be 24 MHz. • VEND_JTAG_SETIO can bypass the JTAG command processor to set the internal TDI, TDO, TMS, and SRST lines to given values. These values are encoded in the wValue field in the format of 11’b0, srst, trst, tck, tms, tdi. • VEND_JTAG_GETTDO can bypass the JTAG response capture unit to read the internal TDO signal directly. This request returns one byte of data, of which the least significant bit represents the status of the TDO line. • GET_DESCRIPTOR is a standard USB request. However, it can also be used with a vendor-specific wValue of 0x2000 to get the JTAG capabilities descriptor. This returns a certain amount of bytes representing the following fixed structure, which describes the capabilities of the USB-to-JTAG adapter (as shown in Table 33.3-5). This structure allows host software to automatically support future revisions of the hardware without the need for an update. The JTAG capability descriptors of ESP32-C5 are as follows. Note that all 16-bit values are little-endian. Table 33.3-5. JTAG Capability Descriptors Byte Value Description 0 1 JTAG protocol capability structure version 1 10 Total length of JTAG protocol capabilities 2 1 Type of this struct: 1 for speed capability struct 3 8 Length of this speed capabilities struct 4 5 4800 JTAG base clock speed in 10 kHz increments. Note that the maximum TCK speed is half of this value 6 7 1 Minimum divider value settable by the VEND_JTAG_SETDIV request 8 9 255 Maximum divider value settable by the VEND_JTAG_SETDIV request 33.4 Interrupts ESP32-C5’s USB Serial/JTAG Controller can generate the USB_SERIAL_JTAG_INTR interrupt signal that will be sent to the Interrupt Matrix. There are several internal interrupt sources from the USB Serial/JTAG Controller that can generate this interrupt signal. • USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT: triggered when flush cmd is received for the JTAG bulk out endpoint. • USB_SERIAL_JTAG_SOF_INT: triggered when SOF frame is received. • USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT: triggered when Serial Port OUT Endpoint receives one packet. • USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT: triggered when Serial Port IN Endpoint is empty. • USB_SERIAL_JTAG_PID_ERR_INT: triggered when PID error is detected. • USB_SERIAL_JTAG_CRC5_ERR_INT: triggered when CRC5 error is detected. • USB_SERIAL_JTAG_CRC16_ERR_INT: triggered when CRC16 error is detected. • USB_SERIAL_JTAG_STUFF_ERR_INT: triggered when a bit stuffing error is detected. Espressif Systems 1151 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 33 USB Serial/JTAG Controller • USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT: triggered when IN token for IN endpoint 1 is received. • USB_SERIAL_JTAG_USB_BUS_RESET_INT: triggered when USB bus reset is detected. • USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT: triggered when OUT endpoint 1 receives packet with zero payload. • USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT: triggered when OUT endpoint 2 receives packet with zero payload. • USB_SERIAL_JTAG_RTS_CHG_INT: triggered when level of RTS from USB serial channel is changed. • USB_SERIAL_JTAG_DTR_CHG_INT: triggered when level of DTR from USB serial channel is changed. • USB_SERIAL_JTAG_GET_LINE_CODE_INT: triggered when level of GET_LINE_CODING request is received. • USB_SERIAL_JTAG_SET_LINE_CODE_INT: triggered when level of SET_LINE_CODING request is received. 33.5 Programming Procedures Little setup is needed for using the USB Serial/JTAG device. The USB-to-JTAG hardware itself does not need any setup aside from the standard USB initialization that the host operating system already does. Apart from that, the CDC-ACM emulation on the host side is also plug-and-play. On the firmware side, very little initialization is needed either. The USB hardware is self-initialized and after boot-up, if a host is connected and listening on the CDC-ACM interface, data can be exchanged as described above without any specific setup except for the situation when the firmware optionally sets up an interrupt service handler. One thing to note is that there may be situations where either the host is not attached or the CDC-ACM virtual port is not opened. In such cases, the packets that are flushed to the host will never be picked up and the send buffer will never be empty. It is important to detect these situations and implement timeout, as this is the only way to reliably detect whether the port on the host side is closed or not. Another thing to note is that the USB device is dependent on the BBPLL for the 48 MHz USB PHY clock. If this PLL is disabled, the USB communication will cease to function. One scenario where this happens is Deep-sleep. The USB Serial/JTAG controller (as well as the attached RISC-V CPU) will be entirely powered down in Deep-sleep mode. If a device needs to be debugged in this mode, it may be preferable to use an external JTAG debugger and a serial interface instead. The CDC-ACM interface can also be used to reset the SoC and take it into or out of download mode. Generating the correct sequence of handshake signals can be a bit complicated, since most operating systems only allow setting or resetting DTR and RTS separately, but not in tandem. Additionally, some drivers (e.g., the standard CDC-ACM driver on Windows) do not set DTR until RTS is set and the user needs to explicitly set RTS in order to ‘propagate’ the DTR value. The recommended procedures are introduced below. To reset the SoC into download mode: Espressif Systems 1152 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 33 USB Serial/JTAG Controller Table 33.5-1. Reset SoC into Download Mode Action Internal state Note Clear DTR RTS=?, DTR=0 Initialize to known values Clear RTS RTS=0, DTR=0 - Set DTR RTS=0, DTR=1 Set download mode flag Clear RTS RTS=0, DTR=1 Propagate DTR Set RTS RTS=1, DTR=1 - Clear DTR RTS=1, DTR=0 Reset SoC Set RTS RTS=1, DTR=0 Propagate DTR Clear RTS RTS=0, DTR=0 Clear download flag To reset the SoC into booting from flash: Table 33.5-2. Reset SoC into Booting from flash Action Internal state Note Clear DTR RTS=?, DTR=0 - Clear RTS RTS=0, DTR=0 Clear download flag Set RTS RTS=1, DTR=0 Reset SoC Clear RTS RTS=0, DTR=0 Exit reset Espressif Systems 1153 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 33 USB Serial/JTAG Controller 33.6 Register Summary The addresses in this section are relative to USB Serial/JTAG controller base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Configuration Registers USB_SERIAL_JTAG_EP1_REG FIFO access for the CDC-ACM data IN and OUT endpoints 0x0000 R/W USB_SERIAL_JTAG_EP1_CONF_REG Configuration and control registers for the CDC-ACM FIFOs 0x0004 varies USB_SERIAL_JTAG_CONF0_REG PHY hardware configuration 0x0018 R/W USB_SERIAL_JTAG_TEST_REG Registers used for debugging the PHY 0x001C varies USB_SERIAL_JTAG_MISC_CONF_REG Clock enable control 0x0044 R/W USB_SERIAL_JTAG_MEM_CONF_REG Memory power control 0x0048 R/W USB_SERIAL_JTAG_CHIP_RST_REG CDC-ACM chip reset control 0x004C varies USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG W0 of GET_LINE_CODING command 0x0058 R/W USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG W1 of GET_LINE_CODING command 0x005C R/W USB_SERIAL_JTAG_CONFIG_UPDATE_REG Configuration registers’ value update 0x0060 WT USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG Serial AFIFO configure register 0x0064 varies USB_SERIAL_JTAG_SERIAL_EP_TIMEOUT0_REG USB UART out endpoint timeout con- figuration 0x006C varies USB_SERIAL_JTAG_SERIAL_EP_TIMEOUT1_REG USB UART out endpoint timeout con- figuration 0x0070 R/W Interrupt Registers USB_SERIAL_JTAG_INT_RAW_REG Interrupt raw status register 0x0008 R/WTC/SS USB_SERIAL_JTAG_INT_ST_REG Interrupt status register 0x000C RO USB_SERIAL_JTAG_INT_ENA_REG Interrupt enable status register 0x0010 R/W USB_SERIAL_JTAG_INT_CLR_REG Interrupt clear status register 0x0014 WT Status Registers USB_SERIAL_JTAG_JFIFO_ST_REG JTAG FIFO status and control registers 0x0020 varies USB_SERIAL_JTAG_FRAM_NUM_REG Last received SOF frame index register 0x0024 RO USB_SERIAL_JTAG_IN_EP0_ST_REG Control IN endpoint status information 0x0028 RO USB_SERIAL_JTAG_IN_EP1_ST_REG CDC-ACM IN endpoint status infor- mation 0x002C RO USB_SERIAL_JTAG_IN_EP2_ST_REG CDC-ACM interrupt IN endpoint sta- tus information 0x0030 RO USB_SERIAL_JTAG_IN_EP3_ST_REG JTAG IN endpoint status information 0x0034 RO USB_SERIAL_JTAG_OUT_EP0_ST_REG Control OUT endpoint status informa- tion 0x0038 RO USB_SERIAL_JTAG_OUT_EP1_ST_REG CDC-ACM OUT endpoint status infor- mation 0x003C RO Espressif Systems 1154 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 33 USB Serial/JTAG Controller Name Description Address Access USB_SERIAL_JTAG_OUT_EP2_ST_REG JTAG OUT endpoint status informa- tion 0x0040 RO USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG W0 of SET_LINE_CODING command 0x0050 RO USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG W1 of SET_LINE_CODING command 0x0054 RO USB_SERIAL_JTAG_BUS_RESET_ST_REG USB Bus reset status register 0x0068 RO Version Registers USB_SERIAL_JTAG_DATE_REG Date register 0x0080 R/W Espressif Systems 1155 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 33 USB Serial/JTAG Controller 33.7 Registers The addresses in this section are relative to USB Serial/JTAG controller base address provided in Table 4.3-2 in Chapter 4 System and Memory. For how to program reserved fields, please refer to Section Programming Reserved Register Field. Register 33.1. USB_SERIAL_JTAG_EP1_REG (0x0000) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 USB_SERIAL_JTAG_RDWR_BYTE 0x0 7 0 Reset USB_SERIAL_JTAG_RDWR_BYTE A write to this register pushes the written data into the CDC TX FIFO; a read from this register pops a byte from the CDC RX FIFO and returns it. When USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set, users can write data (up to 64 bytes) into CDC-ACM TX FIFO through this register. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, users can check how many data is received through USB_SERIAL_JTAG_OUT_EP1_WR_ADDR, then read data from CDC-ACM RX FIFO through this register. (R/W) Espressif Systems 1156 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 33 USB Serial/JTAG Controller Register 33.2. USB_SERIAL_JTAG_EP1_CONF_REG (0x0004) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL 0 2 USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE 1 1 USB_SERIAL_JTAG_WR_DONE 0 0 Reset USB_SERIAL_JTAG_WR_DONE Configures whether to represent writing byte data to CDC-ACM TX FIFO is done. 0: No effect 1: Represents writing byte data to CDC-ACM TX FIFO is done This bit then stays 0 until data in CDC-ACM TX FIFO is read by the USB Host. (WT) USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE Represents whether CDC-ACM TX FIFO has space available. 0: CDC-ACM TX FIFO is full and no data should be written into it 1: CDC-ACM TX FIFO is not full and data can be written into it After writing USB_SERIAL_JTAG_WR_DONE, this bit will be 0 until data in CDC-ACM TX FIFO is read by USB Host. (RO) USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL Represents whether there is data in CDC- ACM RX FIFO. 0: There is no data in CDC-ACM RX FIFO 1: There is data in CDC-ACM RX FIFO (RO) Espressif Systems 1157 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 33 USB Serial/JTAG Controller Register 33.3. USB_SERIAL_JTAG_CONF0_REG (0x0018) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 17 USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL 0 16 USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN 0 15 USB_SERIAL_JTAG_USB_PAD_ENABLE 1 14 USB_SERIAL_JTAG_PULLUP_VALUE 0 13 USB_SERIAL_JTAG_DM_PULLDOWN 0 12 USB_SERIAL_JTAG_DM_PULLUP 0 11 USB_SERIAL_JTAG_DP_PULLDOWN 0 10 USB_SERIAL_JTAG_DP_PULLUP 1 9 USB_SERIAL_JTAG_PAD_PULL_OVERRIDE 0 8 USB_SERIAL_JTAG_VREF_OVERRIDE 0 7 USB_SERIAL_JTAG_VREFL 0 6 5 USB_SERIAL_JTAG_VREFH 0 4 3 USB_SERIAL_JTAG_EXCHG_PINS 0 2 USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE 0 1 (reserved) 0 0 Reset USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE Configures whether to enable software control USB D+ D- exchange. 0: Disable 1: Enable (R/W) USB_SERIAL_JTAG_EXCHG_PINS Configures whether to enable USB D+ D- exchange. 0: Disable 1: Enable (R/W) USB_SERIAL_JTAG_VREFH Configures single-end input high threshold. 0: 1.76 V 1: 1.84 V 2: 1.92 V 3: 2.00 V (R/W) USB_SERIAL_JTAG_VREFL Configures single-end input low threshold. 0: 0.80 V 1: 0.88 V 2: 0.96 V 3: 1.04 V (R/W) USB_SERIAL_JTAG_VREF_OVERRIDE Configures whether to enable software control input thresh- old. 0: Disable 1: Enable (R/W) Continued on the next page... Espressif Systems 1158 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 33 USB Serial/JTAG Controller Register 33.3. USB_SERIAL_JTAG_CONF0_REG (0x0018) Continued from the previous page... USB_SERIAL_JTAG_PAD_PULL_OVERRIDE Configures whether to enable software to control USB D+ D- pullup and pulldown. 0: Disable 1: Enable (R/W) USB_SERIAL_JTAG_DP_PULLUP Configures whether to enable USB D+ pull up when USB_SERIAL_JTAG_PAD_PULL_OVERRIDE is 1. 0: Disable 1: Enable (R/W) USB_SERIAL_JTAG_DP_PULLDOWN Configures whether to enable USB D+ pull down when USB_SERIAL_JTAG_PAD_PULL_OVERRIDE is 1. 0: Disable 1: Enable (R/W) USB_SERIAL_JTAG_DM_PULLUP Configures whether to enable USB D- pull up when USB_SERIAL_JTAG_PAD_PULL_OVERRIDE is 1. 0: Disable 1: Enable (R/W) USB_SERIAL_JTAG_DM_PULLDOWN Configures whether to enable USB D- pull down when USB_SERIAL_JTAG_PAD_PULL_OVERRIDE is 1. 0: Disable 1: Enable (R/W) USB_SERIAL_JTAG_PULLUP_VALUE Configures the pull up value when USB_SERIAL_JTAG_PAD_PULL_OVERRIDE is 1. 0: 2.2 K 1: 1.1 K (R/W) USB_SERIAL_JTAG_USB_PAD_ENABLE Configures whether to enable USB pad function. 0: Disable 1: Enable (R/W) Continued on the next page... Espressif Systems 1159 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 33 USB Serial/JTAG Controller Register 33.3. USB_SERIAL_JTAG_CONF0_REG (0x0018) Continued from the previous page... USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN Configures whether to disconnect USB_JTAG and internal JTAG. 0: USB_JTAG is connected to the internal JTAG port of CPU 1: USB_JTAG and the internal JTAG are disconnected, MTMS, MTDI, and MTCK are output through GPIO Matrix, and MTDO is input through GPIO Matrix (R/W) USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL Configures the clock edge at which DP and DM signals are transmitted to the USB PHY. 0: Transmit on the falling edge of the clock 1: Transmit on the rising edge of the clock (R/W) Espressif Systems 1160 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 33 USB Serial/JTAG Controller Register 33.4. USB_SERIAL_JTAG_TEST_REG (0x001C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 7 USB_SERIAL_JTAG_TEST_RX_DM 0 6 USB_SERIAL_JTAG_TEST_RX_DP 1 5 USB_SERIAL_JTAG_TEST_RX_RCV 1 4 USB_SERIAL_JTAG_TEST_TX_DM 0 3 USB_SERIAL_JTAG_TEST_TX_DP 0 2 USB_SERIAL_JTAG_TEST_USB_OE 0 1 USB_SERIAL_JTAG_TEST_ENABLE 0 0 Reset USB_SERIAL_JTAG_TEST_ENABLE Configures whether to enable the test mode of the USB pad. 0: Resume normal operation 1: Enable the test mode of the USB pad Enabling the test mode of the USB pad allows the USB pad to be controlled/read using the other bits in this register. (R/W) USB_SERIAL_JTAG_TEST_USB_OE Configures whether to enable USB pad output. 0: Set D+ and D- to high impedance 1: Output the values set in USB_SERIAL_JTAG_TEST_TX_DP and USB_SERIAL_JTAG_TEST_TX_DM on the D+ and D- pins (R/W) USB_SERIAL_JTAG_TEST_TX_DP Configures value of USB D+ in test mode when USB_SERIAL_JTAG_TEST_USB_OE is 1. (R/W) USB_SERIAL_JTAG_TEST_TX_DM Configures value of USB D- in test mode when USB_SERIAL_JTAG_TEST_USB_OE is 1. (R/W) USB_SERIAL_JTAG_TEST_RX_RCV Represents the current logical level of the voltage difference between USB D- and USB D+ pads in test mode. 0: USB D- voltage is higher than USB D+ 1: USB D+ voltage is higher than USB D- (RO) USB_SERIAL_JTAG_TEST_RX_DP Represents the logical level of the USB D+ pad in test mode. (RO) USB_SERIAL_JTAG_TEST_RX_DM Represents the logical level of the USB D- pad in test mode. (RO) Espressif Systems 1161 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 33 USB Serial/JTAG Controller Register 33.5. USB_SERIAL_JTAG_MISC_CONF_REG (0x0044) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 USB_SERIAL_JTAG_CLK_EN 0 0 Reset USB_SERIAL_JTAG_CLK_EN Configures whether to force clock on for register. 0: Support clock only when application writes registers 1: Force clock on for register (R/W) Register 33.6. USB_SERIAL_JTAG_MEM_CONF_REG (0x0048) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 2 USB_SERIAL_JTAG_USB_MEM_CLK_EN 1 1 USB_SERIAL_JTAG_USB_MEM_PD 0 0 Reset USB_SERIAL_JTAG_USB_MEM_PD Configures whether to power down USB memory. 0: No effect 1: Power down (R/W) USB_SERIAL_JTAG_USB_MEM_CLK_EN Configures whether to force clock on for USB memory. 0: No effect 1: Force (R/W) Espressif Systems 1162 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 33 USB Serial/JTAG Controller Register 33.7. USB_SERIAL_JTAG_CHIP_RST_REG (0x004C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS 0 2 USB_SERIAL_JTAG_DTR 0 1 USB_SERIAL_JTAG_RTS 0 0 Reset USB_SERIAL_JTAG_RTS Represents the state of RTS signal as set by the most recent SET_LINE_CODING command. (RO) USB_SERIAL_JTAG_DTR Represents the state of DTR signal as set by the most recent SET_LINE_CODING command. (RO) USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS Configures whether to disable chip reset from USB serial channel. 0: No effect 1: Disable (R/W) Register 33.8. USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG (0x0058) USB_SERIAL_JTAG_GET_DW_DTE_RATE 0 31 0 Reset USB_SERIAL_JTAG_GET_DW_DTE_RATE Configures the value of dwDTERate set by software, which is requested by GET_LINE_CODING command. (R/W) Espressif Systems 1163 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 33 USB Serial/JTAG Controller Register 33.9. USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG (0x005C) (reserved) 0 0 0 0 0 0 0 0 31 24 USB_SERIAL_JTAG_GET_BCHAR_FORMAT 0 23 16 USB_SERIAL_JTAG_GET_BPARITY_TYPE 0 15 8 USB_SERIAL_JTAG_GET_BDATA_BITS 0 7 0 Reset USB_SERIAL_JTAG_GET_BDATA_BITS Configures the value of bDataBits set by software, which is requested by GET_LINE_CODING command. (R/W) USB_SERIAL_JTAG_GET_BPARITY_TYPE Configures the value of bParityType set by software, which is requested by GET_LINE_CODING command. (R/W) USB_SERIAL_JTAG_GET_BCHAR_FORMAT Configures the value of bCharFormat set by software, which is requested by GET_LINE_CODING command. (R/W) Register 33.10. USB_SERIAL_JTAG_CONFIG_UPDATE_REG (0x0060) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 USB_SERIAL_JTAG_CONFIG_UPDATE 0 0 Reset USB_SERIAL_JTAG_CONFIG_UPDATE Configures whether to update the value of configuration registers from APB clock domain to 48 MHz clock domain. 0: No effect 1: Update (WT) Espressif Systems 1164 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 33 USB Serial/JTAG Controller Register 33.11. USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG (0x0064) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 6 USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL 0 5 USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY 1 4 USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD 0 3 USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR 0 2 USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD 0 1 USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR 0 0 Reset USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR Configures whether to reset CDC_ACM IN async FIFO write clock domain. 0: No effect 1: Reset (R/W) USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD Configures whether to reset CDC_ACM IN async FIFO read clock domain. 0: No effect 1: Reset (R/W) USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR Configures whether to reset CDC_ACM OUT async FIFO write clock domain. 0: No effect 1: Reset (R/W) USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD Configures whether to reset CDC_ACM OUT async FIFO read clock domain. 0: No effect 1: Reset (R/W) USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY Represents CDC_ACM OUT async FIFO empty signal in read clock domain. (RO) USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL Represents CDC_ACM IN async FIFO full signal in write clock domain. (RO) Espressif Systems 1165 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 33 USB Serial/JTAG Controller Register 33.12. USB_SERIAL_JTAG_SERIAL_EP_TIMEOUT0_REG (0x006C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR 0 2 USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS 0 1 USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN 0 0 Reset USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN USB serial out endpoint timeout enable. When a timeout event occurs, serial out endpoint buffer is automatically cleared and USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUSis asserted. 0: timeout disabled, buffer will not be cleared automatically 1: timeout enabled (R/W) USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS Timeout status bit 0: No timeout occurred. 1: Serial out endpoint has triggered a timeout event. (R/WTC/SS) USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR Write 1 to clear USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS. (WT) Register 33.13. USB_SERIAL_JTAG_SERIAL_EP_TIMEOUT1_REG (0x0070) USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX 0x494100 31 0 Reset USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX USB serial out endpoint timeout max threshold value, indicates the maximum time that waiting for chips to take away data in memory. This value is in steps of 20.83 ns. (R/W) Espressif Systems 1166 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 33 USB Serial/JTAG Controller Register 33.14. USB_SERIAL_JTAG_INT_RAW_REG (0x0008) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW 0 15 USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW 0 14 USB_SERIAL_JTAG_DTR_CHG_INT_RAW 0 13 USB_SERIAL_JTAG_RTS_CHG_INT_RAW 0 12 USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW 0 11 USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW 0 10 USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW 0 9 USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW 0 8 USB_SERIAL_JTAG_STUFF_ERR_INT_RAW 0 7 USB_SERIAL_JTAG_CRC16_ERR_INT_RAW 0 6 USB_SERIAL_JTAG_CRC5_ERR_INT_RAW 0 5 USB_SERIAL_JTAG_PID_ERR_INT_RAW 0 4 USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW 1 3 USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW 0 2 USB_SERIAL_JTAG_SOF_INT_RAW 0 1 USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW 0 0 Reset USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW The raw interrupt status of USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT. (R/WTC/SS) USB_SERIAL_JTAG_SOF_INT_RAW The raw interrupt status of USB_SERIAL_JTAG_SOF_INT. (R/WTC/SS) USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW The raw interrupt status of USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT. (R/WTC/SS) USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW The raw interrupt status of USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT. (R/WTC/SS) USB_SERIAL_JTAG_PID_ERR_INT_RAW The raw interrupt status of USB_SERIAL_JTAG_PID_ERR_INT. (R/WTC/SS) USB_SERIAL_JTAG_CRC5_ERR_INT_RAW The raw interrupt status of USB_SERIAL_JTAG_CRC5_ERR_INT. (R/WTC/SS) USB_SERIAL_JTAG_CRC16_ERR_INT_RAW The raw interrupt status of USB_SERIAL_JTAG_CRC16_ERR_INT. (R/WTC/SS) USB_SERIAL_JTAG_STUFF_ERR_INT_RAW The raw interrupt status of USB_SERIAL_JTAG_STUFF_ERR_INT. (R/WTC/SS) USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW The raw interrupt status of USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT. (R/WTC/SS) USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW The raw interrupt status of USB_SERIAL_JTAG_USB_BUS_RESET_INT. (R/WTC/SS) USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW The raw interrupt status of USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT. (R/WTC/SS) Continued on the next page... Espressif Systems 1167 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 33 USB Serial/JTAG Controller Register 33.14. USB_SERIAL_JTAG_INT_RAW_REG (0x0008) Continued from the previous page... USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW The raw interrupt status of USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT. (R/WTC/SS) USB_SERIAL_JTAG_RTS_CHG_INT_RAW The raw interrupt status of USB_SERIAL_JTAG_RTS_CHG_INT. (R/WTC/SS) USB_SERIAL_JTAG_DTR_CHG_INT_RAW The raw interrupt status of USB_SERIAL_JTAG_DTR_CHG_INT. (R/WTC/SS) USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW The raw interrupt status of USB_SERIAL_JTAG_GET_LINE_CODE_INT. (R/WTC/SS) USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW The raw interrupt status of USB_SERIAL_JTAG_SET_LINE_CODE_INT. (R/WTC/SS) Espressif Systems 1168 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 33 USB Serial/JTAG Controller Register 33.15. USB_SERIAL_JTAG_INT_ST_REG (0x000C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST 0 15 USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST 0 14 USB_SERIAL_JTAG_DTR_CHG_INT_ST 0 13 USB_SERIAL_JTAG_RTS_CHG_INT_ST 0 12 USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST 0 11 USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST 0 10 USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST 0 9 USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST 0 8 USB_SERIAL_JTAG_STUFF_ERR_INT_ST 0 7 USB_SERIAL_JTAG_CRC16_ERR_INT_ST 0 6 USB_SERIAL_JTAG_CRC5_ERR_INT_ST 0 5 USB_SERIAL_JTAG_PID_ERR_INT_ST 0 4 USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST 0 3 USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST 0 2 USB_SERIAL_JTAG_SOF_INT_ST 0 1 USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST 0 0 Reset USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST The masked interrupt status of USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT. (RO) USB_SERIAL_JTAG_SOF_INT_ST The masked interrupt status of USB_SERIAL_JTAG_SOF_INT. (RO) USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST The masked interrupt status of the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT. (RO) USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST The masked interrupt status of USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT. (RO) USB_SERIAL_JTAG_PID_ERR_INT_ST The masked interrupt status of USB_SERIAL_JTAG_PID_ERR_INT. (RO) USB_SERIAL_JTAG_CRC5_ERR_INT_ST The masked interrupt status of USB_SERIAL_JTAG_CRC5_ERR_INT. (RO) USB_SERIAL_JTAG_CRC16_ERR_INT_ST The masked interrupt status of USB_SERIAL_JTAG_CRC16_ERR_INT. (RO) USB_SERIAL_JTAG_STUFF_ERR_INT_ST The masked interrupt status of USB_SERIAL_JTAG_STUFF_ERR_INT. (RO) USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST The masked interrupt status of USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT. (RO) USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST The masked interrupt status of USB_SERIAL_JTAG_USB_BUS_RESET_INT. (RO) USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST The masked interrupt status of USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT (RO) USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST The masked interrupt status of USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT. (RO) Continued on the next page... Espressif Systems 1169 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 33 USB Serial/JTAG Controller Register 33.15. USB_SERIAL_JTAG_INT_ST_REG (0x000C) Continued from the previous page... USB_SERIAL_JTAG_RTS_CHG_INT_ST The masked interrupt status of USB_SERIAL_JTAG_RTS_CHG_INT. (RO) USB_SERIAL_JTAG_DTR_CHG_INT_ST The masked interrupt status of USB_SERIAL_JTAG_DTR_CHG_INT. (RO) USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST The masked interrupt status of USB_SERIAL_JTAG_GET_LINE_CODE_INT. (RO) USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST The masked interrupt status of USB_SERIAL_JTAG_SET_LINE_CODE_INT. (RO) Espressif Systems 1170 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 33 USB Serial/JTAG Controller Register 33.16. USB_SERIAL_JTAG_INT_ENA_REG (0x0010) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA 0 15 USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA 0 14 USB_SERIAL_JTAG_DTR_CHG_INT_ENA 0 13 USB_SERIAL_JTAG_RTS_CHG_INT_ENA 0 12 USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA 0 11 USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA 0 10 USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA 0 9 USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA 0 8 USB_SERIAL_JTAG_STUFF_ERR_INT_ENA 0 7 USB_SERIAL_JTAG_CRC16_ERR_INT_ENA 0 6 USB_SERIAL_JTAG_CRC5_ERR_INT_ENA 0 5 USB_SERIAL_JTAG_PID_ERR_INT_ENA 0 4 USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA 0 3 USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA 0 2 USB_SERIAL_JTAG_SOF_INT_ENA 0 1 USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA 0 0 Reset USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA Write 1 to enable USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT. (R/W) USB_SERIAL_JTAG_SOF_INT_ENA Write 1 to enable USB_SERIAL_JTAG_SOF_INT. (R/W) USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA Write 1 to enable USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT. (R/W) USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA Write 1 to enable USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT. (R/W) USB_SERIAL_JTAG_PID_ERR_INT_ENA Write 1 to enable USB_SERIAL_JTAG_PID_ERR_INT. (R/W) USB_SERIAL_JTAG_CRC5_ERR_INT_ENA Write 1 to enable USB_SERIAL_JTAG_CRC5_ERR_INT. (R/W) USB_SERIAL_JTAG_CRC16_ERR_INT_ENA Write 1 to enable USB_SERIAL_JTAG_CRC16_ERR_INT. (R/W) USB_SERIAL_JTAG_STUFF_ERR_INT_ENA Write 1 to enable USB_SERIAL_JTAG_STUFF_ERR_INT. (R/W) USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA Write 1 to enable USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT. (R/W) USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA Write 1 to enable USB_SERIAL_JTAG_USB_BUS_RESET_INT. (R/W) USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA Write 1 to enable USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT. (R/W) USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA Write 1 to enable USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT. (R/W) Continued on the next page... Espressif Systems 1171 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 33 USB Serial/JTAG Controller Register 33.16. USB_SERIAL_JTAG_INT_ENA_REG (0x0010) Continued from the previous page... USB_SERIAL_JTAG_RTS_CHG_INT_ENA Write 1 to enable USB_SERIAL_JTAG_RTS_CHG_INT. (R/W) USB_SERIAL_JTAG_DTR_CHG_INT_ENA Write 1 to enable USB_SERIAL_JTAG_DTR_CHG_INT. (R/W) USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA Write 1 to enable USB_SERIAL_JTAG_GET_LINE_CODE_INT. (R/W) USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA Write 1 to enable USB_SERIAL_JTAG_SET_LINE_CODE_INT. (R/W) Espressif Systems 1172 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 33 USB Serial/JTAG Controller Register 33.17. USB_SERIAL_JTAG_INT_CLR_REG (0x0014) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR 0 15 USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR 0 14 USB_SERIAL_JTAG_DTR_CHG_INT_CLR 0 13 USB_SERIAL_JTAG_RTS_CHG_INT_CLR 0 12 USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR 0 11 USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR 0 10 USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR 0 9 USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR 0 8 USB_SERIAL_JTAG_STUFF_ERR_INT_CLR 0 7 USB_SERIAL_JTAG_CRC16_ERR_INT_CLR 0 6 USB_SERIAL_JTAG_CRC5_ERR_INT_CLR 0 5 USB_SERIAL_JTAG_PID_ERR_INT_CLR 0 4 USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR 0 3 USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR 0 2 USB_SERIAL_JTAG_SOF_INT_CLR 0 1 USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR 0 0 Reset USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR Write 1 to clear USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT. (WT) USB_SERIAL_JTAG_SOF_INT_CLR Write 1 to clear USB_SERIAL_JTAG_SOF_INT. (WT) USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR Write 1 to clear USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT. (WT) USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR Write 1 to clear USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT. (WT) USB_SERIAL_JTAG_PID_ERR_INT_CLR Write 1 to clear USB_SERIAL_JTAG_PID_ERR_INT. (WT) USB_SERIAL_JTAG_CRC5_ERR_INT_CLR Write 1 to clear USB_SERIAL_JTAG_CRC5_ERR_INT. (WT) USB_SERIAL_JTAG_CRC16_ERR_INT_CLR Write 1 to clear USB_SERIAL_JTAG_CRC16_ERR_INT. (WT) USB_SERIAL_JTAG_STUFF_ERR_INT_CLR Write 1 to clear USB_SERIAL_JTAG_STUFF_ERR_INT. (WT) USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR Write 1 to clear USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT. (WT) USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR Write 1 to clear USB_SERIAL_JTAG_USB_BUS_RESET_INT. (WT) USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR Write 1 to clear USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT. (WT) USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR Write 1 to clear USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT. (WT) Continued on the next page... Espressif Systems 1173 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 33 USB Serial/JTAG Controller Register 33.17. USB_SERIAL_JTAG_INT_CLR_REG (0x0014) Continued from the previous page... USB_SERIAL_JTAG_RTS_CHG_INT_CLR Write 1 to clear USB_SERIAL_JTAG_RTS_CHG_INT. (WT) USB_SERIAL_JTAG_DTR_CHG_INT_CLR Write 1 to clear USB_SERIAL_JTAG_DTR_CHG_INT. (WT) USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR Write 1 to clear USB_SERIAL_JTAG_GET_LINE_CODE_INT. (WT) USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR Write 1 to clear USB_SERIAL_JTAG_SET_LINE_CODE_INT. (WT) Espressif Systems 1174 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 33 USB Serial/JTAG Controller Register 33.18. USB_SERIAL_JTAG_JFIFO_ST_REG (0x0020) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 10 USB_SERIAL_JTAG_OUT_FIFO_RESET 0 9 USB_SERIAL_JTAG_IN_FIFO_RESET 0 8 USB_SERIAL_JTAG_OUT_FIFO_FULL 0 7 USB_SERIAL_JTAG_OUT_FIFO_EMPTY 1 6 USB_SERIAL_JTAG_OUT_FIFO_CNT 0 5 4 USB_SERIAL_JTAG_IN_FIFO_FULL 0 3 USB_SERIAL_JTAG_IN_FIFO_EMPTY 1 2 USB_SERIAL_JTAG_IN_FIFO_CNT 0 1 0 Reset USB_SERIAL_JTAG_IN_FIFO_CNT Represents JTAG IN FIFO counter. (RO) USB_SERIAL_JTAG_IN_FIFO_EMPTY Represents whether JTAG IN FIFO is empty. 0: Not empty 1: Empty (RO) USB_SERIAL_JTAG_IN_FIFO_FULL Represents whether JTAG IN FIFO is full. 0: Not full 1: Full (RO) USB_SERIAL_JTAG_OUT_FIFO_CNT Represents JTAG OUT FIFO counter. (RO) USB_SERIAL_JTAG_OUT_FIFO_EMPTY Represents whether JTAG OUT FIFO is empty. 0: Not empty 1: Empty (RO) USB_SERIAL_JTAG_OUT_FIFO_FULL Represents whether JTAG OUT FIFO is full. 0: Not full 1: Full (RO) USB_SERIAL_JTAG_IN_FIFO_RESET Configures whether to reset JTAG IN FIFO. 0: No effect 1: Reset (R/W) USB_SERIAL_JTAG_OUT_FIFO_RESET Configures whether to reset JTAG OUT FIFO. 0: No effect 1: Reset (R/W) Espressif Systems 1175 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 33 USB Serial/JTAG Controller Register 33.19. USB_SERIAL_JTAG_FRAM_NUM_REG (0x0024) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 11 USB_SERIAL_JTAG_SOF_FRAME_INDEX 0 10 0 Reset USB_SERIAL_JTAG_SOF_FRAME_INDEX Represents frame index of received SOF frame. (RO) Register 33.20. USB_SERIAL_JTAG_IN_EP0_ST_REG (0x0028) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 USB_SERIAL_JTAG_IN_EP0_RD_ADDR 0 15 9 USB_SERIAL_JTAG_IN_EP0_WR_ADDR 0 8 2 USB_SERIAL_JTAG_IN_EP0_STATE 1 1 0 Reset USB_SERIAL_JTAG_IN_EP0_STATE Represents state of IN Endpoint 0. (RO) USB_SERIAL_JTAG_IN_EP0_WR_ADDR Represents write data address of IN endpoint 0. (RO) USB_SERIAL_JTAG_IN_EP0_RD_ADDR Represents read data address of IN endpoint 0. (RO) Espressif Systems 1176 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 33 USB Serial/JTAG Controller Register 33.21. USB_SERIAL_JTAG_IN_EP1_ST_REG (0x002C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 USB_SERIAL_JTAG_IN_EP1_RD_ADDR 0 15 9 USB_SERIAL_JTAG_IN_EP1_WR_ADDR 0 8 2 USB_SERIAL_JTAG_IN_EP1_STATE 1 1 0 Reset USB_SERIAL_JTAG_IN_EP1_STATE Represents state of IN Endpoint 1. (RO) USB_SERIAL_JTAG_IN_EP1_WR_ADDR Represents write data address of IN endpoint 1. (RO) USB_SERIAL_JTAG_IN_EP1_RD_ADDR Represents read data address of IN endpoint 1. (RO) Register 33.22. USB_SERIAL_JTAG_IN_EP2_ST_REG (0x0030) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 USB_SERIAL_JTAG_IN_EP2_RD_ADDR 0 15 9 USB_SERIAL_JTAG_IN_EP2_WR_ADDR 0 8 2 USB_SERIAL_JTAG_IN_EP2_STATE 1 1 0 Reset USB_SERIAL_JTAG_IN_EP2_STATE Represents state of IN Endpoint 2. (RO) USB_SERIAL_JTAG_IN_EP2_WR_ADDR Represents write data address of IN endpoint 2. (RO) USB_SERIAL_JTAG_IN_EP2_RD_ADDR Represents read data address of IN endpoint 2. (RO) Espressif Systems 1177 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 33 USB Serial/JTAG Controller Register 33.23. USB_SERIAL_JTAG_IN_EP3_ST_REG (0x0034) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 USB_SERIAL_JTAG_IN_EP3_RD_ADDR 0 15 9 USB_SERIAL_JTAG_IN_EP3_WR_ADDR 0 8 2 USB_SERIAL_JTAG_IN_EP3_STATE 1 1 0 Reset USB_SERIAL_JTAG_IN_EP3_STATE Represents state of IN Endpoint 3. (RO) USB_SERIAL_JTAG_IN_EP3_WR_ADDR Represents write data address of IN endpoint 3. (RO) USB_SERIAL_JTAG_IN_EP3_RD_ADDR Represents read data address of IN endpoint 3. (RO) Register 33.24. USB_SERIAL_JTAG_OUT_EP0_ST_REG (0x0038) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 USB_SERIAL_JTAG_OUT_EP0_RD_ADDR 0 15 9 USB_SERIAL_JTAG_OUT_EP0_WR_ADDR 0 8 2 USB_SERIAL_JTAG_OUT_EP0_STATE 0 1 0 Reset USB_SERIAL_JTAG_OUT_EP0_STATE Represents state of OUT Endpoint 0. (RO) USB_SERIAL_JTAG_OUT_EP0_WR_ADDR Represents write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected, there are (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR − 2) bytes data in OUT endpoint 0. (RO) USB_SERIAL_JTAG_OUT_EP0_RD_ADDR Represents read data address of OUT endpoint 0. (RO) Espressif Systems 1178 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 33 USB Serial/JTAG Controller Register 33.25. USB_SERIAL_JTAG_OUT_EP1_ST_REG (0x003C) (reserved) 0 0 0 0 0 0 0 0 0 31 23 USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT 0 22 16 USB_SERIAL_JTAG_OUT_EP1_RD_ADDR 0 15 9 USB_SERIAL_JTAG_OUT_EP1_WR_ADDR 0 8 2 USB_SERIAL_JTAG_OUT_EP1_STATE 0 1 0 Reset USB_SERIAL_JTAG_OUT_EP1_STATE Represents state of OUT Endpoint 1. (RO) USB_SERIAL_JTAG_OUT_EP1_WR_ADDR Represents write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected, there are (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR − 2) bytes data in OUT endpoint 1. (RO) USB_SERIAL_JTAG_OUT_EP1_RD_ADDR Represents read data address of OUT endpoint 1. (RO) USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT Represents data count in OUT endpoint 1 when one packet is received. (RO) Register 33.26. USB_SERIAL_JTAG_OUT_EP2_ST_REG (0x0040) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 USB_SERIAL_JTAG_OUT_EP2_RD_ADDR 0 15 9 USB_SERIAL_JTAG_OUT_EP2_WR_ADDR 0 8 2 USB_SERIAL_JTAG_OUT_EP2_STATE 0 1 0 Reset USB_SERIAL_JTAG_OUT_EP2_STATE Represents state of OUT Endpoint 2. (RO) USB_SERIAL_JTAG_OUT_EP2_WR_ADDR Represents write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected there are (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR − 2) bytes data in OUT endpoint 2. (RO) USB_SERIAL_JTAG_OUT_EP2_RD_ADDR Represents read data address of OUT endpoint 2. (RO) Espressif Systems 1179 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 33 USB Serial/JTAG Controller Register 33.27. USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG (0x0050) USB_SERIAL_JTAG_DW_DTE_RATE 0 31 0 Reset USB_SERIAL_JTAG_DW_DTE_RATE Represents the value of dwDTERate set by host through SET_LINE_CODING command. (RO) Register 33.28. USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG (0x0054) (reserved) 0 0 0 0 0 0 0 0 31 24 USB_SERIAL_JTAG_BDATA_BITS 0 23 16 USB_SERIAL_JTAG_BPARITY_TYPE 0 15 8 USB_SERIAL_JTAG_BCHAR_FORMAT 0 7 0 Reset USB_SERIAL_JTAG_BCHAR_FORMAT Represents the value of bCharFormat set by host through SET_LINE_CODING command. (RO) USB_SERIAL_JTAG_BPARITY_TYPE Represents the value of bParityTpye set by host through SET_LINE_CODING command. (RO) USB_SERIAL_JTAG_BDATA_BITS Represents the value of bDataBits set by host through SET_LINE_CODING command. (RO) Espressif Systems 1180 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 33 USB Serial/JTAG Controller Register 33.29. USB_SERIAL_JTAG_BUS_RESET_ST_REG (0x0068) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 USB_SERIAL_JTAG_USB_BUS_RESET_ST 1 0 Reset USB_SERIAL_JTAG_USB_BUS_RESET_ST Represents whether USB bus reset is released. 0: USB Serial/JTAG is in USB bus reset status 1: USB bus reset is released (RO) Register 33.30. USB_SERIAL_JTAG_DATE_REG (0x0080) USB_SERIAL_JTAG_DATE 0x2311240 31 0 Reset USB_SERIAL_JTAG_DATE Version control register. (R/W) Espressif Systems 1181 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Chapter 34 SDIO Slave Controller (SDIO) 34.1 Overview The ESP32-C5 features hardware support for the Secure Digital Input/Output (SDIO) device interface that conforms to the SDIO Specification V2.00. This interface allows an SDIO host to access the ESP32-C5 using the SDIO bus protocol. The SDIO host can directly access the ESP32-C5 SDIO interface registers or use the Direct Memory Access (DMA) engine to access shared memory. This approach reduces processor overhead and maintains high performance. 34.2 Features The SDIO Slave Controller has the following features: • Compatible with SD Physical Layer Specification V2.00 and SDIO V2.00 specifications • Support for two I/O functions (excluding function 0) • Support for SPI, 1-bit SDIO, and 4-bit SDIO transfer modes • Clock frequency range from 0 to 50 MHz • Configurable sample and drive clock edge • Integrated and SDIO-accessible registers for information exchange • Support for SDIO interrupt mechanism • Automatic padding data and discarding the padded data on the SDIO bus • Block size up to 512 bytes • Bidirectional interrupt vector between host and slave • DMA support for data transfer • Wake-up from sleep mode when connection is retained Note: The SDIO Slave controller can be used together with the USB Serial/JTAG controller in 1-bit SDIO transfer mode, but not in 4-bit SDIO transfer mode. Espressif Systems 1182 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) 34.3 Architecture Overview Figure 34.3-1 shows the functional block diagram of the SDIO slave module. Figure 34.3-1. SDIO Slave Block Diagram In this figure, the Host represents any device compatible with SDIO Specification V2.00. It communicates with the ESP32-C5 (configured as the SDIO slave) via the standard SDIO bus. The SDIO Device Interface block enables efficient communication with the external host by providing direct access to SDIO interface registers. It also supports DMA operation for high-speed data transfer over the Advanced High-Performance Bus (AHB) without engaging the CPU. 34.4 Standards Compliance The ESP32-C5 SDIO Slave Controller conforms to the following standards: • SD Specifications Part 1 Physical Layer Specification Version 2.00 (referred to as Physical Layer Specification V2.00 in this chapter) • SD Specifications Part E1 SDIO Specification Version 2.00, January 30, 2007 (referred to as SDIO Specification V2.00 in this chapter) 34.5 Functional Description 34.5.1 Physical Bus • Bus modes: SPI, 1-bit, and 4-bit SDIO transfer modes. • Bus signals: Standard SDIO Specification V2.00 signals, including CS/DI/SCLK/DO/IRQ for SPI mode, CMD/CLK/DATA/IRQ for SDIO 1-bit mode, and CMD/CLK/DAT[3:0] for SDIO 4-bit mode • Bus speed modes: Full-speed mode (0–50 MHz) and low-speed mode (0–400 kHz) • I/O functions: Two I/O functions in addition to function 0. Function 0 is used only for CCCR, FBR, and CIS operations. Functions 1 and 2 can be used simultaneously to transfer application data packets (such as Espressif Systems 1183 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Wi-Fi and Bluetooth packets) and to access SLC Host registers. For more information, please refer to the Physical Layer Specification V2.00 and SDIO Specification V2.00. 34.5.2 Supported Commands The SDIO Slave Controller primarily supports the IO_RW_DIRECT (CMD52) and IO_RW_EXTENDED (CMD53) data transfer commands. IO_RW_DIRECT (CMD52) is used to access registers and transfer data. Figure 34.5-1 shows its fields. For details on each field, please refer to the SDIO Specification V2.00. S D Command Index 110100b R/W flag Function Number RAW flag Stuff Register Address Stuff Write Data of Stuff Bits CRC7 E 1 1 6 1 3 1 1 17 1 8 7 1 Figure 34.5-1. CMD52 Content IO_RW_EXTENDED (CMD53) initiates the transfer of packets of an arbitrary length. Figure 34.5-2 shows its fields. For details on each field, please refer to the SDIO Specification V2.00. S D Command Index 110101b R/W flag Function Number Block Mode 1b OP Code Register Address Byte/Block Count Roundup (Packet_length/Block_Size) E 1 1 6 1 3 1 1 17 9 7 1 CRC7 Figure 34.5-2. CMD53 Content 34.5.3 I/O Function 0 Address Space I/O function 0 is used only for Card Common Control Registers (CCCR), Function Basic Registers (FBR), and Card Information Structure (CIS) operations. Figure 34.5-3 shows its address space map, as specified by the SDIO Specification. For details on each section in this map, please refer to the SDIO Specification V2.00. Espressif Systems 1184 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Figure 34.5-3. Function 0 Address Space As defined in the SDIO Specification, CCCR are common control registers, FBR are control configuration registers for each function, and CIS are status registers for storing card information, such as version, power consumption, and manufacturer. The functions of these registers are optional, and are detailed in the SDIO Specification. The CCCR configuration of ESP32-C5 SDIO slave is shown in Table 34.5-1, and the FBR configuration is shown in Table 34.5-2. Table 34.5-1. SDIO Slave CCCR Configuration Adress Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x00 CCCR/SDIO Revision Set SDIO bit[3:0] using HINF_SDIO_VER[7:4] in HINF_CFG_DATA1_REG Set CCCR bit[3:0] using HINF_SDIO_VER[3:0] in HINF_CFG_DATA1_REG 0x01 SD Specifica- tion Revision 0 (RFU) Set SD bit[3:0] using HINF_SDIO_VER[11:8] in HINF_CFG_DATA1_REG 0x02 I/O Enable 0 (IOE[7:3]) R/W (IOE[2:1]) 0 (RFU) 0x03 I/O Ready 0 (IOR[7:3]) R (IOR[2:1]) 0 (RFU) 0x04 Int Enable 0 (IEN[7:3]) R/W (IEN[2:1]) R/W (IENM) 0x05 Int Pending 0 (INT[7:3]) R (INT[2:1]) 0 (RFU) 0x06 I/O Abort 0 (RFU) W (RES) W (AS[2:0]) 0x07 Bus Interface Control R/W (CD Disable) 1 (SCSI) R/W (ECSI) 0 (RFU) R/W (Bus Width[1:0]) 0x08 Card Capability 0 (4BLS) 0 (LSC) R/W (E4MI) 1 (S4MI) 0 (SBS) 1 (SRW) 1 (SMB) 1 (SDC) Cont’d on next page Espressif Systems 1185 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Table 34.5-1. SDIO Slave CCCR Configuration – cont’d from previous page Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x09- 0x0B Common CIS Pointer Address 0x09: 0x0; Address 0x0A: 0x10; Address 0x0B: 0x0 (Pointer to card’s common CIS) 0x0C Bus Suspend 0 (RFU) 0 (BR) 0 (BS) 0x0D Function Select 0 (DF) 0 (RFU) 0 (FS[3:0]) 0x0E Exec Flags 0 (EX[7:1]) 0 (EXM) 0x0F Ready Flags 0 (RF[7:1]) 0 (RFM) 0x10- 0x11 FN0 Block Size R/W (Supported range: 0-512) (I/O block size for Function 0) 0x12 Power Control 0 (RFU) R/W (EMPC) 1 (SMPC) 0x13 High-Speed 0 (RFU) R/W (EHS) Note a (SHS) a Set SHS using HINF_HIGHSPEED_ENABLE in HINF_CFG_DATA1_REG. Table 34.5-2. SDIO Slave FBR Configuration Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x100 0 (Function 1 CSA enable) 0 (Function 1 supports CSA) 0 (RFU) 0 (Function 1 Standard SDIO Function interface code) 0x101 0 (Function 1 Extended standard SDIO Function interface code) 0x102 0 (RFU) R/W (EPS) 0 (SPS) 0x109- 0x10B Address 0x109: 0x0; Address 0x10A: 0x11; Address 0x10B: 0x0 (Pointer to Function 1 CIS) 0x110- 0x111 R/W (Supported range: 0-512) (I/O block size for Function 1) 0x200 0 (Function 2 CSA enable) 0 (Function 2 supports CSA) 0 (RFU) 0x2 (Function 2 Standard SDIO Function interface code) Cont’d on next page Espressif Systems 1186 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Table 34.5-2. SDIO Slave FBR Configuration – cont’d from previous page Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x201 0 (Function 2 Extended standard SDIO Function interface code) 0x202 0 (RFU) R/W (EPS) 0 (SPS) 0x209- 0x20B Address 0x209: 0x0; Address 0x20A: 0x12; Address 0x20B: 0x0 (Pointer to Function 2 CIS) 0x210- 0x211 R/W (Supported range: 0-512) (I/O block size for Function 2) 34.5.4 I/O Function 1/2 Address Space Map I/O function 1 and function 2 have identical functions and permissions. They can be used simultaneously or independently to transmit application data (such as Wi-Fi or Bluetooth data) in fixed-address packets or incremental-address packets. Both functions can access the same set of SLC Host registers. Figure 34.5-4 shows their address space map. All segments in this space can be accessed by the host. Fixed address Packet Reserved SLC Host Register Incr address Packet 0x0 0x400 - 0x1F7FF 0x1 -0x3F 0x40 -0x3FF Figure 34.5-4. Function 1/2 Address Space Map 34.5.4.1 Accessing SLC HOST Register Space The host can access registers in the contiguous address range from 0x40 to 0x3FF in the slave via I/O functions 1 or 2. To access these registers, the host sets the Register Address field of CMD52 or CMD53 to the low 10 bits of the address. CMD53 also allows the host to access multiple registers in a single operation for higher transfer rates. From SLCHOST_CONF_W0_REG and SLCHOST_CONF_W15_REG, there are 52 bytes of fields accessible and modifiable by both the host and slave, facilitating information exchange. Both host and slave software can access the SLC Host register space simultaneously. Therefore, an upper-layer mechanism should be implemented to prevent errors caused by concurrent access. 34.5.4.2 Transferring Incremental-Address Packets When the host uses addresses 0x400 to 0x1F7FF to transmit multiple application data packets (such as Wi-Fi packets), the address field in CMD53 should be set to increment mode, and the OP Code field should be set to 1. Espressif Systems 1187 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) For example, to transfer (send or receive) three data blocks starting from base address 0x500 using CMD53, the host should: • Set the Block Mode field in CMD53 to 1 (block data unit) • Set the OP Code field to 1 (incremental address mode) • Set the Register Address field to 0x500 (base address) • Set the Byte/Block Count field to 0x3 (three data blocks) • Set other fields according to the SDIO Specification When a packet is transmitted (slave to host or host to slave) through CMD53, the slave determines whether all valid data of the current packet has been transmitted and pads (when sending) or discards (when receiving) invalid data as needed. For more information, see Section 34.5.5.3. 34.5.4.3 Transferring Fixed-Address Packets When the host uses address 0x0 to transmit application data packets (such as Bluetooth packets), both the address field and OP Code field in CMD53 should be set to 0. For example, to transfer (send or receive) three data blocks starting from fixed address 0x0 using CMD53, the host should: • Set the Block Mode field in CMD53 to 1 (block data unit) • Set the OP Code field to 0 (fixed address mode) • Set the Register Address field to 0x0 (fixed address) • Set the Byte/Block Count field to 0x3 (three data blocks) • Set other fields according to the SDIO Specification When a packet is transmitted between the host and slave through CMD53, the slave determines whether all valid data of the current packet has been transmitted and pads or discards invalid data as needed. For more information, see Section 34.5.5.3. 34.5.5 DMA The SDIO Slave Controller uses a dedicated DMA to access transfer data from RAM or store it to RAM. As shown in Figure 34.3-1, RAM is accessed over the AHB. For the RAM space accessible by the Controller, please refer to Chapter 4 System and Memory. To set the RAM address range that can be accessed for one transfer, please configure the *SHAREMEM*_REG fields of SLC register described in Section 34.8. The DMA engine provides two channels: SLC0 and SLC1. SLC0 is used for transferring incremental-address packets, while SLC1 handles fixed-address packets. The SDIO slave supports two I/O functions (Function 1 and Function 2) for data transmission. It is recommended to use Function 1 with SLC0 for incremental-address packets and Function 2 with SLC1 for fixed-address packets. For details on the address ranges of these functions, see Section 34.5.4. DMA accesses RAM over AHB. You can configure the burst operation mode and type by setting the relevant fields of SDIO_SLCCONF0_REG and SDIO_SLC_BURST_LEN_REG. For more information, see Section 34.8. Espressif Systems 1188 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) 34.5.5.1 Linked List The slave software can use the DMA engine by mounting linked lists. The DMA engine transfers data from the RAM address space specified in the RX (slave-to-host) linked list and stores received data in the RAM address space specified in the TX (host-to-slave) linked list. A linked list is composed of multiple descriptors. Figure 34.5-5. DMA Linked List Descriptor Structure of the SDIO Slave The TX and RX linked list descriptors share the same structure, as shown in Figure 34.5-5. Each descriptor consists of three words, with the following fields: • owner (DW0) [31]: Specifies the entity allowed to access the buffer. 0: CPU 1: DMA engine The slave software sets this field to 1 when creating the descriptor. After the DMA write-back permission is enabled and the corresponding buffer is used by the DMA, the field is cleared to 0. • eof (DW0) [30]: Indicates the end of a data packet. 0: The current descriptor is not the last descriptor of the packet 1: The current descriptor is the last descriptor of the packet When the host sends a packet to the slave, the slave software should set the field to 0 while creating the descriptor. DMA sets the field of the last descriptor in the packet to 1; When the host receives packets from the slave, the slave software configures the field depending on whether this descriptor is the last descriptor of the packet. • reserved (DW0) [29:28]: Reserved field. The slave software sets this field to 0x0. • length (DW0) [27:14]: Indicates the number of valid bytes in the corresponding buffer. When the DMA engine is reading data from the buffer, it indicates the number of bytes that can be read; when DMA engine is storing data in the buffer, it indicates the number of bytes of the stored data. When the host sends a packet to the slave, the slave software should set this field to 0x0 while creating the descriptor. DMA writes back the field after the corresponding buffer is used up; when the host receives the packet from the slave and the slave creates the descriptor, the slave software should set this field to the number of bytes that can be read by the corresponding buffer. • size (DW0) [13:0]: Specifies the size of the buffer in bytes. This field must be word-aligned. The slave software configures it during descriptor creation. • buffer address pointer (DW1): Points to the buffer address. This field must be word-aligned. The slave software configures it during descriptor creation. • next descriptor address (DW2): Points to the next descriptor in the linked list. If no next descriptor exists, this field is set to 0. The slave software configures it during descriptor creation. Espressif Systems 1189 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) For more information on DMA write-back linked list descriptor fields, see Section 34.5.5.2. The slave software can combine multiple descriptors into a linked list using the next descriptor address (DW2) field. The SDIO slave DMA linked list is shown in Figure 34.5-6. Figure 34.5-6. DMA Linked List of the SDIO Slave The following example demonstrates the use of a linked list and the bit. Suppose the slave software creates a linked list with three descriptors: • Descriptor 0 points to 500 bytes of data, with its bit set to 0. • Descriptor 1 points to 200 bytes of data, with its bit set to 1. • Descriptor 2 points to 200 bytes of data, with its bit set to 1. 1. If the first CMD53 command requests 400 bytes, the DMA sends the first 400 bytes from Descriptor 0 to the host. 2. If the second CMD53 command requests 400 bytes, the DMA first sends the remaining 100 bytes from Descriptor 0 to the host, followed by 200 bytes from Descriptor 1. Since the bit of Descriptor 1 is set to 1, the DMA considers the valid data for the current CMD53 command complete and pads the remaining 100 bytes with invalid data (0x0). 3. If the third CMD53 command requests 400 bytes, the DMA sends 200 bytes from Descriptor 2 to the host. As the bit of Descriptor 2 is set to 1, the DMA considers the valid data for the current CMD53 command complete and pads the remaining 200 bytes with invalid data (0x0). 34.5.5.2 Write-Back of Linked List When sending packets from the host to the slave, if the buffer specified by a linked list descriptor is full or a packet transmission ends, the DMA engine jumps to the next descriptor to store subsequent data. Before jumping, the DMA writes back the current descriptor. In DW0, the DMA updates the and bits to their latest values. The value of the bit is determined by SDIO_SLC0/1_TX_LOOP_TEST in SDIO_SLCCONF0_REG. When receiving packets from the slave, if the host reads all data in the buffer specified by a linked list descriptor, the DMA engine jumps to the next descriptor to read subsequent data. Before jumping, the slave software can Espressif Systems 1190 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) set SDIO_SLC0/1_RX_AUTO_WRBACK in SDIO_SLCCONF0_REG to 1 so that the DMA writes back the current descriptor. The value to write to the bit is determined by SDIO_SLC0/1_RX_LOOP_TEST in SDIO_SLCCONF0_REG. Other bits in DW0 remain unchanged. The relevant register fields are described in Section 34.8. 34.5.5.3 Data Padding and Discarding To transfer data in blocks, both the host and the slave pad the data sent on the SDIO bus into entire blocks. The slave automatically pads data when sending a packet and discards the padded data after receiving packets. • When the host sends a data packet to the slave through CMD53 and the amount of data reaches the packet length, the SDIO slave considers the valid data of the current packet complete. At this time, the DMA writes back the current linked list descriptor, sets the bit of the current descriptor to 1, and generates the SLC0/1_TX_SUC_EOF_INT interrupt. After determining that the valid data is complete, the remaining data of the current packet is considered invalid and is not received into the buffer by the DMA. The slave does not restart receiving data into the next buffer until the next CMD53. – For incremental-address packets, the slave determines valid data based on the address. Data with an address greater than or equal to 0x1F800 is considered invalid and is discarded. Therefore, the host should set the CMD53 start address field to 0x1F800 – Packet_length (in bytes). The data flow of incremental-address packets on the SDIO bus is shown in Figure 34.5-7. Figure 34.5-7. Data Flow of Sending Incremental-address Packets From Host to Slave – For fixed-address packets, the slave interprets the first three bytes of the data packet as the packet length. These three bytes are also stored in the buffer specified by the linked list. After the received data length matches the value indicated by these three bytes, any subsequent data is considered invalid and discarded. • When the host receives data packets (including incremental-address and fixed-address packets) from the slave through a CMD53 command, and the DMA reads the last byte of a buffer where the bit of the DMA linked list descriptor is set to 1, the SDIO slave considers the valid data of the current packet complete. At this point, the DMA writes back the current descriptor and generates the SLC0/1_RX_EOF_INT interrupt. After the SDIO slave determines that the valid data is complete, the remaining bits of the current data packet are padded with invalid data (0x0) and are not read from the buffer via DMA. The slave restarts reading data from the buffer via DMA when the next CMD53 command is sent by the host. Note: When the host receives either incremental-address or fixed-address data packets from the slave, the bit of the DMA linked list descriptor is always used to determine the end of data, rather than the address 0x1F800. Therefore, when the host sends multiple CMD53 commands to obtain multiple data packets, as Espressif Systems 1191 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) long as the DMA does not encounter the bit set to 1 in the descriptors, the slave obtains the data from buffers in sequence according to the linked list and transmits it to the host. When the DMA encounters the bit set to 1, the data is fetched from the corresponding buffer, and then invalid data is padded to complete the current CMD53 command. The next CMD53 command will fetch data from the buffer pointed to by the next descriptor. 34.5.6 SDIO Bus Timing The SDIO bus operates at high speed, and PCB trace length can affect signal integrity by introducing latency. To ensure proper timing characteristics, the SDIO slave module supports configuration of the input sampling clock edge and output driving clock edge. When incoming data changes near the rising edge of the clock, the slave samples on the falling edge, and vice versa, as shown in Figure 34.5-8. Figure 34.5-8. Sampling Timing Diagram By default, the voltage level of the GPIO25 strapping pin determines the slave pin’s sampling edge. You can also configure the sampling edge using the SLCHOST_CONF_REG register, with the following priority (from high to low): (1) Set SLCHOST_FRC_POS_SAMP to sample the corresponding signal at the rising edge; (2) Set SLCHOST_FRC_NEG_SAMP to sample at the falling edge. The SLCHOST_FRC_POS_SAMP and SLCHOST_FRC_NEG_SAMP fields are five bits wide, corresponding to the CMD line and four DATA lines (0–3). Setting a bit causes the corresponding line to be sampled at the rising or falling clock edge. The slave can also select which edge to drive the output lines, to compensate for any latency caused by the physical signal path. The output timing is shown in Figure 34.5-9. Figure 34.5-9. Output Timing Diagram By default, the voltage level of the MTDI strapping pin determines the slave pin’s output driving edge. You can also configure the output driving edge using the following registers, with priority from high to low: (1) Set SLCHOST_FRC_SDIO11 in SLCHOST_CONF_REG to output the corresponding signal at the falling clock edge; (2) Set SLCHOST_FRC_SDIO22 in SLCHOST_CONF_REG to output at the rising clock edge; (3) Set Espressif Systems 1192 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) HINF_HIGHSPEED_ENABLE in HINF_CFG_DATA1_REG and SLCHOST_HSPEED_CON_EN in SLCHOST_CONF_REG, then set the EHS (Enable High-Speed) bit in CCCR at the host side to output at the rising clock edge. The SLCHOST_FRC_SDIO11 and SLCHOST_FRC_SDIO22 fields are five bits wide, corresponding to the CMD line and four DATA lines (0–3). Setting a bit causes the corresponding line to output at the rising or falling clock edge. Note on priority: The configuration of strapping pins has the lowest priority for controlling the sampling or driving edge. Lower-priority configurations take effect only when higher-priority configurations are not set. For example, the GPIO25 strapping value determines the sampling edge only when SCLHOST_FRC_POS_SAMP and SCLHOST_FRC_NEG_SAMP are not set. 34.6 Interrupt The host and slave can interrupt each other via the interrupt vector. There are eight interrupt vectors between the host and each DMA SLC channel of the slave. To send an interrupt, set the enable bit of the interrupt vector register to 1. 34.6.1 Host Interrupt • SLCHOST_SLC0/1_RX_NEW_PACKET_INT : The slave has a packet to send. This interrupt can be triggered when: – SDIO_SLC0_RXLINK_START or SDIO_SLC1_RXLINK_START is set to enable DMA. – A new RX linked list descriptor is available after DMA processes the RX linked list descriptor with the bit set to 1. – A packet needs to be retransmitted. • SLCHOST_SLC0/1_TX_OVF_INT : Slave TX (transmit) buffer overflow interrupt. • SLCHOST_SLC0/1_RX_UDF_INT : Slave RX (receive) buffer underflow interrupt. • SLCHOST_SLC0/1_TOHOST_BITn_INT (n: 0–7): Slave interrupts the host. 34.6.2 Slave Interrupt • SLC0/1_TX_DSCR_ERR_INT : Slave TX linked list descriptor error. • SLC0/1_RX_DSCR_ERR_INT : Slave RX linked list descriptor error. • SLC0/1_RX_EOF_INT : Slave RX operation is finished. • SLC0/1_RX_DONE_INT : A single buffer is received by the slave. • SLC0/1_TX_SUC_EOF_INT : Slave TX operation is finished. • SLC0/1_TX_DONE_INT : A single buffer is finished during TX operation. • SLC0/1_TX_OVF_INT : Slave TX buffer overflow interrupt. • SLC0/1_RX_UDF_INT : Slave RX buffer underflow interrupt. • SLC0/1_TX_START_INT : Slave TX start interrupt. Espressif Systems 1193 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) • SLC0/1_RX_START_INT : Slave RX start interrupt. • SLC_FRHOST_BITn_INT (n: 0–15): The host interrupts the slave via the SLC0 channel if interrupt vector Bit[7:0] is set or via the SLC1 channel if interrupt vector Bit[15:8] is set. 34.7 Packet Sending and Receiving Procedure The SDIO host and slave devices must follow specific data transfer procedures to successfully exchange data over the SDIO interface. In addition to SDIO Specifications, ESP32-C5 should also follow the procedures below to transmit data over higher abstraction layers, such as Wi-Fi and Bluetooth. 34.7.1 Sending Packets to SDIO Host The transmission of packets from the slave to the host is initiated by the slave. The host is notified with an interrupt (for details, refer to the SDIO Specification). After the host reads the relevant information from the slave, it initiates an SDIO bus transmission accordingly. The procedure is illustrated in Figure 34.7-1. Espressif Systems 1194 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) CPU prepares linked list CPU refreshes SLCHOST_PKT_LEN CPU initiates DMA Slave sends interrupt to Host SlaveHost Host responds to interrupt Reads Slave register Sends CMD52 to clear interrupt (including SLC0/1HOST_INT_ST SLCHOST_PKT_LEN) Sends CMD53 Clears interrupt DMA transfers data SDIO Physical Bus sends data Transmission completed Slave sends interrupt to CPU CPU retrieves buffer END Receives data Transmission completed Discards padding data Packet processing END Figure 34.7-1. Procedure of Slave Sending Packets to Host 1. The slave CPU creates the linked list for the data packets to be sent to the host. For details, see Section 34.5.5.1. 2. The slave CPU updates the length of data to be sent using the register SDIO_SLC0_LEN_CONF_REG. 3. The slave CPU starts DMA by writing the 32-bit address of the first descriptor in linked list to SDIO_SLC0RX_LINK_ADDR_REG or SDIO_SLC1RX_LINK_ADDR_REG and then configuring SDIO_SLC0_RXLINK_START or SDIO_SLC1_RXLINK_START to start DMA. For more information on DMA, please refer to Section 34.5.5. 4. The slave DMA sends an interrupt to the host. Espressif Systems 1195 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) 5. After the host received the interrupt, it reads from SLCHOST_SLC0HOST_INT_ST_REG, SLCHOST_SLC1HOST_INT_ST_REG, and SLCHOST_PKT_LEN_REG for the following information: • SLCHOST_SLC0/1HOST_INT_ST_REG: Interrupt status register. The SLCHOST_SLC0/1_RX_NEW_PACKET_INT_ST bit set to 1 indicates that cause of the interrupt is the slave sending packets. • SLCHOST_PKT_LEN_REG: Packet length accumulator register. The current value minus the value of last time equals the packet length sent this time. 6. The host clears the interrupt by writing to the register SLCHOST_SLC0/1HOST_INT_CLR_REG after the CMD52 command. 7. The host fetches packets from the slave after the CMD53 command. During transmission, when the slave determines that the valid data of the current packet is complete, the remaining bits are padded with invalid data (0x0). For details on determining the end of valid data, see Section 34.5.5.3. 8. After the packets are transmitted, the slave DMA sends an interrupt to the CPU, and the CPU can recycle the buffer. Notes: • Do not set all bits to 0 in the linked list. Otherwise, the DMA may mistakenly send the next packet’s data as part of the current command, causing errors. If all bits are set to 0, the slave software should align the length of each packet to the data block size by padding data, to prevent errors. When the host sends CMD53 to read data, it should accurately control the number of data blocks in each packet and be able to identify the padded data. • It is recommended that each CMD53 command transmit only one data packet and each data packet use only one linked list to avoid exceptions caused by complex transmission. • Avoid sending multiple packets through one linked list, as it complicates the host and software’s ability to distinguish between packets. If necessary, set the bit when creating the linked list to split the packets, so the DMA can pad data accordingly. The length of each packet should be aligned to the data block size to avoid data padding by DMA, and the host should be able to identify the padded data. 34.7.2 Receiving Packets from SDIO Host Transmission of packets from the host to slave is initiated by the host. The slave receives data via DMA and stores it in RAM. After transmission is complete, the CPU is interrupted to process the data. The procedure is shown in Figure 34.7-2. Espressif Systems 1196 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) SlaveHost Waits for enough buffers for Slave Fills packet Sends CMD53 Slave returns Response (R5) Receives SDIO Physical Bus data DMA transfers data Slave sends interrupt to CPU CPU processes data SDIO Physical Bus sends data END Obtains number of available buffers for Slave Figure 34.7-2. Procedure of Slave Receiving Packets from Host The host obtains the number of available receiving buffers from the slave by accessing SLCHOST_SLC0HOST_TOKEN_RDATA_REG or SLCHOST_SLC1HOST_TOKEN_RDATA_REG. The slave CPU should update the value of the register after the receiving DMA linked list is prepared. SLCHOST_HOSTSLCHOST_SLC0_TOKEN1 or SLCHOST_HOSTSLCHOST_SLC1_TOKEN1 stores the accumulated number of available buffers. The host can determine the available buffer space by subtracting the number of buffers already used from the register value. If buffers are insufficient, the host should poll the register until enough buffers are available. During packet transmission to the slave through the CMD53 command, when a buffer specified by a linked list descriptor is full or a packet transmission ends, the DMA jumps to the next buffer to store subsequent data. When the slave determines that the valid data of the current packet is complete, the remaining data is considered invalid and discarded. The DMA writes back the current linked list descriptor, sets the bit of the current descriptor to 1, and generates the SLC0/1_TX_SUC_EOF_INT interrupt. For more information about DMA functions, linked list, and data discarding, see Section 34.5.5. To ensure sufficient receiving buffers, the slave CPU must continuously load buffers onto the receiving linked list. The process is shown in Figure 34.7-3. Espressif Systems 1197 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Figure 34.7-3. Loading Receiving Buffer The CPU should append new buffer segments at the end of the linked list used by DMA and available for receiving data. The CPU must then notify the DMA that the linked list has been updated. This can be done by setting SDIO_SLC0_TXLINK_RESTART or SDIO_SLC1_TXLINK_RESTART. When the CPU initiates DMA to receive packets for the first time, SDIO_SLC0_TXLINK_START or SDIO_SLC1_TXLINK_START should be set to 1. Notes: Use the *_RESTART field to restart DMA only in the two scenarios: • DMA is suspended by configuration of the *_STOP field. You can restart it after configuring the *_RESTART field. • DMA is suspended due to insufficient linked list descriptors. You can restart it by adding descriptors and configuring the *_RESTART field. Finally, the CPU refreshes available buffer information by writing to the SDIO_SLC0TOKEN1_REG or SDIO_SLC1TOKEN1_REG register. Espressif Systems 1198 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) 34.8 Register Summary The addresses in this section are relative to the SDIO Slave Controller base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in the Access column are explained in Section Access Types for Registers. 34.8.1 HINF Register Summary Name Description Address Access Configuration registers HINF_CFG_DATA0_REG SDIO CIS configuration 0x0000 R/W HINF_CFG_DATA1_REG SDIO configuration 0x0004 R/W HINF_CFG_DATA7_REG SDIO configuration 0x001C varies HINF_CIS_CONF_Wn_REG(n: 0-7) SDIO CIS configuration 0x0020+0x4*n R/W HINF_CFG_DATA16_REG SDIO CIS configuration 0x0040 R/W Status registers HINF_CONF_STATUS_REG SDIO CIS function 0 config0 status 0x0054 RO 34.8.2 SLC Register Summary Name Description Address Access Configuration registers SDIO_SLCCONF0_REG DMA configuration 0x0000 R/W SDIO_SLC0RX_LINK_REG SCL0 RX linked list configuration 0x003C varies SDIO_SLC0RX_LINK_ADDR_REG SCL0 RX linked list address 0x0040 R/W SDIO_SLC0TX_LINK_REG SCL0 TX linked list configuration 0x0044 varies SDIO_SLC0TX_LINK_ADDR_REG SCL0 TX linked list address 0x0048 R/W SDIO_SLC1RX_LINK_REG SCL1 RX linked list configuration 0x004C varies SDIO_SLC1RX_LINK_ADDR_REG SCL1 RX linked list address 0x0050 R/W SDIO_SLC1TX_LINK_REG SCL1 TX linked list configuration 0x0054 varies SDIO_SLC1TX_LINK_ADDR_REG SCL1 TX linked list address 0x0058 R/W SDIO_SLC0TOKEN1_REG SLC0 receiving buffer configuration 0x0064 varies SDIO_SLC1TOKEN1_REG SLC1 receiving buffer configuration 0x006C varies SDIO_SLCCONF1_REG DMA configuration 0x0070 R/W SDIO_SLC_RX_DSCR_CONF_REG DMA slave to host configuration register 0x00A8 R/W SDIO_SLC0_LEN_CONF_REG Length control of transmitting packets 0x00F4 varies SDIO_SLC0_TX_SHAREMEM_START_REG SLC0 AHB TX start address range 0x0154 R/W SDIO_SLC0_TX_SHAREMEM_END_REG SLC0 AHB TX end address range 0x0158 R/W SDIO_SLC0_RX_SHAREMEM_START_REG SLC0 AHB RX start address range 0x015C R/W SDIO_SLC0_RX_SHAREMEM_END_REG SLC0 AHB RX end address range 0x0160 R/W SDIO_SLC1_TX_SHAREMEM_START_REG SLC1 AHB TX start address range 0x0164 R/W SDIO_SLC1_TX_SHAREMEM_END_REG SLC1 AHB TX end address range 0x0168 R/W SDIO_SLC1_RX_SHAREMEM_START_REG SLC1 AHB RX start address range 0x016C R/W Espressif Systems 1199 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Name Description Address Access SDIO_SLC1_RX_SHAREMEM_END_REG SLC1 AHB RX end address range 0x0170 R/W SDIO_SLC_BURST_LEN_REG DMA AHB burst type configuration 0x017C R/W Interrupt registers SDIO_SLC0INT_RAW_REG SLC0 to slave raw interrupt status 0x0004 varies SDIO_SLC0INT_ST_REG SLC0 to slave masked interrupt status 0x0008 RO SDIO_SLC0INT_ENA_REG SLC0 to slave interrupt enable 0x000C R/W SDIO_SLC0INT_CLR_REG SLC0 to slave interrupt clear 0x0010 WT SDIO_SLC1INT_RAW_REG SLC1 to slave raw interrupt status 0x0014 varies SDIO_SLC1INT_CLR_REG SLC1 to slave interrupt clear 0x0020 WT SDIO_SLCINTVEC_TOHOST_REG Slave to host interrupt vector set 0x005C WT SDIO_SLC1INT_ST1_REG SLC1 to slave masked interrupt status 0x014C RO SDIO_SLC1INT_ENA1_REG SLC1 to slave interrupt enable 0x0150 R/W Status registers SDIO_SLC0_LENGTH_REG Length of transmitting packets 0x00F8 RO 34.8.3 SLC Host Register Summary Name Description Address Access Configuration registers SLCHOST_CONF_REG Edge configuration 0x01F0 R/W Interrupt registers SLCHOST_SLC0HOST_INT_RAW_REG SLC0 to host raw interrupt status 0x0050 varies SLCHOST_SLC1HOST_INT_RAW_REG SLC1 to host raw interrupt status 0x0054 varies SLCHOST_SLC0HOST_INT_ST_REG SLC0 to host masked interrupt status 0x0058 RO SLCHOST_SLC1HOST_INT_ST_REG SLC1 to host masked interrupt status 0x005C RO SLCHOST_CONF_W7_REG Host to slave interrupt vector set 0x008C R/W SLCHOST_SLC0HOST_INT_CLR_REG SLC0 to host interrupt clear 0x00D4 WT SLCHOST_SLC1HOST_INT_CLR_REG SLC1 to host interrupt clear 0x00D8 WT SLCHOST_SLC0HOST_FUNC1_INT_ENA_REG SLC0 to host interrupt enable 0x00DC R/W SLCHOST_SLC1HOST_FUNC1_INT_ENA_REG SLC0 to host interrupt enable 0x00E0 R/W Status registers SLCHOST_SLC0HOST_TOKEN_RDATA_REG Accumulated number of SLC0 re- ceiving buffers 0x0044 RO SLCHOST_PKT_LEN_REG Length of the transmitting packets 0x0060 RO SLCHOST_SLC1HOST_TOKEN_RDATA_REG Accumulated number of SLC1 re- ceiving buffers 0x00C4 RO Communication Registers SLCHOST_CONF_Wn_REG(n: 0-2) Host and slave communication 0x006C+0x4*n R/W SLCHOST_CONF_W3_REG Host and slave communication 0x0078 R/W SLCHOST_CONF_W4_REG Host and slave communication 0x007C R/W SLCHOST_CONF_W6_REG Host and slave communication 0x0088 R/W Espressif Systems 1200 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Name Description Address Access SLCHOST_CONF_Wn_REG(n: 8-15) Host and slave communication 0x009C+0x4*(n- 8) R/W Espressif Systems 1201 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) 34.9 Registers The addresses in this section are relative to the SDIO Slave Controller base address provided in Table 4.3-2 in Chapter 4 System and Memory. 34.9.1 HINF Registers Register 34.1. HINF_CFG_DATA0_REG (0x0000) HINF_USER_ID_FN1 0x92 31 16 HINF_DEVICE_ID_FN1 0x6666 15 0 Reset HINF_DEVICE_ID_FN1 Configures device ID of function 1 in SDIO CIS. (R/W) HINF_USER_ID_FN1 Configures user ID of function 1 in SDIO CIS. (R/W) Espressif Systems 1202 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Register 34.2. HINF_CFG_DATA1_REG (0x0004) (reserved) 0 31 25 HINF_FUNC2_EPS 0 24 HINF_SDIO_VER 0x232 23 12 HINF_IOENABLE1 0 11 HINF_EMP 0 10 HINF_FUNC1_EPS 0 9 HINF_CD_DISABLE 0 8 HINF_IOENABLE2 0 7 (reserved) 0 6 HINF_SDIO_IOREADY2 0 5 HINF_SDIO_CD_ENABLE 1 4 HINF_HIGHSPEED_MODE 0 3 HINF_HIGHSPEED_ENABLE 0 2 HINF_SDIO_IOREADY1 0 1 (reserved) 1 0 Reset HINF_SDIO_IOREADY1 Configures the field IOR1 in SDIO CCCR and the field function 1 ready in SDIO CIS. 0: The function 1 is not ready 1: The function 1 is ready Please refer to SDIO Specification for details. (R/W) HINF_HIGHSPEED_ENABLE Configures whether to support SHS in SDIO CCCR. 0: Not support High-Speed mode 1: Support High-Speed mode Please refer to SDIO Specification for details. (R/W) HINF_HIGHSPEED_MODE Represents whether EHS status is enabled in SDIO CCCR. 0: Disabled 1: Enabled Please refer to SDIO Specification for details. (RO) HINF_SDIO_CD_ENABLE Configures whether to enable SDIO card detection. 0: Disable 1: Enable (R/W) HINF_SDIO_IOREADY2 Configures the field IOR2 in SDIO CCCR and the field function 2 ready in SDIO CIS. 0: The function 2 is not ready 1: The function 2 is ready Please refer to SDIO Specification for details. (R/W) HINF_IOENABLE2 Represents whether IOE2 is enabled in SDIO CCCR. 0: The function 2 is disabled 1: The function 2 is enabled Please refer to SDIO Specification for details. (RO) Continued on the next page... Espressif Systems 1203 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Register 34.2. HINF_CFG_DATA1_REG (0x0004) Continued from the previous page... HINF_CD_DISABLE Represents whether CD is disabled in SDIO CCCR. 0: Enabled 1: Disabled Please refer to SDIO Specification for details. (RO) HINF_FUNC1_EPS Represents function 1 EPS status in SDIO FBR. 0: The function 1 operates in Higher Current Mode 1: The function 1 works in Lower Current Mode Please refer to SDIO Specification for details. (RO) HINF_EMP Represents EMPC status in SDIO CCCR. 0: Master Power Control is disabled 1: Master Power Control is enabled Please refer to SDIO Specification for details. (RO) HINF_IOENABLE1 Represents IOE1 status in SDIO CCCR. 0: The function 1 is disabled 1: The function 1 is enabled Please refer to SDIO Specification for details. (RO) HINF_SDIO_VER Configures SD bit[3:0], SDIO bit[3:0], CCCR bit[3:0] in SDIO CCCR. HINF_SDIO_VER[11:8] mapping to SD bit[3:0] HINF_SDIO_VER[7:4] mapping to SDIO bit[3:0] HINF_SDIO_VER[3:0] mapping to CCCR bit[3:0] Please refer to SDIO Specification for details. (R/W) HINF_FUNC2_EPS Represents function 2 EPS status in SDIO FBR. 0: The function 2 operates in Higher Current Mode 1: The function 2 works in Lower Current Mode Please refer to SDIO Specification for details. (RO) Espressif Systems 1204 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Register 34.3. HINF_CFG_DATA7_REG (0x001C) (reserved) 0 31 HINF_SDIO_WAKEUP_CLR 0 30 (reserved) 0x238 29 20 HINF_ESDIO_DATA1_INT_EN 0 19 (reserved) 0x1 18 17 HINF_SDIO_RST 0 16 HINF_CHIP_STATE 0x0 15 8 HINF_PIN_STATE 0x0 7 0 Reset HINF_PIN_STATE Configures SDIO CIS address 318 and 574. Please refer to SDIO Specification for details. (R/W) HINF_CHIP_STATE Configures SDIO CIS address 312, 315, 568, and 571. Please refer to SDIO Specification for details. (R/W) HINF_SDIO_RST Configures whether to reset the SDIO slave module. 0: No effect 1: Reset (R/W) HINF_ESDIO_DATA1_INT_EN Configures whether to enable SDIO interrupt on data1 line. 0: Disable 1: Enable (R/W) HINF_SDIO_WAKEUP_CLR Configures whether to clear wake up signal after the chip is waken up by the SDIO slave. 0: No effect 1: Clear (WT) Register 34.4. HINF_CIS_CONF_Wn_REG(n: 0-7) (0x0020+0x4*n) HINF_CIS_CONF_Wn 0xffffffff 31 0 Reset HINF_CIS_CONF_Wn Configures SDIO CIS address (39+4*n) (36+4*n). Please refer to SDIO Spec- ification for details. (R/W) Espressif Systems 1205 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Register 34.5. HINF_CFG_DATA16_REG (0x0040) HINF_USER_ID_FN2 0x92 31 16 HINF_DEVICE_ID_FN2 0x7777 15 0 Reset HINF_DEVICE_ID_FN2 Configures device ID of function 2 in SDIO CIS. (R/W) HINF_USER_ID_FN2 Configures user ID of function 2 in SDIO CIS. (R/W) Register 34.6. HINF_CONF_STATUS_REG (0x0054) (reserved) 0x0 31 8 HINF_FUNC0_CONFIG0 0x0 7 0 Reset HINF_FUNC0_CONFIG0 Represents SDIO CIS function 0 config0 (addr: 0x20f0) status. Please refer to SDIO Specification for details. (RO) Espressif Systems 1206 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) 34.9.2 SLC Registers Register 34.7. SDIO_SLCCONF0_REG (0x0000) (reserved) 1 31 SDIO_SLC1_TOKEN_AUTO_CLR 1 30 SDIO_SLC1_TXDATA_BURST_EN 1 29 SDIO_SLC1_TXDSCR_BURST_EN 1 28 (reserved) 0x3 27 26 SDIO_SLC1_RXDATA_BURST_EN 1 25 SDIO_SLC1_RXDSCR_BURST_EN 1 24 SDIO_SLC1_RX_NO_RESTART_CLR 0 23 SDIO_SLC1_RX_AUTO_WRBACK 0 22 SDIO_SLC1_RX_LOOP_TEST 1 21 SDIO_SLC1_TX_LOOP_TEST 1 20 (reserved) 0x3 19 18 SDIO_SLC1_RX_RST 0 17 SDIO_SLC1_TX_RST 0 16 (reserved) 1 15 SDIO_SLC0_TOKEN_AUTO_CLR 1 14 SDIO_SLC0_TXDATA_BURST_EN 1 13 SDIO_SLC0_TXDSCR_BURST_EN 1 12 (reserved) 0x3 11 10 SDIO_SLC0_RXDATA_BURST_EN 1 9 SDIO_SLC0_RXDSCR_BURST_EN 1 8 SDIO_SLC0_RX_NO_RESTART_CLR 0 7 SDIO_SLC0_RX_AUTO_WRBACK 0 6 SDIO_SLC0_RX_LOOP_TEST 0 5 SDIO_SLC0_TX_LOOP_TEST 0 4 (reserved) 0x0 3 2 SDIO_SLC0_RX_RST 0 1 SDIO_SLC0_TX_RST 0 0 Reset SDIO_SLC0_TX_RST Configures whether to reset TX (host to slave) FSM (finite state machine) in SLC0. 0: No effect 1: Reset (R/W) SDIO_SLC0_RX_RST Configures whether to reset RX (slave to host) FSM in SCL0. 0: No effect 1: Reset (R/W) SDIO_SLC0_TX_LOOP_TEST Configures whether SCL0 loops around when the slave buffer finishes receiving packets from the host. 0: Not loop around 1: Loop around, and hardware will not change the owner bit in the linked list (R/W) SDIO_SLC0_RX_LOOP_TEST Configures whether SCL0 loops around when the slave buffer finishes sending packets to the host. 0: Not loop around 1: Loop around, and hardware will not change the owner bit in the linked list (R/W) SDIO_SLC0_RX_AUTO_WRBACK Configures whether SCL0 changes the owner bit of RX linked list. 0: Not change 1: Change (R/W) SDIO_SLC0_RX_NO_RESTART_CLR Please initialize to 1, and do not modify it. (R/W) SDIO_SLC0_RXDSCR_BURST_EN Configures whether SCL0 can use AHB burst operation when reading the RX linked list from memory. 0: Only use single operation 1: Can use burst operation (R/W) Continued on the next page... Espressif Systems 1207 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Register 34.7. SDIO_SLCCONF0_REG (0x0000) Continued from the previous page... SDIO_SLC0_RXDATA_BURST_EN Configures whether SCL0 can use AHB burst operation when read data from memory. 0: Only use single operation 1: Can use burst operation (R/W) SDIO_SLC0_TXDSCR_BURST_EN Configures whether SCL0 can use AHB burst operation when read the TX linked list from memory. 0: Only use single operation 1: Can use burst operation (R/W) SDIO_SLC0_TXDATA_BURST_EN Configures whether SCL0 can use AHB burst operation when send data to memory. 0: Only use single operation 1: Can use burst operation (R/W) SDIO_SLC0_TOKEN_AUTO_CLR Please initialize to 0, and do not modify it. (R/W) SDIO_SLC1_TX_RST Configures whether to reset TX FSM in SLC1. 0: No effect 1: Reset (R/W) SDIO_SLC1_RX_RST Configures whether to reset RX FSM in SLC1. 0: No effect 1: Reset (R/W) SDIO_SLC1_TX_LOOP_TEST Configures whether SCL1 loops around when the slave buffer finishes receiving packets from the host. 0: Not loop around 1: Loop around, and hardware will not change the owner bit in the linked list (R/W) SDIO_SLC1_RX_LOOP_TEST Configures whether SCL1 loops around when the slave buffer finishes sending packets to the host. 0: Not loop around 1: Loop around, and hardware will not change the owner bit in the linked list (R/W) Continued on the next page... Espressif Systems 1208 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Register 34.7. SDIO_SLCCONF0_REG (0x0000) Continued from the previous page... SDIO_SLC1_RX_AUTO_WRBACK Configures whether SCL1 changes the owner bit of the RX linked list. 0: Not change 1: Change (R/W) SDIO_SLC1_RX_NO_RESTART_CLR Please initialize to 1, and do not modify it. (R/W) SDIO_SLC1_RXDSCR_BURST_EN Configures whether SCL1 can use AHB burst operation when read the RX linked list from memory. 0: Only use single operation 1: Can use burst operation (R/W) SDIO_SLC1_RXDATA_BURST_EN Configures whether SCL1 can use AHB burst operation when reading data from memory. 0: Only use single operation 1: Can use burst operation (R/W) SDIO_SLC1_TXDSCR_BURST_EN Configures whether SCL1 can use AHB burst operation when read the TX linked list from memory. 0: Only use single operation 1: Can use burst operation (R/W) SDIO_SLC1_TXDATA_BURST_EN Configures whether SCL1 can use AHB burst operation when send data to memory. 0: Only use single operation 1: Can use burst operation (R/W) SDIO_SLC1_TOKEN_AUTO_CLR Please initialize to 0, and do not modify it. (R/W) Espressif Systems 1209 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Register 34.8. SDIO_SLC0RX_LINK_REG (0x003C) SDIO_SLC0_RXLINK_PARK 1 31 SDIO_SLC0_RXLINK_RESTART 0 30 SDIO_SLC0_RXLINK_START 0 29 SDIO_SLC0_RXLINK_STOP 0 28 (reserved) 0x0 27 0 Reset SDIO_SLC0_RXLINK_STOP Configures whether to stop SLC0 RX linked list operation. 0: No effect 1: Stop the operation (R/W/SC) SDIO_SLC0_RXLINK_START Configures whether to start SLC0 RX linked list operation from the address indicated by SDIO_SLC0_RXLINK_ADDR. 0: No effect 1: Start the operation (R/W/SC) SDIO_SLC0_RXLINK_RESTART Configures whether to restart and continue SLC0 RX linked list op- eration. 0: No effect 1: Restart the operation (R/W/SC) SDIO_SLC0_RXLINK_PARK Represents SLC0 RX linked list FSM state. 0: The FSM not in idle state 1: The FSM in idle state (RO) Register 34.9. SDIO_SLC0RX_LINK_ADDR_REG (0x0040) SDIO_SLC0_RXLINK_ADDR 0x0 31 0 Reset SDIO_SLC0_RXLINK_ADDR Configures SLC0 RX linked list initial address. (R/W) Espressif Systems 1210 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Register 34.10. SDIO_SLC0TX_LINK_REG (0x0044) SDIO_SLC0_TXLINK_PARK 1 31 SDIO_SLC0_TXLINK_RESTART 0 30 SDIO_SLC0_TXLINK_START 0 29 SDIO_SLC0_TXLINK_STOP 0 28 (reserved) 0x0 27 0 Reset SDIO_SLC0_TXLINK_STOP Configures whether to stop SLC0 TX linked list operation. 0: No effect 1: Stop the operation (R/W/SC) SDIO_SLC0_TXLINK_START Configures whether to start SLC0 TX linked list operation from the ad- dress indicated by SDIO_SLC0_TXLINK_ADDR. 0: No effect 1: Start the operation (R/W/SC) SDIO_SLC0_TXLINK_RESTART Configures whether to restart and continue SLC0 TX linked list op- eration. 0: No effect 1: Restart the operation (R/W/SC) SDIO_SLC0_TXLINK_PARK Represents SLC0 TX linked list FSM state. 0: The FSM not in idle state 1: The FSM in idle state (RO) Register 34.11. SDIO_SLC0TX_LINK_ADDR_REG (0x0048) SDIO_SLC0_TXLINK_ADDR 0x0 31 0 Reset SDIO_SLC0_TXLINK_ADDR Configures SLC0 TX linked list initial address. (R/W) Espressif Systems 1211 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Register 34.12. SDIO_SLC1RX_LINK_REG (0x004C) SDIO_SLC1_RXLINK_PARK 1 31 SDIO_SLC1_RXLINK_RESTART 0 30 SDIO_SLC1_RXLINK_START 0 29 SDIO_SLC1_RXLINK_STOP 0 28 (reserved) 0x100000 27 0 Reset SDIO_SLC1_RXLINK_STOP Configures whether to stop SLC1 RX linked list operation. 0: No effect 1: Stop the operation (R/W/SC) SDIO_SLC1_RXLINK_START Configures whether to start SLC1 RX linked list operation from the address indicated by SDIO_SLC1_RXLINK_ADDR. 0: No effect 1: Start the operation (R/W/SC) SDIO_SLC1_RXLINK_RESTART Configures whether to restart and continue SLC1 RX linked list op- eration. 0: No effect 1: Restart the operation (R/W/SC) SDIO_SLC1_RXLINK_PARK Represents SLC1 RX linked list FSM state. 0: The FSM not in idle state 1: The FSM in idle state (RO) Register 34.13. SDIO_SLC1RX_LINK_ADDR_REG (0x0050) SDIO_SLC1_RXLINK_ADDR 0x0 31 0 Reset SDIO_SLC1_RXLINK_ADDR Configures SLC1 RX linked list initial address. (R/W) Espressif Systems 1212 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Register 34.14. SDIO_SLC1TX_LINK_REG (0x0054) SDIO_SLC1_TXLINK_PARK 1 31 SDIO_SLC1_TXLINK_RESTART 0 30 SDIO_SLC1_TXLINK_START 0 29 SDIO_SLC1_TXLINK_STOP 0 28 (reserved) 0x0 27 0 Reset SDIO_SLC1_TXLINK_STOP Configures whether to stop SLC1 TX linked list operation. 0: No effect 1: Stop the operation (R/W/SC) SDIO_SLC1_TXLINK_START Configures whether to start SLC1 TX linked list operation from the ad- dress indicated by SDIO_SLC1_TXLINK_ADDR. 0: No effect 1: Start the operation (R/W/SC) SDIO_SLC1_TXLINK_RESTART Configures whether to restart and continue SLC1 TX linked list op- eration. 0: No effect 1: Restart the operation (R/W/SC) SDIO_SLC1_TXLINK_PARK Represents SLC1 TX linked list FSM state. 0: The FSM not in idle state 1: The FSM in idle state (RO) Register 34.15. SDIO_SLC1TX_LINK_ADDR_REG (0x0058) SDIO_SLC1_TXLINK_ADDR 0x0 31 0 Reset SDIO_SLC1_TXLINK_ADDR Configures SLC1 TX linked list initial address. (R/W) Espressif Systems 1213 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Register 34.16. SDIO_SLC0TOKEN1_REG (0x0064) (reserved) 0x0 31 28 SDIO_SLC0_TOKEN1 0x0 27 16 (reserved) 0 15 SDIO_SLC0_TOKEN1_INC_MORE 0 14 SDIO_SLC0_TOKEN1_INC 0 13 SDIO_SLC0_TOKEN1_WR 0 12 SDIO_SLC0_TOKEN1_WDATA 0x0 11 0 Reset SDIO_SLC0_TOKEN1_WDATA Configures SLC0 token 1 value. (WT) SDIO_SLC0_TOKEN1_WR Configures this bit to 1 to write SDIO_SLC0_TOKEN1_WDATA into SDIO_SLC0_TOKEN1. (WT) SDIO_SLC0_TOKEN1_INC Configures this bit to 1 to add 1 to SDIO_SLC0_TOKEN1. (WT) SDIO_SLC0_TOKEN1_INC_MORE Configures this bit to 1 to add the value of SDIO_SLC0_TOKEN1_WDATA to SDIO_SLC0_TOKEN1. (WT) SDIO_SLC0_TOKEN1 Represents the SLC0 accumulated number of buffers for receiving packets. (RO) Register 34.17. SDIO_SLC1TOKEN1_REG (0x006C) (reserved) 0x0 31 28 SDIO_SLC1_TOKEN1 0x0 27 16 (reserved) 0 15 SDIO_SLC1_TOKEN1_INC_MORE 0 14 SDIO_SLC1_TOKEN1_INC 0 13 SDIO_SLC1_TOKEN1_WR 0 12 SDIO_SLC1_TOKEN1_WDATA 0x0 11 0 Reset SDIO_SLC1_TOKEN1_WDATA Configures SLC1 token1 value. (WT) SDIO_SLC1_TOKEN1_WR Configures this bit to 1 to write SDIO_SLC1_TOKEN1_WDATA into SDIO_SLC1_TOKEN1. (WT) SDIO_SLC1_TOKEN1_INC Configures this bit to 1 to add 1 to SDIO_SLC1_TOKEN1. (WT) SDIO_SLC1_TOKEN1_INC_MORE Configures this bit to 1 to add the value of SDIO_SLC1_TOKEN1_WDATA to SDIO_SLC1_TOKEN1. (WT) SDIO_SLC1_TOKEN1 Represents SLC1 accumulated number of buffers for receiving packets. (RO) Espressif Systems 1214 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Register 34.18. SDIO_SLCCONF1_REG (0x0070) (reserved) 0x0 31 22 SDIO_SLC1_RX_STITCH_EN 1 21 SDIO_SLC1_TX_STITCH_EN 1 20 SDIO_HOST_INT_LEVEL_SEL 0 19 (reserved) 0x0 18 7 SDIO_SLC0_RX_STITCH_EN 1 6 SDIO_SLC0_TX_STITCH_EN 1 5 SDIO_SLC0_LEN_AUTO_CLR 1 4 SDIO_SDIO_CMD_HOLD_EN 1 3 (reserved) 0x0 2 0 Reset SDIO_SDIO_CMD_HOLD_EN Please initialize to 0, and do not modify it. (R/W) SDIO_SLC0_LEN_AUTO_CLR Please initialize to 0, and do not modify it. (R/W) SDIO_SLC0_TX_STITCH_EN Please initialize to 0, and do not modify it. (R/W) SDIO_SLC0_RX_STITCH_EN Please initialize to 0, and do not modify it. (R/W) SDIO_HOST_INT_LEVEL_SEL Configures the polarity of interrupt to host. 0: Low active 1: High active (R/W) SDIO_SLC1_TX_STITCH_EN Please initialize to 0, and do not modify it. (R/W) SDIO_SLC1_RX_STITCH_EN Please initialize to 0, and do not modify it. (R/W) Register 34.19. SDIO_SLC_RX_DSCR_CONF_REG (0x00A8) (reserved) 0x101b80d 31 1 SDIO_SLC0_TOKEN_NO_REPLACE 0 0 Reset SDIO_SLC0_TOKEN_NO_REPLACE Please initialize to 1, and do not modify it. (R/W) Espressif Systems 1215 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Register 34.20. SDIO_SLC0_LEN_CONF_REG (0x00F4) (reserved) 0x20 31 23 SDIO_SLC0_LEN_INC_MORE 0 22 SDIO_SLC0_LEN_INC 0 21 SDIO_SLC0_LEN_WR 0 20 SDIO_SLC0_LEN_WDATA 0x0 19 0 Reset SDIO_SLC0_LEN_WDATA Configures the length of the data that the slave wants to send. (WT) SDIO_SLC0_LEN_WR Configures this bit to 1 to write SDIO_SLC0_LEN_WDATA into SDIO_SLC0_LEN and SLCHOST_HOSTSLCHOST_SLC0_LEN. (WT) SDIO_SLC0_LEN_INC Configures this bit to 1 to add 1 to SDIO_SLC0_LEN and SL- CHOST_HOSTSLCHOST_SLC0_LEN. (WT) SDIO_SLC0_LEN_INC_MORE Configures this bit to 1 to add the value of SDIO_SLC0_LEN_WDATA to SDIO_SLC0_LEN and SLCHOST_HOSTSLCHOST_SLC0_LEN. (WT) Register 34.21. SDIO_SLC0_TX_SHAREMEM_START_REG (0x0154) SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR 0x0 31 0 Reset SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR Configures SLC0 host to slave channel AHB start address boundary. (R/W) Espressif Systems 1216 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Register 34.22. SDIO_SLC0_TX_SHAREMEM_END_REG (0x0158) SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR 0xffffffff 31 0 Reset SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR Configures SLC0 host to slave channel AHB end address boundary. (R/W) Register 34.23. SDIO_SLC0_RX_SHAREMEM_START_REG (0x015C) SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR 0x0 31 0 Reset SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR Configures SLC0 slave to host channel AHB start address boundary. (R/W) Espressif Systems 1217 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Register 34.24. SDIO_SLC0_RX_SHAREMEM_END_REG (0x0160) SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR 0xffffffff 31 0 Reset SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR Configures SLC0 slave to host channel AHB end address boundary. (R/W) Register 34.25. SDIO_SLC1_TX_SHAREMEM_START_REG (0x0164) SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR 0x0 31 0 Reset SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR Configures SLC1 host to slave channel AHB start address boundary. (R/W) Espressif Systems 1218 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Register 34.26. SDIO_SLC1_TX_SHAREMEM_END_REG (0x0168) SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR 0xffffffff 31 0 Reset SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR Configures SLC1 host to slave channel AHB end address boundary. (R/W) Register 34.27. SDIO_SLC1_RX_SHAREMEM_START_REG (0x016C) SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR 0x0 31 0 Reset SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR Configures SLC1 slave to host channel AHB start address boundary. (R/W) Espressif Systems 1219 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Register 34.28. SDIO_SLC1_RX_SHAREMEM_END_REG (0x0170) SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR 0xffffffff 31 0 Reset SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR Configures SLC1 slave to host channel AHB end address boundary. (R/W) Register 34.29. SDIO_SLC_BURST_LEN_REG (0x017C) (reserved) 0x0 31 4 SDIO_SLC1_RXDATA_BURST_LEN 1 3 SDIO_SLC1_TXDATA_BURST_LEN 1 2 SDIO_SLC0_RXDATA_BURST_LEN 1 1 SDIO_SLC0_TXDATA_BURST_LEN 1 0 Reset SDIO_SLC0_TXDATA_BURST_LEN Configures SLC0 host to slave channel AHB burst type. 0: Can use incr4 1: Can use incr8 (R/W) SDIO_SLC0_RXDATA_BURST_LEN Configures SLC0 slave to host channel AHB burst type. 0: Can use incr and incr4 1: Can use incr and incr8 (R/W) SDIO_SLC1_TXDATA_BURST_LEN Configures SLC1 host to slave channel AHB burst type. 0: Can use incr4 1: Can use incr8 (R/W) SDIO_SLC1_RXDATA_BURST_LEN Configures SLC1 slave to host channel AHB burst type. 0: Can use incr and incr4 1: Can use incr and incr8 (R/W) Espressif Systems 1220 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Register 34.30. SDIO_SLC0INT_RAW_REG (0x0004) (reserved) 0x0 31 21 SDIO_SLC0_RX_DSCR_ERR_INT_RAW 0 20 SDIO_SLC0_TX_DSCR_ERR_INT_RAW 0 19 (reserved) 0 18 SDIO_SLC0_RX_EOF_INT_RAW 0 17 SDIO_SLC0_RX_DONE_INT_RAW 0 16 SDIO_SLC0_TX_SUC_EOF_INT_RAW 0 15 SDIO_SLC0_TX_DONE_INT_RAW 0 14 (reserved) 0x0 13 12 SDIO_SLC0_TX_OVF_INT_RAW 0 11 SDIO_SLC0_RX_UDF_INT_RAW 0 10 SDIO_SLC0_TX_START_INT_RAW 0 9 SDIO_SLC0_RX_START_INT_RAW 0 8 SDIO_SLC_FRHOST_BIT7_INT_RAW 0 7 SDIO_SLC_FRHOST_BIT6_INT_RAW 0 6 SDIO_SLC_FRHOST_BIT5_INT_RAW 0 5 SDIO_SLC_FRHOST_BIT4_INT_RAW 0 4 SDIO_SLC_FRHOST_BIT3_INT_RAW 0 3 SDIO_SLC_FRHOST_BIT2_INT_RAW 0 2 SDIO_SLC_FRHOST_BIT1_INT_RAW 0 1 SDIO_SLC_FRHOST_BIT0_INT_RAW 0 0 Reset SDIO_SLC_FRHOST_BITn_INT_RAW (n: 0-7) The raw interrupt status of SLC_FRHOST_BITn_INT (n: 0-7). (R/WTC/SS) SDIO_SLC0_RX_START_INT_RAW The raw interrupt status of SLC0_RX_START_INT. (R/WTC/SS) SDIO_SLC0_TX_START_INT_RAW The raw interrupt status of SLC0_TX_START_INT. (R/WTC/SS) SDIO_SLC0_RX_UDF_INT_RAW The raw interrupt status of SLC0_RX_UDF_INT. (R/WTC/SS) SDIO_SLC0_TX_OVF_INT_RAW The raw interrupt status of SLC0_TX_OVF_INT. (R/WTC/SS) SDIO_SLC0_TX_DONE_INT_RAW The raw interrupt status of SLC0_TX_DONE_INT. (R/WTC/SS) SDIO_SLC0_TX_SUC_EOF_INT_RAW The raw interrupt status of SLC0_TX_SUC_EOF_INT. (R/WTC/SS) SDIO_SLC0_RX_DONE_INT_RAW The raw interrupt status of SLC0_RX_DONE_INT. (R/WTC/SS) SDIO_SLC0_RX_EOF_INT_RAW The raw interrupt status of SLC0_RX_EOF_INT. (R/WTC/SS) SDIO_SLC0_TX_DSCR_ERR_INT_RAW The raw interrupt status of SLC0_TX_DSCR_ERR_INT. (R/WTC/SS) SDIO_SLC0_RX_DSCR_ERR_INT_RAW The raw interrupt status of SLC0_RX_DSCR_ERR_INT. (R/WTC/SS) Espressif Systems 1221 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Register 34.31. SDIO_SLC0INT_ST_REG (0x0008) (reserved) 0x0 31 21 SDIO_SLC0_RX_DSCR_ERR_INT_ST 0 20 SDIO_SLC0_TX_DSCR_ERR_INT_ST 0 19 (reserved) 0 18 SDIO_SLC0_RX_EOF_INT_ST 0 17 SDIO_SLC0_RX_DONE_INT_ST 0 16 SDIO_SLC0_TX_SUC_EOF_INT_ST 0 15 SDIO_SLC0_TX_DONE_INT_ST 0 14 (reserved) 0x0 13 12 SDIO_SLC0_TX_OVF_INT_ST 0 11 SDIO_SLC0_RX_UDF_INT_ST 0 10 SDIO_SLC0_TX_START_INT_ST 0 9 SDIO_SLC0_RX_START_INT_ST 0 8 SDIO_SLC_FRHOST_BIT7_INT_ST 0 7 SDIO_SLC_FRHOST_BIT6_INT_ST 0 6 SDIO_SLC_FRHOST_BIT5_INT_ST 0 5 SDIO_SLC_FRHOST_BIT4_INT_ST 0 4 SDIO_SLC_FRHOST_BIT3_INT_ST 0 3 SDIO_SLC_FRHOST_BIT2_INT_ST 0 2 SDIO_SLC_FRHOST_BIT1_INT_ST 0 1 SDIO_SLC_FRHOST_BIT0_INT_ST 0 0 Reset SDIO_SLC_FRHOST_BITn_INT_ST (n: 0-7) The masked interrupt status of SLC_FRHOST_BITn_INT (n: 0-7). (RO) SDIO_SLC0_RX_START_INT_ST The masked interrupt status of SLC0_RX_START_INT. (RO) SDIO_SLC0_TX_START_INT_ST The masked interrupt status bit of SLC0_TX_START_INT. (RO) SDIO_SLC0_RX_UDF_INT_ST The masked interrupt status of SLC0_RX_UDF_INT. (RO) SDIO_SLC0_TX_OVF_INT_ST The masked interrupt status of SLC0_TX_OVF_INT. (RO) SDIO_SLC0_TX_DONE_INT_ST The masked interrupt status of SLC0_TX_DONE_INT. (RO) SDIO_SLC0_TX_SUC_EOF_INT_ST The masked interrupt status of SLC0_TX_SUC_EOF_INT. (RO) SDIO_SLC0_RX_DONE_INT_ST The masked interrupt status of SLC0_RX_DONE_INT. (RO) SDIO_SLC0_RX_EOF_INT_ST The masked interrupt status bit of SLC0_RX_EOF_INT. (RO) SDIO_SLC0_TX_DSCR_ERR_INT_ST The masked interrupt status of SLC0_TX_DSCR_ERR_INT. (RO) SDIO_SLC0_RX_DSCR_ERR_INT_ST The masked interrupt status of SLC0_RX_DSCR_ERR_INT. (RO) Espressif Systems 1222 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Register 34.32. SDIO_SLC0INT_ENA_REG (0x000C) (reserved) 0x0 31 21 SDIO_SLC0_RX_DSCR_ERR_INT_ENA 0 20 SDIO_SLC0_TX_DSCR_ERR_INT_ENA 0 19 (reserved) 0 18 SDIO_SLC0_RX_EOF_INT_ENA 0 17 SDIO_SLC0_RX_DONE_INT_ENA 0 16 SDIO_SLC0_TX_SUC_EOF_INT_ENA 0 15 SDIO_SLC0_TX_DONE_INT_ENA 0 14 (reserved) 0x0 13 12 SDIO_SLC0_TX_OVF_INT_ENA 0 11 SDIO_SLC0_RX_UDF_INT_ENA 0 10 SDIO_SLC0_TX_START_INT_ENA 0 9 SDIO_SLC0_RX_START_INT_ENA 0 8 SDIO_SLC_FRHOST_BIT7_INT_ENA 0 7 SDIO_SLC_FRHOST_BIT6_INT_ENA 0 6 SDIO_SLC_FRHOST_BIT5_INT_ENA 0 5 SDIO_SLC_FRHOST_BIT4_INT_ENA 0 4 SDIO_SLC_FRHOST_BIT3_INT_ENA 0 3 SDIO_SLC_FRHOST_BIT2_INT_ENA 0 2 SDIO_SLC_FRHOST_BIT1_INT_ENA 0 1 SDIO_SLC_FRHOST_BIT0_INT_ENA 0 0 Reset SDIO_SLC_FRHOST_BITn_INT_ENA (n: 0-7) Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 0-7). (R/W) SDIO_SLC0_RX_START_INT_ENA Write 1 to enable interrupt SLC0_RX_START_INT. (R/W) SDIO_SLC0_TX_START_INT_ENA Write 1 to enable interrupt SLC0_TX_START_INT. (R/W) SDIO_SLC0_RX_UDF_INT_ENA Write 1 to enable interrupt SLC0_RX_UDF_INT. (R/W) SDIO_SLC0_TX_OVF_INT_ENA Write 1 to enable interrupt SLC0_TX_OVF_INT. (R/W) SDIO_SLC0_TX_DONE_INT_ENA Write 1 to enable interrupt SLC0_TX_DONE_INT. (R/W) SDIO_SLC0_TX_SUC_EOF_INT_ENA Write 1 to enable interrupt SLC0_TX_SUC_EOF_INT. (R/W) SDIO_SLC0_RX_DONE_INT_ENA Write 1 to enable interrupt SLC0_RX_DONE_INT. (R/W) SDIO_SLC0_RX_EOF_INT_ENA Write 1 to enable interrupt SLC0_RX_EOF_INT. (R/W) SDIO_SLC0_TX_DSCR_ERR_INT_ENA Write 1 to enable interrupt SLC0_TX_DSCR_ERR_INT. (R/W) SDIO_SLC0_RX_DSCR_ERR_INT_ENA Write 1 to enable interrupt SLC0_RX_DSCR_ERR_INT. (R/W) Espressif Systems 1223 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Register 34.33. SDIO_SLC0INT_CLR_REG (0x0010) (reserved) 0x0 31 21 SDIO_SLC0_RX_DSCR_ERR_INT_CLR 0 20 SDIO_SLC0_TX_DSCR_ERR_INT_CLR 0 19 (reserved) 0 18 SDIO_SLC0_RX_EOF_INT_CLR 0 17 SDIO_SLC0_RX_DONE_INT_CLR 0 16 SDIO_SLC0_TX_SUC_EOF_INT_CLR 0 15 SDIO_SLC0_TX_DONE_INT_CLR 0 14 (reserved) 0x0 13 12 SDIO_SLC0_TX_OVF_INT_CLR 0 11 SDIO_SLC0_RX_UDF_INT_CLR 0 10 SDIO_SLC0_TX_START_INT_CLR 0 9 SDIO_SLC0_RX_START_INT_CLR 0 8 SDIO_SLC_FRHOST_BIT7_INT_CLR 0 7 SDIO_SLC_FRHOST_BIT6_INT_CLR 0 6 SDIO_SLC_FRHOST_BIT5_INT_CLR 0 5 SDIO_SLC_FRHOST_BIT4_INT_CLR 0 4 SDIO_SLC_FRHOST_BIT3_INT_CLR 0 3 SDIO_SLC_FRHOST_BIT2_INT_CLR 0 2 SDIO_SLC_FRHOST_BIT1_INT_CLR 0 1 SDIO_SLC_FRHOST_BIT0_INT_CLR 0 0 Reset SDIO_SLC_FRHOST_BITn_INT_CLR (n: 0-7) Write 1 to clear interrupt SLC_FRHOST_BITn_INT (n: 0-7).(WT) SDIO_SLC0_RX_START_INT_CLR Write 1 to clear interrupt SLC0_RX_START_INT. (WT) SDIO_SLC0_TX_START_INT_CLR Write 1 to clear interrupt SLC0_TX_START_INT. (WT) SDIO_SLC0_RX_UDF_INT_CLR Write 1 to clear interrupt SLC0_RX_UDF_INT. (WT) SDIO_SLC0_TX_OVF_INT_CLR Write 1 to clear interrupt SLC0_TX_OVF_INT. (WT) SDIO_SLC0_TX_DONE_INT_CLR Write 1 to clear interrupt SLC0_TX_DONE_INT. (WT) SDIO_SLC0_TX_SUC_EOF_INT_CLR Write 1 to clear interrupt SLC0_TX_SUC_EOF_INT. (WT) SDIO_SLC0_RX_DONE_INT_CLR Write 1 to clear interrupt SLC0_RX_DONE_INT. (WT) SDIO_SLC0_RX_EOF_INT_CLR Write 1 to clear interrupt SLC0_RX_EOF_INT. (WT) SDIO_SLC0_TX_DSCR_ERR_INT_CLR Write 1 to clear interrupt SLC0_TX_DSCR_ERR_INT. (WT) SDIO_SLC0_RX_DSCR_ERR_INT_CLR Write 1 to clear interrupt SLC0_RX_DSCR_ERR_INT. (WT) Espressif Systems 1224 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Register 34.34. SDIO_SLC1INT_RAW_REG (0x0014) (reserved) 0x0 31 21 SDIO_SLC1_RX_DSCR_ERR_INT_RAW 0 20 SDIO_SLC1_TX_DSCR_ERR_INT_RAW 0 19 (reserved) 0 18 SDIO_SLC1_RX_EOF_INT_RAW 0 17 SDIO_SLC1_RX_DONE_INT_RAW 0 16 SDIO_SLC1_TX_SUC_EOF_INT_RAW 0 15 SDIO_SLC1_TX_DONE_INT_RAW 0 14 (reserved) 0x0 13 12 SDIO_SLC1_TX_OVF_INT_RAW 0 11 SDIO_SLC1_RX_UDF_INT_RAW 0 10 SDIO_SLC1_TX_START_INT_RAW 0 9 SDIO_SLC1_RX_START_INT_RAW 0 8 SDIO_SLC_FRHOST_BIT15_INT_RAW 0 7 SDIO_SLC_FRHOST_BIT14_INT_RAW 0 6 SDIO_SLC_FRHOST_BIT13_INT_RAW 0 5 SDIO_SLC_FRHOST_BIT12_INT_RAW 0 4 SDIO_SLC_FRHOST_BIT11_INT_RAW 0 3 SDIO_SLC_FRHOST_BIT10_INT_RAW 0 2 SDIO_SLC_FRHOST_BIT9_INT_RAW 0 1 SDIO_SLC_FRHOST_BIT8_INT_RAW 0 0 Reset SDIO_SLC_FRHOST_BITn_INT_RAW (n: 8-15) The raw interrupt status of SLC_FRHOST_BITn_INT (n: 8-15). (R/WTC/SS) SDIO_SLC1_RX_START_INT_RAW The raw interrupt status of SLC1_RX_START_INT. (R/WTC/SS) SDIO_SLC1_TX_START_INT_RAW The raw interrupt status of SLC1_TX_START_INT. (R/WTC/SS) SDIO_SLC1_RX_UDF_INT_RAW The raw interrupt status of SLC1_RX_UDF_INT. (R/WTC/SS) SDIO_SLC1_TX_OVF_INT_RAW The raw interrupt status of SLC1_TX_OVF_INT. (R/WTC/SS) SDIO_SLC1_TX_DONE_INT_RAW The raw interrupt status of SLC1_TX_DONE_INT. (R/WTC/SS) SDIO_SLC1_TX_SUC_EOF_INT_RAW The raw interrupt status of SLC1_TX_SUC_EOF_INT. (R/WTC/SS) SDIO_SLC1_RX_DONE_INT_RAW The raw interrupt status of SLC1_RX_DONE_INT. (R/WTC/SS) SDIO_SLC1_RX_EOF_INT_RAW The raw interrupt status of SLC1_RX_EOF_INT. (R/WTC/SS) SDIO_SLC1_TX_DSCR_ERR_INT_RAW The raw interrupt status of SLC1_TX_DSCR_ERR_INT. (R/WTC/SS) SDIO_SLC1_RX_DSCR_ERR_INT_RAW The raw interrupt status of SLC1_RX_DSCR_ERR_INT. (R/WTC/SS) Espressif Systems 1225 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Register 34.35. SDIO_SLC1INT_CLR_REG (0x0020) (reserved) 0x0 31 21 SDIO_SLC1_RX_DSCR_ERR_INT_CLR 0 20 SDIO_SLC1_TX_DSCR_ERR_INT_CLR 0 19 (reserved) 0 18 SDIO_SLC1_RX_EOF_INT_CLR 0 17 SDIO_SLC1_RX_DONE_INT_CLR 0 16 SDIO_SLC1_TX_SUC_EOF_INT_CLR 0 15 SDIO_SLC1_TX_DONE_INT_CLR 0 14 (reserved) 0x0 13 12 SDIO_SLC1_TX_OVF_INT_CLR 0 11 SDIO_SLC1_RX_UDF_INT_CLR 0 10 SDIO_SLC1_TX_START_INT_CLR 0 9 SDIO_SLC1_RX_START_INT_CLR 0 8 SDIO_SLC_FRHOST_BIT15_INT_CLR 0 7 SDIO_SLC_FRHOST_BIT14_INT_CLR 0 6 SDIO_SLC_FRHOST_BIT13_INT_CLR 0 5 SDIO_SLC_FRHOST_BIT12_INT_CLR 0 4 SDIO_SLC_FRHOST_BIT11_INT_CLR 0 3 SDIO_SLC_FRHOST_BIT10_INT_CLR 0 2 SDIO_SLC_FRHOST_BIT9_INT_CLR 0 1 SDIO_SLC_FRHOST_BIT8_INT_CLR 0 0 Reset SDIO_SLC_FRHOST_BITn_INT_CLR (n: 8-15) Write 1 to clear interrupt SLC_FRHOST_BITn_INT (n: 8-15). (WT) SDIO_SLC1_RX_START_INT_CLR Write 1 to clear interrupt SLC1_RX_START_INT. (WT) SDIO_SLC1_TX_START_INT_CLR Write 1 to clear interrupt SLC1_TX_START_INT. (WT) SDIO_SLC1_RX_UDF_INT_CLR Write 1 to clear interrupt SLC1_RX_UDF_INT. (WT) SDIO_SLC1_TX_OVF_INT_CLR Write 1 to clear interrupt SLC1_TX_OVF_INT. (WT) SDIO_SLC1_TX_DONE_INT_CLR Write 1 to clear interrupt SLC1_TX_DONE_INT. (WT) SDIO_SLC1_TX_SUC_EOF_INT_CLR Write 1 to clear interrupt SLC1_TX_SUC_EOF_INT. (WT) SDIO_SLC1_RX_DONE_INT_CLR Write 1 to clear interrupt SLC1_RX_DONE_INT. (WT) SDIO_SLC1_RX_EOF_INT_CLR Write 1 to clear interrupt SLC1_RX_EOF_INT. (WT) SDIO_SLC1_TX_DSCR_ERR_INT_CLR Write 1 to clear interrupt SLC1_TX_DSCR_ERR_INT. (WT) SDIO_SLC1_RX_DSCR_ERR_INT_CLR Write 1 to clear interrupt SLC1_RX_DSCR_ERR_INT. (WT) Register 34.36. SDIO_SLCINTVEC_TOHOST_REG (0x005C) (reserved) 0x0 31 24 SDIO_SLC1_TOHOST_INTVEC 0x0 23 16 (reserved) 0x0 15 8 SDIO_SLC0_TOHOST_INTVEC 0x0 7 0 Reset SDIO_SLC0_TOHOST_INTVEC The interrupt set bit of SLCHOST_SLC0_TOHOST_BITn_INT (n: 0- 7). These bits will be cleared automatically. (WT) SDIO_SLC1_TOHOST_INTVEC The interrupt set bit of SLCHOST_SLC1_TOHOST_BITn_INT (n: 0- 7). These bits will be cleared automatically. (WT) Espressif Systems 1226 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Register 34.37. SDIO_SLC1INT_ST1_REG (0x014C) (reserved) 0x0 31 21 SDIO_SLC1_RX_DSCR_ERR_INT_ST1 0 20 SDIO_SLC1_TX_DSCR_ERR_INT_ST1 0 19 (reserved) 0 18 SDIO_SLC1_RX_EOF_INT_ST1 0 17 SDIO_SLC1_RX_DONE_INT_ST1 0 16 SDIO_SLC1_TX_SUC_EOF_INT_ST1 0 15 SDIO_SLC1_TX_DONE_INT_ST1 0 14 (reserved) 0x0 13 12 SDIO_SLC1_TX_OVF_INT_ST1 0 11 SDIO_SLC1_RX_UDF_INT_ST1 0 10 SDIO_SLC1_TX_START_INT_ST1 0 9 SDIO_SLC1_RX_START_INT_ST1 0 8 SDIO_SLC_FRHOST_BIT15_INT_ST1 0 7 SDIO_SLC_FRHOST_BIT14_INT_ST1 0 6 SDIO_SLC_FRHOST_BIT13_INT_ST1 0 5 SDIO_SLC_FRHOST_BIT12_INT_ST1 0 4 SDIO_SLC_FRHOST_BIT11_INT_ST1 0 3 SDIO_SLC_FRHOST_BIT10_INT_ST1 0 2 SDIO_SLC_FRHOST_BIT9_INT_ST1 0 1 SDIO_SLC_FRHOST_BIT8_INT_ST1 0 0 Reset SDIO_SLC_FRHOST_BITn_INT_ST1 (n: 8-15) The masked interrupt status of SLC_FRHOST_BITn_INT (n: 8-15). (RO) SDIO_SLC1_RX_START_INT_ST1 The masked interrupt status of SLC1_RX_START_INT. (RO) SDIO_SLC1_TX_START_INT_ST1 The masked interrupt status of SLC1_TX_START_INT. (RO) SDIO_SLC1_RX_UDF_INT_ST1 The masked interrupt status of SLC1_RX_UDF_INT. (RO) SDIO_SLC1_TX_OVF_INT_ST1 The masked interrupt status of SLC1_TX_OVF_INT. (RO) SDIO_SLC1_TX_DONE_INT_ST1 The masked interrupt status of SLC1_TX_DONE_INT. (RO) SDIO_SLC1_TX_SUC_EOF_INT_ST1 The masked interrupt status of SLC1_TX_SUC_EOF_INT. (RO) SDIO_SLC1_RX_DONE_INT_ST1 The masked interrupt status of SLC1_RX_DONE_INT. (RO) SDIO_SLC1_RX_EOF_INT_ST1 The masked interrupt status of SLC1_RX_EOF_INT. (RO) SDIO_SLC1_TX_DSCR_ERR_INT_ST1 The masked interrupt status of SLC1_TX_DSCR_ERR_INT. (RO) SDIO_SLC1_RX_DSCR_ERR_INT_ST1 The masked interrupt status of SLC1_RX_DSCR_ERR_INT. (RO) Espressif Systems 1227 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Register 34.38. SDIO_SLC1INT_ENA1_REG (0x0150) (reserved) 0x0 31 21 SDIO_SLC1_RX_DSCR_ERR_INT_ENA1 0 20 SDIO_SLC1_TX_DSCR_ERR_INT_ENA1 0 19 (reserved) 0 18 SDIO_SLC1_RX_EOF_INT_ENA1 0 17 SDIO_SLC1_RX_DONE_INT_ENA1 0 16 SDIO_SLC1_TX_SUC_EOF_INT_ENA1 0 15 SDIO_SLC1_TX_DONE_INT_ENA1 0 14 (reserved) 0x0 13 12 SDIO_SLC1_TX_OVF_INT_ENA1 0 11 SDIO_SLC1_RX_UDF_INT_ENA1 0 10 SDIO_SLC1_TX_START_INT_ENA1 0 9 SDIO_SLC1_RX_START_INT_ENA1 0 8 SDIO_SLC_FRHOST_BIT15_INT_ENA1 0 7 SDIO_SLC_FRHOST_BIT14_INT_ENA1 0 6 SDIO_SLC_FRHOST_BIT13_INT_ENA1 0 5 SDIO_SLC_FRHOST_BIT12_INT_ENA1 0 4 SDIO_SLC_FRHOST_BIT11_INT_ENA1 0 3 SDIO_SLC_FRHOST_BIT10_INT_ENA1 0 2 SDIO_SLC_FRHOST_BIT9_INT_ENA1 0 1 SDIO_SLC_FRHOST_BIT8_INT_ENA1 0 0 Reset SDIO_SLC_FRHOST_BITn_INT_ENA1 (n: 8-15) Write 1 to enable interrupt SLC_FRHOST_BITn_INT (n: 8-15). (R/W) SDIO_SLC1_RX_START_INT_ENA1 Write 1 to enable interrupt SLC1_RX_START_INT. (R/W) SDIO_SLC1_TX_START_INT_ENA1 Write 1 to enable interrupt SLC1_TX_START_INT. (R/W) SDIO_SLC1_RX_UDF_INT_ENA1 Write 1 to enable interrupt SLC1_RX_UDF_INT. (R/W) SDIO_SLC1_TX_OVF_INT_ENA1 Write 1 to enable interrupt SLC1_TX_OVF_INT. (R/W) SDIO_SLC1_TX_DONE_INT_ENA1 Write 1 to enable interrupt SLC1_TX_DONE_INT. (R/W) SDIO_SLC1_TX_SUC_EOF_INT_ENA1 Write 1 to enable interrupt SLC1_TX_SUC_EOF_INT. (R/W) SDIO_SLC1_RX_DONE_INT_ENA1 Write 1 to enable interrupt SLC1_RX_DONE_INT. (R/W) SDIO_SLC1_RX_EOF_INT_ENA1 Write 1 to enable interrupt SLC1_RX_EOF_INT. (R/W) SDIO_SLC1_TX_DSCR_ERR_INT_ENA1 Write 1 to enable interrupt SLC1_TX_DSCR_ERR_INT. (R/W) SDIO_SLC1_RX_DSCR_ERR_INT_ENA1 Write 1 to enable interrupt SLC1_RX_DSCR_ERR_INT. (R/W) Register 34.39. SDIO_SLC0_LENGTH_REG (0x00F8) (reserved) 0x0 31 20 SDIO_SLC0_LEN 0x0 19 0 Reset SDIO_SLC0_LEN Represents the accumulated length of data that the slave wants to send. (RO) Espressif Systems 1228 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) 34.9.3 SLC Host Registers Register 34.40. SLCHOST_CONF_REG (0x01F0) (reserved) 0x0 31 28 SLCHOST_HSPEED_CON_EN 0 27 (reserved) 0x0 26 20 SLCHOST_FRC_POS_SAMP 0x0 19 15 SLCHOST_FRC_NEG_SAMP 0x0 14 10 SLCHOST_FRC_SDIO20 0x0 9 5 SLCHOST_FRC_SDIO11 0x0 4 0 Reset SLCHOST_FRC_SDIO11 Configure 1 to bit[4] to force drive CMD signal at the falling clock edge. Configures 1 to bit[3:0] corresponding bit to force drive DAT[3:0] signal corresponding bit at the falling clock edge. (R/W) SLCHOST_FRC_SDIO20 Configure 1 to bit[4] to force drive CMD signal at the rising clock edge. Configures 1 to bit[3:0] corresponding bit to force drive DAT[3:0] signal corresponding bit at the rising clock edge. (R/W) SLCHOST_FRC_NEG_SAMP Configure 1 to bit[4] to force sample CMD signal at the falling clock edge. Configures 1 to bit[3:0] corresponding bit to force sample DAT[3:0] signal corresponding bit at the falling clock edge. (R/W) SLCHOST_FRC_POS_SAMP Configure 1 to bit[4] to force sample CMD signal at the rising clock edge. Configures 1 to bit[3:0] corresponding bit to force sample DAT[3:0] signal corresponding bit at the rising clock edge. (R/W) SLCHOST_HSPEED_CON_EN Configures 1 to this bit, configures 1 to HINF_HIGHSPEED_ENABLE, and then the host configures 1 to EHS in CCCR to force drive CMD and DAT signals at the rising clock edge. (R/W) Espressif Systems 1229 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Register 34.41. SLCHOST_SLC0HOST_INT_RAW_REG (0x0050) (reserved) 0x0 31 24 SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW 0 23 (reserved) 0x0 22 18 SLCHOST_SLC0_TX_OVF_INT_RAW 0 17 SLCHOST_SLC0_RX_UDF_INT_RAW 0 16 (reserved) 0x0 15 8 SLCHOST_SLC0_TOHOST_BIT7_INT_RAW 0 7 SLCHOST_SLC0_TOHOST_BIT6_INT_RAW 0 6 SLCHOST_SLC0_TOHOST_BIT5_INT_RAW 0 5 SLCHOST_SLC0_TOHOST_BIT4_INT_RAW 0 4 SLCHOST_SLC0_TOHOST_BIT3_INT_RAW 0 3 SLCHOST_SLC0_TOHOST_BIT2_INT_RAW 0 2 SLCHOST_SLC0_TOHOST_BIT1_INT_RAW 0 1 SLCHOST_SLC0_TOHOST_BIT0_INT_RAW 0 0 Reset SLCHOST_SLC0_TOHOST_BITn_INT_RAW (n: 0-7) The raw interrupt status of SL- CHOST_SLC0_TOHOST_BITn_INT (n: 0-7). (R/WTC/SS) SLCHOST_SLC0_RX_UDF_INT_RAW The raw interrupt status of SLCHOST_SLC0_RX_UDF_INT. (R/WTC/SS) SLCHOST_SLC0_TX_OVF_INT_RAW The raw interrupt status of SLCHOST_SLC0_TX_OVF_INT. (R/WTC/SS) SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW The raw interrupt status of SL- CHOST_SLC0_RX_NEW_PACKET_INT. (R/WTC/SS) Espressif Systems 1230 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Register 34.42. SLCHOST_SLC1HOST_INT_RAW_REG (0x0054) (reserved) 0x0 31 26 SLCHOST_SLC1_RX_NEW_PACKET_INT_RAW 0 25 (reserved) 0x0 24 18 SLCHOST_SLC1_TX_OVF_INT_RAW 0 17 SLCHOST_SLC1_RX_UDF_INT_RAW 0 16 (reserved) 0x0 15 8 SLCHOST_SLC1_TOHOST_BIT7_INT_RAW 0 7 SLCHOST_SLC1_TOHOST_BIT6_INT_RAW 0 6 SLCHOST_SLC1_TOHOST_BIT5_INT_RAW 0 5 SLCHOST_SLC1_TOHOST_BIT4_INT_RAW 0 4 SLCHOST_SLC1_TOHOST_BIT3_INT_RAW 0 3 SLCHOST_SLC1_TOHOST_BIT2_INT_RAW 0 2 SLCHOST_SLC1_TOHOST_BIT1_INT_RAW 0 1 SLCHOST_SLC1_TOHOST_BIT0_INT_RAW 0 0 Reset SLCHOST_SLC1_TOHOST_BITn_INT_RAW (n: 0-7) The raw interrupt status of SL- CHOST_SLC1_TOHOST_BITn_INT (n: 0-7). (R/WTC/SS) SLCHOST_SLC1_RX_UDF_INT_RAW The raw interrupt status of SLCHOST_SLC1_RX_UDF_INT. (R/WTC/SS) SLCHOST_SLC1_TX_OVF_INT_RAW The raw interrupt status of SLCHOST_SLC1_TX_OVF_INT. (R/WTC/SS) SLCHOST_SLC1_RX_NEW_PACKET_INT_RAW The raw interrupt status of SL- CHOST_SLC1_RX_NEW_PACKET_INT. (R/WTC/SS) Espressif Systems 1231 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Register 34.43. SLCHOST_SLC0HOST_INT_ST_REG (0x0058) (reserved) 0x0 31 24 SLCHOST_SLC0_RX_NEW_PACKET_INT_ST 0 23 (reserved) 0x0 22 18 SLCHOST_SLC0_TX_OVF_INT_ST 0 17 SLCHOST_SLC0_RX_UDF_INT_ST 0 16 (reserved) 0x0 15 8 SLCHOST_SLC0_TOHOST_BIT7_INT_ST 0 7 SLCHOST_SLC0_TOHOST_BIT6_INT_ST 0 6 SLCHOST_SLC0_TOHOST_BIT5_INT_ST 0 5 SLCHOST_SLC0_TOHOST_BIT4_INT_ST 0 4 SLCHOST_SLC0_TOHOST_BIT3_INT_ST 0 3 SLCHOST_SLC0_TOHOST_BIT2_INT_ST 0 2 SLCHOST_SLC0_TOHOST_BIT2_INT_ST 0 1 SLCHOST_SLC0_TOHOST_BIT0_INT_ST 0 0 Reset SLCHOST_SLC0_TOHOST_BITn_INT_ST (n: 0-7) The masked interrupt status of SL- CHOST_SLC0_TOHOST_BITn_INT (n: 0-7). (RO) SLCHOST_SLC0_RX_UDF_INT_ST The masked interrupt status of SLCHOST_SLC0_RX_UDF_INT. (RO) SLCHOST_SLC0_TX_OVF_INT_ST The masked interrupt status of SLCHOST_SLC0_TX_OVF_INT. (RO) SLCHOST_SLC0_RX_NEW_PACKET_INT_ST The masked interrupt status of SL- CHOST_SLC0_RX_NEW_PACKET_INT. (RO) Espressif Systems 1232 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Register 34.44. SLCHOST_SLC1HOST_INT_ST_REG (0x005C) (reserved) 0x0 31 26 SLCHOST_SLC1_RX_NEW_PACKET_INT_ST 0 25 (reserved) 0x0 24 18 SLCHOST_SLC1_TX_OVF_INT_ST 0 17 SLCHOST_SLC1_RX_UDF_INT_ST 0 16 (reserved) 0x0 15 8 SLCHOST_SLC1_TOHOST_BIT7_INT_ST 0 7 SLCHOST_SLC1_TOHOST_BIT6_INT_ST 0 6 SLCHOST_SLC1_TOHOST_BIT5_INT_ST 0 5 SLCHOST_SLC1_TOHOST_BIT4_INT_ST 0 4 SLCHOST_SLC1_TOHOST_BIT3_INT_ST 0 3 SLCHOST_SLC1_TOHOST_BIT2_INT_ST 0 2 SLCHOST_SLC1_TOHOST_BIT1_INT_ST 0 1 SLCHOST_SLC1_TOHOST_BIT0_INT_ST 0 0 Reset SLCHOST_SLC1_TOHOST_BITn_INT_ST (n: 0-7) The masked interrupt status of SL- CHOST_SLC1_TOHOST_BITn_INT (n: 0-7). (RO) SLCHOST_SLC1_RX_UDF_INT_ST The masked interrupt status of SLCHOST_SLC1_RX_UDF_INT. (RO) SLCHOST_SLC1_TX_OVF_INT_ST The masked interrupt status of SLCHOST_SLC1_TX_OVF_INT. (RO) SLCHOST_SLC1_RX_NEW_PACKET_INT_ST The masked interrupt status of SL- CHOST_SLC1_RX_NEW_PACKET_INT. (RO) Register 34.45. SLCHOST_CONF_W7_REG (0x008C) SLCHOST_SLCHOST_CONF31 0x0 31 24 (reserved) 0x0 23 16 SLCHOST_SLCHOST_CONF29 0x0 15 8 (reserved) 0x0 7 0 Reset SLCHOST_SLCHOST_CONF29 The interrupt set bits of SLCINT_SLC_FRHOST_BITn_INT (n: 0-7). These bits will not be cleared automatically. (R/W) SLCHOST_SLCHOST_CONF31 The interrupt set bits of SLCINT_SLC_FRHOST_BITn_INT (n: 8-15). These bits will not be cleared automatically. (R/W) Espressif Systems 1233 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Register 34.46. SLCHOST_SLC0HOST_INT_CLR_REG (0x00D4) (reserved) 0x0 31 24 SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR 0 23 (reserved) 0x0 22 18 SLCHOST_SLC0_TX_OVF_INT_CLR 0 17 SLCHOST_SLC0_RX_UDF_INT_CLR 0 16 (reserved) 0x0 15 8 SLCHOST_SLC0_TOHOST_BIT7_INT_CLR 0 7 SLCHOST_SLC0_TOHOST_BIT6_INT_CLR 0 6 SLCHOST_SLC0_TOHOST_BIT5_INT_CLR 0 5 SLCHOST_SLC0_TOHOST_BIT4_INT_CLR 0 4 SLCHOST_SLC0_TOHOST_BIT3_INT_CLR 0 3 SLCHOST_SLC0_TOHOST_BIT2_INT_CLR 0 2 SLCHOST_SLC0_TOHOST_BIT1_INT_CLR 0 1 SLCHOST_SLC0_TOHOST_BIT0_INT_CLR 0 0 Reset SLCHOST_SLC0_TOHOST_BITn_INT_CLR (n: 0-7) Write 1 to clear interrupt SL- CHOST_SLC0_TOHOST_BITn_INT (n: 0-7). (WT) SLCHOST_SLC0_RX_UDF_INT_CLR Write 1 to clear interrupt SLCHOST_SLC0_RX_UDF_INT. (WT) SLCHOST_SLC0_TX_OVF_INT_CLR Write 1 to clear interrupt SLCHOST_SLC0_TX_OVF_INT. (WT) SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR Write 1 to clear interrupt SL- CHOST_SLC0_RX_NEW_PACKET_INT. (WT) Espressif Systems 1234 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Register 34.47. SLCHOST_SLC1HOST_INT_CLR_REG (0x00D8) (reserved) 0x0 31 26 SLCHOST_SLC1_RX_NEW_PACKET_INT_CLR 0 25 (reserved) 0x0 24 18 SLCHOST_SLC1_TX_OVF_INT_CLR 0 17 SLCHOST_SLC1_RX_UDF_INT_CLR 0 16 (reserved) 0x0 15 8 SLCHOST_SLC1_TOHOST_BIT7_INT_CLR 0 7 SLCHOST_SLC1_TOHOST_BIT6_INT_CLR 0 6 SLCHOST_SLC1_TOHOST_BIT5_INT_CLR 0 5 SLCHOST_SLC1_TOHOST_BIT4_INT_CLR 0 4 SLCHOST_SLC1_TOHOST_BIT3_INT_CLR 0 3 SLCHOST_SLC1_TOHOST_BIT2_INT_CLR 0 2 SLCHOST_SLC1_TOHOST_BIT1_INT_CLR 0 1 SLCHOST_SLC1_TOHOST_BIT0_INT_CLR 0 0 Reset SLCHOST_SLC1_TOHOST_BITn_INT_CLR (n: 0-7) Write 1 to clear interrupt SL- CHOST_SLC1_TOHOST_BITn_INT (n: 0-7). (WT) SLCHOST_SLC1_RX_UDF_INT_CLR Write 1 to clear interrupt SLCHOST_SLC1_RX_UDF_INT. (WT) SLCHOST_SLC1_TX_OVF_INT_CLR Write 1 to clear interrupt SLCHOST_SLC1_TX_OVF_INT. (WT) SLCHOST_SLC1_RX_NEW_PACKET_INT_CLR Write 1 to clear interrupt SL- CHOST_SLC1_RX_NEW_PACKET_INT. (WT) Espressif Systems 1235 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Register 34.48. SLCHOST_SLC0HOST_FUNC1_INT_ENA_REG (0x00DC) (reserved) 0x0 31 24 SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA 0 23 (reserved) 0x0 22 18 SLCHOST_FN1_SLC0_TX_OVF_INT_ENA 0 17 SLCHOST_FN1_SLC0_RX_UDF_INT_ENA 0 16 (reserved) 0x0 15 8 SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA 0 7 SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA 0 6 SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA 0 5 SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA 0 4 SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA 0 3 SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA 0 2 SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA 0 1 SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA 0 0 Reset SLCHOST_FN1_SLC0_TOHOST_BITn_INT_ENA (n: 0-7) Write 1 to enable SL- CHOST_SLC0_TOHOST_BITn_INT (n: 0-7). (R/W) SLCHOST_FN1_SLC0_RX_UDF_INT_ENA Write 1 to enable SLCHOST_SLC0_RX_UDF_INT. (R/W) SLCHOST_FN1_SLC0_TX_OVF_INT_ENA Write 1 to enable SLCHOST_SLC0_TX_OVF_INT. (R/W) SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA Write 1 to enable SL- CHOST_SLC0_RX_NEW_PACKET_INT. (R/W) Espressif Systems 1236 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Register 34.49. SLCHOST_SLC1HOST_FUNC1_INT_ENA_REG (0x00E0) (reserved) 0x0 31 26 SLCHOST_FN1_SLC1_RX_NEW_PACKET_INT_ENA 0 25 (reserved) 0x0 24 18 SLCHOST_FN1_SLC1_TX_OVF_INT_ENA 0 17 SLCHOST_FN1_SLC1_RX_UDF_INT_ENA 0 16 (reserved) 0x0 15 8 SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA 0 7 SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA 0 6 SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA 0 5 SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA 0 4 SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA 0 3 SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA 0 2 SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA 0 1 SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA 0 0 Reset SLCHOST_FN1_SLC1_TOHOST_BITn_INT_ENA (n: 0-7) Write 1 to enable SL- CHOST_SLC1_TOHOST_BITn_INT (n: 0-7). (R/W) SLCHOST_FN1_SLC1_RX_UDF_INT_ENA Write 1 to enable SLCHOST_SLC1_RX_UDF_INT. (R/W) SLCHOST_FN1_SLC1_TX_OVF_INT_ENA Write 1 to enable SLCHOST_SLC1_TX_OVF_INT. (R/W) SLCHOST_FN1_SLC1_RX_NEW_PACKET_INT_ENA Write 1 to enable SL- CHOST_SLC1_RX_NEW_PACKET_INT. (R/W) Register 34.50. SLCHOST_SLC0HOST_TOKEN_RDATA_REG (0x0044) (reserved) 0x0 31 28 SLCHOST_HOSTSLCHOST_SLC0_TOKEN1 0x0 27 16 (reserved) 0x0 15 0 Reset SLCHOST_HOSTSLCHOST_SLC0_TOKEN1 Represents the SLC0 accumulated number of buffers for receiving data. (RO) Espressif Systems 1237 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Register 34.51. SLCHOST_PKT_LEN_REG (0x0060) SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK 0x0 31 20 SLCHOST_HOSTSLCHOST_SLC0_LEN 0x0 19 0 Reset SLCHOST_HOSTSLCHOST_SLC0_LEN Represents the accumulated length of data that the slave wants to send. The value gets updated only when the host reads it. (RO) SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK Check SLCHOST_HOSTSLCHOST_SLC0_LEN. Its value is SLCHOST_HOSTSLCHOST_SLC0_LEN bit[9:0] plus bit[19:10]. (RO) Register 34.52. SLCHOST_SLC1HOST_TOKEN_RDATA_REG (0x00C4) (reserved) 0x0 31 28 SLCHOST_HOSTSLCHOST_SLC1_TOKEN1 0x0 27 16 (reserved) 0x0 15 0 Reset SLCHOST_HOSTSLCHOST_SLC1_TOKEN1 Represents the SLC1 accumulated number of buffers for receiving data. (RO) Espressif Systems 1238 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Register 34.53. SLCHOST_CONF_Wn_REG(n: 0-2) (0x006C+0x4*n) SLCHOST_SLCHOST_CONFn 0x0 31 0 Reset SLCHOST_SLCHOST_CONFn The information interaction register between the host and slave. Both of them can access it. (R/W) Register 34.54. SLCHOST_CONF_W3_REG (0x0078) SLCHOST_SLCHOST_CONF3 0x0 31 16 (reserved) 0xc0 15 0 Reset SLCHOST_SLCHOST_CONF3 The information interaction register between the host and slave. Both of them can access it. (R/W) Register 34.55. SLCHOST_CONF_W4_REG (0x007C) SLCHOST_SLCHOST_CONF4 0x0 31 16 (reserved) 0x1ff 15 0 Reset SLCHOST_SLCHOST_CONF4 The information interaction register between the host and slave. Both of them can access it. (R/W) Espressif Systems 1239 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 34 SDIO Slave Controller (SDIO) Register 34.56. SLCHOST_CONF_W6_REG (0x0088) SLCHOST_SLCHOST_CONF6 0x0 31 0 Reset SLCHOST_SLCHOST_CONF6 The information interaction register between the host and slave. Both of them can access it. (R/W) Register 34.57. SLCHOST_CONF_Wn_REG(n: 8-15) (0x009C+0x4*(n-8)) SLCHOST_SLCHOST_CONFn 0x0 31 0 Reset SLCHOST_SLCHOST_CONFn The information interaction register between the host and slave. Both of them can access it. (R/W) Espressif Systems 1240 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 35 LED PWM Controller (LEDC) Chapter 35 LED PWM Controller (LEDC) 35.1 Overview The LED PWM Controller is a peripheral designed to generate PWM signals for LED control. It has specialized features such as automatic duty cycle fading. However, the LED PWM Controller can also be used to generate PWM signals for other purposes. 35.2 Feature List The LED PWM Controller has the following features: • Six independent PWM generators (i.e. six channels) • Maximum PWM duty cycle resolution: 20 bits • Four independent timers that support fractional division • Adjustable phase of PWM signal output • PWM duty cycle dithering • Automatic duty cycle fading — gradual increase/decrease of a PWM’s duty cycle without interference from the processor. An interrupt will be generated upon fade completion • Up to 16 duty cycle ranges for each PWM generator to generate gamma curve signals — each range can be independently configured in terms of fading direction (increase or decrease), fading amount (the amount by which the duty cycle increases or decreases each time), the number of fades (how many times the duty cycle fades in one range), and fading frequency • PWM signal output in low-power mode (Light-sleep mode) • Event generation and task response related to the Event Task Matrix (ETM) peripheral Note that the four timers are identical regarding their features and operation. The following sections refer to the timers collectively as Timerx (where x ranges from 0 to 3). Likewise, the six PWM generators are also identical in features and operation, and thus are collectively referred to as PWMn (where n ranges from 0 to 5). 35.3 Architectural Overview Figure 35.3-1 shows the architecture of the LED PWM Controller. Espressif Systems 1241 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 35 LED PWM Controller (LEDC) Figure 35.3-1. LED PWM Architecture Each of the four timers has an internal timebase counter (i.e., a counter that counts on cycles of a reference clock) and thus can be independently configured (i.e., configurable clock divider, and counter overflow value). Each PWM generator selects one of the timers by configuring the LEDC_TIMER_SEL_CHn, and uses the timer’s counter value timerx_cnt as a reference to generate its PWM signal. Figure 35.3-2 illustrates the main functional blocks of the timer and the PWM generator. Figure 35.3-2. Timer and PWM Generator Block Diagram 35.4 Functional Description 35.4.1 Timers Each timer in LED PWM Controller internally maintains a timebase counter. Referring to Figure 35.3-2, this clock signal used by the timebase counter is named ref_pulsex. All timers use the same clock source LEDC_CLK, which is then passed through a clock divider to generate ref_pulsex for the counter. Espressif Systems 1242 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 35 LED PWM Controller (LEDC) 35.4.1.1 Clock Source LED PWM registers configured by software are clocked by APB_CLK. To use the LED PWM peripheral, the APB_CLK signal going to the LED PWM has to be enabled. The APB_CLK signal to LED PWM can be enabled by setting the PCR_LEDC_CLK_EN field in the PCR_LEDC_CONF_REG register. The LEDC_CLK signal to LED PWM can be enabled by setting the PCR_LEDC_SCLK_EN field in the PCR_LEDC_SCLK_CONF_REG register. The LED PWM peripheral can be reset via software by setting the PCR_LEDC_RST_EN field in the PCR_LEDC_CONF_REG register. Timers in the LED PWM Controller choose their common clock source from one of the following clock signals: XTAL_CLK, RC_FAST_CLK, and PLL_F80M_CLK. The procedure for selecting a clock source signal for LEDC_CLK is described below: • XTAL_CLK: Set PCR_LEDC_SCLK_SEL[1:0] to 0 • RC_FAST_CLK: Set PCR_LEDC_SCLK_SEL[1:0] to 1 • PLL_F80M_CLK: Set PCR_LEDC_SCLK_SEL[1:0] to 2 The LEDC_CLK signal will then be passed through the clock divider. For more information, please refer to Chapter 7 Reset and Clock. 35.4.1.2 Clock Divider Configuration The LEDC_CLK signal is passed through a clock divider to generate the ref_pulsex signal for the counter. The frequency of ref_pulsex is equal to the frequency of LEDC_CLK divided by the divisor LEDC_CLK_DIV (see Figure 35.3-2). The clock divider is a fractional divider. Thus, the divisor LEDC_CLK_DIV can be non-integer values. LEDC_CLK_DIV is configured according to the following equation. LEDC_CLK_DIV = A + B 256 (35.1) • The integer part A corresponds to the most significant 10 bits of LEDC_CLK_DIV_TIMERx (i.e., LEDC_TIMERx_CONF_REG[22:13]) • The fractional part B corresponds to the least significant 8 bits of LEDC_CLK_DIV_TIMERx (i.e., LEDC_TIMERx_CONF_REG[12:5]) When the fractional part B is 0, LEDC_CLK_DIV is equivalent to an integer divisor (i.e., an integer prescaler). In other words, a ref_pulsex clock pulse is generated after every A number of LEDC_CLK clock pulses. However, when B is not 0, LEDC_CLK_DIV becomes a non-integer divisor. The clock divider implements non-integer frequency division by alternating between A and (A+1) LEDC_CLK clock pulses per ref_pulsex clock pulse. In this way, the average frequency of ref_pulsex clock pulse will be the desired frequency (i.e. the non-integer divided frequency). For every 256 ref_pulsex clock pulses: • A number of B ref_pulsex clock pulses are generated every (A+1) LEDC_CLK clock pulses • A number of (256-B) ref_pulsex clock pulses are generated every A LEDC_CLK clock pulses • The ref_pulsex clock pulses generated every (A+1) pulses are evenly distributed amongst those generated every A pulses Espressif Systems 1243 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 35 LED PWM Controller (LEDC) Figure 35.4-1 illustrates the relation between LEDC_CLK clock pulses and ref_pulsex clock pulses when LEDC_CLK_DIV is a non-integer value. Figure 35.4-1. Frequency Division When LEDC_CLK_DIV is a Non-Integer Value To change the timer’s clock divisor at runtime, first configure the LEDC_CLK_DIV_TIMERx field, and then set the LEDC_TIMERx_PARA_UP field to apply the new configuration. This will cause the newly configured values to take effect upon the next overflow of the counter. The LEDC_TIMERx_PARA_UP field will be automatically cleared by hardware. 35.4.1.3 20-Bit Counter Each timer contains a 20-bit timebase counter that uses ref_pulsex as its reference clock (see Figure 35.3-2). The LEDC_TIMERx_DUTY_RES field configures the actual used bit width of this 20-bit counter. Hence, the maximum resolution of the PWM signal is 20 bits. The counter counts up to 2 LEDC_TIMERx_DUTY_RES − 1, overflows and begins counting from 0 again. The counter’s value can be read, reset, and suspended by software. Figure 35.4-2 shows the relationship between the counter and PWM resolution. Figure 35.4-2. Relationship Between Counter And Resolution Every time the counter overflows, it can trigger the LEDC_TIMERx_OVF_INT interrupt (generated automatically by hardware without configuration). It can also be configured to trigger LEDC_OVF_CNT_CHn_INT interrupt after overflowing LEDC_OVF_NUM_CHn + 1 times. To configure LEDC_OVF_CNT_CHn_INT interrupt, please: 1. Configure LEDC_TIMER_SEL_CHn to select the timer for the PWM generator 2. Enable the overflow counter by setting LEDC_OVF_CNT_EN_CHn 3. Configure LEDC_OVF_NUM_CHn with the number of counter overflows (that triggers an interrupt) minus 1 4. Enable the overflow interrupt by setting LEDC_OVF_CNT_CHn_INT_ENA 5. Configure LEDC_TIMERx_DUTY_RES to specify the counter bit width for the selected Timerx and wait for a LEDC_OVF_CNT_CHn_INT interrupt Espressif Systems 1244 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 35 LED PWM Controller (LEDC) To change the overflow value at runtime, first set the LEDC_TIMERx_DUTY_RES field, and then set the LEDC_TIMERx_PARA_UP field. This will cause the newly configured values to take effect upon the next overflow of the counter. If LEDC_OVF_CNT_EN_CHn field is reconfigured, LEDC_PARA_UP_CHn should be set to apply the new configuration. In summary, these configuration values need to be updated by setting LEDC_TIMERx_PARA_UP or LEDC_PARA_UP_CHn. LEDC_TIMERx_PARA_UP and LEDC_PARA_UP_CHn will be automatically cleared by hardware. Referring to Figure 35.3-2, the frequency of a PWM generator output signal (sig_outn) is dependent on the frequency of the timer’s clock source LEDC_CLK, the clock divisor LEDC_CLK_DIV, and the duty resolution (counter width) LEDC_TIMERx_DUTY_RES: f PWM = f LEDC_CLK LEDC_CLK_DIV · 2 LEDC_TIMERx_DUTY_RES (35.2) Based on the formula above, the desired duty resolution can be calculated as follows: LEDC_TIMERx_DUTY_RES = log 2  f LEDC_CLK f PWM · LEDC_CLK_DIV  (35.3) Table 35.4-1 lists the commonly-used frequencies and their corresponding resolutions. Table 35.4-1. Commonly-used Frequencies and Resolutions LEDC_CLK PWM Frequency Highest Resolution (bit) 1 Lowest Resolution (bit) 2 REF_80M_CLK (80 MHz) 1 kHz 16 6 REF_80M_CLK (80 MHz) 5 kHz 13 3 REF_80M_CLK (80 MHz) 10 kHz 12 2 XTAL_40M_CLK (40 MHz) 1 kHz 15 5 XTAL_40M_CLK (40 MHz) 4 kHz 13 3 FOSC_20M_CLK (20 MHz) 1 kHz 14 4 FOSC_20M_CLK (20 MHz) 2 kHz 13 3 1 The highest resolution is calculated when the clock divisor LEDC_CLK_DIV is 1. If the highest resolution calculated by the formula is higher than the counter’s width 20 bits, then the highest resolution should be 20 bits. 2 The lowest resolution is calculated when the clock divisor LEDC_CLK_DIV is 1023 + 255 256 . If the lowest resolution calculated by the formula is lower than 0, then the lowest resolution should be 1. 35.4.2 PWM Generators To generate a PWM signal, a PWM generator (PWMn) needs a timer (Timerx). Each PWM generator can be configured separately by setting LEDC_TIMER_SEL_CHn to use one of four timers to generate the PWM output. As shown in Figure 35.3-2, each PWM generator has a comparator and two multiplexers. A PWM generator compares the timer’s 20-bit counter value (Timerx_cnt) to two trigger values Hpointn and Lpointn. When the timer’s counter value is equal to Hpointn or Lpointn, the PWM signal is high or low, respectively, as described below: Espressif Systems 1245 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 35 LED PWM Controller (LEDC) • If Timerx_cnt == Hpointn, sig_outn is 1. • If Timerx_cnt == Lpointn, sig_outn is 0. Figure 35.4-3 illustrates how Hpointn and Lpointn are used to generate a fixed duty cycle PWM output signal. Figure 35.4-3. LED PWM Output Signal Diagram For a particular PWM generator (PWMn), its Hpointn is sampled from the LEDC_HPOINT_CHn field each time the selected timer’s counter overflows. Likewise, Lpointn is also sampled on every counter overflow and is calculated from the sum of the LEDC_DUTY_CHn[24:4] and LEDC_HPOINT_CHn fields. By setting Hpointn and Lpointn via the LEDC_HPOINT_CHn and LEDC_DUTY_CHn[24:4] fields, the relative phase and duty cycle of the PWM output can be set. The PWM output signal (sig_outn) is enabled by setting LEDC_SIG_OUT_EN_CHn. When LEDC_SIG_OUT_EN_CHn is cleared, PWM signal output is disabled, and the output signal (sig_outn) will output a constant level specified by LEDC_IDLE_LV_CHn. The bits LEDC_DUTY_CHn[3:0] are used to dither the duty cycles of the PWM output signal (sig_outn) by periodically altering the duty cycle of sig_outn. When LEDC_DUTY_CHn[3:0] is not 0, then for every 16 cycles of sig_outn, LEDC_DUTY_CHn[3:0] of those cycles will have PWM pulses that are one timer tick longer than the other (16 - LEDC_DUTY_CHn[3:0]) cycles. For instance, if LEDC_DUTY_CHn[24:4] is set to 10 and LEDC_DUTY_CHn[3:0] is set to 5, then 5 of 16 cycles will have a PWM pulse with a duty value of 11 and the rest of the 16 cycles will have a PWM pulse with a duty value of 10. The average duty cycle after 16 cycles is 10.3125. If fields LEDC_TIMER_SEL_CHn, LEDC_HPOINT_CHn, LEDC_DUTY_CHn[24:4], and LEDC_SIG_OUT_EN_CHn are reconfigured, LEDC_PARA_UP_CHn must be set to apply the new configuration. This will cause the newly configured values to take effect upon the next overflow of the counter. LEDC_PARA_UP_CHn field will be automatically cleared by hardware. 35.4.3 Duty Cycle Fading The PWM generators can fade the duty cycle of a PWM output signal (i.e. gradually change the duty cycle from one value to another). Each PWM generator can have up to 16 duty cycle ranges, which can be independently configured in terms of fading direction (increase or decrease), fading amount, the number of fades, and fading frequency. If Duty Cycle Fading is enabled, every range’s Lpointn value will change according to its fading configuration. Espressif Systems 1246 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 35 LED PWM Controller (LEDC) Please note that during the duty cycle fading process, if the duty cycle of a PWM output signal (PWMn) can reach 100%, its LEDC_HPOINT_CHn needs to be set to 0 to ensure the correctness of Lpointn. 35.4.3.1 Linear Duty Cycle Fading Linear fading PWM signals can be generated by configuring the direction, fading amount, the number of fades, and fading frequency of the first duty cycle range. The programming procedures will be described in detail in the section 35.7. After the procedures, the PWM generator can fade the duty cycle of a PWM signal once per LEDC_CHn_GAMMA_DUTY_CYCLE times of counter overflows. Every time when the PWM signal is faded, Lpointn increases or decreases (configured by LEDC_CHn_GAMMA_DUTY_INC) by LEDC_CHn_GAMMA_SCALE, and the duty cycle increases or decreases (configured by LEDC_CHn_GAMMA_DUTY_INC) by LEDC_CHn_GAMMA_SCALE LEDC_TIMERx_DUTY_RES (35.4) The duty cycle is faded for LEDC_CHn_GAMMA_DUTY_NUM times. After that, the PWM generator stops fading and keeps outputting signals at this duty cycle. Upon each fading the duty cycle increases or decreases by the same amount, and therefore the PWM signal is a linear fading signal. Figure 35.4-4 shows a linear fading PWM signal. Figure 35.4-4. Output Signal of Linear Duty Cycle Fading 35.4.3.2 Gamma Curve Fading Gamma curve fading PWM signals can be generated by configuring the fading direction, fading amount, the number of fades and fading frequency of multiple duty cycle fading ranges. The programming procedures will be described in detail in the section 35.7. Espressif Systems 1247 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 35 LED PWM Controller (LEDC) After the procedures, the PWM generator can generate a PWM signal with LEDC_CHn_GAMMA_ENTRY_NUM ranges. The duty cycle of the PWM signal fades according to the configurations of range 0 first, and then range 1, till range (LEDC_CHn_GAMMA_ENTRY_NUM − 1) (the last range) where Duty Cycle Fading ends. The PWM signal fades independently in each range. According to the configuration of each range, every time when the counter overflows for LEDC_CHn_GAMMA_DUTY_CYCLE times, Lpointn increases or decreases (configured by LEDC_CHn_GAMMA_DUTY_INC) by LEDC_CHn_GAMMA_SCALE, and accordingly the duty cycle increases or decreases (configured by LEDC_CHn_GAMMA_DUTY_INC) by LEDC_CHn_GAMMA_SCALE LEDC_TIMERx_DUTY_RES (35.5) After the duty cycle fades for LEDC_CHn_GAMMA_DUTY_NUM times in a range, Duty Cycle Fading in this range finishes. When Duty Cycle Fading finishes in all ranges (the number of ranges is specified by LEDC_CHn_GAMMA_ENTRY_NUM), the PWM signal stops fading and keeps the duty cycle of the last fade. Given that the duty cycle fades differently and linearly in each range, several linear fading ranges would be fitted to a gamma curve. Figure 35.4-5 illustrates a gamma curve fading PWM signal. Figure 35.4-5. Output Signal of Gamma Curve Fading 35.4.3.3 Suspend and Resume Duty Cycle Fading To suspend Duty Cycle Fading that has already been started, write 1 to the LEDC_CHn_GAMMA_PAUSE field of the LEDC_CHn_GAMMA_CONF_REG register. Once LEDC_CHn_GAMMA_PAUSE is set to 1, the PWM signal keeps the duty cycle of the most recent fade. To resume Duty Cycle Fading, write 1 to the LEDC_CHn_GAMMA_RESUME field of the LEDC_CHn_GAMMA_CONF_REG register. Once LEDC_CHn_GAMMA_RESUME is set to 1, the PWM signal resumes fading from the range where the suspension occurs, until fading in the last range finishes. The fading will continue from the state when it was paused until all the ranges complete duty cycle fading (when Espressif Systems 1248 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 35 LED PWM Controller (LEDC) LEDC_CHn_GAMMA_RESUME is set to 1, LEDC_CHn_GAMMA_PAUSE is cleared automatically by hardware. 35.5 Event Task Matrix Feature The LEDC on ESP32-C5 supports the Event Task Matrix (ETM) function, which allows LEDC’s ETM tasks to be triggered by any peripherals’ ETM events, or LEDC’s ETM events to trigger any peripherals’ ETM tasks. This section introduces the ETM tasks and events related to LEDC. For more information, please refer to Chapter 10 Event Task Matrix (ETM). ETM-related events and tasks are enabled by configuring corresponding fields of LEDC_EVT_TASK_EN0_REG, LEDC_EVT_TASK_EN1_REG and LEDC_EVT_TASK_EN2_REG registers. For the correspondence between events, tasks, and fields, Please refer to Section 35.9). LEDC can receive the following ETM tasks: • LEDC_TASK_DUTY_SCALE_UPDATE_CHn: If the LEDC_TASK_DUTY_SCALE_UPDATE_CHn_EN field is enabled, upon receiving the LEDC_TASK_DUTY_SCALE_UPDATE_CHn task, PWMn generates fading PWM signals according to the newly configured LEDC_CHn_GAMMA_SCALE field. • LEDC_TASK_TIMERx_RES_UPDATE: If the LEDC_TASK_TIMERx_RES_UPDATE_EN field is enabled, upon receiving the LEDC_TASK_TIMERx_RES_UPDATE task, Timerx updates its counter’s overflow value to the value configured in the LEDC_TIMERx_DUTY_RES field at the next overflow of the counter. • LEDC_TASK_TIMERx_CAP: If the LEDC_TASK_TIMERx_CAP_EN field is enabled, upon receiving the LEDC_TASK_TIMERx_CAP task, Timerx captures its counter’s value, and stores the value into the LEDC_TIMERx_CNT_CAP field of register LEDC_TIMERx_CNT_CAP_REG. • LEDC_TASK_SIG_OUT_DIS_CHn: If the LEDC_TASK_SIG_OUT_DIS_CHn_EN field is enabled, upon receiving the LEDC_TASK_SIG_OUT_DIS_CHn task, PWMn’s signal output is disabled, and the output signal (sig_outn) outputs a constant level as specified by field LEDC_IDLE_LV_CHn, as shown in Figure 35.3-2. • LEDC_TASK_OVF_CNT_RST_CHn: If the LEDC_TASK_OVF_CNT_RST_CHn_EN field is enabled, upon receiving the LEDC_TASK_OVF_CNT_RST_CHn task, PWMn timer’s overflow counter is reset to 0. • LEDC_TASK_TIMERx_RST: If the LEDC_TASK_TIMERx_RST_EN field is enabled, upon receiving the LEDC_TASK_TIMERx_RST task, Timerx’s counter is reset to 0. • LEDC_TASK_TIMERx_RESUME and LEDC_TASK_TIMERx_PAUSE: If the LEDC_TASK_TIMERx_PAUSE_RESUME_EN field is enabled, upon receiving the LEDC_TASK_TIMERx_RESUME and LEDC_TASK_TIMERx_PAUSE task, Timerx is suspended and resumed alternately. That is, when the task is received, Timerx is paused; and when the task is received again, Timerx is resumed. • LEDC_TASK_GAMMA_RESTART_CHn: If the LEDC_TASK_GAMMA_RESTART_CHn_EN field is enabled, upon receiving the LEDC_TASK_GAMMA_RESTART_CHn task, the PWMn restarts to generate the fading PWM signal. • LEDC_TASK_GAMMA_PAUSE_CHn: If the LEDC_TASK_GAMMA_PAUSE_CHn_EN field is enabled, upon receiving the LEDC_TASK_GAMMA_PAUSE_CHn task, PWMn suspends Duty Cycle Fading at the next timer overflow. That is, after the task has been received, PWMn keeps the duty cycle of the last fade. Espressif Systems 1249 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 35 LED PWM Controller (LEDC) • LEDC_TASK_GAMMA_RESUME_CHn: If the LEDC_TASK_GAMMA_RESUME_CHn_EN field is enabled, upon receiving the LEDC_TASK_GAMMA_RESUME_CHn task, PWMn resumes Duty Cycle Fading at the next counter overflow. That is, after the task has been received, PWMn resumes fading from the range where the suspension occurs. LEDC can generate the following ETM events: • LEDC_EVT_DUTY_CHNG_END_CHn: Generated when the LEDC_EVT_DUTY_CHNG_END_CHn_EN field is enabled, and PWMn has finished Duty Cycle Fading. • LEDC_EVT_OVF_CNT_PLS_CHn: Generated when the LEDC_EVT_OVF_CNT_PLS_CHn_EN field is enabled and when PWMn timer’s counter overflows for LEDC_OVF_NUM_CHn + 1 times. • LEDC_EVT_TIME_OVF_TIMERx: Generated when the LEDC_EVT_TIME_OVF_TIMERx_EN field is enabled and Timerx’s counter overflows. • LEDC_EVT_TIMERx_CMP: Generated when the LEDC_EVT_TIMERx_CMP_EN field is enabled and the value of Timerx)’s counter reaches that of the LEDC_TIMERx_CMP field of register LEDC_TIMERx_CMP_REG. In practical applications, LEDC’s ETM events can trigger its own ETM tasks. For example, LEDC_EVT_DUTY_CHNG_END_CHn event can trigger the LEDC_TASK_GAMMA_RESTART_CHn task, thus starting the next fading directly after the current fading is completed. 35.6 Interrupts ESP32-C5’s LEDC can generate the LEDC_INT interrupt signal, which will be sent to the Interrupt Matrix. Interrupt signal LEDC_INT can be generated by the following internal interrupt sources: • LEDC_OVF_CNT_CHn_INT: Triggered when the timer counter overflows for LEDC_OVF_NUM_CHn + 1 times and the register LEDC_OVF_CNT_EN_CHn is set to 1. • LEDC_DUTY_CHNG_END_CHn_INT: Triggered when a fade on PWMn has finished. • LEDC_TIMERx_OVF_INT: Triggered when Timerx has reached its maximum counter value. The above interrupt sources can only be triggered when the interrupt enable register XXX_ENA is set to 1. Write 1 to XXX_CLR will clear the interrupt (XXX is the interrupt source name). 35.7 Programming Procedures The configuration process of the LED PWM controller to generate PWM signals is as follows: 1. Configure the Timerx according to section 35.4.1. After that, the clock source, divider, and counter are ready. 2. Configure the PWMn generator according to section 35.4.2. After that, PWMn selects one of the four timers and the phase and duty cycle of the PWMn output is set. 3. Choose the corresponding configuration process based on the different duty cycle fading types: (a) Linear duty cycle fading: i. Configure the LEDC_DUTY_CHn field with the initial value of Lpointn. Espressif Systems 1250 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 35 LED PWM Controller (LEDC) ii. Set the LEDC_DUTY_START_CHn field to enable Duty Cycle Fading. When this field is cleared, Duty Cycle Fading will be disabled. iii. Write the linear duty cycle fading configuration to (LEDC_CHn_MEM starting address + duty cycle range number * 4), the LEDC_CHn_MEM starting address is provided in Table 35.8-1. Please note that the following bit names are just for easier description, and there are no such register fields. A. Bit 0 of the configuration data is used to configure the direction (hereafter referred to as LEDC_CHn_GAMMA_DUTY_INC). When it is set or cleared, the Lpointn will increase or decrease in the current configured range. B. Bit 1 to 10 of the configuration data is used to configure the number of times the counter overflows per an increment or decrement of Lpointn (hereafter referred to as LEDC_CHn_GAMMA_DUTY_CYCLE). In other words, Lpointn will increase or decrease after the counter overflows for the configured number of times. C. Bit 11 to 20 of the configuration data is used to configure the amount by which Lpointn increase or decrease in the current configured range (hereafter referred to as LEDC_CHn_GAMMA_SCALE). D. Bit 21 to 30 of the configuration data is used to configure the number of fades in the current configured range (hereafter referred to as LEDC_CHn_GAMMA_DUTY_NUM). E. The duty cycle range number (from 0 to 15) specifies to which range the above configuration data apply. For linear duty cycle fading only the first range needs to be configured, so the duty cycle range number should be configured as 0. iv. Configure the number of ranges per each fading (1 in this case) via the LEDC_CHn_GAMMA_ENTRY_NUM field of the LEDC_CHn_GAMMA_CONF_REG. Once the specified number of ranges have been faded, Duty Cycle Fading stops and the PWM generator triggers the LEDC_DUTY_CHNG_END_CHn_INT interrupt. For linear duty cycle fading there is only one duty cycle range (i.e. the first one), so configure LEDC_CHn_GAMMA_ENTRY_NUM as 1. v. Set the LEDC_PARA_UP_CHn field to apply the above configurations. After this field is set, the configurations for Duty Cycle Fading will take effect upon the next overflow of the counter, and the PWM generator will output a linear fading PWM signal following configurations. LEDC_PARA_UP_CHn field will be automatically cleared by hardware. (b) Gamma curve fading: i. The same as Step 1 in Section 35.4.3.1. ii. The same as Step 2 in Section 35.4.3.1. iii. Configure multiple duty cycle ranges with the following steps. Write the gamma curve fading configuration to (LEDC_CHn_MEM starting address + duty cycle range number * 4), the LEDC_CHn_MEM starting address is provided in Table 35.8-1. A. Bit 0 of the configuration data is used to configure the direction (hereafter referred to as LEDC_CHn_GAMMA_DUTY_INC). When it is set or cleared, the Lpointn will increment or decrement in the current configured range. Espressif Systems 1251 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 35 LED PWM Controller (LEDC) B. Bit 1 to 10 of the configuration data is used to configure the number of times the counter overflows per an increase or decrease of Lpointn (hereafter referred to as LEDC_CHn_GAMMA_DUTY_CYCLE). In other words, Lpointn will increase or decrease after the counter overflows for the configured number of times. C. Bit 11 to 20 of the configuration data is used to configure the amount by which Lpointn increase or decrease in the current configured range (hereafter referred to as LEDC_CHn_GAMMA_SCALE). D. Bit 21 to 30 of the configuration data is used to configure the number of fades in the current configured range (hereafter referred to as LEDC_CHn_GAMMA_DUTY_NUM). E. The duty cycle range number (from 0 to 15) specifies to which range the above configuration data apply. For gamma curve fading, it must start from 0 and increase by 1 for the next range to be configured. F. Once the above procedures are finished, the configuration for one range is complete. Other ranges are configured by repeating the same set of procedures. You can configure any number of ranges from 0 to 15, and each can be configured independently. iv. After all required ranges are configured, write the total number of ranges configured in Step 3 to the LEDC_CHn_GAMMA_ENTRY_NUM field of the LEDC_CHn_GAMMA_CONF_REG register. v. Set the LEDC_PARA_UP_CHn field to apply the above configuration. After this field is set, the configurations for duty cycle fading will take effect upon the next overflow of the counter, and the PWM generator will output a gamma curve fading PWM signal following the configurations. LEDC_PARA_UP_CHn field will be automatically cleared by hardware. After the above procedures, the LED PWM controller will generate the desired PWM signals. At any time, duty cycle fading can be suspended or resumed, more detials can be found in setction 35.4.3.3. If the duty cycle fading configurations need to be changed before the PWM signals stop fading (that is, the LEDC_DUTY_CHNG_END_CHn_INT has not been triggered), the duty cycle fading needs to be suspended before changing the configurations. However, if the duty cycle fading configurations need to be changed after the PWM signals stop fading (that is, the LEDC_DUTY_CHNG_END_CHn_INT has been triggered), the configurations can be changed directly. At any time, PWM signal output can be enabled or disabled by software, and the output signal level can be changed, more details can be found in section 35.4.2. 35.8 Memory Blocks Each LEDC channel has a memory to store duty cycle fading configuration data. Each memory can store configuration data for up to 16 ranges. The addresses in this section are relative to LED PWM Controller base address provided in Table 4.3-2 in Chapter 4 System and Memory. Table 35.8-1. LEDC Memory Blocks Name Description Size Starting Address Ending Address Access LEDC_CHn_MEM Memory of PWMn 64 B 0x400 + PWMn * 64 0x400 + (PWMn + 1) * 64 R/W Espressif Systems 1252 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 35 LED PWM Controller (LEDC) 35.9 Register Summary The addresses in this section are relative to LED PWM Controller base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Configuration Register LEDC_CH0_CONF0_REG Configuration register 0 for channel 0 0x0000 varies LEDC_CH0_HPOINT_REG High point register for channel 0 0x0004 R/W LEDC_CH0_DUTY_REG Initial duty cycle register for channel 0 0x0008 R/W LEDC_CH0_CONF1_REG Configuration register 1 for channel 0 0x000C R/W/SC LEDC_CH1_CONF0_REG Configuration register 0 for channel 1 0x0014 varies LEDC_CH1_HPOINT_REG High point register for channel 1 0x0018 R/W LEDC_CH1_DUTY_REG Initial duty cycle register for channel 1 0x001C R/W LEDC_CH1_CONF1_REG Configuration register 1 for channel 1 0x0020 R/W/SC LEDC_CH2_CONF0_REG Configuration register 0 for channel 2 0x0028 varies LEDC_CH2_HPOINT_REG High point register for channel 2 0x002C R/W LEDC_CH2_DUTY_REG Initial duty cycle register for channel 2 0x0030 R/W LEDC_CH2_CONF1_REG Configuration register 1 for channel 2 0x0034 R/W/SC LEDC_CH3_CONF0_REG Configuration register 0 for channel 3 0x003C varies LEDC_CH3_HPOINT_REG High point register for channel 3 0x0040 R/W LEDC_CH3_DUTY_REG Initial duty cycle register for channel 3 0x0044 R/W LEDC_CH3_CONF1_REG Configuration register 1 for channel 3 0x0048 R/W/SC LEDC_CH4_CONF0_REG Configuration register 0 for channel 4 0x0050 varies LEDC_CH4_HPOINT_REG High point register for channel 4 0x0054 R/W LEDC_CH4_DUTY_REG Initial duty cycle register for channel 4 0x0058 R/W LEDC_CH4_CONF1_REG Configuration register 1 for channel 4 0x005C R/W/SC LEDC_CH5_CONF0_REG Configuration register 0 for channel 5 0x0064 varies LEDC_CH5_HPOINT_REG High point register for channel 5 0x0068 R/W LEDC_CH5_DUTY_REG Initial duty cycle register for channel 5 0x006C R/W LEDC_CH5_CONF1_REG Configuration register 1 for channel 5 0x0070 R/W/SC LEDC_TIMER0_CONF_REG Timer 0 configuration register 0x00A0 varies LEDC_TIMER1_CONF_REG Timer 1 configuration register 0x00A8 varies LEDC_TIMER2_CONF_REG Timer 2 configuration register 0x00B0 varies LEDC_TIMER3_CONF_REG Timer 3 configuration register 0x00B8 varies LEDC_CH0_GAMMA_CONF_REG LEDC channel 0 gamma config register 0x0100 varies LEDC_CH1_GAMMA_CONF_REG LEDC channel 1 gamma config register 0x0104 varies LEDC_CH2_GAMMA_CONF_REG LEDC channel 2 gamma config register 0x0108 varies LEDC_CH3_GAMMA_CONF_REG LEDC channel 3 gamma config register 0x010C varies LEDC_CH4_GAMMA_CONF_REG LEDC channel 4 gamma config register 0x0110 varies LEDC_CH5_GAMMA_CONF_REG LEDC channel 5 gamma config register. 0x0114 varies LEDC_EVT_TASK_EN0_REG LEDC event task enable bit register 0 0x0120 R/W LEDC_EVT_TASK_EN1_REG LEDC event task enable bit register 1 0x0124 R/W Espressif Systems 1253 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 35 LED PWM Controller (LEDC) Name Description Address Access LEDC_EVT_TASK_EN2_REG LEDC event task enable bit register 2 0x0128 R/W LEDC_TIMER0_CMP_REG LEDC timer 0 compare value register 0x0140 R/W LEDC_TIMER1_CMP_REG LEDC timer 1 compare value register 0x0144 R/W LEDC_TIMER2_CMP_REG LEDC timer 2 compare value register 0x0148 R/W LEDC_TIMER3_CMP_REG LEDC timer 3 compare value register 0x014C R/W LEDC_CONF_REG LEDC global configuration register 0x0170 R/W Status Register LEDC_CH0_DUTY_R_REG Current duty cycle register for channel 0 0x0010 RO LEDC_CH1_DUTY_R_REG Current duty cycle register for channel 1 0x0024 RO LEDC_CH2_DUTY_R_REG Current duty cycle register for channel 2 0x0038 RO LEDC_CH3_DUTY_R_REG Current duty cycle register for channel 3 0x004C RO LEDC_CH4_DUTY_R_REG Current duty cycle register for channel 4 0x0060 RO LEDC_CH5_DUTY_R_REG Current duty cycle register for channel 5 0x0074 RO LEDC_TIMER0_VALUE_REG Timer 0 current counter value register 0x00A4 RO LEDC_TIMER1_VALUE_REG Timer 1 current counter value register 0x00AC RO LEDC_TIMER2_VALUE_REG Timer 2 current counter value register 0x00B4 RO LEDC_TIMER3_VALUE_REG Timer 3 current counter value register 0x00BC RO LEDC_TIMER0_CNT_CAP_REG LEDC timer 0 captured count value register 0x0150 RO LEDC_TIMER1_CNT_CAP_REG LEDC timer 1 captured count value register 0x0154 RO LEDC_TIMER2_CNT_CAP_REG LEDC timer 2 captured count value register 0x0158 RO LEDC_TIMER3_CNT_CAP_REG LEDC timer 3 captured count value register 0x015C RO Interrupt Register LEDC_INT_RAW_REG Interrupt raw status register 0x00C0 R/WTC/SS LEDC_INT_ST_REG Interrupt masked status register 0x00C4 RO LEDC_INT_ENA_REG Interrupt enable register 0x00C8 R/W LEDC_INT_CLR_REG Interrupt clear register 0x00CC WT Version Register LEDC_DATE_REG Version control register 0x0174 R/W Espressif Systems 1254 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 35 LED PWM Controller (LEDC) 35.10 Registers The addresses in this section are relative to LED PWM Controller base address provided in Table 4.3-2 in Chapter 4 System and Memory. For how to program reserved fields, please refer to Section Programming Reserved Register Field. Espressif Systems 1255 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 35 LED PWM Controller (LEDC) Register 35.1. LEDC_CHn_CONF0_REG (n: 0-5) (0x0000+0x14*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 17 LEDC_OVF_CNT_RESET_CHn 0 16 LEDC_OVF_CNT_EN_CHn 0 15 LEDC_OVF_NUM_CHn 0 14 5 LEDC_PARA_UP_CHn 0 4 LEDC_IDLE_LV_CHn 0 3 LEDC_SIG_OUT_EN_CHn 0 2 LEDC_TIMER_SEL_CHn 0 1 0 Reset LEDC_TIMER_SEL_CHn Configures which timer is channel n selected. 0: Select Timer 0 1: Select Timer 1 2: Select Timer 2 3: Select Timer 3 (R/W) LEDC_SIG_OUT_EN_CHn Configures whether to enable signal output on channel n. 0: Signal output disable 1: Signal output enable (R/W) LEDC_IDLE_LV_CHn Configures the output value when channel n is inactive. Valid only when LEDC_SIG_OUT_EN_CHn is 0. 0: Output level is low 1: Output level is high (R/W) LEDC_PARA_UP_CHn Configures whether to update LEDC_HPOINT_CHn, LEDC_DUTY_START_CHn, LEDC_SIG_OUT_EN_CHn, LEDC_TIMER_SEL_CHn, LEDC_OVF_CNT_EN_CHn fields and duty cycle range configurations for channel n, and will be automatically cleared by hardware. 0: Invalid. No effect 1: Update This bit is cleared by hardware (WT) LEDC_OVF_NUM_CHn Configures the maximum times of overflow minus 1. The LEDC_OVF_CNT_CHn_INT interrupt will be triggered when channel n overflows for (LEDC_OVF_NUM_CHn + 1) times. (R/W) LEDC_OVF_CNT_EN_CHn Configures whether to enable the ovf_cnt of channel n. 0: Disable 1: Enable (R/W) Continued on the next page... Espressif Systems 1256 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 35 LED PWM Controller (LEDC) Register 35.1. LEDC_CHn_CONF0_REG (n: 0-5) (0x0000+0x14*n) Continued from the previous page... LEDC_OVF_CNT_RESET_CHn Configures whether to reset the ovf_cnt of channel n. 0: Invalid. No effect 1: Reset the ovf_cnt (WT) Register 35.2. LEDC_CHn_HPOINT_REG (n: 0-5) (0x0004+0x14*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 31 20 LEDC_HPOINT_CHn 0x000 19 0 Reset LEDC_HPOINT_CHn Configures high point of signal output on channel n. The output value changes to high when the selected timers have reached the value specified by this register. (R/W) Register 35.3. LEDC_CHn_DUTY_REG (n: 0-5) (0x0008+0x14*n) (reserved) 0 0 0 0 0 0 0 31 25 LEDC_DUTY_CHn 0x00000 24 0 Reset LEDC_DUTY_CHn Configures the duty cycle of signal output on channel n. (R/W) Espressif Systems 1257 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 35 LED PWM Controller (LEDC) Register 35.4. LEDC_CHn_CONF1_REG (n: 0-5) (0x000C+0x14*n) LEDC_DUTY_START_CHn 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 0 Reset LEDC_DUTY_START_CHn Configures whether the duty cycle fading configurations take effect. 0: Not take effect 1: Take effect (R/W/SC) Register 35.5. LEDC_TIMERx_CONF_REG (x: 0-3) (0x00A0+0x8*x) (reserved) 0 0 0 0 0 31 27 LEDC_TIMERx_PARA_UP 0 26 (reserved) 0 25 LEDC_TIMERx_RST 1 24 LEDC_TIMERx_PAUSE 0 23 LEDC_CLK_DIV_TIMERx 0x000 22 5 LEDC_TIMERx_DUTY_RES 0x0 4 0 Reset LEDC_TIMERx_DUTY_RES Configures the bit width of the counter in timer x. Valid values are 1 to 20. (R/W) LEDC_CLK_DIV_TIMERx Configures the divisor for the divider in timer x. The least significant eight bits represent the fractional part. The most significant ten bits represent the integer part. (R/W) LEDC_TIMERx_PAUSE Configures whether to pause the counter in timer x. 0: Normal 1: Pause (R/W) LEDC_TIMERx_RST Configures whether to reset timer x. The counter will show 0 after reset. 0: Not reset 1: Reset (R/W) LEDC_TIMERx_PARA_UP Configures whether to update LEDC_CLK_DIV_TIMERx and LEDC_TIMERx_DUTY_RES. 0: Invalid. No effect 1: Update (WT) Espressif Systems 1258 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 35 LED PWM Controller (LEDC) Register 35.6. LEDC_CHn_GAMMA_CONF_REG (n: 0-5) (0x0100+0x4*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 7 LEDC_CHn_GAMMA_RESUME 0 6 LEDC_CHn_GAMMA_PAUSE 0 5 LEDC_CHn_GAMMA_ENTRY_NUM 0x0 4 0 Reset LEDC_CHn_GAMMA_ENTRY_NUM Configures the number of duty cycle fading ranges for LEDC channel n. (R/W) LEDC_CHn_GAMMA_PAUSE Configures whether to pause duty cycle fading of LEDC channel n. 0: Invalid. No effect 1: Pause (WT) LEDC_CHn_GAMMA_RESUME Configures whether to resume duty cycle fading of LEDC channel n. 0: Invalid. No effect 1: Resume (WT) Espressif Systems 1259 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 35 LED PWM Controller (LEDC) Register 35.7. LEDC_EVT_TASK_EN0_REG (0x0120) (reserved) 0 0 31 30 LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN 0 29 LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN 0 28 LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN 0 27 LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN 0 26 LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN 0 25 LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN 0 24 LEDC_EVT_TIME3_CMP_EN 0 23 LEDC_EVT_TIME2_CMP_EN 0 22 LEDC_EVT_TIME1_CMP_EN 0 21 LEDC_EVT_TIME0_CMP_EN 0 20 LEDC_EVT_TIME_OVF_TIMER3_EN 0 19 LEDC_EVT_TIME_OVF_TIMER2_EN 0 18 LEDC_EVT_TIME_OVF_TIMER1_EN 0 17 LEDC_EVT_TIME_OVF_TIMER0_EN 0 16 (reserved) 0 0 15 14 LEDC_EVT_OVF_CNT_PLS_CH5_EN 0 13 LEDC_EVT_OVF_CNT_PLS_CH4_EN 0 12 LEDC_EVT_OVF_CNT_PLS_CH3_EN 0 11 LEDC_EVT_OVF_CNT_PLS_CH2_EN 0 10 LEDC_EVT_OVF_CNT_PLS_CH1_EN 0 9 LEDC_EVT_OVF_CNT_PLS_CH0_EN 0 8 (reserved) 0 0 7 6 LEDC_EVT_DUTY_CHNG_END_CH5_EN 0 5 LEDC_EVT_DUTY_CHNG_END_CH4_EN 0 4 LEDC_EVT_DUTY_CHNG_END_CH3_EN 0 3 LEDC_EVT_DUTY_CHNG_END_CH2_EN 0 2 LEDC_EVT_DUTY_CHNG_END_CH1_EN 0 1 LEDC_EVT_DUTY_CHNG_END_CH0_EN 0 0 Reset LEDC_EVT_DUTY_CHNG_END_CHn_EN (n: 0-5) Configures whether to enable the LEDC_EVT_DUTY_CHNG_END_CHn event. 0: Disable 1: Enable (R/W) LEDC_EVT_OVF_CNT_PLS_CHn_EN (n: 0-5) Configures whether to enable the LEDC_EVT_OVF_CNT_PLS_CHn event. 0: Disable 1: Enable (R/W) LEDC_EVT_TIME_OVF_TIMERx_EN (x: 0-3) Configures whether to enable the LEDC_EVT_TIME_OVF_TIMERx event. 0: Disable 1: Enable (R/W) LEDC_EVT_TIMERx_CMP_EN (x: 0-3) Configures whether to enable the LEDC_EVT_TIMERx_CMP event. 0: Disable 1: Enable (R/W) LEDC_TASK_DUTY_SCALE_UPDATE_CHn_EN (n: 0-5) Configures whether to enable the LEDC_TASK_DUTY_SCALE_UPDATE_CHn task. 0: Disable 1: Enable (R/W) Espressif Systems 1260 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 35 LED PWM Controller (LEDC) Register 35.8. LEDC_EVT_TASK_EN1_REG (0x0124) LEDC_TASK_TIMER3_PAUSE_RESUME_EN 0 31 LEDC_TASK_TIMER2_PAUSE_RESUME_EN 0 30 LEDC_TASK_TIMER1_PAUSE_RESUME_EN 0 29 LEDC_TASK_TIMER0_PAUSE_RESUME_EN 0 28 LEDC_TASK_TIMER3_RST_EN 0 27 LEDC_TASK_TIMER2_RST_EN 0 26 LEDC_TASK_TIMER1_RST_EN 0 25 LEDC_TASK_TIMER0_RST_EN 0 24 (reserved) 0 0 23 22 LEDC_TASK_OVF_CNT_RST_CH5_EN 0 21 LEDC_TASK_OVF_CNT_RST_CH4_EN 0 20 LEDC_TASK_OVF_CNT_RST_CH3_EN 0 19 LEDC_TASK_OVF_CNT_RST_CH2_EN 0 18 LEDC_TASK_OVF_CNT_RST_CH1_EN 0 17 LEDC_TASK_OVF_CNT_RST_CH0_EN 0 16 (reserved) 0 0 15 14 LEDC_TASK_SIG_OUT_DIS_CH5_EN 0 13 LEDC_TASK_SIG_OUT_DIS_CH4_EN 0 12 LEDC_TASK_SIG_OUT_DIS_CH3_EN 0 11 LEDC_TASK_SIG_OUT_DIS_CH2_EN 0 10 LEDC_TASK_SIG_OUT_DIS_CH1_EN 0 9 LEDC_TASK_SIG_OUT_DIS_CH0_EN 0 8 LEDC_TASK_TIMER3_CAP_EN 0 7 LEDC_TASK_TIMER2_CAP_EN 0 6 LEDC_TASK_TIMER1_CAP_EN 0 5 LEDC_TASK_TIMER0_CAP_EN 0 4 LEDC_TASK_TIMER3_RES_UPDATE_EN 0 3 LEDC_TASK_TIMER2_RES_UPDATE_EN 0 2 LEDC_TASK_TIMER1_RES_UPDATE_EN 0 1 LEDC_TASK_TIMER0_RES_UPDATE_EN 0 0 Reset LEDC_TASK_TIMERx_RES_UPDATE_EN (x: 0-3) Configures whether to enable LEDC_TASK_TIMERx_RES_UPDATE task. 0: Disable 1: Enable (R/W) LEDC_TASK_TIMERx_CAP_EN (x: 0-3) Configures whether to enable LEDC_TASK_TIMERx_CAP task. 0: Disable 1: Enable (R/W) LEDC_TASK_SIG_OUT_DIS_CHn_EN (n: 0-5) Configures whether to enable LEDC_TASK_SIG_OUT_DIS_CHn task. 0: Disable 1: Enable (R/W) LEDC_TASK_OVF_CNT_RST_CHn_EN (n: 0-5) Configures whether to enable LEDC_TASK_OVF_CNT_RST_CHn task. 0: Disable 1: Enable (R/W) LEDC_TASK_TIMERx_RST_EN (x: 0-3) Configures whether to enable LEDC_TASK_TIMERx_RST task. 0: Disable 1: Enable (R/W) LEDC_TASK_TIMERx_PAUSE_RESUME_EN (x: 0-3) Configures whether to enable LEDC_TASK_TIMERx_PAUSE and LEDC_TASK_TIMERx_RESUME task. 0: Disable 1: Enable (R/W) Espressif Systems 1261 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 35 LED PWM Controller (LEDC) Register 35.9. LEDC_EVT_TASK_EN2_REG (0x0128) (reserved) 0 0 0 0 0 0 0 0 0 0 31 22 LEDC_TASK_GAMMA_RESUME_CH5_EN 0 21 LEDC_TASK_GAMMA_RESUME_CH4_EN 0 20 LEDC_TASK_GAMMA_RESUME_CH3_EN 0 19 LEDC_TASK_GAMMA_RESUME_CH2_EN 0 18 LEDC_TASK_GAMMA_RESUME_CH1_EN 0 17 LEDC_TASK_GAMMA_RESUME_CH0_EN 0 16 (reserved) 0 0 15 14 LEDC_TASK_GAMMA_PAUSE_CH5_EN 0 13 LEDC_TASK_GAMMA_PAUSE_CH4_EN 0 12 LEDC_TASK_GAMMA_PAUSE_CH3_EN 0 11 LEDC_TASK_GAMMA_PAUSE_CH2_EN 0 10 LEDC_TASK_GAMMA_PAUSE_CH1_EN 0 9 LEDC_TASK_GAMMA_PAUSE_CH0_EN 0 8 (reserved) 0 0 7 6 LEDC_TASK_GAMMA_RESTART_CH5_EN 0 5 LEDC_TASK_GAMMA_RESTART_CH4_EN 0 4 LEDC_TASK_GAMMA_RESTART_CH3_EN 0 3 LEDC_TASK_GAMMA_RESTART_CH2_EN 0 2 LEDC_TASK_GAMMA_RESTART_CH1_EN 0 1 LEDC_TASK_GAMMA_RESTART_CH0_EN 0 0 Reset LEDC_TASK_GAMMA_RESTART_CHn_EN (n: 0-5) Configures whether to enable LEDC_TASK_GAMMA_RESTART_CHn task. 0: Disable 1: Enable (R/W) LEDC_TASK_GAMMA_PAUSE_CHn_EN (n: 0-5) Configures whether to enable LEDC_TASK_GAMMA_PAUSE_CHn task. 0: Disable 1: Enable (R/W) LEDC_TASK_GAMMA_RESUME_CHn_EN (n: 0-5) Configures whether to enable LEDC_TASK_GAMMA_RESUME_CHn task. 0: Disable 1: Enable (R/W) Register 35.10. LEDC_TIMERx_CMP_REG (x: 0-3) (0x0140+0x4*x) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 31 20 LEDC_TIMERx_CMP 0x000 19 0 Reset LEDC_TIMERx_CMP Configures the comparison value for LEDC timer x. (R/W) Espressif Systems 1262 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 35 LED PWM Controller (LEDC) Register 35.11. LEDC_CONF_REG (0x0170) LEDC_CLK_EN 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 8 LEDC_GAMMA_RAM_CLK_EN_CH5 0 7 LEDC_GAMMA_RAM_CLK_EN_CH4 0 6 LEDC_GAMMA_RAM_CLK_EN_CH3 0 5 LEDC_GAMMA_RAM_CLK_EN_CH2 0 4 LEDC_GAMMA_RAM_CLK_EN_CH1 0 3 LEDC_GAMMA_RAM_CLK_EN_CH0 0 2 (reserved) 0 1 0 Reset LEDC_GAMMA_RAM_CLK_EN_CHn (n: 0-5) Configures whether to open LEDC channel n gamma RAM clock gate. 0: Open the clock gate only when an application writes or reads LEDC channel n gamma RAM 1: Force open the clock gate for LEDC channel n gamma RAM (R/W) LEDC_CLK_EN Configures whether to open the register clock gate. 0: Open the clock gate only when an application writes registers 1: Force open the clock gate for register (R/W) Register 35.12. LEDC_CHn_DUTY_R_REG (n: 0-5) (0x0010+0x14*n) (reserved) 0 0 0 0 0 0 0 31 25 LEDC_DUTY_CHn_R 0x00000 24 0 Reset LEDC_DUTY_CHn_R Represents the current duty cycle of output signal on channel n. (RO) Register 35.13. LEDC_TIMERx_VALUE_REG (x: 0-3) (0x00A4+0x8*x) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 31 20 LEDC_TIMERx_CNT 0 19 0 Reset LEDC_TIMERx_CNT Represents the current counter value of timer x. (RO) Espressif Systems 1263 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 35 LED PWM Controller (LEDC) Register 35.14. LEDC_TIMERx_CNT_CAP_REG (x: 0-3) (0x0150+0x4*x) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 31 20 LEDC_TIMERx_CNT_CAP 0x000 19 0 Reset LEDC_TIMERx_CNT_CAP Represents the captured LEDC timer x count value. (RO) Register 35.15. LEDC_INT_RAW_REG (0x00C0) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 18 LEDC_OVF_CNT_CH5_INT_RAW 0 17 LEDC_OVF_CNT_CH4_INT_RAW 0 16 LEDC_OVF_CNT_CH3_INT_RAW 0 15 LEDC_OVF_CNT_CH2_INT_RAW 0 14 LEDC_OVF_CNT_CH1_INT_RAW 0 13 LEDC_OVF_CNT_CH0_INT_RAW 0 12 (reserved) 0 0 11 10 LEDC_DUTY_CHNG_END_CH5_INT_RAW 0 9 LEDC_DUTY_CHNG_END_CH4_INT_RAW 0 8 LEDC_DUTY_CHNG_END_CH3_INT_RAW 0 7 LEDC_DUTY_CHNG_END_CH2_INT_RAW 0 6 LEDC_DUTY_CHNG_END_CH1_INT_RAW 0 5 LEDC_DUTY_CHNG_END_CH0_INT_RAW 0 4 LEDC_TIMER3_OVF_INT_RAW 0 3 LEDC_TIMER2_OVF_INT_RAW 0 2 LEDC_TIMER1_OVF_INT_RAW 0 1 LEDC_TIMER0_OVF_INT_RAW 0 0 Reset LEDC_TIMERx_OVF_INT_RAW (x: 0-3) Raw status bit: The raw interrupt status of LEDC_TIMERx_OVF_INT. Triggered when the timer x has reached its maximum counter value. (R/WTC/SS) LEDC_DUTY_CHNG_END_CHn_INT_RAW (n: 0-5) Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CHn_INT. Triggered when the fading of duty has finished. (R/WTC/SS) LEDC_OVF_CNT_CHn_INT_RAW (n: 0-5) Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CHn_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CHn. (R/WTC/SS) Espressif Systems 1264 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 35 LED PWM Controller (LEDC) Register 35.16. LEDC_INT_ST_REG (0x00C4) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 18 LEDC_OVF_CNT_CH5_INT_ST 0 17 LEDC_OVF_CNT_CH4_INT_ST 0 16 LEDC_OVF_CNT_CH3_INT_ST 0 15 LEDC_OVF_CNT_CH2_INT_ST 0 14 LEDC_OVF_CNT_CH1_INT_ST 0 13 LEDC_OVF_CNT_CH0_INT_ST 0 12 (reserved) 0 0 11 10 LEDC_DUTY_CHNG_END_CH5_INT_ST 0 9 LEDC_DUTY_CHNG_END_CH4_INT_ST 0 8 LEDC_DUTY_CHNG_END_CH3_INT_ST 0 7 LEDC_DUTY_CHNG_END_CH2_INT_ST 0 6 LEDC_DUTY_CHNG_END_CH1_INT_ST 0 5 LEDC_DUTY_CHNG_END_CH0_INT_ST 0 4 LEDC_TIMER3_OVF_INT_ST 0 3 LEDC_TIMER2_OVF_INT_ST 0 2 LEDC_TIMER1_OVF_INT_ST 0 1 LEDC_TIMER0_OVF_INT_ST 0 0 Reset LEDC_TIMERx_OVF_INT_ST (x: 0-3) Masked status bit: The masked interrupt status of LEDC_TIMERx_OVF_INT. Valid only when LEDC_TIMERx_OVF_INT_ENA is set to 1. (RO) LEDC_DUTY_CHNG_END_CHn_INT_ST (n: 0-5) Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CHn_INT. Valid only when LEDC_DUTY_CHNG_END_CHn_INT_ENA is set to 1. (RO) LEDC_OVF_CNT_CHn_INT_ST (n: 0-5) Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CHn_INT. Valid only when LEDC_OVF_CNT_CHn_INT_ENA is set to 1. (RO) Register 35.17. LEDC_INT_ENA_REG (0x00C8) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 18 LEDC_OVF_CNT_CH5_INT_ENA 0 17 LEDC_OVF_CNT_CH4_INT_ENA 0 16 LEDC_OVF_CNT_CH3_INT_ENA 0 15 LEDC_OVF_CNT_CH2_INT_ENA 0 14 LEDC_OVF_CNT_CH1_INT_ENA 0 13 LEDC_OVF_CNT_CH0_INT_ENA 0 12 (reserved) 0 0 11 10 LEDC_DUTY_CHNG_END_CH5_INT_ENA 0 9 LEDC_DUTY_CHNG_END_CH4_INT_ENA 0 8 LEDC_DUTY_CHNG_END_CH3_INT_ENA 0 7 LEDC_DUTY_CHNG_END_CH2_INT_ENA 0 6 LEDC_DUTY_CHNG_END_CH1_INT_ENA 0 5 LEDC_DUTY_CHNG_END_CH0_INT_ENA 0 4 LEDC_TIMER3_OVF_INT_ENA 0 3 LEDC_TIMER2_OVF_INT_ENA 0 2 LEDC_TIMER1_OVF_INT_ENA 0 1 LEDC_TIMER0_OVF_INT_ENA 0 0 Reset LEDC_TIMERx_OVF_INT_ENA (x: 0-3) Enable bit: Write 1 to enable LEDC_TIMERx_OVF_INT. (R/W) LEDC_DUTY_CHNG_END_CHn_INT_ENA (n: 0-5) Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CHn_INT. (R/W) LEDC_OVF_CNT_CHn_INT_ENA (n: 0-5) Enable bit: Write 1 to enable LEDC_OVF_CNT_CHn_INT. (R/W) Espressif Systems 1265 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 35 LED PWM Controller (LEDC) Register 35.18. LEDC_INT_CLR_REG (0x00CC) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 18 LEDC_OVF_CNT_CH5_INT_CLR 0 17 LEDC_OVF_CNT_CH4_INT_CLR 0 16 LEDC_OVF_CNT_CH3_INT_CLR 0 15 LEDC_OVF_CNT_CH2_INT_CLR 0 14 LEDC_OVF_CNT_CH1_INT_CLR 0 13 LEDC_OVF_CNT_CH0_INT_CLR 0 12 (reserved) 0 0 11 10 LEDC_DUTY_CHNG_END_CH5_INT_CLR 0 9 LEDC_DUTY_CHNG_END_CH4_INT_CLR 0 8 LEDC_DUTY_CHNG_END_CH3_INT_CLR 0 7 LEDC_DUTY_CHNG_END_CH2_INT_CLR 0 6 LEDC_DUTY_CHNG_END_CH1_INT_CLR 0 5 LEDC_DUTY_CHNG_END_CH0_INT_CLR 0 4 LEDC_TIMER3_OVF_INT_CLR 0 3 LEDC_TIMER2_OVF_INT_CLR 0 2 LEDC_TIMER1_OVF_INT_CLR 0 1 LEDC_TIMER0_OVF_INT_CLR 0 0 Reset LEDC_TIMERx_OVF_INT_CLR (x: 0-3) Clear bit: Write 1 to clear LEDC_TIMERx_OVF_INT. (WT) LEDC_DUTY_CHNG_END_CHn_INT_CLR (n: 0-5) Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CHn_INT. (WT) LEDC_OVF_CNT_CHn_INT_CLR (n: 0-5) Clear bit: Write 1 to clear LEDC_OVF_CNT_CHn_INT. (WT) Register 35.19. LEDC_DATE_REG (0x0174) (reserved) 0 0 0 0 31 28 LEDC_LEDC_DATE 0x2311220 27 0 Reset LEDC_LEDC_DATE Configures the version. (R/W) Espressif Systems 1266 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Chapter 36 Motor Control PWM (MCPWM) 36.1 Overview The Motor Control Pulse Width Modulator (MCPWM) peripheral is intended for motor and power control. It provides six PWM outputs that can be set up to operate in several topologies. One common topology uses a pair of PWM outputs driving an H-bridge to control motor rotation speed and rotation direction. The MCPWM can be divided into five main modules: PWM timers, PWM operators, Capture module, Event Task Matrix (ETM) module, and Fault Detection module. Each PWM timer provides timing references that can either run freely or be synced to other timers or external sources. Each PWM operator has all the necessary control resources to generate waveform pairs for one PWM channel. The Capture module is used for systems that need to accurately time external events. The ETM module responds to tasks received by the MCPWM, generating corresponding events depending on the state of motion. The Fault Detection module is used to capture external faults, allowing the system to respond by choice. ESP32-C5 has one MCPWM peripheral, which is MCPWM0. 36.2 Features An MCPWM peripheral has one clock divider (prescaler), three PWM timers, three PWM operators, a Capture module, an ETM module, and a Fault Detection module. MCPWM’s core clock can be selected from three clock sources: PLL_F160M_CLK, XTAL_CLK, and RC_FAST_CLK (configured by the PCR_PWM_CLKM_SEL field of the PCR_PWM_CLK_CONF_REG register). Figure 36.2-1 shows the submodules inside MCPWM and the signals on the interface. PWM timers are used for generating timing references. The PWM operators generate the desired waveform based on the timing references. Any PWM operator can be configured to use the timing references of any PWM timers. Different PWM operators can use the same PWM timer’s timing reference to generate PWM signals, or different PWM timers’ values to generate separate PWM signals. Different PWM timers can also be synchronized together. Espressif Systems 1267 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Figure 36.2-1. MCPWM Module Overview Below is an overview of the submodules’ functionality in Figure 36.2-1: • PWM Timers 0, 1, and 2: – Every PWM timer has a dedicated 8-bit clock prescaler. – The 16-bit counter in the PWM timer can work in Count-Up Mode, Count-Down Mode, or Count-Up-Down Mode. – A hardware sync or software sync can trigger a reload on the PWM timer with a phase register. It will also trigger the prescaler’s restart, so that the timer’s clock can also be synced. The source of the hard sync can come from any GPIO or any other PWM timer’s sync_out. The source of the soft sync comes from writing toggle value to the MCPWM_TIMERn_SYNC_SW bit. • PWM Operators 0, 1, and 2: – Every PWM operator has two PWM outputs: PWMxA and PWMxB. They can work independently, in symmetric or asymmetric configurations. – The control of the PWM signal can be updated asynchronously. – Configurable dead time on rising and falling edges; each set up independently. – All events can trigger CPU interrupts. – Modulating of PWM output by high-frequency carrier signals, useful when gate drivers are insulated with a transformer. – Period, time-stamp, and important control registers have shadow registers with flexible updating methods. • Fault Detection Module: – Programmable fault handling in both cycle-by-cycle mode and one-shot mode. Espressif Systems 1268 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) – A fault condition can force the PWM output to either high or low logic levels. • Capture Module: – Clock of the capture module is the same as MCPWM’s core clock. – Speed measurement of rotating machinery. – Measurement of elapsed time between position sensor pulses – Period and duty cycle measurement of pulse train signals – Decoding current or voltage amplitude derived from duty-cycle-encoded signals of current/voltage sensors – Three individual capture channels, each of which with a time-stamp register (32-bit) – Selection of edge polarity and prescaling of input capture signals – The capture timer can sync with a PWM timer or external signals. – Interrupt on each of the three capture channels • ETM Module: – Generation of different events depending on the different running states of each timer and operator. – Each timer and operator responds to its corresponding task and automatically performs the corresponding operation. – Each event and task can be enabled independently. When an event is not enabled, the corresponding event will not be generated. When a task is not enabled, the corresponding task will not be responded to. Espressif Systems 1269 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) 36.3 Modules 36.3.1 Overview The key modules in each MCPWM are timer module, operator module, fault detection module, capture module, and ETM module. See their functions in the following sections. 36.3.1.1 Timer Module Figure 36.3-1. Timer Module This module contains a timer, which can count at a specified period. It can work in Count-Up Mode, Count-Down Mode, or Count-Up-Down Mode. It supports different synchronization input sources (a total of seven optional input sources) for reloading the count value and direction, allowing synchronization among multiple timers. Furthermore, it provides synchronization output options (a total of four optional output sources) for use by other timers. The timerx status in the figure represents the timer status output by the timer module, such as the counting mode, and count value equal to zero or period. 36.3.1.2 Operator Module Figure 36.3-2. Operator Module A PWM operator contains a PWM generator, a dead time generator, and a PWM carrier module. Their functions are shown in Table 36.3-1. Espressif Systems 1270 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Table 36.3-1. Functions of Each Submodule in the Operator Module Submodule Functions PWM Generator Generate PWM signals according to the configured duty cycle and waveform. Dead Time Generator Choose to add dead time to the rising and falling edges of the PWM signal generated by the PWM generator (add delays to the rising and falling edges), and perform operations such as inversion. PWM Carrier Choose to add a carrier to the PWM signal generated by the dead time generator. The carrier frequency and the first pulse duration of the PWM waveform after adding the carrier can be configured. Fault Detector Detect faults and generate corresponding fault events, respond to fault events based on the specified interval mode (one-shot mode or cycle-by-cycle mode), and when a fault event occurs, take action on the PWM signal generated by the PWM carrier in the specified way. 36.3.1.3 Capture Module Figure 36.3-3. Capture Module The module contains a timer that can be synchronized. When the input capture signal is valid, the count value of the timer is captured. 36.3.1.4 ETM Module Figure 36.3-4. ETM Module The module responds to received tasks, or generate and output events. Each event and task can be enabled independently. Espressif Systems 1271 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) 36.3.2 PWM Timer Module MCPWM has three PWM timer modules. Any of them can determine the necessary event timing for any of the three PWM operator modules. By using the synchronization signals from the GPIO matrix, built-in synchronization logic allows multiple PWM timer modules in one or more MCPWM peripherals to work together as a system. 36.3.2.1 Configurations of the PWM Timer Module Users can configure the following functions of the PWM timer module: • Control how often events occur by specifying the PWM timer frequency or period. • Configure a particular PWM timer to synchronize phases with other PWM timers or modules. • Configure the following timer counting modes: count-up, count-down, count-up-down. • Change the rate of the PWM timer clock (PT_CLK) with a prescaler. Each timer has its own prescaler configured with MCPWM_TIMERn_PRESCALE of the register MCPWM_TIMER0_CFG0_REG. The PWM timer increments or decrements at a slower pace, depending on the setting of this field. The new MCPWM_TIMERn_PRESCALE configuration value will take effect when the timer stops and starts counting again. 36.3.2.2 PWM Timer’s Working Modes and Timing Event Generation The PWM timer has three working modes, selected by the PWMx timer mode field: • Count-Up Mode: The PWM timer increments from zero until reaching the value configured in the period field. Once done, the PWM timer returns to zero and starts increasing again. PWM period = the value of the period field + 1. Note: The period field is MCPWM_TIMERn_PERIOD (x = 0, 1, 2), i.e., MCPWM_TIMER0_PERIOD, MCPWM_TIMER1_PERIOD, MCPWM_TIMER2_PERIOD. • Count-Down Mode: The PWM timer decrements to zero, starting from the value configured in the period field. Once done, the PWM timer returns to the period value and starts decrementing again. In this case, the PWM period = the value of period field + 1. • Count-Up-Down Mode: This is a combination of the two modes mentioned above. The PWM timer starts increasing from zero until the period value is reached. Then, the timer decreases back to zero. The PWM timer cycles incrementally and decrementally in this mode. The PWM period = the value of the period field × 2. Figures 36.3-5 to 36.3-8 show PWM timer waveforms in different modes, including timer behavior during synchronization events. In Count-Up mode, the counting direction after synchronization is always counting up. In Count-Down mode, the counting direction after synchronization is always counting down. In Count-Up-Down Mode, the counting direction after synchronization can be chosen by setting the MCPWM_TIMERn_PHASE_DIRECTION. Espressif Systems 1272 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Figure 36.3-5. Count-Up Mode Waveform Figure 36.3-6. Count-Down Mode Waveforms Figure 36.3-7. Count-Up-Down Mode Waveforms, Count-Down at Synchronization Event Espressif Systems 1273 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Figure 36.3-8. Count-Up-Down Mode Waveforms, Count-Up at Synchronization Event When the PWM timer is running, it generates the following timing events periodically and automatically: • UTEP: The timing event generated when the PWM timer’s value is equal to the value of the period field (MCPWM_TIMERn_PERIOD) and when the PWM timer is increasing. • UTEZ: The timing event generated when the PWM timer’s value equals zero and when the PWM timer is increasing. • DTEP: The timing event generated when the PWM timer’s value equals the value of the period field (MCPWM_TIMERn_PERIOD) and when the PWM timer is decreasing. • DTEZ: The timing event generated when the PWM timer’s value equals zero and when the PWM timer is decreasing. Figures 36.3-9 to 36.3-11 show the timing waveforms of U/DTEP and U/DTEZ. Espressif Systems 1274 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Figure 36.3-9. UTEP and UTEZ Generation in Count-Up Mode Espressif Systems 1275 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Figure 36.3-10. DTEP and DTEZ Generation in Count-Down Mode Figure 36.3-11. DTEP and UTEZ Generation in Count-Up-Down Mode Espressif Systems 1276 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Please note that in the Count-Up-Down Mode, when the counting direction is increasing, the timer range is [0, period value - 1], and when the counting direction is decreasing, the timer range is [period value, 1]. That is, in this mode, when synchronizing the timer to 0, decreasing counting direction will be illegal, namely, MCPWM_TIMERn_PHASE_DIRECTION cannot be set to 1. Similarly, when synchronizing the timer to period value, increasing counting direction will be illegal, namely, MCPWM_TIMERn_PHASE_DIRECTION cannot be set to 0. Therefore, when the timer is synchronized to 0, the counting direction can only be increasing, and MCPWM_TIMERn_PHASE_DIRECTION will be 0. When the timer is synchronized to the period value, the counting direction can only be decreasing, and MCPWM_TIMERn_PHASE_DIRECTION will be 1. Espressif Systems 1277 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) 36.3.2.3 Shadow Register of PWM Timer The PWM timer’s period register and the PWM timer’s clock prescaler register have shadow registers. The shadow registers can back up the values that are about to be written to the valid registers. It also supports writing the values saved into the active register at a specific moment of hardware synchronization. The functionality of both register types is as follows: • Active Register: Directly responsible for controlling all actions performed by hardware. • Shadow Register: Acts as a temporary buffer for a value to be written to the active register. At a specific, user-configured point in time, the value saved in the shadow register is copied to the active register. Before this happens, the content of the shadow register has no direct effect on the controlled hardware. This helps to prevent erroneous operation of the hardware, which may happen when a register is asynchronously modified by software. Both the shadow register and the active register have the same memory address. The software always writes into, or reads from the shadow register. The moment of updating the clock prescaler’s active register is at the time when the timer starts operating. When MCPWM_GLOBAL_UP_EN is set to 1, the moment of updating the period active register can be selected by the following ways: – By configuring the update method register MCPWM_TIMERn_PERIOD_UPMETHOD to 0, the update will start immediately. – By configuring the update method register MCPWM_TIMERn_PERIOD_UPMETHOD to 1, the update can start when the PWM timer is equal to zero. – By configuring the update method register MCPWM_TIMERn_PERIOD_UPMETHOD to 2, the update can start when the PWM timer is synchronized. – By configuring the update method register MCPWM_TIMERn_PERIOD_UPMETHOD to 3, the update can start when the PWM timer is equal to zero or is synchronized. – Software can also trigger a globally forced update bit MCPWM_GLOBAL_FORCE_UP which will prompt all registers in the module to be updated according to shadow registers. 36.3.2.4 PWM Timer Synchronization and Phase Locking The PWM modules adopt a flexible synchronization method. Each PWM timer has a synchronization input and a synchronization output. The synchronization input can be selected from three synchronization outputs of the three PWM timers and three synchronization signals from the GPIO matrix. The synchronization output can be generated when the PWM timer’s value equals to period or zero, the synchronization input signal is active, or software synchronizes. Thus, each PWM timer can flexibly select the synchronization input for different phase synchronization methods. During synchronization, the PWM timer clock prescaler will reset its counter and restart dividing the clock in order to ensure the correctness of the timer. 36.3.3 PWM Operator Module The PWM Operator module has the following functions: • Generates a PWM signal pair, based on timing references obtained from the corresponding PWM timer. Espressif Systems 1278 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) • Each signal out of the PWM signal pair includes a specific pattern of dead time (i.e., adding delays to the rising and falling edges of the PWM signal). • Superimposes a carrier on the PWM signal, if configured to do so. • Handles response under fault conditions. Figure 36.3-12 shows the block diagram of a PWM operator. Figure 36.3-12. Block Diagram of A PWM Operator 36.3.3.1 PWM Generator Module Purpose of the PWM Generator Module In this module, important timing events are generated or imported. The events are then converted into specific actions to generate the desired waveforms at the PWMxA and PWMxB outputs. The PWM generator module performs the following actions: • Generation of timing events based on time stamps configured using the A and B registers. Events happen when the following conditions are met (for the configuration of registers A and B, see section 36.3.3.1): – UTEA: the PWM timer is counting up and its value is equal to register A. – UTEB: the PWM timer is counting up and its value is equal to register B. – DTEA: the PWM timer is counting down and its value is equal to register A. – DTEB: the PWM timer is counting down and its value is equal to register B. • Generation of U/DT0, U/DT1 timing events based on fault or synchronization events. – UT0: the PWM timer is counting up and FAULT0 detected (field MCPWM_GENn_T0_SEL is set to 0) or FAULT1 detected (field MCPWM_GENn_T0_SEL is set to 1) or FAULT2 detected (field MCPWM_GENn_T0_SEL is set to 2) or synchronized (field MCPWM_GENn_T0_SEL is set to 3). – UT1: the PWM timer is counting up and FAULT0 detected (field MCPWM_GENn_T1_SEL is set to 0) or FAULT1 detected (field MCPWM_GENn_T1_SEL is set to 1) or FAULT2 detected (field MCPWM_GENn_T1_SEL is set to 2) or synchronized (field MCPWM_GENn_T1_SEL is set to 3). – DT0: the PWM timer is counting down and FAULT0 detected (field MCPWM_GENn_T0_SEL is set to 0) or FAULT1 detected (field MCPWM_GENn_T0_SEL is set to 1) or FAULT2 detected (field Espressif Systems 1279 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) MCPWM_GENn_T0_SEL is set to 2) or synchronized (field MCPWM_GENn_T0_SEL is set to 3). – DT1: the PWM timer is counting down and FAULT0 detected(field MCPWM_GENn_T1_SEL is set to 0) or FAULT1 detected (field MCPWM_GENn_T1_SEL is set to 1) or FAULT2 detected (field MCPWM_GENn_T1_SEL is set to 2) or synchronized (field MCPWM_GENn_T1_SEL is set to 3). • Management of priority when these timing events occur concurrently. • Generation of set, clear, and toggle actions, based on the timing events. • Controlling of the PWM duty cycle, depending on the configuration of the PWM generator module. • Handling of new time stamp values, using shadow registers to prevent glitches in the PWM cycle. Shadow Register of PWM Generator The time stamp registers A and B used by the hardware have shadow registers, which are registers MCPWM_GENn_A_REG and MCPWM_GENn_B_REG. Shadowing provides a way of updating registers in sync with the hardware. When MCPWM_GLOBAL_UP_EN is set to 1, the shadow registers can be written to the active register at a specified time. The update method field for MCPWM_GENn_A_REG and MCPWM_GENn_B_REG is MCPWM_GENn_CFG_UPMETHOD. Software can also trigger a globally forced update bit MCPWM_GLOBAL_FORCE_UP which will prompt all registers in the module to be updated according to shadow registers. For a description of the shadow registers, please see Section 36.3.2.3. Timing Events For convenience, all timing signals and events are summarized in Table 36.3-2. Table 36.3-2. Timing Events Used in PWM Generator Signal Event Description PWM Timer Operation DTEP PWM timer value is equal to the period register value PWM timer counts down DTEZ PWM timer value is equal to zero DTEA PWM timer value is equal to register A DTEB PWM timer value is equal to register B DT0 event Based on fault or synchronization events DT1 event Based on fault or synchronization events UTEP PWM timer value is equal to the period register value PWM timer counts up UTEZ PWM timer value is equal to zero UTEA PWM timer value is equal to register A UTEB PWM timer value is equal to register B UT0 event Based on fault or synchronization events UT1 event Based on fault or synchronization events Software-force event Software-initiated asynchronous event N/A The purpose of a software-force event is to impose non-continuous or continuous changes on the PWMxA and PWMxB outputs. The change is done asynchronously. Software-force control is handled by the MCPWM_GENn_FORCE_REG registers. Espressif Systems 1280 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) The selection and configuration of T0/T1 in the PWM generator module is independent of the configuration of fault events in the fault handler module. A particular trip event may or may not be configured to cause trip action in the fault handler submodule, but the same event can be used by the PWM generator to trigger T0/T1 for controlling PWM waveforms. It is important to know that when the PWM timer is in Count-Up-Down Mode. It will always decrement after a TEP event, and increment after a TEZ event. So, when the PWM timer is in Count-Up-Down Mode, DTEP and UTEZ events will occur, while UTEP and DTEZ events never occurs. The PWM generator can handle multiple events at the same time. Events are prioritized by the hardware and relevant details are provided in Table 36.3-3 and Table 36.3-4. Priority levels range from 1 (the highest) to 7 (the lowest). Please note that the priority of TEP and TEZ events depends on the PWM timer’s counting mode. If the value of A or B is set to be greater than the period, then U/DTEA and U/DTEB will never occur. Table 36.3-3. Timing Events Priority When PWM Timer Increments Priority Level Event 1 (highest) Software-forced event 2 UTEP 3 UT0 4 UT1 5 UTEB 6 UTEA 7 (lowest) UTEZ Table 36.3-4. Timing Events Priority when PWM Timer Decrements Priority level Event 1 (highest) Software-forced event 2 DTEZ 3 DT0 4 DT1 5 DTEB 6 DTEA 7 (lowest) DTEP Notes: 1. UTEP and UTEZ do not happen simultaneously. When the PWM timer is in Count-Up Mode, UTEP will always happen one cycle earlier than UTEZ, as demonstrated in Figure 36.3-9, so their action on PWM signals will not interrupt each other. When the PWM timer is in Count-Up-Down Mode, UTEP will not occur. 2. DTEP and DTEZ do not happen simultaneously. When the PWM timer is in Count-Down Mode, DTEZ will always happen one cycle earlier than DTEP, as demonstrated in Figure 36.3-10, so their action on PWM signals will not interrupt each other. When the PWM timer is in Count-Up-Down Mode, DTEZ will not occur. Espressif Systems 1281 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) PWM Signal Generation The PWM generator module controls the behavior of outputting PWMxA and PWMxB when a particular timing event occurs. The timing events are further qualified by the PWM timer’s counting mode (increment or decrement). Knowing the counting mode, the module may then perform an independent action at each stage of the PWM timer counting up or down. The following actions may be configured on PWMxA and PWMxB outputs: • Set High: Set the output of PWMxA or PWMxB to a high level. • Clear Low: Clear the output of PWMxA or PWMxB by setting it to a low level. • Toggle: Change the current output level of PWMxA or PWMxB to the opposite value. If it is currently pulled up, then pull it down, or vice versa. • Do Nothing: Keep both outputs PWMxA and PWMxB unchanged. In this state, interrupts can still be triggered. Actions on outputs is configured by using registers MCPWM_GENn_A_REG and MCPWM_GENn_B_REG. So, the action to be taken on each output is set independently. Also, there is great flexibility in selecting actions to be taken on a given output based on events. More specifically, any event listed in Table 36.3-2 can operate on either output of PWMxA or PWMxB. To check out registers for particular generator 0, 1, or 2, please refer to the register description in Section 36.5. Waveforms for Common Configurations In the configuration of various waveforms below, period refers to the configuration value stored in the period register of the PWM timer selected by the PWM operator (i.e. MCPWM_TIMERn _PERIOD (x = 0, 1, 2)). For configuration methods, please refer to the section 36.3.2. A and B denote the time stamp registers A and B used by the hardware. For register configuration, please refer to the section 36.3.3.1. UTEA/B, UTEZ/P, DTEA/B, DTEZ/P, DT0/1, and UT0/1 represent different timing events of the PWM generator. For event definition, please refer to the section 36.3.3.1. The upward arrow, downward arrow, and T mark signify setting the PWM waveform high, setting it low, toggling it when the timing event occurs. See section 36.3.3.1 for configuration. PWMxA and PWMxB are the output signals of PWM generatorx. Figure 36.3-13 presents the symmetric PWM waveform generated when the PWM timer is in Count-Up-Down mode. DC 0%–100% modulation can be calculated via the formula below: Duty = (P er iod − A) ÷ P eriod If A matches the PWM timer value and the PWM timer is incrementing, then the PWM output is pulled up. If A matches the PWM timer value while the PWM timer is decrementing, then the PWM output is pulled low. Espressif Systems 1282 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Figure 36.3-13. Symmetrical Waveform in Count-Up-Down Mode The PWM waveforms in Figures 36.3-14 to 36.3-17 show some common PWM generator configurations. Espressif Systems 1283 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Figure 36.3-14. Count-Up, Single Edge Asymmetric Waveform, with Independent Modulation on PWMxA and PWMxB — Active High The duty modulation for PWMxA is set by B, active high and proportional to B. The duty modulation for PWMxB is set by A, active high and proportional to A. P eriod = ( M CP W M _T IM ERn_P ERIOD + 1) × T P T _clk Espressif Systems 1284 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Figure 36.3-15. Count-Up, Pulse Placement Asymmetric Waveform with Independent Modulation on PWMxA Pulses may be generated anywhere within the PWM cycle (zero to period). PWMxA’s high time duty is proportional to (B – A). P eriod = ( M CP W M _T IM ERn_P ERIOD + 1) × T P T _clk Espressif Systems 1285 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Figure 36.3-16. Count-Up-Down, Dual Edge Symmetric Waveform, with Independent Modulation on PWMxA and PWMxB — Active High The duty modulation for PWMxA is set by A, active high and proportional to A. The duty modulation for PWMxB is set by B, active high and proportional to B. Outputting PWMxA and PWMxB can drive separate switches. P eriod = (2 × M CP W M_T IM ERn_P ERIOD) × T P T _clk Espressif Systems 1286 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Figure 36.3-17. Count-Up-Down, Dual Edge Symmetric Waveform, with Independent Modulation on PWMxA and PWMxB — Complementary The duty modulation of PWMxA is set by A, is active high and proportional to A. The duty modulation of PWMxB is set by B, is active low and proportional to B. Outputs PWMx can drive upper/lower (complementary) switches. Dead time = B – A. Edge placement is configurable by software. Dead time generator module supports configuring edge delay methods when required. P eriod = (2 × M CP W M_T IM ERn_P ERIOD) × T P T _clk Espressif Systems 1287 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Figure 36.3-18. Count-Up-Down, Fault or Synchronization Events, with Same Modulation on PWMxA and PWMxB Figure 36.3-18 shows a waveform when UT0/1 and DT0/1 events are generated. In this example, T0 selects FAULT0 and T1 selects FAULT1. The events selected by T0 and T1 can be configured independently, these events can be FAULT0, FAULT1, FAULT2 or synchronous. For detailed configuration, see section 36.3.3.1. Software-Force Events There are two types of software-force events inside the PWM generator: • Non-continuous-immediate (NCI) software-force events: Such types of events are immediately effective on PWM outputs when triggered by software. The forcing is non-continuous, which means the next active timing events will be able to alter the PWM outputs. • Continuous (CNTU) software-force events: Such types of events are continuous. The forced PWM outputs will continue until they are released by software. The events’ triggers are configurable. They can be Espressif Systems 1288 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) configured to be timing events or immediate events. For NCI software-force events, set register MCPWM_GENn_A_NCIFORCE or MCPWM_GENn_B_NCIFORCE to 1 and then to 0 to trigger the NCI software-forced events of PWMxA or PWMxB. Configure register MCPWM_GENn_A_NCIFORCE_MODE or MCPWM_GENn_B_NCIFORCE_MODE to specify the operation on the PWMxA or PWMxB waveform when the NCI software-force event occurs. Configuring the registers to 0 or 3 means no operation, 1 means low level, and 2 means high level. For CNTU software-force events, set register MCPWM_GENn_CNTUFORCE_UPMETHOD to specify the trigger method of CNTU software-force events. Setting all bits to 0 means trigger CNTU software-force events immediately, setting bit 0 to 1 means the TEZ event triggers CNTU software-force events, setting bit 1 to 1 means the TEP event triggers CNTU software-force events, setting bit 2 to 1 means the TEA event triggers CNTU software-force events, setting bit 3 to 1 means the TEB event triggers CNTU software-force events, setting bit 4 to 1 means CNTU software-force events triggered when the PWM timer selected by the PWM generator is synchronized, and setting bit 5 to 1 means the CNTU software-forced events will not be triggered. Configure register MCPWM_GENn_A_CNTUFORCE_MODE or MCPWM_GENn_B_CNTUFORCE_MODE to specify the operation on the PWMxA or PWMxB waveform when the CNTU software-force events occur. Configuring the registers to 0 or 3 means no operation, 1 means low level, and 2 means high level. Figure 36.3-19 shows a waveform of NCI software-force events. NCI events are used to force PWMxA output low. Forcing on PWMxB is disabled in this case. Espressif Systems 1289 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Figure 36.3-19. Example of an NCI Software-Force Event on PWMxA Espressif Systems 1290 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Figure 36.3-20 shows a waveform of CNTU software-force events. TEZ events are selected as triggers for CNTU software-force events. CNTU is used to force the PWMxB output low. Forcing on PWMxA is disabled. Figure 36.3-20. Example of a CNTU Software-Force Event on PWMxB Espressif Systems 1291 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) 36.3.3.2 Dead Time Generator Module Purpose of the Dead Time Generator Module Section 36.3.3.1 introduced several options to generate signals on PWMxA and PWMxB outputs, with a specific placement of signal edges. The required dead time is obtained by altering the edge placement between signals and by setting the signal’s duty cycle. Another option to control the dead time is to use a specialized module – Dead Time Generator. The key functions of the Dead Time Generator module are as follows: • Generating output signal pairs (PWMxA and PWMxB) with a dead time from a common source, which can be either the input signal PWMxA or PWMxB. • Creating a dead time by adding delay to signal edges: – Rising edge delay (RED) – Falling edge delay (FED) • Can generate PWM signal in various format. The typical dead time configurations are: – Active high complementary (AHC) – Active low complementary (ALC) – Active high (AH) – Active low (AL) • This module may also be bypassed, if the dead time is configured directly in the generator module. Shadow Register of Dead Time Generator Delay registers RED and FED are shadowed with registers MCPWM_DTn_RED_CFG_REG and MCPWM_DTn_FED_CFG_REG. When MCPWM_GLOBAL_UP_EN is set to 1, the values saved in the shadow registers can be written to the active register at the specified time. The update method register for MCPWM_DTn_RED_CFG_REG is MCPWM_DBn_RED_UPMETHOD. The update method register for MCPWM_DTn_FED_CFG_REG is MCPWM_DBn_FED_UPMETHOD. The Software can also trigger a globally forced update bit MCPWM_GLOBAL_FORCE_UP which will prompt all registers in the module to be updated according to shadow registers. For the description of shadow registers, please see section 36.3.2.3. Espressif Systems 1292 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Highlights for Operation of the Dead Time Generator Options for setting up the dead time module are shown in Figure 36.3-21. Figure 36.3-21. Options for Setting up the Dead Time Generator Module S0-S8 in the figure above are switches controlled by fields in register MCPWM_DTn_CFG_REG shown in Table 36.3-5. Table 36.3-5. Dead Time Generator Switches Control Fields Switch Field S0 MCPWM_DBn_B_OUTBYPASS S1 MCPWM_DBn_A_OUTBYPASS S2 MCPWM_DBn_RED_OUTINVERT S3 MCPWM_DBn_FED_OUTINVERT S4 MCPWM_DBn_RED_INSEL S5 MCPWM_DBn_FED_INSEL S6 MCPWM_DBn_A_OUTSWAP S7 MCPWM_DBn_B_OUTSWAP S8 MCPWM_DBn_DEB_MODE All switch combinations are supported, but not all of them represent the typical modes of use. Table 36.3-6 documents some typical dead time configurations. In these configurations, the position of S4 and S5 sets PWMxA as the common source of both falling edge delay (FED) and rising edge delay (RED). The modes presented in table 36.3-6 may be categorized as follows: • Mode 1: Bypass delays on both FED and RED In this mode, the dead time module is disabled. Signals of PWMxA and PWMxB pass through without any modifications. • Mode 2-5: Classical Dead Time Polarity Settings Espressif Systems 1293 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) These four modes represent typical configurations of polarity and should cover the active-high/low modes in available industry power switch gate drivers. The typical waveforms are shown in Figures 36.3-22 to 36.3-25. • Modes 6 and 7: Bypass delay on the falling edge (FED) or rising edge (RED) In these two modes, either RED or FED is bypassed. As a result, the corresponding delay is not applied. Table 36.3-6. Typical Dead Time Generator Operating Modes Mode Mode Description S0 S1 S2 S3 1 PWMxA and PWMxB Pass Through/No Delay 1 1 X X 2 Active High Complementary (AHC), see Figure 36.3-22 0 0 0 1 3 Active Low Complementary (ALC), see Figure 36.3-23 0 0 1 0 4 Active High (AH), see Figure 36.3-24 0 0 0 0 5 Active Low (AL), see Figure 36.3-25 0 0 1 1 6 PWMxA Output = PWMxA In (No Delay) 0 1 0 or 1 0 or 1 PWMxB Output = PWMxA Input with Falling Edge Delay 7 PWMxA Output = PWMxA Input with Rising Edge Delay 1 0 0 or 1 0 or 1 PWMxB Output = PWMxB Input with No Delay Note: For all the modes above, the position of the binary switches S4 to S8 is set to 0. Figure 36.3-22. Active High Complementary (AHC) Dead Time Waveforms Espressif Systems 1294 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Figure 36.3-23. Active Low Complementary (ALC) Dead Time Waveforms Figure 36.3-24. Active High (AH) Dead Time Waveforms Espressif Systems 1295 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Figure 36.3-25. Active Low (AL) Dead Time Waveforms RED and FED delays may be set up independently. The delay value is programmed using the 16-bit field MCPWM_DBn_RED and MCPWM_DBn_FED. The register value represents the number of clock (DT_clk) periods by which a signal edge is delayed. DT_clk can be selected from PWM_clk or PT_clk through register MCPWM_DBn_CLK_SEL. To calculate the delay on the falling edge (FED) and rising edge (RED), use the following formulas: F ED = M CP W M _DT n_F ED × T DT _clk RED = M CP W M _DT n_RED × T DT _clk Espressif Systems 1296 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) 36.3.3.3 PWM Carrier Module The coupling of PWM output to a motor driver may need isolation with a transformer. Transformers deliver only AC signals, while the duty cycle of a PWM signal may range anywhere from 0% to 100%. The PWM carrier module passes such a PWM signal through a transformer by using a high frequency carrier to modulate the signal. Function Overview The following key characteristics of this module are configurable: • Carrier frequency • Pulse width of the first pulse • Duty cycle of the second and the subsequent pulses • Enabling/disabling the carrier function Operational Highlights The PWM carrier clock (PC_clk) is derived from PWM_CLK. The frequency and duty cycle are configured by the MCPWM_CHOPPERn_PRESCALE and MCPWM_CHOPPERn_DUTY bits in the MCPWM_CARRIERn_CFG_REG register. The purpose of one-shot pulses is to provide the high-energy impulse to reliably turn on the power switch. Subsequent pulses sustain the power-on status. The width of a one-shot pulse is configurable with the MCPWM_CHOPPERn_OSHTWTH field. Enabling/disabling of the carrier module is done with the MCPWM_CHOPPERn_EN bit. Waveform Examples Figure 36.3-26 shows an example of waveforms, where a carrier is superimposed on original PWM pulses. This figure does not show the first one-shot pulse and the duty-cycle control. Related details are covered in the following two sections. Figure 36.3-26. Example of Waveforms Showing PWM Carrier Action Espressif Systems 1297 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) One-Shot Pulse The width of the first pulse can be configured to 16 different values, which can be calculated by the following equation: T 1stpulse = T P W M _clk × 8 × (MCP W M_CARRIERn_P RESCALE + 1) × (MCP W M_CARRIERn_OSHT W T H + 1) Where: • T P M W _clk is the period of the PWM clock (PWM_clk). • (MCP W M_CARRIERn_OSHT W T H + 1) is the width of the first pulse (whose value ranges from 1 to 16). • (MCP W M_CARRIERn_P RESCALE + 1) is the PWM carrier clock’s (PC_clk) prescaler value. The first one-shot pulse and subsequent sustaining pulses are shown in Figure 36.3-27. Figure 36.3-27. Example of the First Pulse and the Subsequent Sustaining Pulses of the PWM Carrier Submodule Duty Cycle Control After issuing the first one-shot pulse, the remaining PWM signal is modulated according to the carrier frequency. Users can configure the duty cycle of this signal. Tuning of duty may be required, so that the signal passes through the isolating transformer and can still operate (turn on/off) the motor drive, changing rotation speed and direction. The duty cycle may be set to one of seven values, using MCPWM_CHOPPERn_DUTY, or bits [7:5] of register MCPWM_CARRIERn_CFG_REG. Below is the formula for calculating the duty cycle: Duty = MCP W M_CARRIERn_DU T Y ÷ 8 All seven settings of the duty cycle are shown in Figure 36.3-28. Espressif Systems 1298 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Figure 36.3-28. Possible Duty Cycle Settings for Sustaining Pulses in the PWM Carrier Submodule 36.3.3.4 Fault Detection Module Each MCPWM peripheral is connected to three fault signals (FAULT0, FAULT1, and FAULT2) which are sourced from the GPIO matrix. These signals are intended to indicate external fault conditions, and may be preprocessed by the Fault Detection module to generate fault events. Fault events can then execute the user code to control MCPWM outputs in response to specific faults. Function of Fault Detection Module The key actions performed by the fault detection module are: • Forcing outputs PWMxA and PWMxB, upon detected fault, to one of the following states: – High – Low – Toggle – No action taken • Execution of one-shot trip (OST) upon detection of over-current conditions/short circuits. • Cycle-by-cycle trip (CBC) to provide current-limiting operation. • Allocation of either one-shot or cycle-by-cycle operation for each fault signal. • Generation of interrupts for each fault input. • Support for software-force tripping. • Enabling or disabling of module function as required. Espressif Systems 1299 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Operation and Configuration Tips This section provides the operational tips and set-up options for the Fault Detection module. Fault signals coming from pins are sampled and synced in the GPIO matrix. In order to guarantee the successful sampling of fault pulses, each pulse duration must be at least two APB clock cycles. The Fault Detection module will then sample fault signals by using PWM_clk. So, the duration of fault pulses coming from GPIO matrix must be at least one PWM_clk cycle. Differently put, regardless of the period relation between APB clock and PWM_clk, the width of fault signal pulses on pins must be at least equal to the sum of two APB clock cycles and one PWM_clk cycle. Each level of fault signals, FAULT0 to FAULT2, can be used by the Fault Detection module to generate fault events (fault_event0 to fault_event2). Every fault event can be configured individually to provide CBC action, OST action, or none. • Cycle-by-Cycle (CBC) action: When CBC action is triggered, the state of PWMxA and PWMxB will be changed immediately according to the configuration of fields MCPWM_TZn_A_CBC_U/D and MCPWM_TZn_B_CBC_U/D. Different actions can be indicated when the PWM timer is incrementing or decrementing. Different CBC action interrupts can be triggered for different fault events. Status field MCPWM_TZn_CBC_ON indicates whether a CBC action is on or off. When the fault event is no longer present, CBC actions on PWMxA/B will be cleared at a specified point, which is either a D/UTEP or D/UTEZ event. Field MCPWM_TZn_CBCPULSE determines at which event PWMxA and PWMxB will be able to resume normal actions. Therefore, in this mode, the CBC action is cleared or refreshed upon every PWM cycle. • One-Shot (OST) action: When OST action is triggered, the state of PWMxA and PWMxB will be changed immediately, depending on the setting of fields MCPWM_TZn_A_OST_U/D and MCPWM_TZn_B_OST_U/D. Different actions can be configured when PWM timer is incrementing or decrementing. Different OST action interrupts can be triggered from different fault events. Status field MCPWM_TZn_OST_ON indicates whether an OST action is on or off. The OST actions on PWMxA/B are not automatically cleared when the fault event is no longer present. One-shot actions must be cleared manually by setting the MCPWM_TZn_CLR_OST bit. 36.3.4 Capture Module 36.3.4.1 Introduction The capture module contains three complete capture channels. Channel inputs CAP0, CAP1, and CAP2 are sourced from the GPIO matrix. Thanks to the flexibility of the GPIO matrix, CAP0, CAP1, and CAP2 can be configured from any pin input. Multiple capture channels can be sourced from the same pin input, while prescaling for each channel can be set differently. Also, capture channels are sourced from different pins. This provides several options for handling capture signals by hardware in the background, instead of having them processed directly by the CPU. A capture module has the following independent key resources: • One 32-bit timer (counter) which can be synchronized with the PWM timer, another module, or software. • Three capture channels, each equipped with a 32-bit time-stamp and a capture prescaler. • Independent edge polarity (rising/falling edge) selection for any capture channel. • Input capture signal prescaling (from 1 to 256). Espressif Systems 1300 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) • Interrupt capabilities on any of the three capture events. 36.3.4.2 Capture Timer The capture timer is a 32-bit counter incrementing continuously. It is enabled by setting MCPWM_CAP_TIMER_EN to 1. Its operating clock source is MCPWM core clock. When MCPWM_CAP_SYNCI_EN is configured, the counter will be loaded with phase stored in register MCPWM_CAP_TIMER_PHASE_REG at the time of a sync event. Sync events can select from PWM timers sync-out, or PWM module sync-in by configuring MCPWM_CAP_SYNCI_SEL. Sync events can also be generated by setting MCPWM_CAP_SYNC_SW. The capture timer provides timing references for all three capture channels. 36.3.4.3 Capture Channel The capture signal coming to a capture channel will be inverted first, if needed, and then prescaled. Each capture channel has a prescaler register of MCPWM_CAPn_PRESCALE. Finally, specified edges of preprocessed capture signal will trigger capture events. Setting MCPWM_CAPn_EN to enable a capture channel. The capture event occurs at the time selected by the MCPWM_CAPn_MODE. When a capture event occurs, the capture timer’s value is stored in time-stamp register MCPWM_CAP_CHn_REG. Different interrupts can be generated for different capture channels at capture events. The edge that triggers a capture event is recorded in register MCPWM_CAPn_EDGE. The capture event can be also forced by software setting MCPWM_CAPn_SW. 36.3.5 ETM Module 36.3.5.1 Overview The MCPWM peripheral on ESP32-C5 supports the Event Task Matrix (ETM) function, which allows MCPWM’s ETM tasks to be triggered by any peripherals’ ETM events, or MCPWM’s ETM events to trigger any peripherals’ ETM tasks. The capture module, the fault detection module, three timers, and three operators can generate events and respond to tasks independently. This section introduces the ETM tasks and events related to MCPWM. For more information, please refer to Chapter 10 Event Task Matrix (ETM). 36.3.5.2 MCPWM-Related ETM Events When setting enable field to 1, after the generation condition is met, the corresponding event would be generated. For details, please refer to Table 36.3-7 below: Table 36.3-7. MCPWM-Related ETM Events Enable Field Generation Condition Event Generated MCPWM_EVT_CAPn_EN CAPn capture event occurs MCPWM0_EVT_CAPn MCPWM_EVT_TZn_OST_EN PWM operator n performs a One-Shot trip (OST) operation MCPWM0_EVT_TZn_OST MCPWM_EVT_TZn_CBC_EN PWM operator n performs a cycle-by-cycle trip (CBC) operation MCPWM0_EVT_TZn_CBC MCPWM_EVT_Fn_CLR_EN Fault event fault_eventn is cleared MCPWM0_EVT_Fn_CLR MCPWM_EVT_Fn_EN Fault event fault_eventn is generated MCPWM0_EVT_Fn 1 See Section 36.3.3.1 for a detailed description of timer stamp A and B. Espressif Systems 1301 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Enable Field Generation Condition Event Generated MCPWM_EVT_OPn_TEB_EN The count value of the timer that PWM operator n selects is equal to the value of timer stamp B 1 MCPWM0_EVT_OPn_TEB MCPWM_EVT_OPn_TEA_EN The count value of the timer that PWM operator n selects is equal to the value of timer stamp A 1 MCPWM0_EVT_OPn_TEA MCPWM_EVT_OPn_TEE1_EN The count value of the timer that PWM operator n selects is equal to the value of register MCPWM_OPn_TSTMP_E1_REG MCPWM0_EVT_OPn_TEE1 MCPWM_EVT_OPn_TEE2_EN The count value of the timer that PWM operator n selects is equal to the value of register MCPWM_OPn_TSTMP_E2_REG MCPWM0_EVT_OPn_TEE2 MCPWM_EVT_TIMERn_TEP_EN The count value of timer n is equal to the period value MCPWM_TIMERn_PERIOD MCPWM0_EVT_TIMERn_TEP MCPWM_EVT_TIMERn_TEZ_EN The count value of timer n is equal to 0 MCPWM0_EVT_TIMERn_TEZ MCPWM_EVT_TIMERn_STOP_EN Timer n’s count stops MCPWM0_EVT_TIMERn_STOP 1 See Section 36.3.3.1 for a detailed description of timer stamp A and B. 36.3.5.3 MCPWM-Related ETM Tasks When setting the enable field to 1, after inputting valid tasks, the corresponding response operation would be generated. For details, please refer to Table 36.3-8 below: Table 36.3-8. ETM Related Tasks Enable Field Valid Task Input Response Operation MCPWM_TASK_CAPn_EN MCPWM0_TASK_CAPn CAPn channel performs a capture operation MCPWM_TASK_CLRn_OST_EN MCPWM0_TASK_CLRn_OST PWM operator n clears the One-Shot Trip operation MCPWM_TASK_TZn_OST_EN MCPWM0_TASK_TZn_OST PWM operator n performs a One-Shot Trip (OST) operation MCPWM_TASK_TIMERn_PERIOD_UP_EN MCPWM0_TASK_TIMERn_PERIOD_UP The period of timer n is updated to the value configured in the period register MCPWM_TIMERn_PERIOD MCPWM_TASK_TIMERn_SYNC_EN MCPWM0_TASK_TIMERn_SYN Timer n performs a sync operation MCPWM_TASK_GEN_STOP_EN MCPWM0_TASK_GEN_STOP All the timers stop counting and the PWM signals output by all PWM operators remain unchanged Espressif Systems 1302 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Enable Field Valid Task Input Response Operation MCPWM_TASK_CMPRn_B_UP_EN MCPWM0_TASK_CMPRn_B_UP Timer stamp B of the PWM operator n is updated to the value of the shadow register MCPWM_GENn_B MCPWM_TASK_CMPRn_A_UP_EN MCPWM0_TASK_CMPRn_A_UP Timer stamp A of the PWM operator n is updated to the value of the shadow register MCPWM_GENn_A 36.4 Interrupts ESP32-C5’s MCPWM0 can generate the PWM0_INTR interrupt signal. The PWM0_INTR will be sent to the Interrupt Matrix. Interrupt signal PWM0_INTR can be generated by the following internal interrupt sources: • MCPWM_TIMERx_STOP_INT: Triggered when timerx stops. • MCPWM_TIMERx_TEZ_INT: Triggered by the TEZ event of PWM timerx. • MCPWM_TIMERx_TEP_INT: Triggered by the TEP event of PWM timerx. • MCPWM_FAULTx_INT: Triggered when fault_eventx starts. • MCPWM_FAULTx_CLR_INT: Triggered after fault_eventx ends. • MCPWM_CMPRx_TEA_INT: Triggered by the TEA event of PWM operatorx. • MCPWM_CMPRx_TEB_INT: Triggered by the TEB event of PWM operatorx. • MCPWM_TZx_CBC_INT: Triggered by the CBC action of PWMx. • MCPWM_TZx_OST_INT: Triggered by the OST action of PWMx. • MCPWM_CAPx_INT: Triggered by the capture event on channelx. The above interrupt sources can only be triggered when the interrupt enable register interrupt_source_name_ENA is set to 1. Write 1 to interrupt_source_name_CLR will clear the interrupt. Note: For definitions of interrupt, interrupt signal, interrupt source, and their correlations, please refer to Chapter 9 Interrupt Matrix > Section 9.2 Terminology. Each interrupt source can be configured by a common set of registers that are described in Section Interrupt Configuration Registers. The specific registers can be found in Section 36.5 Register Summary. Espressif Systems 1303 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) 36.5 Register Summary The addresses in this section are relative to Motor Control PWM base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Prescaler Configuration MCPWM_CLK_CFG_REG PWM clock prescaler register 0x0000 R/W MCPWM Timer 0 Configuration and Status MCPWM_TIMER0_CFG0_REG PWM timer0 period and update method config- uration register 0x0004 R/W MCPWM_TIMER0_CFG1_REG PWM timer0 working mode and start/stop con- trol configuration register 0x0008 varies MCPWM_TIMER0_SYNC_REG PWM timer0 sync function configuration register 0x000C R/W MCPWM_TIMER0_STATUS_REG PWM timer0 status register 0x0010 RO MCPWM Timer 1 Configuration and Status MCPWM_TIMER1_CFG0_REG PWM timer1 period and update method config- uration register 0x0014 R/W MCPWM_TIMER1_CFG1_REG PWM timer1 working mode and start/stop con- trol configuration register 0x0018 varies MCPWM_TIMER1_SYNC_REG PWM timer1 sync function configuration register 0x001C R/W MCPWM_TIMER1_STATUS_REG PWM timer1 status register 0x0020 RO MCPWM Timer 2 Configuration and status MCPWM_TIMER2_CFG0_REG PWM timer2 period and update method config- uration register 0x0024 R/W MCPWM_TIMER2_CFG1_REG PWM timer2 working mode and start/stop con- trol configuration register 0x0028 varies MCPWM_TIMER2_SYNC_REG PWM timer2 sync function configuration register 0x002C R/W MCPWM_TIMER2_STATUS_REG PWM timer2 status register 0x0030 RO Common Configuration for MCPWM Timers MCPWM_TIMER_SYNCI_CFG_REG Synchronization input selection for three PWM timers 0x0034 R/W MCPWM_OPERATOR_TIMERSEL_REG Select specific timer for PWM operators 0x0038 R/W MCPWM Operator 0 Configuration and Status MCPWM_GEN0_STMP_CFG_REG Transfer status and update method for time stamp registers A and B 0x003C varies MCPWM_GEN0_TSTMP_A_REG Shadow register for register A 0x0040 R/W MCPWM_GEN0_TSTMP_B_REG Shadow register for register B 0x0044 R/W MCPWM_GEN0_CFG0_REG Fault event T0 and T1 handling 0x0048 R/W MCPWM_GEN0_FORCE_REG Permissives to force PWM0A and PWM0B out- puts by software 0x004C R/W MCPWM_GEN0_A_REG Actions triggered by events on PWM0A 0x0050 R/W MCPWM_GEN0_B_REG Actions triggered by events on PWM0B 0x0054 R/W Espressif Systems 1304 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Name Description Address Access MCPWM_DT0_CFG_REG Dead time type selection and configuration 0x0058 R/W MCPWM_DT0_FED_CFG_REG Shadow register for falling edge delay (FED) 0x005C R/W MCPWM_DT0_RED_CFG_REG Shadow register for rising edge delay (RED) 0x0060 R/W MCPWM_CARRIER0_CFG_REG Carrier enable and configuration 0x0064 R/W MCPWM_FH0_CFG0_REG Actions on PWM0A and PWM0B trip events 0x0068 R/W MCPWM_FH0_CFG1_REG Software triggers for fault handler actions 0x006C R/W MCPWM_FH0_STATUS_REG Status of fault events 0x0070 RO MCPWM Operator 1 Configuration and Status MCPWM_GEN1_STMP_CFG_REG Transfer status and update method for time stamp registers A and B 0x0074 varies MCPWM_GEN1_TSTMP_A_REG Shadow register for register A 0x0078 R/W MCPWM_GEN1_TSTMP_B_REG Shadow register for register B 0x007C R/W MCPWM_GEN1_CFG0_REG Fault event T0 and T1 handling 0x0080 R/W MCPWM_GEN1_FORCE_REG Permissives to force PWM1A and PWM1B out- puts by software 0x0084 R/W MCPWM_GEN1_A_REG Actions triggered by events on PWM1A 0x0088 R/W MCPWM_GEN1_B_REG Actions triggered by events on PWM1B 0x008C R/W MCPWM_DT1_CFG_REG Dead time type selection and configuration 0x0090 R/W MCPWM_DT1_FED_CFG_REG Shadow register for falling edge delay (FED) 0x0094 R/W MCPWM_DT1_RED_CFG_REG Shadow register for rising edge delay (RED) 0x0098 R/W MCPWM_CARRIER1_CFG_REG Carrier enable and configuration 0x009C R/W MCPWM_FH1_CFG0_REG Actions on PWM1A and PWM1B trip events 0x00A0 R/W MCPWM_FH1_CFG1_REG Software triggers for fault handler actions 0x00A4 R/W MCPWM_FH1_STATUS_REG Status of fault events 0x00A8 RO MCPWM Operator 2 Configuration and Status MCPWM_GEN2_STMP_CFG_REG Transfer status and update method for time stamp registers A and B 0x00AC varies MCPWM_GEN2_TSTMP_A_REG Shadow register for register A 0x00B0 R/W MCPWM_GEN2_TSTMP_B_REG Shadow register for register B 0x00B4 R/W MCPWM_GEN2_CFG0_REG Fault event T0 and T1 handling 0x00B8 R/W MCPWM_GEN2_FORCE_REG Permissives to force PWM2A and PWM2B out- puts by software 0x00BC R/W MCPWM_GEN2_A_REG Actions triggered by events on PWM2A 0x00C0 R/W MCPWM_GEN2_B_REG Actions triggered by events on PWM2B 0x00C4 R/W MCPWM_DT2_CFG_REG Dead time type selection and configuration 0x00C8 R/W MCPWM_DT2_FED_CFG_REG Shadow register for falling edge delay (FED) 0x00CC R/W MCPWM_DT2_RED_CFG_REG Shadow register for rising edge delay (RED) 0x00D0 R/W MCPWM_CARRIER2_CFG_REG Carrier enable and configuration 0x00D4 R/W MCPWM_FH2_CFG0_REG Actions on PWM2A and PWM2B trip events 0x00D8 R/W MCPWM_FH2_CFG1_REG Software triggers for fault handler actions 0x00DC R/W MCPWM_FH2_STATUS_REG Status of fault events 0x00E0 RO Fault Detection Configuration and Status MCPWM_FAULT_DETECT_REG Fault detection configuration and status 0x00E4 varies Espressif Systems 1305 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Name Description Address Access Capture Configuration and Status MCPWM_CAP_TIMER_CFG_REG Configure capture timer 0x00E8 varies MCPWM_CAP_TIMER_PHASE_REG Phase for capture timer sync 0x00EC R/W MCPWM_CAP_CH0_CFG_REG Capture channel 0 configuration and enable 0x00F0 varies MCPWM_CAP_CH1_CFG_REG Capture channel 1 configuration and enable 0x00F4 varies MCPWM_CAP_CH2_CFG_REG Capture channel 2 configuration and enable 0x00F8 varies MCPWM_CAP_CH0_REG ch0 capture value status register 0x00FC RO MCPWM_CAP_CH1_REG ch1 capture value status register 0x0100 RO MCPWM_CAP_CH2_REG ch2 capture value status register 0x0104 RO MCPWM_CAP_STATUS_REG Edge of last capture trigger 0x0108 RO Enable Update of Active Registers MCPWM_UPDATE_CFG_REG Enable update 0x010C R/W Manage Interrupts MCPWM_INT_ENA_REG Interrupt enable bits 0x0110 R/W MCPWM_INT_RAW_REG Raw interrupt status 0x0114 R/WTC /SS MCPWM_INT_ST_REG Masked interrupt status 0x0118 RO MCPWM_INT_CLR_REG Interrupt clear bits 0x011C WT MCPWM Event Enable Registers MCPWM_EVT_EN_REG MCPWM event enable register 0x0120 R/W MCPWM_EVT_EN2_REG MCWM event enable register2 0x0128 R/W MCPWM Task Enable Register MCPWM_TASK_EN_REG MCPWM task enable register 0x0124 R/W MCPWM Generator Configuration Registers MCPWM_OP0_TSTMP_E1_REG Generator0 time stamp E1 value configuration register 0x012C R/W MCPWM_OP0_TSTMP_E2_REG Generator0 time stamp E2 value configuration register 0x0130 R/W MCPWM_OP1_TSTMP_E1_REG Generator1 time stamp E1 value configuration register 0x0134 R/W MCPWM_OP1_TSTMP_E2_REG Generator1 time stamp E2 value configuration register 0x0138 R/W MCPWM_OP2_TSTMP_E1_REG Generator2 time stamp E1 value configuration register 0x013C R/W MCPWM_OP2_TSTMP_E2_REG Generator2 time stamp E2 value configuration register 0x0140 R/W MCPWM APB Configuration Register MCPWM_CLK_REG MCPWM APB configuration register 0x0144 R/W Version Register MCPWM_VERSION_REG Version control register 0x0148 R/W Espressif Systems 1306 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) 36.6 Registers The addresses in this section are relative to Motor Control PWM base address provided in Table 4.3-2 in Chapter 4 System and Memory. For how to program reserved fields, please refer to Section Programming Reserved Register Field. Register 36.1. MCPWM_CLK_CFG_REG (0x0000) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 MCPWM_CLK_PRESCALE 0x0 7 0 Reset MCPWM_CLK_PRESCALE Configures the prescaler value of the clock, so that the period of PWM_clk = 6.25 ns * (PWM_CLK_PRESCALE + 1). (R/W) Register 36.2. MCPWM_TIMERn_CFG0_REG (n: 0-2) (0x0004+0x10*n) (reserved) 0 0 0 0 0 0 31 26 MCPWM_TIMERn_PERIOD_UPMETHOD 0 25 24 MCPWM_TIMERn_PERIOD 0xff 23 8 MCPWM_TIMERn_PRESCALE 0x0 7 0 Reset MCPWM_TIMERn_PRESCALE Configures the prescaler value of timern, so that the period of PT0_clk = Period of PWM_clk * (PWM_TIMERn_PRESCALE + 1). (R/W) MCPWM_TIMERn_PERIOD Configures the period shadow of PWM timern. (R/W) MCPWM_TIMERn_PERIOD_UPMETHOD Configures the update method for active register of PWM timern period. 0: Immediate 1: TEZ 2: Sync 3: TEZ or sync TEZ here and below means timer equals zero event. (R/W) Espressif Systems 1307 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.3. MCPWM_TIMERn_CFG1_REG(n: 0-2) (0x0008+0x10*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 5 MCPWM_TIMERn_MOD 0x0 4 3 MCPWM_TIMERn_START 0x0 2 0 Reset MCPWM_TIMERn_START Configures conditions to start/stop PWM timern. 0: If PWM timer0 starts, then stops at TEZ 1: If timer0 starts, then stops at TEP 2: PWM timer0 starts and runs on 3: Timer0 starts and stops at the next TEZ 4: Timer0 starts and stops at the next TEP 5: Invalid. No effect 6: Invalid. No effect 7: Invalid. No effect TEP here and below means the event that happens when the timer equals to period. (R/W/SC) MCPWM_TIMERn_MOD Configures the working mode of PWM timern. 0: Freeze 1: Increase mode 2: Decrease mode 3: Up-down mode (R/W) Espressif Systems 1308 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.4. MCPWM_TIMERn_SYNC_REG (n: 0-2) (0x000C+0x10*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 31 21 MCPWM_TIMERn_PHASE_DIRECTION 0 20 MCPWM_TIMERn_PHASE 0 19 4 MCPWM_TIMERn_SYNCO_SEL 0 3 2 MCPWM_TIMERn_SYNC_SW 0 1 MCPWM_TIMERn_SYNCI_EN 0 0 Reset MCPWM_TIMERn_SYNCI_EN Configures whether to enable timern reloading with phase on sync input event. 0: Disable 1: Enable (R/W) MCPWM_TIMERn_SYNC_SW Configures whether to trigger a software sync. 0: No effect 1: Trigger a software sync (R/W) MCPWM_TIMERn_SYNCO_SEL Configures PWM timern sync out selection. 0: sync_in. The sync out will always generate when toggling the MCPWM_TIMERn_SYNC_SW bit. 1: TEZ 2: TEP 3: No effect (R/W) MCPWM_TIMERn_PHASE Configures the phase for timern reload on sync event. (R/W) MCPWM_TIMERn_PHASE_DIRECTION Configures the PWM timern’s direction when timern mode is up-down mode. 0: Increase 1: Decrease (R/W) Espressif Systems 1309 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.5. MCPWM_TIMERn_STATUS_REG(n: 0-2) (0x0010+0x10*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 17 MCPWM_TIMERn_DIRECTION 0 16 MCPWM_TIMERn_VALUE 0 15 0 Reset MCPWM_TIMERn_VALUE Represents current PWM timern counter value. (RO) MCPWM_TIMERn_DIRECTION Represents current PWM timern counter direction. 0: Increment 1: Decrement (RO) Register 36.6. MCPWM_TIMER_SYNCI_CFG_REG (0x0034) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 12 MCPWM_EXTERNAL_SYNCI2_INVERT 0 11 MCPWM_EXTERNAL_SYNCI1_INVERT 0 10 MCPWM_EXTERNAL_SYNCI0_INVERT 0 9 MCPWM_TIMER2_SYNCISEL 0 8 6 MCPWM_TIMER1_SYNCISEL 0 5 3 MCPWM_TIMER0_SYNCISEL 0 2 0 Reset MCPWM_TIMERn_SYNCISEL Configures sync input for PWM timern. 1: PWM timer0 sync out 2: PWM timer1 sync out 3: PWM timer2 sync out 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix Other values: no sync input selected (R/W) MCPWM_EXTERNAL_SYNCIn_INVERT Configures whether to invert SYNCn from GPIO matrix. 0: Not invert 1: Invert (R/W) Espressif Systems 1310 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.7. MCPWM_OPERATOR_TIMERSEL_REG (0x0038) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 6 MCPWM_OPERATOR2_TIMERSEL 0 5 4 MCPWM_OPERATOR1_TIMERSEL 0 3 2 MCPWM_OPERATOR0_TIMERSEL 0 1 0 Reset MCPWM_OPERATORn_TIMERSEL Configures which PWM timer will be the timing reference for PWM operatorn. 0: timer0 1: timer1 2: timer2 3: Invalid, will select timer2 (R/W) Espressif Systems 1311 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.8. MCPWM_GENn_STMP_CFG_REG (n: 0-2) (0x003C+0x38*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 10 MCPWM_CMPRn_B_SHDW_FULL 0 9 MCPWM_CMPRn_A_SHDW_FULL 0 8 MCPWM_CMPRn_B_UPMETHOD 0 7 4 MCPWM_CMPRn_A_UPMETHOD 0 3 0 Reset MCPWM_CMPRn_A_UPMETHOD Configures the update method for PWM generatorn time stamp A’s active register. When all bits are set to 0: Immediately When bit0 is set to 1: TEZ When bit1 is set to 1: TEP When bit2 is set to 1: Sync When bit3 is set to 1: Disable the update (R/W) MCPWM_CMPRn_B_UPMETHOD Configures the update method for PWM generatorn time stamp B’s active register. When all bits are set to 0: Immediately When bit0 is set to 1: TEZ When bit1 is set to 1: TEP When bit2 is set to 1: Sync When bit3 is set to 1: Disable the update (R/W) MCPWM_CMPRn_A_SHDW_FULL Configures whether the value in the shadow register is written to the corresponding active register at a specific time. This field is set and reset by hardware. 0: Write the latest value in the shadow register to A’s active register 1: Write the value to the PWM generatorn time stamp A’s shadow register, and wait to be transferred to A’s active register (R/SC/WTC) MCPWM_CMPRn_B_SHDW_FULL Configures whether the value in the shadow register is written to the corresponding active register at a specific time. This field is set and reset by hardware. 0: Write the latest value in the shadow register to B’s active register 1: Write the value to the PWM generatorn time stamp B’s shadow register, and wait to be trans- ferred to B’s active register (R/SC/WTC) Espressif Systems 1312 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.9. MCPWM_GENn_TSTMP_A_REG(n: 0-2) (0x0040+0x38*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 MCPWM_CMPRn_A 0 15 0 Reset MCPWM_CMPRn_A Configures the value of PWM generator n time stamp A’s shadow register. (R/W) Register 36.10. MCPWM_GENn_TSTMP_B_REG(n: 0-2) (0x0044+0x38*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 MCPWM_CMPRn_B 0 15 0 Reset MCPWM_CMPRn_B Configures the value of PWM generator n time stamp B’s shadow register. (R/W) Espressif Systems 1313 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.11. MCPWM_GENn_CFG0_REG(n: 0-2) (0x0048+0x38*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 10 MCPWM_GENn_T1_SEL 0 9 7 MCPWM_GENn_T0_SEL 0 6 4 MCPWM_GENn_CFG_UPMETHOD 0 3 0 Reset MCPWM_GENn_CFG_UPMETHOD Configures the update method for PWM generatorn’s active register. When all bits are set to 0: Immediately When bit0 is set to 1: TEZ When bit1 is set to 1: TEP When bit2 is set to 1: Sync When bit3 is set to 1: Disable the update (R/W) MCPWM_GENn_T0_SEL Configures source selection for PWM generatorn event_t0, take effect im- mediately. 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: Invalid, selects nothing (R/W) MCPWM_GENn_T1_SEL Configures source selection for PWM generatorn event_t1, take effect im- mediately. 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: Invalid, selects nothing (R/W) Espressif Systems 1314 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.12. MCPWM_GENn_FORCE_REG(n: 0-2) (0x004C+0x38*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 MCPWM_GENn_B_NCIFORCE_MODE 0 15 14 MCPWM_GENn_B_NCIFORCE 0 13 MCPWM_GENn_A_NCIFORCE_MODE 0 12 11 MCPWM_GENn_A_NCIFORCE 0 10 MCPWM_GENn_B_CNTUFORCE_MODE 0 9 8 MCPWM_GENn_A_CNTUFORCE_MODE 0 7 6 MCPWM_GENn_CNTUFORCE_UPMETHOD 0x20 5 0 Reset MCPWM_GENn_CNTUFORCE_UPMETHOD Configures the update method for continuous soft- ware force of PWM generatorn. When all bits are set to 0: Immediately When bit0 is set to 1: TEZ When bit1 is set to 1: TEP When bit2 is set to 1: TEA When bit3 is set to 1: TEB When bit4 is set to 1: Sync When bit5 is set to 1: Disable update TEA/B means an event generated when the timer’s value equals to that of register A/B. (R/W) MCPWM_GENn_A_CNTUFORCE_MODE Configures the continuous software force mode for PWMn A. 0: Disabled 1: Low 2: High 3: Disabled (R/W) MCPWM_GENn_B_CNTUFORCE_MODE Configures the continuous software force mode for PWMn B. 0: Disabled 1: Low 2: High 3: Disabled (R/W) MCPWM_GENn_A_NCIFORCE Configures whether to trigger the non-continuous immediate software-force event for PWMn A. 0: Invalid 1: Trigger a force event (R/W) Continued on the next page... Espressif Systems 1315 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.12. MCPWM_GENn_FORCE_REG(n: 0-2) (0x004C+0x38*n) Continued from the previous page... MCPWM_GENn_A_NCIFORCE_MODE Configures non-continuous immediate software force mode for PWMn A. 0: Disabled 1: Low 2: High 3: Disabled (R/W) MCPWM_GENn_B_NCIFORCE Configures whether to trigger the non-continuous immediate software-force event for PWMn B. 0: Invalid 1: Trigger a force event (R/W) MCPWM_GENn_B_NCIFORCE_MODE Configures non-continuous immediate software force mode for PWMn B. 0: Disabled 1: Low 2: High 3: Disabled (R/W) Espressif Systems 1316 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.13. MCPWM_GENn_A_REG(n: 0-2) (0x0050+0x38*n) (reserved) 0 0 0 0 0 0 0 0 31 24 MCPWM_GENn_A_DT1 0 23 22 MCPWM_GENn_A_DT0 0 21 20 MCPWM_GENn_A_DTEB 0 19 18 MCPWM_GENn_A_DTEA 0 17 16 MCPWM_GENn_A_DTEP 0 15 14 MCPWM_GENn_A_DTEZ 0 13 12 MCPWM_GENn_A_UT1 0 11 10 MCPWM_GENn_A_UT0 0 9 8 MCPWM_GENn_A_UTEB 0 7 6 MCPWM_GENn_A_UTEA 0 5 4 MCPWM_GENn_A_UTEP 0 3 2 MCPWM_GENn_A_UTEZ 0 1 0 Reset MCPWM_GENn_A_UTEZ Configures action on PWMn A triggered by event TEZ when timer increas- ing. 0: No change 1: Low 2: High 3: Toggle (R/W) MCPWM_GENn_A_UTEP Configures action on PWMn A triggered by event TEP when timer increas- ing. 0: No change 1: Low 2: High 3: Toggle (R/W) MCPWM_GENn_A_UTEA Configures action on PWMn A triggered by event TEA when timer increas- ing. 0: No change 1: Low 2: High 3: Toggle (R/W) MCPWM_GENn_A_UTEB Configures action on PWMn A triggered by event TEB when timer increas- ing. 0: No change 1: Low 2: High 3: Toggle (R/W) Continued on the next page... Espressif Systems 1317 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.13. MCPWM_GENn_A_REG(n: 0-2) (0x0050+0x38*n) Continued from the previous page... MCPWM_GENn_A_UT0 Configures action on PWMn A triggered by event_t0 when timer increasing. 0: No change 1: Low 2: High 3: Toggle (R/W) MCPWM_GENn_A_UT1 Configures action on PWMn A triggered by event_t1 when timer increasing. 0: No change 1: Low 2: High 3: Toggle (R/W) MCPWM_GENn_A_DTEZ Configures action on PWMn A triggered by event TEZ when timer decreas- ing. 0: No change 1: Low 2: High 3: Toggle (R/W) MCPWM_GENn_A_DTEP Configures action on PWMn A triggered by event TEP when timer decreas- ing. 0: No change 1: Low 2: High 3: Toggle (R/W) MCPWM_GENn_A_DTEA Configures action on PWMn A triggered by event TEA when timer decreas- ing. 0: No change 1: Low 2: High 3: Toggle (R/W) Continued on the next page... Espressif Systems 1318 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.13. MCPWM_GENn_A_REG(n: 0-2) (0x0050+0x38*n) Continued from the previous page... MCPWM_GENn_A_DTEB Configures action on PWMn A triggered by event TEB when timer de- creasing. 0: No change 1: Low 2: High 3: Toggle (R/W) MCPWM_GENn_A_DT0 Configures action on PWMn A triggered by event_t0 when timer decreasing. 0: No change 1: Low 2: High 3: Toggle (R/W) MCPWM_GENn_A_DT1 Configures action on PWMn A triggered by event_t1 when timer decreasing. 0: No change 1: Low 2: High 3: Toggle (R/W) Espressif Systems 1319 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.14. MCPWM_GENn_B_REG(n: 0-2) (0x0054+0x38*n) (reserved) 0 0 0 0 0 0 0 0 31 24 MCPWM_GENn_B_DT1 0 23 22 MCPWM_GENn_B_DT0 0 21 20 MCPWM_GENn_B_DTEB 0 19 18 MCPWM_GENn_B_DTEA 0 17 16 MCPWM_GENn_B_DTEP 0 15 14 MCPWM_GENn_B_DTEZ 0 13 12 MCPWM_GENn_B_UT1 0 11 10 MCPWM_GENn_B_UT0 0 9 8 MCPWM_GENn_B_UTEB 0 7 6 MCPWM_GENn_B_UTEA 0 5 4 MCPWM_GENn_B_UTEP 0 3 2 MCPWM_GENn_B_UTEZ 0 1 0 Reset MCPWM_GENn_B_UTEZ Configures action on PWMn B triggered by event TEZ when timer increas- ing. 0: No change 1: Low 2: High 3: Toggle (R/W) MCPWM_GENn_B_UTEP Configures action on PWMn B triggered by event TEP when timer increas- ing. 0: No change 1: Low 2: High 3: Toggle (R/W) MCPWM_GENn_B_UTEA Configures action on PWMn B triggered by event TEA when timer increas- ing. 0: No change 1: Low 2: High 3: Toggle (R/W) MCPWM_GENn_B_UTEB Configures action on PWMn B triggered by event TEB when timer increas- ing. 0: No change 1: Low 2: High 3: Toggle (R/W) MCPWM_GENn_B_UT0 Configures action on PWMn B triggered by event_t0 when timer increasing. 0: No change 1: Low 2: High 3: Toggle (R/W) Continued on the next page... Espressif Systems 1320 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.14. MCPWM_GENn_B_REG(n: 0-2) (0x0054+0x38*n) Continued from the previous page... MCPWM_GENn_B_UT1 Configures action on PWMn B triggered by event_t1 when timer increasing. 0: No change 1: Low 2: High 3: Toggle (R/W) MCPWM_GENn_B_DTEZ Configures action on PWMn B triggered by event TEZ when timer decreas- ing. 0: No change 1: Low 2: High 3: Toggle (R/W) MCPWM_GENn_B_DTEP Configures action on PWMn B triggered by event TEP when timer de- creasing. 0: No change 1: Low 2: High 3: Toggle (R/W) MCPWM_GENn_B_DTEA Configures action on PWMn B triggered by event TEA when timer de- creasing. 0: No change 1: Low 2: High 3: Toggle (R/W) MCPWM_GENn_B_DTEB Configures action on PWMn B triggered by event TEB when timer de- creasing. 0: No change 1: Low 2: High 3: Toggle (R/W) Continued on the next page... Espressif Systems 1321 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.14. MCPWM_GENn_B_REG(n: 0-2) (0x0054+0x38*n) Continued from the previous page... MCPWM_GENn_B_DT0 Configures action on PWMn B triggered by event_t0 when timer decreasing. 0: No change 1: Low 2: High 3: Toggle (R/W) MCPWM_GENn_B_DT1 Configures action on PWMn B triggered by event_t1 when timer decreasing. 0: No change 1: Low 2: High 3: Toggle (R/W) Espressif Systems 1322 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.15. MCPWM_DTn_CFG_REG(n: 0-2) (0x0058+0x38*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 18 MCPWM_DBn_CLK_SEL 0 17 MCPWM_DBn_B_OUTBYPASS 1 16 MCPWM_DBn_A_OUTBYPASS 1 15 MCPWM_DBn_FED_OUTINVERT 0 14 MCPWM_DBn_RED_OUTINVERT 0 13 MCPWM_DBn_FED_INSEL 0 12 MCPWM_DBn_RED_INSEL 0 11 MCPWM_DBn_B_OUTSWAP 0 10 MCPWM_DBn_A_OUTSWAP 0 9 MCPWM_DBn_DEB_MODE 0 8 MCPWM_DBn_RED_UPMETHOD 0 7 4 MCPWM_DBn_FED_UPMETHOD 0 3 0 Reset MCPWM_DBn_FED_UPMETHOD Configures the update method for FED (Falling edge delay) active register. 0: Immediate Bit0 is set to 1: TEZ Bit1 is set to 1: TEP Bit2 is set to 1: Sync Bit3 is set to 1: Disable the update (R/W) MCPWM_DBn_RED_UPMETHOD Configures the update method for RED (Rising edge delay) active register. 0: Immediate Bit0 is set to 1: TEZ Bit1 is set to 1: TEP Bit2 is set to 1: Sync Bit3 is set to 1: Disable the update (R/W) MCPWM_DBn_DEB_MODE Configures the S8 switch in Table 36.3-5. 0: FED/RED take effect on different paths separately 1: FED/RED take effect on B path, A out is in bypass or dulpB mode (R/W) MCPWM_DBn_A_OUTSWAP Configures the S6 switch in Table 36.3-5. For typical configurations, please refer to Table 36.3-6. (R/W) MCPWM_DBn_B_OUTSWAP Configures the S7 switch in Table 36.3-5. For typical configurations, please refer to Table 36.3-6. (R/W) MCPWM_DBn_RED_INSEL Configures the S4 switch in Table 36.3-5. For typical configurations, please refer to Table 36.3-6. (R/W) MCPWM_DBn_FED_INSEL Configures the S5 switch in Table 36.3-5. For typical configurations, please refer to Table 36.3-6. (R/W) MCPWM_DBn_RED_OUTINVERT Configures the S2 switch in Table 36.3-5. For typical configura- tions, please refer to Table 36.3-6. (R/W) Continued on the next page... Espressif Systems 1323 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.15. MCPWM_DTn_CFG_REG(n: 0-2) (0x0058+0x38*n) Continued from the previous page... MCPWM_DBn_FED_OUTINVERT Configures the S3 switch in Table 36.3-5. For typical configura- tions, please refer to Table 36.3-6. (R/W) MCPWM_DBn_A_OUTBYPASS Configures the S1 switch in Table 36.3-5. For typical configurations, please refer to Table 36.3-6. (R/W) MCPWM_DBn_B_OUTBYPASS Configures the S0 switch in Table 36.3-5. For typical configurations, please refer to Table 36.3-6. (R/W) MCPWM_DBn_CLK_SEL Configures dead time generator n clock selection. 0: PWM_CLK 1: PT_CLK (R/W) Register 36.16. MCPWM_DTn_FED_CFG_REG(n: 0-2) (0x005C+0x38*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 MCPWM_DBn_FED 0 15 0 Reset MCPWM_DBn_FED Configures the shadow register for FED. (R/W) Register 36.17. MCPWM_DTn_RED_CFG_REG(n: 0-2) (0x0060+0x38*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 MCPWM_DBn_RED 0 15 0 Reset MCPWM_DBn_RED Configures the shadow register for RED. (R/W) Espressif Systems 1324 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.18. MCPWM_CARRIERn_CFG_REG(n: 0-2) (0x0064+0x38*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 14 MCPWM_CHOPPERn_IN_INVERT 0 13 MCPWM_CHOPPERn_OUT_INVERT 0 12 MCPWM_CHOPPERn_OSHTWTH 0 11 8 MCPWM_CHOPPERn_DUTY 0 7 5 MCPWM_CHOPPERn_PRESCALE 0 4 1 MCPWM_CHOPPERn_EN 0 0 Reset MCPWM_CHOPPERn_EN Configures whether to enable carriern. 0: Bypassed 1: Enabled (R/W) MCPWM_CHOPPERn_PRESCALE Configures the prescale value of PWM carriern clock (PC_clk), so that period of PC_clk = period of PWM_clk * (PWM_CARRIERn_PRESCALE + 1). (R/W) MCPWM_CHOPPERn_DUTY Configures carrier duty. Duty = PWM_CARRIERn_DUTY / 8. (R/W) MCPWM_CHOPPERn_OSHTWTH Configures width of the first pulse. Measurement unit: Periods of the carrier. (R/W) MCPWM_CHOPPERn_OUT_INVERT Configures whether to invert the output of PWMn A and PWMn B for this submodule. 0: Normal 1: Invert (R/W) MCPWM_CHOPPERn_IN_INVERT Configures whether to invert the input of PWMn A and PWMn B for this submodule. 0: Normal 1: Invert (R/W) Espressif Systems 1325 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.19. MCPWM_FHn_CFG0_REG(n: 0-2) (0x0068+0x38*n) (reserved) 0 0 0 0 0 0 0 0 31 24 MCPWM_TZn_B_OST_U 0 23 22 MCPWM_TZn_B_OST_D 0 21 20 MCPWM_TZn_B_CBC_U 0 19 18 MCPWM_TZn_B_CBC_D 0 17 16 MCPWM_TZn_A_OST_U 0 15 14 MCPWM_TZn_A_OST_D 0 13 12 MCPWM_TZn_A_CBC_U 0 11 10 MCPWM_TZn_A_CBC_D 0 9 8 MCPWM_TZn_Fn_OST 0 7 MCPWM_TZn_F1_OST 0 6 MCPWM_TZn_F2_OST 0 5 MCPWM_TZn_SW_OST 0 4 MCPWM_TZn_F0_CBC 0 3 MCPWM_TZn_F1_CBC 0 2 MCPWM_TZn_F2_CBC 0 1 MCPWM_TZn_SW_CBC 0 0 Reset MCPWM_TZn_SW_CBC Configures whether to enable software force cycle-by-cycle mode action. 0: Disable 1: Enable (R/W) MCPWM_TZn_F2_CBC Configures whether event_f2 will trigger cycle-by-cycle mode action. 0: Disable 1: Enable (R/W) MCPWM_TZn_F1_CBC Configures whether event_f1 will trigger cycle-by-cycle mode action. 0: Disable 1: Enable (R/W) MCPWM_TZn_F0_CBC Configures whether event_f0 will trigger cycle-by-cycle mode action. 0: Disable 1: Enable (R/W) MCPWM_TZn_SW_OST Configures whether to enable software force one-shot mode action. 0: Disable 1: Enable (R/W) MCPWM_TZn_F2_OST Configures whether event_f2 will trigger one-shot mode action. 0: Disable 1: Enable (R/W) MCPWM_TZn_F1_OST Configures whether event_f1 will trigger one-shot mode action. 0: Disable 1: Enable (R/W) MCPWM_TZn_Fn_OST Configures whether event_f0 will trigger one-shot mode action. 0: Disable 1: Enable (R/W) Continued on the next page... Espressif Systems 1326 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.19. MCPWM_FHn_CFG0_REG(n: 0-2) (0x0068+0x38*n) Continued from the previous page... MCPWM_TZn_A_CBC_D Configures cycle-by-cycle mode action on PWMn A when fault event oc- curs and timer is decreasing. 0: Do nothing 1: Force low 2: Force high 3: Toggle (R/W) MCPWM_TZn_A_CBC_U Configures cycle-by-cycle mode action on PWMn A when fault event oc- curs and timer is increasing. 0: Do nothing 1: Force low 2: Force high 3: Toggle (R/W) MCPWM_TZn_A_OST_D Configures one-shot mode action on PWMn A when fault event occurs and timer is decreasing. 0: Do nothing 1: Force low 2: Force high 3: Toggle (R/W) MCPWM_TZn_A_OST_U Configures one-shot mode action on PWMn A when fault event occurs and timer is increasing. 0: Do nothing 1: Force low 2: Force high 3: Toggle (R/W) MCPWM_TZn_B_CBC_D Configures cycle-by-cycle mode action on PWMn B when fault event oc- curs and timer is decreasing. 0: Do nothing 1: Force low 2: Force high 3: Toggle (R/W) Continued on the next page... Espressif Systems 1327 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.19. MCPWM_FHn_CFG0_REG(n: 0-2) (0x0068+0x38*n) Continued from the previous page... MCPWM_TZn_B_CBC_U Configures cycle-by-cycle mode action on PWMn B when fault event oc- curs and timer is increasing. 0: Do nothing 1: Force low 2: Force high 3: Toggle (R/W) MCPWM_TZn_B_OST_D Configures one-shot mode action on PWMn B when fault event occurs and timer is decreasing. 0: Do nothing 1: Force low 2: Force high 3: Toggle (R/W) MCPWM_TZn_B_OST_U Configures one-shot mode action on PWMn B when fault event occurs and timer is increasing. 0: Do nothing 1: Force low 2: Force high 3: Toggle (R/W) Espressif Systems 1328 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.20. MCPWM_FHn_CFG1_REG(n: 0-2) (0x006C+0x38*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 5 MCPWM_TZn_FORCE_OST 0 4 MCPWM_TZn_FORCE_CBC 0 3 MCPWM_TZn_CBCPULSE 0 2 1 MCPWM_TZn_CLR_OST 0 0 Reset MCPWM_TZn_CLR_OST Configures whether to generate a one-shot mode action clear by software. 0: No effect 1: Triggers a clear for ongoing one-shot mode action by software (R/W) MCPWM_TZn_CBCPULSE Configures the refresh moment selection of cycle-by-cycle mode action. 0: Select nothing, will not refresh Bit0 is set to 1: TEZ Bit1 is set to 1: TEP (R/W) MCPWM_TZn_FORCE_CBC Configures whether to generate a software cycle-by-cycle mode ac- tion. 0: No effect 1: Triggers a cycle-by-cycle mode action by software (R/W) MCPWM_TZn_FORCE_OST Configures whether to generate a software one-shot mode action. 0: No effect 1: Triggers a one-shot mode action by software (R/W) Espressif Systems 1329 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.21. MCPWM_FHn_STATUS_REG(n: 0-2) (0x0070+0x38*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 2 MCPWM_TZn_OST_ON 0 1 MCPWM_TZn_CBC_ON 0 0 Reset MCPWM_TZn_CBC_ON Represents whether an cycle-by-cycle mode action is on going. 0: No action 1: Ongoing (RO) MCPWM_TZn_OST_ON Represents whether a one-shot mode action is ongoing. 0: No action 1: Ongoing (RO) Register 36.22. MCPWM_FAULT_DETECT_REG (0x00E4) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 9 MCPWM_EVENT_F2 0 8 MCPWM_EVENT_F1 0 7 MCPWM_EVENT_F0 0 6 MCPWM_F2_POLE 0 5 MCPWM_F1_POLE 0 4 MCPWM_F0_POLE 0 3 MCPWM_F2_EN 0 2 MCPWM_F1_EN 0 1 MCPWM_F0_EN 0 0 Reset MCPWM_Fn_EN Configures whether to enable event_fn generation. 0: Disable 1: Enable (R/W) MCPWM_Fn_POLE Configures event_fn trigger polarity on FAULTn source from GPIO matrix. 0: Level low 1: Level high (R/W) MCPWM_EVENT_Fn Represents whether an event_fn is ongoing. This field is set and reset by hard- ware. 0: No action 1: Ongoing (RO) Espressif Systems 1330 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.23. MCPWM_CAP_TIMER_CFG_REG (0x00E8) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 6 MCPWM_CAP_SYNC_SW 0 5 MCPWM_CAP_SYNCI_SEL 0 4 2 MCPWM_CAP_SYNCI_EN 0 1 MCPWM_CAP_TIMER_EN 0 0 Reset MCPWM_CAP_TIMER_EN Configures whether to enable capture timer increment incrementing un- der APB_CLK. 0: Disable 1: Enable (R/W) MCPWM_CAP_SYNCI_EN Configures whether to enable capture timer sync. 0: Disable 1: Enable (R/W) MCPWM_CAP_SYNCI_SEL Configures the selection of capture module sync input. 0: None 1: Timer0 sync_out 2: Timer1 sync_out 3: Timer2 sync_out 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix 7: None (R/W) MCPWM_CAP_SYNC_SW When MCPWM_CAP_SYNCI_EN is set to 1, configures whether to trig- ger a capture timer sync so that capture timer is loaded with value in phase register. 0: No effect 1: Trigger a capture timer sync (WT) Espressif Systems 1331 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.24. MCPWM_CAP_TIMER_PHASE_REG (0x00EC) MCPWM_CAP_PHASE 0 31 0 Reset MCPWM_CAP_PHASE Configures phase value for capture timer sync operation. (R/W) Register 36.25. MCPWM_CAP_CHn_CFG_REG (n: 0-2) (0x00F0+0x4*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 13 MCPWM_CAPn_SW 0 12 MCPWM_CAPn_IN_INVERT 0 11 MCPWM_CAPn_PRESCALE 0 10 3 MCPWM_CAPn_MODE 0 2 1 MCPWM_CAPn_EN 0 0 Reset MCPWM_CAPn_EN Configures whether to enable capture on channel n. 0: Disable 1: Enable (R/W) MCPWM_CAPn_MODE Configures the edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable capture on the falling edge. When bit1 is set to 1: enable capture on the rising edge. (R/W) MCPWM_CAPn_PRESCALE Configures the prescale value on the rising edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + 1. (R/W) MCPWM_CAPn_IN_INVERT Configures whether to invert CAPn from GPIO matrix before prescale. 0: Normal 1: Invert (R/W) MCPWM_CAPn_SW Configures whether to trigger a software-forced capture on channel 0. 0: Not trigger 1: Trigger (WT) Espressif Systems 1332 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.26. MCPWM_CAP_CHn_REG (n: 0-2) (0x00FC+0x4*n) MCPWM_CAPn_VALUE 0 31 0 Reset MCPWM_CAPn_VALUE Represents value of last capture on CAPn. (RO) Register 36.27. MCPWM_CAP_STATUS_REG (0x0108) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 MCPWM_CAP2_EDGE 0 2 MCPWM_CAP1_EDGE 0 1 MCPWM_CAP0_EDGE 0 0 Reset MCPWM_CAPn_EDGE Represents the edge of the last capture trigger on channel n. 0: Rising edge 1: Falling edge (RO) Espressif Systems 1333 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.28. MCPWM_UPDATE_CFG_REG (0x010C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 8 MCPWM_OP2_FORCE_UP 0 7 MCPWM_OP2_UP_EN 1 6 MCPWM_OP1_FORCE_UP 0 5 MCPWM_OP1_UP_EN 1 4 MCPWM_OP0_FORCE_UP 0 3 MCPWM_OP0_UP_EN 1 2 MCPWM_GLOBAL_FORCE_UP 0 1 MCPWM_GLOBAL_UP_EN 1 0 Reset MCPWM_GLOBAL_UP_EN Configures whether to globally update all active registers. 0: No effect 1: Update all active registers globally (R/W) MCPWM_GLOBAL_FORCE_UP Configures whether to trigger a forced update of all active registers globally. 0: No effect 1: Trigger a forced update (R/W) MCPWM_OP0_UP_EN Configures whether to update active registers in PWM operator 0 when MCPWM_GLOBAL_UP_EN is set to 1. 0: No effect 1: Update active registers in PWM operator 0 (R/W) MCPWM_OP0_FORCE_UP Configures whether to trigger a forced update of active registers in PWM operator 0. 0: No effect 1: Trigger a forced update (R/W) MCPWM_OP1_UP_EN Configures whether to update active registers in PWM operator 1 when MCPWM_GLOBAL_UP_EN is set to 1. 0: No effect 1: Update active registers in PWM operator 1 (R/W) Continued on the next page... Espressif Systems 1334 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.28. MCPWM_UPDATE_CFG_REG (0x010C) Continued from the previous page... MCPWM_OP1_FORCE_UP Configures whether to trigger a forced update of active registers in PWM operator 1. 0: No effect 1: Trigger a forced update (R/W) MCPWM_OP2_UP_EN Configures whether to update active registers in PWM operator 2 when MCPWM_GLOBAL_UP_EN is set to 1. 0: No effect 1: Update active registers in PWM operator 2 (R/W) MCPWM_OP2_FORCE_UP Configures whether to trigger a forced update of active registers in PWM operator 2. 0: No effect 1: Trigger a forced update (R/W) Espressif Systems 1335 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.29. MCPWM_INT_ENA_REG (0x0110) (reserved) 0 0 31 30 MCPWM_CAP2_INT_ENA 0 29 MCPWM_CAP1_INT_ENA 0 28 MCPWM_CAP0_INT_ENA 0 27 MCPWM_TZ2_OST_INT_ENA 0 26 MCPWM_TZ1_OST_INT_ENA 0 25 MCPWM_TZ0_OST_INT_ENA 0 24 MCPWM_TZ2_CBC_INT_ENA 0 23 MCPWM_TZ1_CBC_INT_ENA 0 22 MCPWM_TZ0_CBC_INT_ENA 0 21 MCPWM_CMPR2_TEB_INT_ENA 0 20 MCPWM_CMPR1_TEB_INT_ENA 0 19 MCPWM_CMPR0_TEB_INT_ENA 0 18 MCPWM_CMPR2_TEA_INT_ENA 0 17 MCPWM_CMPR1_TEA_INT_ENA 0 16 MCPWM_CMPR0_TEA_INT_ENA 0 15 MCPWM_FAULT2_CLR_INT_ENA 0 14 MCPWM_FAULT1_CLR_INT_ENA 0 13 MCPWM_FAULT0_CLR_INT_ENA 0 12 MCPWM_FAULT2_INT_ENA 0 11 MCPWM_FAULT1_INT_ENA 0 10 MCPWM_FAULT0_INT_ENA 0 9 MCPWM_TIMER2_TEP_INT_ENA 0 8 MCPWM_TIMER1_TEP_INT_ENA 0 7 MCPWM_TIMER0_TEP_INT_ENA 0 6 MCPWM_TIMER2_TEZ_INT_ENA 0 5 MCPWM_TIMER1_TEZ_INT_ENA 0 4 MCPWM_TIMER0_TEZ_INT_ENA 0 3 MCPWM_TIMER2_STOP_INT_ENA 0 2 MCPWM_TIMER1_STOP_INT_ENA 0 1 MCPWM_TIMER0_STOP_INT_ENA 0 0 Reset MCPWM_TIMER0_STOP_INT_ENA Write 1 to enable MCPWM_TIMER0_STOP_INT. (R/W) MCPWM_TIMER1_STOP_INT_ENA Write 1 to enable MCPWM_TIMER1_STOP_INT. (R/W) MCPWM_TIMER2_STOP_INT_ENA Write 1 to enable MCPWM_TIMER2_STOP_INT. (R/W) MCPWM_TIMER0_TEZ_INT_ENA Write 1 to enable MCPWM_TIMER0_TEZ_INT. (R/W) MCPWM_TIMER1_TEZ_INT_ENA Write 1 to enable MCPWM_TIMER1_TEZ_INT. (R/W) MCPWM_TIMER2_TEZ_INT_ENA Write 1 to enable MCPWM_TIMER2_TEZ_INT. (R/W) MCPWM_TIMER0_TEP_INT_ENA Write 1 to enable MCPWM_TIMER0_TEP_INT. (R/W) MCPWM_TIMER1_TEP_INT_ENA Write 1 to enable MCPWM_TIMER1_TEP_INT. (R/W) MCPWM_TIMER2_TEP_INT_ENA Write 1 to enable MCPWM_TIMER2_TEP_INT. (R/W) MCPWM_FAULT0_INT_ENA Write 1 to enable MCPWM_FAULT0_INT. (R/W) MCPWM_FAULT1_INT_ENA Write 1 to enable MCPWM_FAULT1_INT. (R/W) MCPWM_FAULT2_INT_ENA Write 1 to enable MCPWM_FAULT2_INT. (R/W) MCPWM_FAULT0_CLR_INT_ENA Write 1 to enable MCPWM_FAULT0_CLR_INT. (R/W) MCPWM_FAULT1_CLR_INT_ENA Write 1 to enable MCPWM_FAULT1_CLR_INT. (R/W) MCPWM_FAULT2_CLR_INT_ENA Write 1 to enable MCPWM_FAULT2_CLR_INT. (R/W) MCPWM_CMPR0_TEA_INT_ENA Write 1 to enable MCPWM_CMPR0_TEA_INT. (R/W) MCPWM_CMPR1_TEA_INT_ENA Write 1 to enable MCPWM_CMPR1_TEA_INT. (R/W) MCPWM_CMPR2_TEA_INT_ENA Write 1 to enable MCPWM_CMPR2_TEA_INT. (R/W) MCPWM_CMPR0_TEB_INT_ENA Write 1 to enable MCPWM_CMPR0_TEB_INT. (R/W) MCPWM_CMPR1_TEB_INT_ENA Write 1 to enable MCPWM_CMPR1_TEB_INT. (R/W) MCPWM_CMPR2_TEB_INT_ENA Write 1 to enable MCPWM_CMPR2_TEB_INT. (R/W) MCPWM_TZ0_CBC_INT_ENA Write 1 to enable MCPWM_TZ0_CBC_INT. (R/W) Continued on the next page... Espressif Systems 1336 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.29. MCPWM_INT_ENA_REG (0x0110) Continued from the previous page... MCPWM_TZ1_CBC_INT_ENA Write 1 to enable MCPWM_TZ1_CBC_INT. (R/W) MCPWM_TZ2_CBC_INT_ENA Write 1 to enable MCPWM_TZ2_CBC_INT. (R/W) MCPWM_TZ0_OST_INT_ENA Write 1 to enable MCPWM_TZ0_OST_INT. (R/W) MCPWM_TZ1_OST_INT_ENA Write 1 to enable MCPWM_TZ1_OST_INT. (R/W) MCPWM_TZ2_OST_INT_ENA Write 1 to enable MCPWM_TZ2_OST_INT. (R/W) MCPWM_CAP0_INT_ENA Write 1 to enable MCPWM_CAP0_INT. (R/W) MCPWM_CAP1_INT_ENA Write 1 to enable MCPWM_CAP1_INT. (R/W) MCPWM_CAP2_INT_ENA Write 1 to enable MCPWM_CAP2_INT. (R/W) Espressif Systems 1337 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.30. MCPWM_INT_RAW_REG (0x0114) (reserved) 0 0 31 30 MCPWM_CAP2_INT_RAW 0 29 MCPWM_CAP1_INT_RAW 0 28 MCPWM_CAP0_INT_RAW 0 27 MCPWM_TZ2_OST_INT_RAW 0 26 MCPWM_TZ1_OST_INT_RAW 0 25 MCPWM_TZ0_OST_INT_RAW 0 24 MCPWM_TZ2_CBC_INT_RAW 0 23 MCPWM_TZ1_CBC_INT_RAW 0 22 MCPWM_TZ0_CBC_INT_RAW 0 21 MCPWM_CMPR2_TEB_INT_RAW 0 20 MCPWM_CMPR1_TEB_INT_RAW 0 19 MCPWM_CMPR0_TEB_INT_RAW 0 18 MCPWM_CMPR2_TEA_INT_RAW 0 17 MCPWM_CMPR1_TEA_INT_RAW 0 16 MCPWM_CMPR0_TEA_INT_RAW 0 15 MCPWM_FAULT2_CLR_INT_RAW 0 14 MCPWM_FAULT1_CLR_INT_RAW 0 13 MCPWM_FAULT0_CLR_INT_RAW 0 12 MCPWM_FAULT2_INT_RAW 0 11 MCPWM_FAULT1_INT_RAW 0 10 MCPWM_FAULT0_INT_RAW 0 9 MCPWM_TIMER2_TEP_INT_RAW 0 8 MCPWM_TIMER1_TEP_INT_RAW 0 7 MCPWM_TIMER0_TEP_INT_RAW 0 6 MCPWM_TIMER2_TEZ_INT_RAW 0 5 MCPWM_TIMER1_TEZ_INT_RAW 0 4 MCPWM_TIMER0_TEZ_INT_RAW 0 3 MCPWM_TIMER2_STOP_INT_RAW 0 2 MCPWM_TIMER1_STOP_INT_RAW 0 1 MCPWM_TIMER0_STOP_INT_RAW 0 0 Reset MCPWM_TIMER0_STOP_INT_RAW Represents the raw status of MCPWM_TIMER0_STOP_INT. (R/WTC/SS) MCPWM_TIMER1_STOP_INT_RAW Represents the raw status of MCPWM_TIMER1_STOP_INT. (R/WTC/SS) MCPWM_TIMER2_STOP_INT_RAW Represents the raw status of MCPWM_TIMER2_STOP_INT. (R/WTC/SS) MCPWM_TIMER0_TEZ_INT_RAW Represents the raw status of MCPWM_TIMER0_TEZ_INT. (R/WTC/SS) MCPWM_TIMER1_TEZ_INT_RAW Represents the raw status of MCPWM_TIMER1_TEZ_INT. (R/WTC/SS) MCPWM_TIMER2_TEZ_INT_RAW Represents the raw status of MCPWM_TIMER2_TEZ_INT. (R/WTC/SS) MCPWM_TIMER0_TEP_INT_RAW Represents the raw status of MCPWM_TIMER0_TEP_INT. (R/WTC/SS) MCPWM_TIMER1_TEP_INT_RAW Represents the raw status of MCPWM_TIMER1_TEP_INT. (R/WTC/SS) MCPWM_TIMER2_TEP_INT_RAW Represents the raw status of MCPWM_TIMER2_TEP_INT. (R/WTC/SS) MCPWM_FAULT0_INT_RAW Represents the raw status of MCPWM_FAULT0_INT. (R/WTC/SS) MCPWM_FAULT1_INT_RAW Represents the raw status of MCPWM_FAULT1_INT. (R/WTC/SS) MCPWM_FAULT2_INT_RAW Represents the raw status of MCPWM_FAULT2_INT. (R/WTC/SS) MCPWM_FAULT0_CLR_INT_RAW Represents the raw status of MCPWM_FAULT0_CLR_INT. (R/WTC/SS) MCPWM_FAULT1_CLR_INT_RAW Represents the raw status of MCPWM_FAULT1_CLR_INT. (R/WTC/SS) Continued on the next page... Espressif Systems 1338 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.30. MCPWM_INT_RAW_REG (0x0114) Continued from the previous page... MCPWM_FAULT2_CLR_INT_RAW Represents the raw status of MCPWM_FAULT2_CLR_INT. (R/WTC/SS) MCPWM_CMPR0_TEA_INT_RAW Represents the raw status of MCPWM_CMPR0_TEA_INT. (R/WTC/SS) MCPWM_CMPR1_TEA_INT_RAW Represents the raw status of MCPWM_CMPR1_TEA_INT. (R/WTC/SS) MCPWM_CMPR2_TEA_INT_RAW Represents the raw status of MCPWM_CMPR2_TEA_INT. (R/WTC/SS) MCPWM_CMPR0_TEB_INT_RAW Represents the raw status of MCPWM_CMPR0_TEB_INT. (R/WTC/SS) MCPWM_CMPR1_TEB_INT_RAW Represents the raw status of MCPWM_CMPR1_TEB_INT. (R/WTC/SS) MCPWM_CMPR2_TEB_INT_RAW Represents the raw status of MCPWM_CMPR2_TEB_INT. (R/WTC/SS) MCPWM_TZ0_CBC_INT_RAW Represents the raw status of MCPWM_TZ0_CBC_INT. (R/WTC/SS) MCPWM_TZ1_CBC_INT_RAW Represents the raw status of MCPWM_TZ1_CBC_INT. (R/WTC/SS) MCPWM_TZ2_CBC_INT_RAW Represents the raw status of MCPWM_TZ2_CBC_INT. (R/WTC/SS) MCPWM_TZ0_OST_INT_RAW Represents the raw status of MCPWM_TZ0_OST_INT. (R/WTC/SS) MCPWM_TZ1_OST_INT_RAW Represents the raw status of MCPWM_TZ1_OST_INT. (R/WTC/SS) MCPWM_TZ2_OST_INT_RAW Represents the raw status of MCPWM_TZ2_OST_INT. (R/WTC/SS) MCPWM_CAP0_INT_RAW Represents the raw status of MCPWM_CAP0_INT. (R/WTC/SS) MCPWM_CAP1_INT_RAW Represents the raw status of MCPWM_CAP1_INT. (R/WTC/SS) MCPWM_CAP2_INT_RAW Represents the raw status of MCPWM_CAP2_INT. (R/WTC/SS) Espressif Systems 1339 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.31. MCPWM_INT_ST_REG (0x0118) (reserved) 0 0 31 30 MCPWM_CAP2_INT_ST 0 29 MCPWM_CAP1_INT_ST 0 28 MCPWM_CAP0_INT_ST 0 27 MCPWM_TZ2_OST_INT_ST 0 26 MCPWM_TZ1_OST_INT_ST 0 25 MCPWM_TZ0_OST_INT_ST 0 24 MCPWM_TZ2_CBC_INT_ST 0 23 MCPWM_TZ1_CBC_INT_ST 0 22 MCPWM_TZ0_CBC_INT_ST 0 21 MCPWM_CMPR2_TEB_INT_ST 0 20 MCPWM_CMPR1_TEB_INT_ST 0 19 MCPWM_CMPR0_TEB_INT_ST 0 18 MCPWM_CMPR2_TEA_INT_ST 0 17 MCPWM_CMPR1_TEA_INT_ST 0 16 MCPWM_CMPR0_TEA_INT_ST 0 15 MCPWM_FAULT2_CLR_INT_ST 0 14 MCPWM_FAULT1_CLR_INT_ST 0 13 MCPWM_FAULT0_CLR_INT_ST 0 12 MCPWM_FAULT2_INT_ST 0 11 MCPWM_FAULT1_INT_ST 0 10 MCPWM_FAULT0_INT_ST 0 9 MCPWM_TIMER2_TEP_INT_ST 0 8 MCPWM_TIMER1_TEP_INT_ST 0 7 MCPWM_TIMER0_TEP_INT_ST 0 6 MCPWM_TIMER2_TEZ_INT_ST 0 5 MCPWM_TIMER1_TEZ_INT_ST 0 4 MCPWM_TIMER0_TEZ_INT_ST 0 3 MCPWM_TIMER2_STOP_INT_ST 0 2 MCPWM_TIMER1_STOP_INT_ST 0 1 MCPWM_TIMER0_STOP_INT_ST 0 0 Reset MCPWM_TIMER0_STOP_INT_ST Represents the masked status of MCPWM_TIMER0_STOP_INT. (RO) MCPWM_TIMER1_STOP_INT_ST Represents the masked status of MCPWM_TIMER1_STOP_INT. (RO) MCPWM_TIMER2_STOP_INT_ST Represents the masked status of MCPWM_TIMER2_STOP_INT. (RO) MCPWM_TIMER0_TEZ_INT_ST Represents the masked status of MCPWM_TIMER0_TEZ_INT. (RO) MCPWM_TIMER1_TEZ_INT_ST Represents the masked status of MCPWM_TIMER1_TEZ_INT. (RO) MCPWM_TIMER2_TEZ_INT_ST Represents the masked status of MCPWM_TIMER2_TEZ_INT. (RO) MCPWM_TIMER0_TEP_INT_ST Represents the masked status of MCPWM_TIMER0_TEP_INT. (RO) MCPWM_TIMER1_TEP_INT_ST Represents the masked status of MCPWM_TIMER1_TEP_INT. (RO) MCPWM_TIMER2_TEP_INT_ST Represents the masked status of MCPWM_TIMER2_TEP_INT. (RO) MCPWM_FAULT0_INT_ST Represents the masked status of MCPWM_FAULT0_INT. (RO) MCPWM_FAULT1_INT_ST Represents the masked status of MCPWM_FAULT1_INT. (RO) MCPWM_FAULT2_INT_ST Represents the masked status of MCPWM_FAULT2_INT. (RO) MCPWM_FAULT0_CLR_INT_ST Represents the masked status of MCPWM_FAULT0_CLR_INT. (RO) MCPWM_FAULT1_CLR_INT_ST Represents the masked status of MCPWM_FAULT1_CLR_INT. (RO) Continued on the next page... Espressif Systems 1340 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.31. MCPWM_INT_ST_REG (0x0118) Continued from the previous page... MCPWM_FAULT2_CLR_INT_ST Represents the masked status of MCPWM_FAULT2_CLR_INT. (RO) MCPWM_CMPR0_TEA_INT_ST Represents the masked status of MCPWM_CMPR0_TEA_INT. (RO) MCPWM_CMPR1_TEA_INT_ST Represents the masked status of MCPWM_CMPR1_TEA_INT. (RO) MCPWM_CMPR2_TEA_INT_ST Represents the masked status of MCPWM_CMPR2_TEA_INT. (RO) MCPWM_CMPR0_TEB_INT_ST Represents the masked status of MCPWM_CMPR0_TEB_INT. (RO) MCPWM_CMPR1_TEB_INT_ST Represents the masked status of MCPWM_CMPR1_TEB_INT. (RO) MCPWM_CMPR2_TEB_INT_ST Represents the masked status of MCPWM_CMPR2_TEB_INT. (RO) MCPWM_TZ0_CBC_INT_ST Represents the masked status of MCPWM_TZ0_CBC_INT_ST. (RO) MCPWM_TZ1_CBC_INT_ST Represents the masked status of MCPWM_TZ1_CBC_INT_ST. (RO) MCPWM_TZ2_CBC_INT_ST Represents the masked status of MCPWM_TZ2_CBC_INT_ST. (RO) MCPWM_TZ0_OST_INT_ST Represents the masked status of MCPWM_TZ0_OST_INT. (RO) MCPWM_TZ1_OST_INT_ST Represents the masked status of MCPWM_TZ1_OST_INT. (RO) MCPWM_TZ2_OST_INT_ST Represents the masked status of MCPWM_TZ2_OST_INT. (RO) MCPWM_CAP0_INT_ST Represents the masked status of MCPWM_CAP0_INT. (RO) MCPWM_CAP1_INT_ST Represents the masked status of MCPWM_CAP1_INT. (RO) MCPWM_CAP2_INT_ST Represents the masked status of MCPWM_CAP2_INT. (RO) Espressif Systems 1341 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.32. MCPWM_INT_CLR_REG (0x011C) (reserved) 0 0 31 30 MCPWM_CAP2_INT_CLR 0 29 MCPWM_CAP1_INT_CLR 0 28 MCPWM_CAP0_INT_CLR 0 27 MCPWM_TZ2_OST_INT_CLR 0 26 MCPWM_TZ1_OST_INT_CLR 0 25 MCPWM_TZ0_OST_INT_CLR 0 24 MCPWM_TZ2_CBC_INT_CLR 0 23 MCPWM_TZ1_CBC_INT_CLR 0 22 MCPWM_TZ0_CBC_INT_CLR 0 21 MCPWM_CMPR2_TEB_INT_CLR 0 20 MCPWM_CMPR1_TEB_INT_CLR 0 19 MCPWM_CMPR0_TEB_INT_CLR 0 18 MCPWM_CMPR2_TEA_INT_CLR 0 17 MCPWM_CMPR1_TEA_INT_CLR 0 16 MCPWM_CMPR0_TEA_INT_CLR 0 15 MCPWM_FAULT2_CLR_INT_CLR 0 14 MCPWM_FAULT1_CLR_INT_CLR 0 13 MCPWM_FAULT0_CLR_INT_CLR 0 12 MCPWM_FAULT2_INT_CLR 0 11 MCPWM_FAULT1_INT_CLR 0 10 MCPWM_FAULT0_INT_CLR 0 9 MCPWM_TIMER2_TEP_INT_CLR 0 8 MCPWM_TIMER1_TEP_INT_CLR 0 7 MCPWM_TIMER0_TEP_INT_CLR 0 6 MCPWM_TIMER2_TEZ_INT_CLR 0 5 MCPWM_TIMER1_TEZ_INT_CLR 0 4 MCPWM_TIMER0_TEZ_INT_CLR 0 3 MCPWM_TIMER2_STOP_INT_CLR 0 2 MCPWM_TIMER1_STOP_INT_CLR 0 1 MCPWM_TIMER0_STOP_INT_CLR 0 0 Reset MCPWM_TIMER0_STOP_INT_CLR Write 1 to clear MCPWM_TIMER0_STOP_INT. (WT) MCPWM_TIMER1_STOP_INT_CLR Write 1 to clear MCPWM_TIMER1_STOP_INT. (WT) MCPWM_TIMER2_STOP_INT_CLR Write 1 to clear MCPWM_TIMER2_STOP_INT. (WT) MCPWM_TIMER0_TEZ_INT_CLR Write 1 to clear MCPWM_TIMER0_TEZ_INT. (WT) MCPWM_TIMER1_TEZ_INT_CLR Write 1 to clear MCPWM_TIMER1_TEZ_INT. (WT) MCPWM_TIMER2_TEZ_INT_CLR Write 1 to clear MCPWM_TIMER2_TEZ_INT. (WT) MCPWM_TIMER0_TEP_INT_CLR Write 1 to clear MCPWM_TIMER0_TEP_INT. (WT) MCPWM_TIMER1_TEP_INT_CLR Write 1 to clear MCPWM_TIMER1_TEP_INT. (WT) MCPWM_TIMER2_TEP_INT_CLR Write 1 to clear MCPWM_TIMER2_TEP_INT. (WT) MCPWM_FAULT0_INT_CLR Write 1 to clear MCPWM_FAULT0_INT. (WT) MCPWM_FAULT1_INT_CLR Write 1 to clear MCPWM_FAULT1_INT. (WT) MCPWM_FAULT2_INT_CLR Write 1 to clear MCPWM_FAULT2_INT. (WT) MCPWM_FAULT0_CLR_INT_CLR Write 1 to clear MCPWM_FAULT0_CLR_INT. (WT) MCPWM_FAULT1_CLR_INT_CLR Write 1 to clear MCPWM_FAULT1_CLR_INT. (WT) MCPWM_FAULT2_CLR_INT_CLR Write 1 to clear MCPWM_FAULT2_CLR_INT. (WT) MCPWM_CMPR0_TEA_INT_CLR Write 1 to clear MCPWM_CMPR0_TEA_INT. (WT) MCPWM_CMPR1_TEA_INT_CLR Write 1 to clear MCPWM_CMPR1_TEA_INT. (WT) MCPWM_CMPR2_TEA_INT_CLR Write 1 to clear MCPWM_CMPR2_TEA_INT. (WT) MCPWM_CMPR0_TEB_INT_CLR Write 1 to clear MCPWM_CMPR0_TEB_INT. (WT) MCPWM_CMPR1_TEB_INT_CLR Write 1 to clear MCPWM_CMPR1_TEB_INT. (WT) MCPWM_CMPR2_TEB_INT_CLR Write 1 to clear MCPWM_CMPR2_TEB_INT. (WT) MCPWM_TZ0_CBC_INT_CLR Write 1 to clear MCPWM_TZ0_CBC_INT. (WT) Continued on the next page... Espressif Systems 1342 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.32. MCPWM_INT_CLR_REG (0x011C) Continued from the previous page... MCPWM_TZ1_CBC_INT_CLR Write 1 to clear MCPWM_TZ1_CBC_INT. (WT) MCPWM_TZ2_CBC_INT_CLR Write 1 to clear MCPWM_TZ2_CBC_INT. (WT) MCPWM_TZ0_OST_INT_CLR Write 1 to clear MCPWM_TZ0_OST_INT. (WT) MCPWM_TZ1_OST_INT_CLR Write 1 to clear MCPWM_TZ1_OST_INT. (WT) MCPWM_TZ2_OST_INT_CLR Write 1 to clear MCPWM_TZ2_OST_INT. (WT) MCPWM_CAP0_INT_CLR Write 1 to clear MCPWM_CAP0_INT. (WT) MCPWM_CAP1_INT_CLR Write 1 to clear MCPWM_CAP1_INT. (WT) MCPWM_CAP2_INT_CLR Write 1 to clear MCPWM_CAP2_INT. (WT) Espressif Systems 1343 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.33. MCPWM_EVT_EN_REG (0x0120) (reserved) 0 0 31 30 MCPWM_EVT_CAP2_EN 0 29 MCPWM_EVT_CAP1_EN 0 28 MCPWM_EVT_CAP0_EN 0 27 MCPWM_EVT_TZ2_OST_EN 0 26 MCPWM_EVT_TZ1_OST_EN 0 25 MCPWM_EVT_TZ0_OST_EN 0 24 MCPWM_EVT_TZ2_CBC_EN 0 23 MCPWM_EVT_TZ1_CBC_EN 0 22 MCPWM_EVT_TZ0_CBC_EN 0 21 MCPWM_EVT_F2_CLR_EN 0 20 MCPWM_EVT_F1_CLR_EN 0 19 MCPWM_EVT_F0_CLR_EN 0 18 MCPWM_EVT_F2_EN 0 17 MCPWM_EVT_F1_EN 0 16 MCPWM_EVT_F0_EN 0 15 MCPWM_EVT_OP2_TEB_EN 0 14 MCPWM_EVT_OP1_TEB_EN 0 13 MCPWM_EVT_OP0_TEB_EN 0 12 MCPWM_EVT_OP2_TEA_EN 0 11 MCPWM_EVT_OP1_TEA_EN 0 10 MCPWM_EVT_OP0_TEA_EN 0 9 MCPWM_EVT_TIMER2_TEP_EN 0 8 MCPWM_EVT_TIMER1_TEP_EN 0 7 MCPWM_EVT_TIMER0_TEP_EN 0 6 MCPWM_EVT_TIMER2_TEZ_EN 0 5 MCPWM_EVT_TIMER1_TEZ_EN 0 4 MCPWM_EVT_TIMER0_TEZ_EN 0 3 MCPWM_EVT_TIMER2_STOP_EN 0 2 MCPWM_EVT_TIMER1_STOP_EN 0 1 MCPWM_EVT_TIMER0_STOP_EN 0 0 Reset MCPWM_EVT_TIMER0_STOP_EN Configures whether to enable timer0 stop event generation. 0: Disable 1: Enable (R/W) MCPWM_EVT_TIMER1_STOP_EN Configures whether to enable timer1 stop event generation. 0: Disable 1: Enable (R/W) MCPWM_EVT_TIMER2_STOP_EN Configures whether to enable timer2 stop event generation. 0: Disable 1: Enable (R/W) MCPWM_EVT_TIMER0_TEZ_EN Configures whether to enable timer0 equal zero event generation. 0: Disable 1: Enable (R/W) MCPWM_EVT_TIMER1_TEZ_EN Configures whether to enable timer1 equal zero event generation. 0: Disable 1: Enable (R/W) MCPWM_EVT_TIMER2_TEZ_EN Configures whether to enable timer2 equal zero event generation. 0: Disable 1: Enable (R/W) Continued on the next page... Espressif Systems 1344 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.33. MCPWM_EVT_EN_REG (0x0120) Continued from the previous page... MCPWM_EVT_TIMER0_TEP_EN Configures whether to enable timer0 equal period event genera- tion. 0: Disable 1: Enable (R/W) MCPWM_EVT_TIMER1_TEP_EN Configures whether to enable timer1 equal period event genera- tion. 0: Disable 1: Enable (R/W) MCPWM_EVT_TIMER2_TEP_EN Configures whether to enable timer2 equal period event genera- tion. 0: Disable 1: Enable (R/W) MCPWM_EVT_OP0_TEA_EN Configures whether to enable PWM generator0 timer equal A event generation. 0: Disable 1: Enable (R/W) MCPWM_EVT_OP1_TEA_EN Configures whether to enable PWM generator1 timer equal A event generation. 0: Disable 1: Enable (R/W) MCPWM_EVT_OP2_TEA_EN Configures whether to enable PWM generator2 timer equal A event generation. 0: Disable 1: Enable (R/W) MCPWM_EVT_OP0_TEB_EN Configures whether to enable PWM generator0 timer equal B event generation. 0: Disable 1: Enable (R/W) Continued on the next page... Espressif Systems 1345 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.33. MCPWM_EVT_EN_REG (0x0120) Continued from the previous page... MCPWM_EVT_OP1_TEB_EN Configures whether to enable PWM generator1 timer equal B event generation. 0: Disable 1: Enable (R/W) MCPWM_EVT_OP2_TEB_EN Configures whether to enable PWM generator2 timer equal B event generation. 0: Disable 1: Enable (R/W) MCPWM_EVT_F0_EN Configures whether to enable FAULT0 event generation. 0: Disable 1: Enable (R/W) MCPWM_EVT_F1_EN Configures whether to enable FAULT1 event generation. 0: Disable 1: Enable (R/W) MCPWM_EVT_F2_EN Configures whether to enable FAULT2 event generation. 0: Disable 1: Enable (R/W) MCPWM_EVT_F0_CLR_EN Configures whether to enable FAULT0 clear event generation. 0: Disable 1: Enable (R/W) MCPWM_EVT_F1_CLR_EN Configures whether to enable FAULT1 clear event generation. 0: Disable 1: Enable (R/W) MCPWM_EVT_F2_CLR_EN Configures whether to enable FAULT2 clear event generation. 0: Disable 1: Enable (R/W) Continued on the next page... Espressif Systems 1346 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.33. MCPWM_EVT_EN_REG (0x0120) Continued from the previous page... MCPWM_EVT_TZ0_CBC_EN Configures whether to enable cycle by cycle trip0 event generation. 0: Disable 1: Enable (R/W) MCPWM_EVT_TZ1_CBC_EN Configures whether to enable cycle by cycle trip1 event generation. 0: Disable 1: Enable (R/W) MCPWM_EVT_TZ2_CBC_EN Configures whether to enable cycle by cycle trip2 event generation. 0: Disable 1: Enable (R/W) MCPWM_EVT_TZ0_OST_EN Configures whether to enable one shot trip0 event generation. 0: Disable 1: Enable (R/W) MCPWM_EVT_TZ1_OST_EN Configures whether to enable one shot trip1 event generation. 0: Disable 1: Enable (R/W) MCPWM_EVT_TZ2_OST_EN Configures whether to enable one shot trip2 event generation. 0: Disable 1: Enable (R/W) MCPWM_EVT_CAP0_EN Configures whether to enable capture0 event generation. 0: Disable 1: Enable (R/W) MCPWM_EVT_CAP1_EN Configures whether to enable capture1 event generation. 0: Disable 1: Enable (R/W) MCPWM_EVT_CAP2_EN Configures whether to enable capture2 event generation. 0: Disable 1: Enable (R/W) Espressif Systems 1347 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.34. MCPWM_EVT_EN2_REG (0x0128) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 6 MCPWM_EVT_OP2_TEE2_EN 0 5 MCPWM_EVT_OP1_TEE2_EN 0 4 MCPWM_EVT_OP0_TEE2_EN 0 3 MCPWM_EVT_OP2_TEE1_EN 0 2 MCPWM_EVT_OP1_TEE1_EN 0 1 MCPWM_EVT_OP0_TEE1_EN 0 0 Reset MCPWM_EVT_OPn_TEE1_EN Configures whether to generate the MCPWM_EVT_OPn_TEE1 event when the PWM generatorn timer equals OPn_TSTMP_E1_REG. 0: Not generate 1: Generate (R/W) MCPWM_EVT_OPn_TEE2_EN Configures whether to generate the MCPWM_EVT_OPn_TEE2 event when the PWM generatorn timer equals OPn_TSTMP_E2_REG. 0: Not generate 1: Generate (R/W) Espressif Systems 1348 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.35. MCPWM_TASK_EN_REG (0x0124) (reserved) 0 0 0 0 0 0 0 0 0 0 31 22 MCPWM_TASK_CAP2_EN 0 21 MCPWM_TASK_CAP1_EN 0 20 MCPWM_TASK_CAP0_EN 0 19 MCPWM_TASK_CLR2_OST_EN 0 18 MCPWM_TASK_CLR1_OST_EN 0 17 MCPWM_TASK_CLR0_OST_EN 0 16 MCPWM_TASK_TZ2_OST_EN 0 15 MCPWM_TASK_TZ1_OST_EN 0 14 MCPWM_TASK_TZ0_OST_EN 0 13 MCPWM_TASK_TIMER2_PERIOD_UP_EN 0 12 MCPWM_TASK_TIMER1_PERIOD_UP_EN 0 11 MCPWM_TASK_TIMER0_PERIOD_UP_EN 0 10 MCPWM_TASK_TIMER2_SYNC_EN 0 9 MCPWM_TASK_TIMER1_SYNC_EN 0 8 MCPWM_TASK_TIMER0_SYNC_EN 0 7 MCPWM_TASK_GEN_STOP_EN 0 6 MCPWM_TASK_CMPR2_B_UP_EN 0 5 MCPWM_TASK_CMPR1_B_UP_EN 0 4 MCPWM_TASK_CMPR0_B_UP_EN 0 3 MCPWM_TASK_CMPR2_A_UP_EN 0 2 MCPWM_TASK_CMPR1_A_UP_EN 0 1 MCPWM_TASK_CMPR0_A_UP_EN 0 0 Reset MCPWM_TASK_CMPR0_A_UP_EN Configures whether to receive update task of PWM generator0 timer stamp A’s shadow register. 0: No effect 1: Receive (R/W) MCPWM_TASK_CMPR1_A_UP_EN Configures whether to receive update task of PWM generator1 timer stamp A’s shadow register. 0: No effect 1: Receive (R/W) MCPWM_TASK_CMPR2_A_UP_EN Configures whether to receive update task of PWM generator2 timer stamp A’s shadow register. 0: No effect 1: Receive (R/W) MCPWM_TASK_CMPR0_B_UP_EN Configures whether to receive update task of PWM generator0 timer stamp B’s shadow register. 0: No effect 1: Receive (R/W) MCPWM_TASK_CMPR1_B_UP_EN Configures whether to receive update task of PWM generator1 timer stamp B’s shadow register. 0: No effect 1: Receive (R/W) MCPWM_TASK_CMPR2_B_UP_EN Configures whether to receive update task of PWM generator2 timer stamp B’s shadow register. 0: No effect 1: Receive (R/W) Continued on the next page... Espressif Systems 1349 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.35. MCPWM_TASK_EN_REG (0x0124) Continued from the previous page... MCPWM_TASK_GEN_STOP_EN Configures whether to receive all PWM generate stop task. 0: No effect 1: Receive (R/W) MCPWM_TASK_TIMER0_SYNC_EN Configures whether to receive timer0 sync task. 0: No effect 1: Receive (R/W) MCPWM_TASK_TIMER1_SYNC_EN Configures whether to receive timer1 sync task. 0: No effect 1: Receive (R/W) MCPWM_TASK_TIMER2_SYNC_EN Configures whether to receive timer2 sync task. 0: No effect 1: Receive (R/W) MCPWM_TASK_TIMER0_PERIOD_UP_EN Configures whether to receive timer0 period update task. 0: No effect 1: Receive (R/W) MCPWM_TASK_TIMER1_PERIOD_UP_EN Configures whether to receive timer1 period update task. 0: No effect 1: Receive (R/W) MCPWM_TASK_TIMER2_PERIOD_UP_EN Configures whether to receive timer2 period update task. 0: No effect 1: Receive (R/W) Continued on the next page... Espressif Systems 1350 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.35. MCPWM_TASK_EN_REG (0x0124) Continued from the previous page... MCPWM_TASK_TZ0_OST_EN Configures whether to receive one shot trip0 task. 0: No effect 1: Receive (R/W) MCPWM_TASK_TZ1_OST_EN Configures whether to receive one shot trip1 task. 0: No effect 1: Receive (R/W) MCPWM_TASK_TZ2_OST_EN Configures whether to receive one shot trip2 task. 0: No effect 1: Receive (R/W) MCPWM_TASK_CLR0_OST_EN Configures whether to receive one shot trip0 clear task. 0: No effect 1: Receive (R/W) MCPWM_TASK_CLR1_OST_EN Configures whether to receive one shot trip1 clear task. 0: No effect 1: Receive (R/W) MCPWM_TASK_CLR2_OST_EN Configures whether to receive one shot trip2 clear task. 0: No effect 1: Receive (R/W) MCPWM_TASK_CAP0_EN Configures whether to receive capture0 task. 0: No effect 1: Receive (R/W) MCPWM_TASK_CAP1_EN Configures whether to receive capture1 task. 0: No effect 1: Receive (R/W) MCPWM_TASK_CAP2_EN Configures whether to receive capture2 task. 0: No effect 1: Receive (R/W) Espressif Systems 1351 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.36. MCPWM_OPn_TSTMP_E1_REG (n: 0-2) (0x012C+0x8*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 MCPWM_OPn_TSTMP_E1 0 15 0 Reset MCPWM_OPn_TSTMP_E1 Configures the time stamp E1 value of the generatorn. (R/W) Register 36.37. MCPWM_OPn_TSTMP_E2_REG(n: 0-2) (0x0130+0x8*n) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 MCPWM_OPn_TSTMP_E2 0 15 0 Reset MCPWM_OPn_TSTMP_E2 Configures the time stamp E2 value of the generatorn. (R/W) Register 36.38. MCPWM_CLK_REG (0x0144) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 1 MCPWM_CLK_EN 0 0 Reset MCPWM_CLK_EN Configures whether to force open register clock gate. 0: Open the clock gate only when application writes registers 1: Force open the clock gate for register (R/W) Espressif Systems 1352 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 36 Motor Control PWM (MCPWM) Register 36.39. MCPWM_VERSION_REG (0x0148) (reserved) 0 0 0 0 31 28 MCPWM_DATE 0x2212290 27 0 Reset MCPWM_DATE Version control register. (R/W) Espressif Systems 1353 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 37 Remote Control Peripheral (RMT) Chapter 37 Remote Control Peripheral (RMT) 37.1 Overview The Remote Control (RMT) module is designed to transmit and receive infrared remote control signals. A variety of remote control protocols can be encoded/decoded via software based on the RMT module. The RMT module converts pulse codes stored in the module’s built-in RAM into output signals, or converts input signals into pulse codes and stores them in RAM. In addition, the RMT module optionally modulates its output signals with a carrier wave, or optionally demodulates and filters its input signals. The RMT module has four channels, numbered from zero to three. Each channel is able to independently transmit or receive signals. • Channels 0 1 (TX channel) are dedicated to transmitting signals; • Channels 2 3 (RX channel) are dedicated to receiving signals. Each TX/RX channel has the same functionality controlled by a dedicated set of registers and is able to independently transmit or receive data. TX channels are indicated by n which is used as a placeholder for the channel number, and by m for RX channels. 37.2 Features The RMT module has the following features: • Four channels: – TX channels 0 1 – RX channels 2 3 – Four channels share a 192 x 32-bit RAM • The transmitter supports: – Normal TX mode – Wrap TX mode – Modulation on TX pulses – Continuous TX mode – Multiple channels (programmable) transmitting data simultaneously • The receiver supports: – Normal RX mode Espressif Systems 1354 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 37 Remote Control Peripheral (RMT) – Wrap RX mode – RX filtering – Demodulation on RX pulses 37.3 Functional Description 37.3.1 RMT Architecture Same as TX Channel n RMT_REF_CNT_RST_CHn RMT_DIV_CNT_CHn mem_rdatan RMT_CARRIER_EN_CHn RMT_CONTI_MODE_CHn RMT_TX_LIM_CHn RMT_TX_WRAP_EN_CHn TX Channel n block2 block3 block1 block0 RAM RMT_MEM_SIZE_CHn/m RMT_MEM_RD_RST_CHn RMT_MEM_WR_RST_CHm TX Channel n+1 mem_wdata rmt_sclk mem_rdn mem_wrm clk_div Carrier_Generator RMT_IDLE_OUT_EN_CHn sig_out RMT_CARRIER_HIGH_CHn RMT_CARRIER_LOW_CHn RMT_CARRIER_OUT_LV_CHn Modulator 0 1 CK Div Counter CLR FSM tx_en Flip_Flop D EN RMT_IDLE_OUT_LV_CHn 1 0 Comparator period level Detect_Edge 0 1 1 0 Demodulator Filter RMT_CARRIER_EN_CHm RMT_CARRIER_HIGH_THRES_CHm RMT_CARRIER_LOW_THRES_CHm RMT_CARRIER_OUT_LV_CHm Receiver rmt_sclk RMT_RX_FILTER_EN_CHm CK Div Counter CLR FSM rx_en CLK_DIV_NUMERATOR CLK_DIV_DENOMINATOR CLK_DIV_NUM Frac Divider (8 bits) PLL_F80M_CLK RC_FAST_CLK Clock 2 1 0 XTAL_CLK CLK_SRC_SEL CLK_EN APB BUS Same as RX Channel m RX Channel m+1 sig _in clk_div Transmitter mem_wr(m+1) mem_rdata(n+1) mem_rd(n+1) RMT_RX_FILTER_THRES_CHm RX Channel m Modulator Note: In the figure, n = 0 and m = 2. Figure 37.3-1. RMT Architecture As shown in Figure 37.3-1, each TX channel has: • Clock divider counter (Div Counter) • State machine (FSM) • Transmitter Each RX channel also has: • Clock divider counter (Div Counter) • State machine (FSM) • Receiver Espressif Systems 1355 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 37 Remote Control Peripheral (RMT) The four channels share a 192 x 32-bit RAM. In the “Clock” frame, the clock-related registers that need to be configured for RMT are specified below: • CLK_EN: PCR_RMT_SCLK_EN to enable the rmt_sclk clock • CLK_SRC_SEL: PCR_RMT_SCLK_SEL to select the rmt_sclk clock • CLK_DIV_NUM: PCR_RMT_SCLK_DIV_NUM to configure the integral part of the divisor for the rmt_sclk clock • CLK_DIV_NUMERATOR: PCR_RMT_SCLK_DIV_A to configure the denominator of the divisor’s fractional part for the rmt_sclk clock • CLK_DIV_DENOMINATOR: PCR_RMT_SCLK_DIV_B to configure the numerator of the divisor’s fractional part for the rmt_sclk clock 37.3.2 RAM 37.3.2.1 Structure of RAM Figure 37.3-2 shows the format of pulse code in RAM. Each pulse code contains a 16-bit entry with two fields: “level” and “period”. “level” (0 or 1) indicates a low-/high-level value that has been received or is going to be sent, while “period” points out the number of clock cycles (see clk_div in Figure 37.3-1) that the level lasts for. Figure 37.3-2. Format of Pulse Code in RAM The minimum value for the period is zero (0) and is interpreted as a transmission end-marker. For a non-zero period (i.e., not an end-marker), its value is limited by APB clock and RMT clock according to the formula below: 3 × T apb_clk + 5 × T rmt_sclk < period × T clk_div (1) 37.3.2.2 Use of RAM The RAM is divided into four 48 x 32-bit blocks. By default, each channel uses one block (block 0 for channel 0, block 1 for channel 1, and so on). If the data size of one single transfer is larger than the block size of TX channel n or RX channel m, users can configure the channel: • to enable wrap mode by setting RMT_MEM_TX/RX_WRAP_EN_CHn/m; Espressif Systems 1356 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 37 Remote Control Peripheral (RMT) • or to use more blocks by configuring RMT_MEM_SIZE_CHn/m. Setting RMT_MEM_SIZE_CHn/m > 1 allows channel n/m to use the memory of the subsequent channels, i.e., block (n/m) block (n/m+RMT_MEM_SIZE_CHn/m–1). In such case, the subsequent channels n/m+1 n/m + RMT_MEM_SIZE_CHn/m–1 can not be used since their RAM blocks are occupied. For example, if channel 0 is configured to use block 0 and block 1, then channel 1 will be unavailable since its block is occupied, while channel 2 and channel 3 are not affected and can be used normally. Note that the RAM used by each channel is mapped from low address to high address. In such mode, channel 0 is able to use the RAM blocks of channels 1, 2, and 3 by setting RMT_MEM_SIZE_CH0, but channel 3 can not use the blocks of channels 0, 1, or 2. Therefore, the maximum value of RMT_MEM_SIZE_CHn should not exceed (4–n) and the value of RMT_MEM_SIZE_CHm should not exceed (2–m). The RMT RAM can be accessed via APB bus, or read by the transmitter and written by the receiver. To avoid any possible access conflict between the receiver writing RAM and the APB bus reading RAM, RMT can be configured to designate the RAM block’s owner, be it the receiver or the APB bus, by configuring RMT_MEM_OWNER_CHm. If this ownership is violated, a flag signal RMT_MEM_OWNER_ERR_CHm will be generated. 37.3.2.3 RAM Access APB bus is able to access RAM in FIFO mode and in NONFIFO (Direct Address) mode, depending on the configuration of RMT_APB_FIFO_MASK: • 0: use FIFO mode; • 1: use NONFIFO mode. FIFO Mode In FIFO mode, the APB reads data from or writes data to RAM via a fixed address stored in RMT_CHn/mDATA_REG. NONFIFO Mode In NONFIFO mode, the APB writes data to or reads data from a continuous address range. • The write-starting address of TX channel n is (RMT base address + 0x400 + nx48). The access address for the second data and the following data are (RMT base address + 0x400 + nx48 + 0x4), and so on, incremented by 0x4. • The read-starting address of RX channel m is (RMT base address + 0x460 + mx48). The access address for the second data and the following data are (RMT base address + 0x460 + mx48 + 0x4), and so on, incremented by 0x4. 37.3.3 Clock The clock source of RMT can be PLL_F80M_CLK, RC_FAST_CLK, or XTAL_CLK, depending on the configuration of PCR_RMT_SCLK_SEL. RMT clock can be enabled by setting PCR_RMT_SCLK_EN. RMT working clock (see rmt_sclk in Figure 37.3-1) is obtained by dividing the selected clock source with a fractional divider. The divider is PCR_RMT_SCLK_DIV_NUM + 1 + PCR_RMT_SCLK_DIV_A / PCR_RMT_SCLK_DIV_B For more information, see Chapter 7 Reset and Clock. RMT_DIV_CNT_CHn/m is used to configure the divider coefficient of internal clock divider for RMT channels. The coefficient is normally equal to the value of Espressif Systems 1357 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 37 Remote Control Peripheral (RMT) RMT_DIV_CNT_CHn/m, except for value 0 that represents divider 256. The clock divider can be reset by setting RMT_REF_CNT_RST_CHn/m. The clock generated from the divider can be used by the counter (see Figure 37.3-1). 37.3.4 Transmitter Note: Updating the configuration described in this and subsequent sections requires to set RMT_CONF_UPDATE_CHn/m first. See Section 37.4. 37.3.4.1 Normal TX Mode When RMT_TX_START_CHn is set, the transmitter of channel n starts reading and transmitting pulse codes from the starting address of its RAM block. The codes are transmitted starting from low-address entry. When an end-marker (a zero period) is encountered, the transmitter stops the transmission, returns to idle state, and generates an RMT_CHn_TX_END_INT interrupt. Setting RMT_TX_STOP_CHn to 1 also stops the transmission and immediately sets the transmitter back to idle. The output level of a transmitter in idle state is determined by the “level” field of the end-marker or by the content of RMT_IDLE_OUT_LV_CHn, depending on the configuration of RMT_IDLE_OUT_EN_CHn: • 0: the level in idle state is determined by the “level” field of the end-marker; • 1: the level is determined by RMT_IDLE_OUT_LV_CHn. 37.3.4.2 Wrap TX Mode To transmit more pulse codes than can be fitted in the channel’s RAM, users can enable wrap TX mode for channel n by setting RMT_MEM_TX_WRAP_EN_CHn. In this mode, the transmitter transmits the data from RAM in loops till an end-marker is encountered. For example, if RMT_MEM_SIZE_CHn = 1, the transmitter starts transmitting data from the address 48 * n, and then the data from higher RAM address. Once the transmitter finishes transmitting the data from (48 * (n+1)–1), it continues transmitting data from 48 * n again till an end-marker is encountered. Wrap mode is also applicable for RMT_MEM_SIZE_CHn > 1. When the size of transmitted pulse codes is larger than or equal to the value set by RMT_TX_LIM_CHn, an RMT_CHn_TX_THR_EVENT_INT interrupt is triggered. In wrap mode, RMT_TX_LIM_CHn can be set to a half or a fraction of the size of the channel’s RAM block. When an RMT_CHn_TX_THR_EVENT_INT interrupt is detected by software, the already used RAM region can be updated by new pulse codes. In such way, the transmitter can seamlessly transmit unlimited pulse codes in wrap mode. 37.3.4.3 TX Modulation Transmitter output can be modulated with a carrier wave by setting RMT_CARRIER_EN_CHn. The carrier waveform is configurable. In a carrier cycle, high level lasts for (RMT_CARRIER_HIGH_CHn + 1) rmt_sclk cycles, while low level lasts for (RMT_CARRIER_LOW_CHn + 1) rmt_sclk cycles. When RMT_CARRIER_OUT_LV_CHn is set, carrier wave is added on the high-level of output signals; while RMT_CARRIER_OUT_LV_CHn is cleared, carrier wave is added on the low-level of output signals. Carrier wave can be added on all output signals during modulation, or just added on valid pulse codes (the data stored in RAM), which can be set by configuring RMT_CARRIER_EFF_EN_CHn: Espressif Systems 1358 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 37 Remote Control Peripheral (RMT) • 0: add carrier wave on all output signals; • 1: add carrier wave only on valid signals. 37.3.4.4 Continuous TX Mode The continuous TX mode can be enabled by setting RMT_TX_CONTI_MODE_CHn. In this mode, the transmitter transmits the pulse codes from RAM in loops: • If an end-marker is encountered, the transmitter starts transmitting the first data of the channel’s RAM again. • If no end-marker is encountered, there are two possible situations. In normal TX mode (RMT_MEM_TX_WRAP_EN_CHn = 0), an error interrupt occurs because the RAM is empty without any data to transmit. In wrap TX mode (RMT_MEM_TX_WRAP_EN_CHn = 1), the transmitter starts transmitting the first data again after the last data is transmitted. If RMT_TX_LOOP_CNT_EN_CHn is set, the loop counting is incremented by 1 each time an end-marker is encountered. If the counting reaches the value set by RMT_TX_LOOP_NUM_CHn, an RMT_CHn_TX_LOOP_INT interrupt is generated. If RMT_LOOP_STOP_EN_CHn is set, the transmission stops instantly after an RMT_CHn_TX_LOOP_INT interrupt is generated. Otherwise, the transmission continues. In an end-marker, if its period[14:0] is 0, then the period of the previous data must satisfy: 6 × T apb_clk + 12 × T rmt_sclk < period × T clk_div (2) The period of the other data only need to satisfy relation (1). 37.3.4.5 Simultaneous TX Mode RMT module supports multiple channels transmitting data simultaneously. To use this function, follow the steps below: 1. Configure RMT_TX_SIM_CHn to choose which multiple channels are used to transmit data simultaneously; 2. Set RMT_TX_SIM_EN to enable this transmission mode; 3. Set RMT_TX_START_CHn for each selected channel to start data transmission. The transmission starts once the final channel is configured. Due to hardware limitations, there is no guarantee that two channels can start transmitting data exactly at the same time. The interval between two channels starting transmitting data is within 3 x T clk_div . 37.3.5 Receiver 37.3.5.1 Normal RX Mode The receiver of channel m is controlled by RMT_RX_EN_CHm: • 0: the receiver stops receiving data; • 1: the receiver starts working. When the receiver becomes active, it starts counting from the first edge of the signal, detecting signal levels and counting clock cycles the level lasts for. Each cycle count (period) is then written back to RAM together with the level information (level). When the receiver detects no change in a signal level for a number of clock cycles more Espressif Systems 1359 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 37 Remote Control Peripheral (RMT) than the value set by RMT_IDLE_THRES_CHm, the receiver stops receiving data, returns to idle state, and generates an RMT_CHm_RX_END_INT interrupt. Please note that RMT_IDLE_THRES_CHm should be configured to a maximum value according to your application, otherwise a valid received level may be mistaken as a level in idle state. If the RAM space of this RX channel is used up by the received data, the receiver stops receiving data, and an RMT_CHm_ERR_INT interrupt is triggered by RAM FULL event. 37.3.5.2 Wrap RX Mode To receive more pulse codes than can be fitted in the channel’s RAM, users can enable wrap mode for channel m by configuring RMT_MEM_RX_WRAP_EN_CHm. In wrap mode, the receiver stores the received data to RAM space of this channel in loops. The receiving ends when the receiver detects no change in a signal level for a number of clock cycles more than the value set by RMT_IDLE_THRES_CHm. The receiver returns to idle state and generates an RMT_CHm_RX_END_INT interrupt. For example, if RMT_MEM_SIZE_CHm is set to 1, the receiver starts receiving data and stores the data to address 48 * m, and then to higher RAM address. When the receiver finishes storing the received data to (48 * (m + 1)–1), the receiver continues receiving data and storing data to the address 48 * m again, and the receiving ends when no change is detected on a signal level for more than RMT_IDLE_THRES_CHm clock cycles. Wrap mode is also applicable when RMT_MEM_SIZE_CHm > 1. An RMT_CHm_RX_THR_EVENT_INT interrupt is generated when the size of received pulse codes is larger than or equal to the value set by RMT_RX_LIM_CHm. In wrap mode, RMT_RX_LIM_CHm can be set to a half or a fraction of the size of the channel’s RAM block. When an RMT_CHm_RX_THR_EVENT_INT interrupt is detected, the already used RAM region can be updated by subsequent data. 37.3.5.3 RX Filtering Users can enable the receiver to filter input signals by setting RMT_RX_FILTER_EN_CHm for channel m. The filter samples input signals continuously, and detects the signals which remain unchanged for a continuous RMT_RX_FILTER_THRES_CHm rmt_sclk cycles as valid. Otherwise, the signals will be detected as invalid. Only the valid signals can pass through the filter. The filter removes pulses with a length of less than RMT_RX_FILTER_THRES_CHm rmt_sclk cycles. 37.3.5.4 RX Demodulation Users can enable RX demodulation on input signals or on filtered signals by setting RMT_CARRIER_EN_CHm. RX demodulation can be applied to high-level carrier wave or low-level carrier wave, depending on the configuration of RMT_CARRIER_OUT_LV_CHm: • 0: demodulate low-level carrier wave; • 1: demodulate high-level carrier wave. Users can configure RMT_CARRIER_HIGH_THRES_CHm and RMT_CARRIER_LOW_THRES_CHm to set the thresholds to demodulate high-level carrier or low-level carrier. If the high-level of a signal lasts for less than RMT_CARRIER_HIGH_THRES_CHm clk_div cycles, or the low-level lasts for less than RMT_CARRIER_LOW_THRES_CHm clk_div cycles, the signal is detected as a carrier and is then filtered out. Espressif Systems 1360 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 37 Remote Control Peripheral (RMT) 37.4 Configuration Update To update RMT registers configuration, please set RMT_CONF_UPDATE_CHn/m for each channel first. All the bits/fields listed in the second column of Table 37.4-1 should follow this rule. Table 37.4-1. Configuration Update Register Bit/Field Configuration Update TX Channel RMT_CHnCONF0_REG RMT_CARRIER_OUT_LV_CHn RMT_CARRIER_EN_CHn RMT_CARRIER_EFF_EN_CHn RMT_DIV_CNT_CHn RMT_IDLE_OUT_EN_CHn RMT_IDLE_OUT_LV_CHn RMT_TX_CONTI_MODE_CHn RMT_CHnCARRIER_DUTY_REG RMT_CARRIER_HIGH_CHn RMT_CARRIER_LOW_CHn RMT_CHn_TX_LIM_REG RMT_TX_LOOP_CNT_EN_CHn RMT_TX_LOOP_NUM_CHn RMT_TX_LIM_CHn RMT_TX_SIM_REG RMT_TX_SIM_EN RX Channel RMT_CHmCONF0_REG RMT_CARRIER_OUT_LV_CHm RMT_CARRIER_EN_CHm RMT_IDLE_THRES_CHm RMT_DIV_CNT_CHm RMT_CHmCONF1_REG RMT_RX_FILTER_THRES_CHm RMT_RX_EN_CHm RMT_CHm_RX_CARRIER_RM_REG RMT_CARRIER_HIGH_THRES_CHm RMT_CARRIER_LOW_THRES_CHm RMT_CHm_RX_LIM_REG RMT_RX_LIM_CHm RMT_REF_CNT_RST_REG RMT_REF_CNT_RST_CHm 37.5 Interrupts ESP32-C5’s RMT can generate the RMT_INTR interrupt signal that will be sent to the Interrupt Matrix. The following interrupt sources can generate the RMT_INTR interrupt signal: • RMT_CHn/m_ERR_INT: triggered when channel n/m does not read or write data correctly. For example, if the transmitter still tries to read data from RAM when the RAM is empty, or the receiver still tries to write data into RAM when the RAM is full, this interrupt will be triggered. • RMT_CHn_TX_THR_EVENT_INT: triggered when the amount of data the transmitter has transmitted reaches the value set in RMT_CHn_TX_LIM_REG. Espressif Systems 1361 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 37 Remote Control Peripheral (RMT) • RMT_CHm_RX_THR_EVENT_INT: triggered each time when the amount of data received by the receiver reaches the value set in RMT_CHm_RX_LIM_REG. • RMT_CHn_TX_END_INT: triggered when the transmitter has finished transmitting signals. • RMT_CHm_RX_END_INT: triggered when the receiver has finished receiving signals. • RMT_CHn_TX_LOOP_INT: triggered when the loop counting reaches the value set by RMT_TX_LOOP_NUM_CHn. Note: For definitions of interrupt, interrupt signal, interrupt source, and their correlations, please refer to Chapter 9 Interrupt Matrix > Section 9.2 Terminology. Each interrupt source can be configured by a common set of registers that are described in Section Interrupt Configuration Registers. The specific registers can be found in Section 37.6 Register Summary. Espressif Systems 1362 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 37 Remote Control Peripheral (RMT) 37.6 Register Summary The addresses in this section are relative to Remote Control Peripheral base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access FIFO read and writer registers RMT_CH0DATA_REG The read and write data register for channel 0 by APB FIFO access 0x0000 HRO RMT_CH1DATA_REG The read and write data register for channel 1 by APB FIFO access 0x0004 HRO RMT_CH2DATA_REG The read and write data register for channel 2 by APB FIFO access 0x0008 HRO RMT_CH3DATA_REG The read and write data register for channel 3 by APB FIFO access 0x000C HRO Configuration registers RMT_CH0CONF0_REG Configuration register 0 for channel 0 0x0010 varies RMT_CH1CONF0_REG Configuration register 0 for channel 1 0x0014 varies RMT_CH2CONF0_REG Configuration register 0 for channel 2 0x0018 R/W RMT_CH2CONF1_REG Configuration register 1 for channel 2 0x001C varies RMT_CH3CONF0_REG Configuration register 0 for channel 3 0x0020 R/W RMT_CH3CONF1_REG Configuration register 1 for channel 3 0x0024 varies RMT_SYS_CONF_REG Configuration register for RMT APB 0x0068 R/W RMT_REF_CNT_RST_REG RMT clock divider reset register 0x0070 WT Status registers RMT_CH0STATUS_REG Channel 0 status register 0x0028 RO RMT_CH1STATUS_REG Channel 1 status register 0x002C RO RMT_CH2STATUS_REG Channel 2 status register 0x0030 RO RMT_CH3STATUS_REG Channel 3 status register 0x0034 RO Interrupt registers RMT_INT_RAW_REG Raw interrupt status 0x0038 R/WTC/SS RMT_INT_ST_REG Masked interrupt status 0x003C RO RMT_INT_ENA_REG Interrupt enable bits 0x0040 R/W RMT_INT_CLR_REG Interrupt clear bits 0x0044 WT Carrier wave duty cycle registers RMT_CH0CARRIER_DUTY_REG Duty cycle configuration register for channel 0 0x0048 R/W RMT_CH1CARRIER_DUTY_REG Duty cycle configuration register for channel 1 0x004C R/W RMT_CH2_RX_CARRIER_RM_REG Carrier remove register for channel 2 0x0050 R/W RMT_CH3_RX_CARRIER_RM_REG Carrier remove register for channel 3 0x0054 R/W TX event configuration registers RMT_CH0_TX_LIM_REG Configuration register for channel 0 TX event 0x0058 varies RMT_CH1_TX_LIM_REG Configuration register for channel 1 TX event 0x005C varies RMT_TX_SIM_REG RMT TX synchronous register 0x006C R/W Espressif Systems 1363 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 37 Remote Control Peripheral (RMT) Name Description Address Access RX event configuration registers RMT_CH2_RX_LIM_REG Configuration register for channel 2 RX event 0x0060 R/W RMT_CH3_RX_LIM_REG Configuration register for channel 3 RX event 0x0064 R/W Version control register RMT_DATE_REG Version control register 0x00CC R/W Espressif Systems 1364 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 37 Remote Control Peripheral (RMT) 37.7 Registers The addresses in this section are relative to Remote Control Peripheral base address provided in Table 4.3-2 in Chapter 4 System and Memory. Register 37.1. RMT_CHnDATA_REG (n: 0-3) (0x0000+0x4*n) RMT_CHnDATA 0x000000 31 0 Reset RMT_CHnDATA Read and write data for channel n via APB FIFO. (HRO) Register 37.2. RMT_CHnCONF0_REG (n: 0-1) (0x0010+0x4*n) (reserved) 0 0 0 0 0 0 0 31 25 RMT_CONF_UPDATE_CHn 0 24 (reserved) 0 23 RMT_CARRIER_OUT_LV_CHn 1 22 RMT_CARRIER_EN_CHn 1 21 RMT_CARRIER_EFF_EN_CHn 1 20 (reserved) 0 19 RMT_MEM_SIZE_CHn 0x1 18 16 RMT_DIV_CNT_CHn 0x2 15 8 RMT_TX_STOP_CHn 0 7 RMT_IDLE_OUT_EN_CHn 0 6 RMT_IDLE_OUT_LV_CHn 0 5 RMT_MEM_TX_WRAP_EN_CHn 0 4 RMT_TX_CONTI_MODE_CHn 0 3 RMT_APB_MEM_RST_CHn 0 2 RMT_MEM_RD_RST_CHn 0 1 RMT_TX_START_CHn 0 0 Reset RMT_TX_START_CHn Configures whether to enable sending data in channel n. 0: No effect 1: Enable (WT) RMT_MEM_RD_RST_CHn Configures whether to reset RAM read address accessed by the trans- mitter for channel n. 0: No effect 1: Reset (WT) RMT_APB_MEM_RST_CHn Configures whether to reset RAM W/R address accessed by APB FIFO for channel n. 0: No effect 1: Reset (WT) Continued on the next page... Espressif Systems 1365 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 37 Remote Control Peripheral (RMT) Register 37.2. RMT_CHnCONF0_REG (n: 0-1) (0x0010+0x4*n) Continued from the previous page... RMT_TX_CONTI_MODE_CHn Configures whether to enable continuous TX mode for channel n. 0: No Effect 1: Enable In this mode, the transmitter starts transmission from the first data. If an end-marker is encountered, the transmitter starts transmitting data from the first data again. if no end-marker is encountered, the transmitter starts transmitting the first data again when the last data is transmitted. (R/W) RMT_MEM_TX_WRAP_EN_CHn Configures whether to enable wrap TX mode for channel n. 0: No effect 1: Enable In this mode, if the TX data size is larger than the channel’s RAM block size, the transmitter con- tinues transmitting the first data to the last data in loops. (R/W) RMT_IDLE_OUT_LV_CHn Configures the level of output signal for channel n when the transmitter is in idle state. (R/W) RMT_IDLE_OUT_EN_CHn Configures whether to enable the output for channel n in idle state. 0: No effect 1: Enable (R/W) RMT_TX_STOP_CHn Configures whether to stop the transmitter of channel n sending data out. 0: No effect 1: Stop (R/W/SC) RMT_DIV_CNT_CHn Configures the divider for clock of channel n. Measurement unit: rmt_sclk (R/W) RMT_MEM_SIZE_CHn Configures the maximum number of memory blocks allocated to channel n. (R/W) RMT_CARRIER_EFF_EN_CHn Configures whether to add carrier modulation on the output signal only at data-sending state for channel n. 0: Add carrier modulation on the output signal at data-sending state and idle state for channel n 1: Add carrier modulation on the output signal only at data-sending state for channel n Only valid when RMT_CARRIER_EN_CHn is 1. (R/W) Continued on the next page... Espressif Systems 1366 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 37 Remote Control Peripheral (RMT) Register 37.2. RMT_CHnCONF0_REG (n: 0-1) (0x0010+0x4*n) Continued from the previous page... RMT_CARRIER_EN_CHn Configures whether to enable the carrier modulation on output signal for channel n. 0: Disable 1: Enable (R/W) RMT_CARRIER_OUT_LV_CHn Configures the position of carrier wave for channel n. 0: Add carrier wave on low level 1: Add carrier wave on high level (R/W) RMT_CONF_UPDATE_CHn Synchronization of RMT Channel n. (WT) Register 37.3. RMT_CHmCONF0_REG (m: 2-3) (0x0018+0x8*(m-2)) (reserved) 0 0 31 30 RMT_CARRIER_OUT_LV_CHm 1 29 RMT_CARRIER_EN_CHm 1 28 (reserved) 0 0 27 26 RMT_MEM_SIZE_CHm 0x1 25 23 RMT_IDLE_THRES_CHm 0x7fff 22 8 RMT_DIV_CNT_CHm 0x2 7 0 Reset RMT_DIV_CNT_CHm Configures the clock divider of channel m. Measurement unit: rmt_sclk (R/W) RMT_IDLE_THRES_CHm Configures RX threshold. When no edge is detected on the input signal for continuous clock cycles longer than this field value, the receiver stops receiving data. Measurement unit: clk_div (R/W) Continued on the next page... Espressif Systems 1367 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 37 Remote Control Peripheral (RMT) Register 37.3. RMT_CHmCONF0_REG (m: 2-3) (0x0018+0x8*(m-2)) Continued from the previous page... RMT_MEM_SIZE_CHm Configures the maximum number of memory blocks allocated to channel m. (R/W) RMT_CARRIER_EN_CHm Configures whether to enable carrier modulation on output signal for channel m. 0: Disable 1: Enable (R/W) RMT_CARRIER_OUT_LV_CHm Configures the position of carrier wave for channel m. 0: Add carrier wave on low level 1: Add carrier wave on high level (R/W) Register 37.4. RMT_CHmCONF1_REG (m: 2-3) (0x001C+0x8*(m-2)) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 RMT_CONF_UPDATE_CHm 0 15 (reserved) 0 14 RMT_MEM_RX_WRAP_EN_CHm 0 13 RMT_RX_FILTER_THRES_CHm 0xf 12 5 RMT_RX_FILTER_EN_CHm 0 4 RMT_MEM_OWNER_CHm 1 3 RMT_APB_MEM_RST_CHm 0 2 RMT_MEM_WR_RST_CHm 0 1 RMT_RX_EN_CHm 0 0 Reset RMT_RX_EN_CHm Configures whether to enable the receiver to start receiving data in channel m. 0: Disable 1: Enable (R/W) RMT_MEM_WR_RST_CHm Configures whether to reset RAM write address accessed by the re- ceiver for channel m. 0: No effect 1: Reset (WT) RMT_APB_MEM_RST_CHm Configures whether to reset RAM W/R address accessed by APB FIFO for channel m. 0: No effect 1: Reset (WT) Continued on the next page... Espressif Systems 1368 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 37 Remote Control Peripheral (RMT) Register 37.4. RMT_CHmCONF1_REG (m: 2-3) (0x001C+0x8*(m-2)) Continued from the previous page... RMT_MEM_OWNER_CHm Configures the ownership of channel m’s RAM block. 0: APB bus is using the RAM 1: Receiver is using the RAM (R/W/SC) RMT_RX_FILTER_EN_CHm Configures whether to enable the receiver’s filter for channel m. 0: Disable 1: Enable (R/W) RMT_RX_FILTER_THRES_CHm Configures whether the receiver, when receiving data, ignores the input pulse when its width is shorter than this register value in units of rmt_sclk cycles. 0: No effect 1: Reset (R/W) RMT_MEM_RX_WRAP_EN_CHm Configures whether to enable wrap RX mode for channel m. 0: Disable 1: Enable In this mode, if the RX data size is larger than channel m’s RAM block size, the receiver stores the RX data from the first address to the last address in loops. (R/W) RMT_CONF_UPDATE_CHm Synchronization of RMT Channel m. (WT) Register 37.5. RMT_SYS_CONF_REG (0x0068) RMT_CLK_EN 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 1 RMT_APB_FIFO_MASK 0 0 Reset RMT_APB_FIFO_MASK Configures the memory access mode. 0: Access memory by FIFO 1: Access memory directly (R/W) RMT_CLK_EN Configures whether to enable signal of RMT register clock gate. 0: Power down the drive clock of registers 1: Power up the drive clock of registers (R/W) Espressif Systems 1369 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 37 Remote Control Peripheral (RMT) Register 37.6. RMT_REF_CNT_RST_REG (0x0070) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 4 RMT_REF_CNT_RST_CH3 0 3 RMT_REF_CNT_RST_CH2 0 2 RMT_REF_CNT_RST_CH1 0 1 RMT_REF_CNT_RST_CH0 0 0 Reset RMT_REF_CNT_RST_CHn (n: 0-1) Configures whether to reset the clock divider of channel n. 0: No effect 1: Reset (WT) RMT_REF_CNT_RST_CHm (m: 2-3) Configures whether to reset the clock divider of channel m. 0: No effect 1: Reset (WT) Espressif Systems 1370 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 37 Remote Control Peripheral (RMT) Register 37.7. RMT_CHnSTATUS_REG (n: 0-1) (0x0028+0x4*n) RMT_APB_MEM_RADDR_CHn 0x0 31 24 RMT_APB_MEM_WR_ERR_CHn 0 23 RMT_MEM_EMPTY_CHn 0 22 RMT_APB_MEM_RD_ERR_CHn 0 21 RMT_APB_MEM_WADDR_CHn 0 20 12 RMT_STATE_CHn 0 11 9 RMT_MEM_RADDR_EX_CHn 0 8 0 Reset RMT_MEM_RADDR_EX_CHn Represents the memory address offset when transmitter of channel n is using the RAM. (RO) RMT_STATE_CHn Represents the FSM status of channel n. (RO) RMT_APB_MEM_WADDR_CHn Represents the memory address offset when writes RAM over APB bus. (RO) RMT_APB_MEM_RD_ERR_CHn Represents whether the offset address exceeds memory size when reading via APB bus. 0: Not exceed 1: Exceed (RO) RMT_MEM_EMPTY_CHn Represents whether the TX data size exceeds the memory size and the wrap TX mode is disabled. 0: Not exceed 1: Exceed (RO) RMT_APB_MEM_WR_ERR_CHn Represents whether the offset address exceeds memory size (overflows) when writes via APB bus. 0: Not exceed 1: Exceed (RO) RMT_APB_MEM_RADDR_CHn Represents the memory address offset when reading RAM over APB bus. (RO) Espressif Systems 1371 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 37 Remote Control Peripheral (RMT) Register 37.8. RMT_CHmSTATUS_REG (m: 2-3) (0x0030+0x4*(m-2)) (reserved) 0 0 0 0 31 28 RMT_APB_MEM_RD_ERR_CHm 0 27 RMT_MEM_FULL_CHm 0 26 RMT_MEM_OWNER_ERR_CHm 0 25 RMT_STATE_CHm 0 24 22 (reserved) 0 21 RMT_APB_MEM_RADDR_CHm 0 20 12 (reserved) 0 0 0 11 9 RMT_MEM_WADDR_EX_CHm 0 8 0 Reset RMT_MEM_WADDR_EX_CHm Represents the memory address offset when receiver of channel m is using the RAM. (RO) RMT_APB_MEM_RADDR_CHm Represents the memory address offset when reads RAM over APB bus. (RO) RMT_STATE_CHm Represents the FSM status of channel m. (RO) RMT_MEM_OWNER_ERR_CHm Represents whether the ownership of memory block is wrong. 0: The ownership of memory block is correct 1: The ownership of memory block is wrong (RO) RMT_MEM_FULL_CHm Represents whether the receiver receives more data than the memory can fit. 0: The receiver does not receive more data than the memory can fit 1: The receiver receives more data than the memory can fit (RO) RMT_APB_MEM_RD_ERR_CHm Represents whether the offset address exceeds memory size (overflows) when reads RAM via APB bus. 0: Not exceed 1: Exceed (RO) Espressif Systems 1372 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 37 Remote Control Peripheral (RMT) Register 37.9. RMT_INT_RAW_REG (0x0038) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 14 RMT_CH1_TX_LOOP_INT_RAW 0 13 RMT_CH0_TX_LOOP_INT_RAW 0 12 RMT_CH3_RX_THR_EVENT_INT_RAW 0 11 RMT_CH2_RX_THR_EVENT_INT_RAW 0 10 RMT_CH1_TX_THR_EVENT_INT_RAW 0 9 RMT_CH0_TX_THR_EVENT_INT_RAW 0 8 RMT_CH3_ERR_INT_RAW 0 7 RMT_CH2_ERR_INT_RAW 0 6 RMT_CH1_ERR_INT_RAW 0 5 RMT_CH0_ERR_INT_RAW 0 4 RMT_CH3_RX_END_INT_RAW 0 3 RMT_CH2_RX_END_INT_RAW 0 2 RMT_CH1_TX_END_INT_RAW 0 1 RMT_CH0_TX_END_INT_RAW 0 0 Reset RMT_CHn_TX_END_INT_RAW (n: 0-1) The raw interrupt status of RMT_CHn_TX_END_INT. Trig- gered when the transmission is done. (R/WTC/SS) RMT_CHm_RX_END_INT_RAW (m: 2-3) The raw interrupt status of RMT_CHm_RX_END_INT. Trig- gered when the reception is done. (R/WTC/SS) RMT_CHn_ERR_INT_RAW (n: 0-3) The raw interrupt status of RMT_CHn/m_ERR_INT. Triggered when error occurs. (R/WTC/SS) RMT_CHn_TX_THR_EVENT_INT_RAW (n: 0-1) The raw interrupt status of RMT_CHn_TX_THR_EVENT_INT. Triggered when the transmitter sent more data than the configured value. (R/WTC/SS) RMT_CHm_RX_THR_EVENT_INT_RAW (m: 2-3) The raw interrupt status of RMT_CHm_RX_THR_EVENT_INT. Triggered when the receiver receives more data than the configured value. (R/WTC/SS) RMT_CHn_TX_LOOP_INT_RAW (n: 0-1) The raw interrupt status of RMT_CHn_TX_LOOP_INT. Trig- gered when the loop count reaches the configured threshold value. (R/WTC/SS) Espressif Systems 1373 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 37 Remote Control Peripheral (RMT) Register 37.10. RMT_INT_ST_REG (0x003C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 14 RMT_CH1_TX_LOOP_INT_ST 0 13 RMT_CH0_TX_LOOP_INT_ST 0 12 RMT_CH3_RX_THR_EVENT_INT_ST 0 11 RMT_CH2_RX_THR_EVENT_INT_ST 0 10 RMT_CH1_TX_THR_EVENT_INT_ST 0 9 RMT_CH0_TX_THR_EVENT_INT_ST 0 8 RMT_CH3_ERR_INT_ST 0 7 RMT_CH2_ERR_INT_ST 0 6 RMT_CH1_ERR_INT_ST 0 5 RMT_CH0_ERR_INT_ST 0 4 RMT_CH3_RX_END_INT_ST 0 3 RMT_CH2_RX_END_INT_ST 0 2 RMT_CH1_TX_END_INT_ST 0 1 RMT_CH0_TX_END_INT_ST 0 0 Reset RMT_CHn_TX_END_INT_ST (n: 0-1) The masked interrupt status of RMT_CHn_TX_END_INT. (RO) RMT_CHm_RX_END_INT_ST (m: 2-3) The masked interrupt status of RMT_CHm_RX_END_INT. (RO) RMT_CHn_ERR_INT_ST (n: 0-3) The masked interrupt status of RMT_CHn/m_ERR_INT. (RO) RMT_CHn_TX_THR_EVENT_INT_ST (n: 0-1) The masked interrupt status of RMT_CHn_TX_THR_EVENT_INT. (RO) RMT_CHm_RX_THR_EVENT_INT_ST (m: 2-3) The masked interrupt status of RMT_CHm_RX_THR_EVENT_INT. (RO) RMT_CHn_TX_LOOP_INT_ST (n: 0-1) The masked interrupt status of RMT_CHn_TX_LOOP_INT. (RO) Espressif Systems 1374 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 37 Remote Control Peripheral (RMT) Register 37.11. RMT_INT_ENA_REG (0x0040) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 14 RMT_CH1_TX_LOOP_INT_ENA 0 13 RMT_CH0_TX_LOOP_INT_ENA 0 12 RMT_CH3_RX_THR_EVENT_INT_ENA 0 11 RMT_CH2_RX_THR_EVENT_INT_ENA 0 10 RMT_CH1_TX_THR_EVENT_INT_ENA 0 9 RMT_CH0_TX_THR_EVENT_INT_ENA 0 8 RMT_CH3_ERR_INT_ENA 0 7 RMT_CH2_ERR_INT_ENA 0 6 RMT_CH1_ERR_INT_ENA 0 5 RMT_CH0_ERR_INT_ENA 0 4 RMT_CH3_RX_END_INT_ENA 0 3 RMT_CH2_RX_END_INT_ENA 0 2 RMT_CH1_TX_END_INT_ENA 0 1 RMT_CH0_TX_END_INT_ENA 0 0 Reset RMT_CHn_TX_END_INT_ENA (n: 0-1) Write 1 to enable RMT_CHn_TX_END_INT. (R/W) RMT_CHm_RX_END_INT_ENA (m: 2-3) Write 1 to enable RMT_CHm_RX_END_INT. (R/W) RMT_CHn_ERR_INT_ENA (n: 0-3) Write 1 to enable RMT_CHn/m_ERR_INT. (R/W) RMT_CHn_TX_THR_EVENT_INT_ENA (n: 0-1) Write 1 to enable RMT_CHn_TX_THR_EVENT_INT. (R/W) RMT_CHm_RX_THR_EVENT_INT_ENA (m: 2-3) Write 1 to enable RMT_CHm_RX_THR_EVENT_INT. (R/W) RMT_CHn_TX_LOOP_INT_ENA (n: 0-1) Write 1 to enable RMT_CHn_TX_LOOP_INT. (R/W) Espressif Systems 1375 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 37 Remote Control Peripheral (RMT) Register 37.12. RMT_INT_CLR_REG (0x0044) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 14 RMT_CH1_TX_LOOP_INT_CLR 0 13 RMT_CH0_TX_LOOP_INT_CLR 0 12 RMT_CH3_RX_THR_EVENT_INT_CLR 0 11 RMT_CH2_RX_THR_EVENT_INT_CLR 0 10 RMT_CH1_TX_THR_EVENT_INT_CLR 0 9 RMT_CH0_TX_THR_EVENT_INT_CLR 0 8 RMT_CH3_ERR_INT_CLR 0 7 RMT_CH2_ERR_INT_CLR 0 6 RMT_CH1_ERR_INT_CLR 0 5 RMT_CH0_ERR_INT_CLR 0 4 RMT_CH3_RX_END_INT_CLR 0 3 RMT_CH2_RX_END_INT_CLR 0 2 RMT_CH1_TX_END_INT_CLR 0 1 RMT_CH0_TX_END_INT_CLR 0 0 Reset RMT_CHn_TX_END_INT_CLR (n: 0-1) Write 1 to clear the RMT_CHn_TX_END_INT interrupt. (WT) RMT_CHm_RX_END_INT_CLR (m: 2-3) Write 1 to clear the RMT_CHm_RX_END_INT interrupt. (WT) RMT_CHn_ERR_INT_CLR (n: 0-3) Write 1 to clear the RMT_CHn/m_ERR_INT interrupt. (WT) RMT_CHn_TX_THR_EVENT_INT_CLR (n: 0-1) Write 1 to clear the RMT_CHn_TX_THR_EVENT_INT interrupt. (WT) RMT_CHm_RX_THR_EVENT_INT_CLR (m: 2-3) Write 1 to clear the RMT_CHm_RX_THR_EVENT_INT interrupt. (WT) RMT_CHn_TX_LOOP_INT_CLR (n: 0-1) Write 1 to clear the RMT_CHn_TX_LOOP_INT interrupt. (WT) Register 37.13. RMT_CHnCARRIER_DUTY_REG (n: 0-1) (0x0048+0x4*n) RMT_CARRIER_HIGH_CHn 0x40 31 16 RMT_CARRIER_LOW_CHn 0x40 15 0 Reset RMT_CARRIER_LOW_CHn Configures carrier wave’s low level clock period for channel n. Measurement unit: rmt_sclk (R/W) RMT_CARRIER_HIGH_CHn Configures carrier wave’s high level clock period for channel n. Measurement unit: rmt_sclk (R/W) Espressif Systems 1376 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 37 Remote Control Peripheral (RMT) Register 37.14. RMT_CHm_RX_CARRIER_RM_REG (m: 2-3) (0x0050+0x4*(m-2)) RMT_CARRIER_HIGH_THRES_CHm 0x00 31 16 RMT_CARRIER_LOW_THRES_CHm 0x00 15 0 Reset RMT_CARRIER_LOW_THRES_CHm Configures the low level period in a carrier modulation mode for channel m. The low level period in a carrier modulation mode is (RMT_CARRIER_LOW_THRES_CHm + 1) for channel m. Measurement unit: clk_div (R/W) RMT_CARRIER_HIGH_THRES_CHm Configures the high level period in a carrier modulation mode for channel m. The high level period in a carrier modulation mode is (RMT_CARRIER_HIGH_THRES_CHm + 1) for channel m. Measurement unit: clk_div (R/W) Espressif Systems 1377 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 37 Remote Control Peripheral (RMT) Register 37.15. RMT_CHn_TX_LIM_REG (n: 0-1) (0x0058+0x4*n) (reserved) 0 0 0 0 0 0 0 0 0 0 31 22 RMT_LOOP_STOP_EN_CHn 0 21 RMT_LOOP_COUNT_RESET_CHn 0 20 RMT_TX_LOOP_CNT_EN_CHn 0 19 RMT_TX_LOOP_NUM_CHn 0 18 9 RMT_TX_LIM_CHn 0x80 8 0 Reset RMT_TX_LIM_CHn Configures the maximum entries that channel n can send out. (R/W) RMT_TX_LOOP_NUM_CHn Configures the maximum loop count when Continuous TX mode is valid. (R/W) RMT_TX_LOOP_CNT_EN_CHn Configures whether to enable loop count. 0: No effect 1: Enable (R/W) RMT_LOOP_COUNT_RESET_CHn Configures whether to reset the loop count when tx_conti_mode is valid. 0: No effect 1: Reset (WT) RMT_LOOP_STOP_EN_CHn Configures whether to enable the loop send stop function after the loop counter counts to loop number for channel n. 0: No effect 1: Enable (R/W) Espressif Systems 1378 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 37 Remote Control Peripheral (RMT) Register 37.16. RMT_TX_SIM_REG (0x006C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 RMT_TX_SIM_EN 0 2 RMT_TX_SIM_CH1 0 1 RMT_TX_SIM_CH0 0 0 Reset RMT_TX_SIM_CHn (n: 0-1) Configures whether to enable channel n to start sending data syn- chronously with other enabled channels. 0: No effect 1: Enable (R/W) RMT_TX_SIM_EN Configures whether to enable multiple of channels to start sending data syn- chronously. 0: No effect 1: Enable (R/W) Register 37.17. RMT_CHm_RX_LIM_REG (m: 2-3) (0x0060+0x4*(m-2)) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 9 RMT_RX_LIM_CHm 0x80 8 0 Reset RMT_RX_LIM_CHm Configures the maximum entries that Channel m can receive. (R/W) Register 37.18. RMT_DATE_REG (0x00CC) (reserved) 0 0 0 0 31 28 RMT_DATE 0x2108213 27 0 Reset RMT_DATE Version control register. (R/W) Espressif Systems 1379 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 38 Parallel IO Controller (PARLIO) Chapter 38 Parallel IO Controller (PARLIO) 38.1 Introduction ESP32-C5 contains a Parallel IO controller (PARLIO) capable of transferring data between external devices and internal memory on a parallel bus through GDMA. It is composed of a TX unit and an RX unit, which are fixed as a transmitter and a receiver respectively. With the two units combined, PARLIO achieves full-duplex communication. Due to its flexibility, PARLIO can function as a general interface to connect various peripherals. For example, with SPI as the master device and PARLIO as the slave device, a peer-to-peer transfer can be achieved. For detailed application examples, refer to Section 38.8. 38.2 Glossary This section covers terminology used to describe the functionality of PARLIO. RX unit Module in PARLIO responsible for receiving data from external par- allel bus and storing them into internal memory. TX unit Module in PARLIO responsible for transmitting data from internal memory to external parallel bus. RXD Parallel data received from the IO interface of the RX unit. TXD Parallel data sent from the IO interface of the TX unit. Frame Transferred data unit from the moment the START signal is set to the moment the End of Frame (EOF) signal is received. Free-running clock Clock that toggles continuously. Otherwise, the clock only toggles during the period when valid data is received and remains constant for the rest of the time. GDMA SUC EOF Signal that indicates GDMA successful end of frame. When GDMA receives this signal, a GDMA interrupt will be triggered, indicating that the current frame is correct and the receive is finished. GDMA ERR EOF Signal that indicates GDMA error end of frame. When GDMA re- ceives this signal, a GDMA interrupt will be triggered, indicating that the current frame has error and the receive is finished. CDC Clock domain crossing. 38.3 Features The PARLIO module has the following main features: Espressif Systems 1380 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 38 Parallel IO Controller (PARLIO) • Variety of clock sources: – Including external IO clock PAD_CLK_TX/RX and internal system clocks XTAL_CLK, PLL_F240M_CLK, and RC_FAST_CLK – Maximum clock frequency of 40 MHz – Integer clock frequency division • 1/2/4/8-bit configurable data bus width • Full-duplex communication with 8-bit data bus width • Bit reversal when data bus width is 1/2/4-bit • RX unit for receiving IO parallel data, which supports: – Output clock gating – RX unit input and output clock inverse – Various receive modes – Configurable GDMA SUC EOF generation – Configurable IO pin of external enable signal • TX unit for sending IO parallel data, which supports: – Chip select function – Output clock gating – TX unit input and output clock inverse – Configurable bus idle value Espressif Systems 1381 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 38 Parallel IO Controller (PARLIO) 38.4 Architectural Overview Register Group Clock Generator XTAL_CLK PLL_F160M_CLK RC_FASK_CLK RX FIFO Control // TX FIFO Control // IO Bus // // RX FIFO_inf TX FIFO_inf RX FIFO TX FIFO RXD PAD_CLK_RX PAD_CLK_TX CLK_TX_out TXD AXI PARLIO CLK_TX CLK_RX // GDMA_push_inf // GDMA_pop_inf GDMA Clock Domains CLK_RX_out RX Core APB TX Core RX Unit TX Unit Figure 38.4-1. PARLIO Architecture Figure 38.4-1 shows the architecture of PARLIO. In addition to the RX unit and the TX unit, a group of status configuration registers is also included. The RX unit receives the RXD, stores it in an asynchronous FIFO after the serial-to-parallel conversion, and then stores the data to internal memory via GDMA. The TX unit fetches data from the internal memory via GDMA, stores it in an asynchronous FIFO, and outputs the data from the IO bus via the TXD signal after the parallel-to-serial conversion. 38.5 Functional Description 38.5.1 Clock Generator There are four input clock domains in PARLIO, namely, RX Core, TX Core, AHB, and APB, as shown in Figure 38.4-1. The status configuration register group works in the APB clock domain. The GDMA interface logic works in the AHB clock domain. RX Core and TX Core clock domains each have four clock sources for selection, i.e., the internal system clock sources XTAL_CLK, RC_FAST_CLK, PLL_F240M_CLK, and the external clock source (PAD_CLK_TX/RX), as shown in Figure 38.5-1. Clock sources can be selected by configuring PCR_PARL_CLK_RX_SEL and Espressif Systems 1382 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 38 Parallel IO Controller (PARLIO) PCR_PARL_CLK_TX_SEL. The clock can be divided by configuring PCR_PARL_CLK_RX_DIV_NUM and PCR_PARL_CLK_TX_DIV_NUM. The clock division factor can be configured up to (2 16 − 1). The input clock of the TX and RX units can be inverted. The operating clock of the TX and RX units can also be inverted before being output to IO. The TX and RX units also support clock gating of the output clock. PLL_F240M_CLK XTAL_CLK RC_FAST_CLK PAD_CLK_RX DIV CLK_RX_in INV CLK_RX DIV CLK_TX CLK_TX_out INV PCR_PARL_CLK_RX_SEL PCR_PARL_CLK_TX_SEL RX_INV TX_INV Clock Generator PLL_F240M_CLK XTAL_CLK RC_FAST_CLK PAD_CLK_TX Figure 38.5-1. PARLIO Clock Generation 38.5.2 Clock and Reset Restriction Due to the versatility of PARLIO, the PAD clocks of PARLIO (PAD_CLK_TX/RX) may come from different masters (external devices or internal clock sources). These clocks might be either free-running clock or not. If the clock is not free-running, some internal control signals of PARLIO cannot process CDC, so there are certain restrictions during the operation. 1. During the reset of the asynchronous FIFO, it takes two clock cycles to initialize FIFO. Therefore, if the reset of AHB clock domain is performed with a clock that is not free-running, the reset synchronization must be performed two clock cycles in advance. The specific operation is shown in the table below. Table 38.5-1. Operations to Reset AHB Clock Domain with Clock Restrictions Clock Restriction The Current Frame The Next Frame Specific Operation Free-running clock Not free-running clock Users can reset the next frame transfer before switching to the clock that is not free-running. After the reset is com- pleted, users can switch the clock. Not free-running clock Free-running clock The next frame can be reset freely. Users only need to ensure that there is an interval of two clock cycles between the reset and the start of the transfer. Not free-running clock Not free-running clock If the next frame transfer needs to be reset, users need to first switch to the internal free-running clock, and then switch to the actual clock after the reset is completed. Espressif Systems 1383 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 38 Parallel IO Controller (PARLIO) 2. Due to the restrictions caused by a clock that is not free-running, PARL_IO_RX_START and PARL_IO_TX_START cannot perform CDC processing. Therefore, it is necessary to wait until PARL_IO_RX_START and PARL_IO_TX_START are stable before starting the data transfer, otherwise the transfer might enter a metastable state. Here are the specific operation steps in the RX unit: (a) Clear PCR_PARL_CLK_RX_EN to turn off RX Core clock domain; (b) Write 1 to PARL_IO_RX_START; (c) Set PCR_PARL_CLK_RX_EN to turn on RX Core clock domain; (d) Operate the external device to start sending data; (e) Clear PCR_PARL_CLK_RX_EN to turn off RX Core clock domain; (f) Write 0 to PARL_IO_RX_START. Here are the specific operation steps in the TX unit: (a) Clear PCR_PARL_CLK_TX_EN to turn off TX Core clock domain; (b) Write 1 to PARL_IO_TX_START; (c) Set PCR_PARL_CLK_TX_EN to turn on TX Core clock domain; (d) Operate the external device to start receiving data; (e) Clear PCR_PARL_CLK_TX_EN to turn off TX Core clock domain; (f) Write 0 to PARL_IO_TX_START. 3. Reset should follow the requirements below: • The clock reset during the chip start-up should follow the sequence below: (a) Reset APB clock domain; (b) Reset AHB clock domain; (c) Reset Core clock domain. • Inter-frame transfer requires Core clock domain reset and async FIFO reset. 38.5.3 Master-Slave Mode The TX and RX units can function as both master and slave. When the TX unit serves as master, it is necessary to set the internal free-running clock as the clock source. The TX unit drives TXD on the rising edge of the clock. When the TX unit functions as a slave device, there are three scenarios, as shown in the table below. Espressif Systems 1384 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 38 Parallel IO Controller (PARLIO) Table 38.5-2. Requirements for TX Unit Operating as Slave with Clock Restrictions Clock Restriction Clock Sent by Master Clock Waveform Requirement Free-running clock Any waveform There is no requirement for the sampling edge of the master clock. Not free-running clock Positive waveform (Figure 38.5-2) The master clock should sample TXD at the falling edge. Not free-running clock Negative waveform (Figure 38.5-3) The master device should invert the original clock and con- vert it to the waveform as Figure 38.5-2 shows before output. Figure 38.5-2. Positive Waveform Figure 38.5-3. Negative Waveform When the RX unit serves as the master, it is required to set the clock source as the internal free-running clock. The RX unit drives RXD on the rising edge of the clock. When the RX unit functions as the slave, there are three scenarios, as shown in the table below. Table 38.5-3. Requirements for RX Unit Operating as Slave with Clock Restrictions Clock Restriction Clock Sent by Master Clock Waveform Requirement Free-running clock Any waveform There is no requirement for the sampling edge of the master clock, and the valid data is subject to the external enable signal. Not free-running clock Positive waveform (Figure 38.5-2) It is required for the master device to drive the data at the rising edge and the RX unit to sample the data at the falling edge (i.e., to inverse the master clock). Not free-running clock Negative waveform (Figure 38.5-3) It is required for the master device to drive the data at the falling edge and the RX unit to sample the data at the rising edge (i.e., to use the original master clock). 38.5.4 Receive Modes of the RX Unit PARLIO supports 8 receive modes, which can be divided into three major categories according to the enable signal: • Level Enable mode: data received is enabled by the external signal level; Espressif Systems 1385 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 38 Parallel IO Controller (PARLIO) • Pulse Enable mode: data received is enabled by the external signal pulse; • Software Enable mode: the enable signal of data received can be configured by users directly. The RX unit also supports inverse of the external enable signal. If the external enable signal is active-low, users can enable the function by setting PARL_IO_RX_EXT_EN_INV to switch to the corresponding receive mode introduced as follows. 38.5.4.1 Level Enable Mode Figure 38.5-4 shows the Level Enable mode. In this mode, an active level on the external enable signal must be aligned with valid data. Since the external level enable signal occupies one IO pin, there are at most 7 IO pins left usable for RXD. Mode LEVEL_ENABLE Description signal level high Valid data signal level low Valid data Sub-mode sub-mode 1 sub-mode 2 Figure 38.5-4. Sub-Modes of Level Enable Mode for RX Unit 38.5.4.2 Pulse Enable Mode Pulse Enable mode can be divided into 6 sub-modes depending on the pulse active level and its alignment with valid data. For detailed classification, see Figure 38.5-5. Sub-modes 1 4 all contain start pulse and end pulse. The difference lies in whether start pulse and end pulse are aligned with valid data. Sub-modes 5 6 only contain start pulse and the end of valid data is signaled by configuring PARL_IO_RX_BITLEN. Since the external pulse enable signal occupies one IO pin, there are at most 7 IO pins left usable for RXD. However, in sub-modes 4 and 6, as the data is considered valid before the pulse’s first edge and after the pulse’s last edge, the enable signal IO pin can serve as a data IO pin at the same time. Therefore, there are 8 IO pins usable for RXD in these two sub-modes. Espressif Systems 1386 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 38 Parallel IO Controller (PARLIO) Figure 38.5-5. Sub-Modes of Pulse Enable Mode for RX Unit 38.5.4.3 Software Enable Mode The enable signal in Software Enable mode is determined by the internal configuration register. If users switch to this mode, the receive will only be activated when both PARL_IO_RX_SW_EN and PARL_IO_RX_START are set to 1. Since the enable signal does not occupy IO pins on the interface, there are at most 8 IO pins usable by the RXD. Due to the differences of clock domains, the enable signal cannot be aligned with valid data. Thus, the validity of data needs to be identified by the valid clock edge. In this case, the RX Core clock needs to be aligned with valid data. SW_ENABLE / Valid data / Mode DescriptionSub-mode Figure 38.5-6. Sub-Mode of Software Enable Mode for RX Unit 38.5.5 RX Unit GDMA SUC EOF Generation The RX unit generates a GDMA SUC EOF signal to indicate the end of current frame transfer and send it to the GDMA interface. GDMA SUC EOF can be generated by an external enable signal or triggered by the internally configured bit length. • When GDMA SUC EOF is generated by the internally configured bit length, there is no restriction on the receive mode selection, but PARL_IO_RX_BITLEN must be configured. If the configured value of PARL_IO_RX_BITLEN is less than the actual received data, the GDMA SUC EOF will be triggered in Espressif Systems 1387 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 38 Parallel IO Controller (PARLIO) advance. In this case, the RX unit stops reading data from the FIFO, but the FIFO continues to receive external data until an RX_FIFO_WOVF_INT interrupt is triggered. • When GDMA SUC EOF is generated by the external enable signal, only sub-modes 1 and 3 of Pulse Enable mode can be selected. In this mode, the transfer is not affected by the value of PARL_IO_RX_BITLEN, and the transferred data length of the frame is not limited. 38.5.6 RX Unit Timeout The RX unit supports receive timeout. If the RX FIFO has not been receiving valid data for a long time, a timeout will be triggered. In such case, a GDMA ERR EOF signal will be generated and sent to the GDMA interface to indicate the end of the reception. Configure PARL_IO_RX_TIMEOUT_THRES to set the timeout threshold. The timeout function is enabled by default and can be disabled by users. The upper threshold of the configurable timeout is (2 16 − 1) cycles of GDMA clock domain, and the lower threshold depends on the relative frequency relationship between GDMA clock domain and RX Core clock domain. It is recommended to set a relatively large value for PARL_IO_RX_TIMEOUT_THRES to avoid undesired GDMA ERR EOF signals. 38.5.7 Unlimited Length Data Transmission of TX Unit By default, the end of transmission for the TX unit is determined by the configured value of PARL_IO_TX_BITLEN. When the transmitted data reaches the configured value, the system generates a GDMA SUC EOF interrupt signal, indicating the completion of the current data frame transmission. This approach limits the maximum length of a single frame transmission to the bit width defined by PARL_IO_TX_BITLEN, preventing it from achieving unlimited length data transmission. To enable larger single-frame transmissions, set PARL_IO_TX_EOF_GEN_SEL to 1. In this mode, the hardware uses the EOF configured in the GDMA inlink list as the end-of-transmission signal for a single frame. As a result, data transmission is no longer constrained by the bit width of PARL_IO_TX_BITLEN, allowing for significantly larger data frames. 38.5.8 TX Chip Select Function To emulate the LCD I8080 protocol, the TX unit is equipped with an output chip select (CS) signal, which is active low. Configure PARL_IO_TX_CS_START_DELAY and PARL_IO_TX_CS_STOP_DELAY to control the phase relationship between the DMA output data and the CS signal. Note that when clock gating is enabled and the CS signal is used as the control source for clock gating, configuring these two registers not only implements the basic function, but also allows control over the phase relationship between the output clock and the CS signal. 38.5.9 Output Clock Gating of TX Unit The TX unit supports output clock gating. The clock gating function is disabled by default, and can be enabled by software via setting PARL_IO_TX_GATING_EN. Currently, the most significant bit (MSB) of TXD can be configured to be controlled by one of two sources: DMA output data or the chip select signal (CS). Set PARL_IO_TX_VALID_OUTPUT_EN to 0 to select the DMA output data as the control source. In this case, the TX unit must be configured with the maximum bit width, because when the control source is the DMA output data, the gating signal is fixed to the MSB of TXD. The clock signal can be toggled when this bit is at a high level. Note that when selecting DMA output data as the control source, if Espressif Systems 1388 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 38 Parallel IO Controller (PARLIO) the peripheral is in an idle state, the clock gating will be controlled by the MSB of the user-configured bus idle value. For configuration guidelines, refer to Section 38.5.10 Bus Idle Value of TX Unit. When the gating function is enabled while using DMA output data as the control source, there are at most 7 IO pins left usable for TXD as the gating signal occupies one IO. Set PARL_IO_TX_VALID_OUTPUT_EN to 1 to select the chip select signal (CS) as the control source. In this case, there is no limit to the bit width. 38.5.10 Bus Idle Value of TX Unit The TX unit is regarded as in idle state when it is not transmitting data. It supports a configurable bus idle value. Note that the configured idle value should not conflict with other enabled functions. For example, when the MSB of TXD is used as the valid signal, users should avoid configuring the MSB of the idle value as 1. 38.5.11 Data Transfer in a Single Frame The RX unit and the TX unit transfer data in the unit of bits, i.e., a single frame transfers 1 bit of data at least. When the RX unit generates GDMA EOF signals through bit length, the maximum length of the single-frame transmission is (2 19 − 1) bits. When the RX unit generates GDMA EOF signals through the enable signal from an external device, there is no limit to the amount of bits of the single-frame transmission. The TX unit only generates GDMA EOF signals through byte length, so the maximum length of a single frame transmission is (2 19 − 1) bytes. Since PARLIO transfers data in the unit of bytes on the GDMA side, it will process the IO data when it is not aligned with the bytes. • When receiving data, PARLIO will automatically pad 0 to the high bits of the data stored in memory via GDMA to make it aligned with bytes. • When sending data, PARLIO will truncate the data retrieved from memory according to the configured value of PARL_IO_TX_BITLEN. Data exceeding the value will not be sent. When the configured data bus width is 2/4/8-bit, the bit length must be configured as a multiple of the corresponding bus width. 38.5.12 Bit Reversal in One Byte The sequence of data within one byte can be reversed when data bus width is 1/2/4-bit. Taking the RX unit as an example, when the configured bus width is 2 bits, the data needs to be packed into one byte before being written into the RX FIFO. Presume that the original bit sequence is: {{b 0 , b 1 }, {b 2 , b 3 }, {b 4 , b 5 }, {b 6 , b 7 }} If the bit reversal is enabled, the sequence will be reordered to: {{b 6 , b 7 }, {b 4 , b 5 }, {b 2 , b 3 }, {b 0 , b 1 }} Espressif Systems 1389 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 38 Parallel IO Controller (PARLIO) 38.6 Interrupts ESP32-C5’s PARLIO module can generate the following interrupt signals that will be sent to the Interrupt Matrix. • PARL_IO_TX_INTR • PARL_IO_RX_INTR There are several internal interrupt sources from PARLIO that can generate the above interrupt signals. The interrupt sources from PARLIO are listed with their trigger conditions and the resulted interrupt signals in Table 38.6-1. Table 38.6-1. PARLIO’s Internal Interrupt Sources Internal Interrupt Source Trigger Condition Interrupt Signal TX_FIFO_REMPTY_INT TX FIFO is empty, indicating possible error in the data sent by TX PARL_IO_TX_INTR RX_FIFO_WOVF_INT RX FIFO is full, indicating possible error in the data received by RX PARL_IO_RX_INTR TX_EOF_INT TX finishes sending a complete frame of data PARL_IO_TX_INTR Note: For definitions of interrupt, interrupt signal, interrupt source, and their correlations, please refer to Chapter 9 Interrupt Matrix > Section 9.2 Terminology. Each interrupt source can be configured by a common set of registers that are described in Section Interrupt Configuration Registers. The specific registers can be found in Section 38.9 Register Summary. 38.7 Programming Procedures 38.7.1 Data Receiving Operation Process This section introduces the programming procedure for receiving data in the RX unit. Perform the following procedure to receive parallel data from IO pins connected to external devices to be stored in the internal memory. For detailed description of the clock and reset operation restrictions in the RX unit, refer to Section 38.5.2. 1. Reset the RX unit. For specific reset scenarios and sequences, refer to Section 38.5.2. 2. Set PARL_IO_RX_FIFO_WOVF_INT_CLR and PARL_IO_RX_FIFO_WOVF_INT_ENA. 3. Select the RXD IO pins. If a PAD clock is used, the clock IO pin also needs to be configured. 4. Select the clock source and divide the clock by configuring PCR registers. 5. Turn off the clock of RX Core clock domain. 6. Select the receive mode and enable functions required as described in Sections 38.3 and 38.5. 7. Configure GDMA inlink list. 8. Set PARL_IO_RX_REG_UPDATE to synchronize the register signals. Espressif Systems 1390 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 38 Parallel IO Controller (PARLIO) 9. Set PARL_IO_RX_START. 10. Turn on the clock of RX Core clock domain. 11. Operate the external device to start sending data. 12. Poll the GDMA SUC EOF interrupt. 13. Clear the GDMA SUC EOF interrupt. 14. Turn off the clock of RX Core clock domain. 15. Clear PARL_IO_RX_START. 38.7.2 Data Transmitting Operation Process This section introduces the programming procedure for transmitting data in the TX unit. Perform the following procedure to transmit parallel data from internal memory to the IO pins connected to external devices. For detailed description of the clock and reset operation restrictions in the TX unit, refer to Section 38.5.2. 1. Reset the TX unit. For specific reset scenarios and sequences, refer to Section 38.5.2. 2. Set PARL_IO_TX_FIFO_REMPTY_INT_CLR, PARL_IO_TX_EOF_INT_CLR, PARL_IO_TX_FIFO_REMPTY_INT_ENA, and PARL_IO_TX_EOF_INT_ENA consecutively. 3. Select the TXD IO pins. If a PAD clock is used, the clock IO PAD also needs to be configured. 4. Select the clock source and divide the clock by configuring PCR registers. 5. Turn off the clock of TX Core clock domain. 6. Select the functions required as described in Section 38.5. 7. Configure GDMA outlink list. 8. Poll the PARL_IO_TX_READY. 9. Set PARL_IO_TX_START. 10. Turn on the clock of TX Core clock domain. 11. Operate the external device to start receiving data. 12. Poll the PARL_IO_TX_EOF_INT_ST. 13. Set PARL_IO_TX_EOF_INT_CLR. 14. Turn off the clock of TX Core clock domain. 15. Clear PARL_IO_TX_START. 38.8 Application Examples This section introduces some PARLIO application examples and their detailed operation process. All peripherals used in the examples are from ESP series chips and can work with PARLIO to form a complete data path. Note: The data paths constructed in the examples may not be the optimal. For example, users can use the SPI peripherals Espressif Systems 1391 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 38 Parallel IO Controller (PARLIO) on two identical ESP chips to complete the peer-to-peer transfer in real case instead of using PARLIO to work with SPI. However, these examples demonstrate the flexibility of the PARLIO interface to a certain extent. 38.8.1 Co-working with SPI In this example, external SPI sends data as a master device and PARLIO RX unit receives data as a slave device, and at the same time, PARLIO TX sends data as a master device and SPI receives data as a slave device, thus achieving a peer-to-peer serial data transfer. • Follow the operation process below to achieve SPI transmit and PARLIO receive: 1. Configure SPI clock. 2. Configure SPI as the master device. 3. Configure signal pins. Connect FSPICLK to PAD_CLK_RX, FSPICS0 to RXD[7], and FSPID to RXD[0]. 4. Write the data sent into the SPI buffer and configure the bit length of the data sent. 5. Set SPI_UPDATE to update the configured register value. 6. Reset PARLIO RX unit. 7. Configure PARLIO RX unit clock. 8. Turn off the PARLIO RX Core clock domain. 9. Configure PARLIO receive mode as sub-mode 1 of Level Enable mode. Configure RX unit data bus width as 1 bit. Configure PARL_IO_RX_BITLEN according to the sending length of SPI. Set PARL_IO_RX_REG_UPDATE. 10. Configure PARLIO GDMA inlink list. 11. Set PARL_IO_RX_START. 12. Turn on the PARLIO RX Core clock domain. 13. Set SPI_USR to start transmitting data of SPI. 14. Poll GDMA SUC EOF interrupt. 15. Clear PARL_IO_RX_START. • Follow the operation process below to achieve PARLIO transmit and SPI receive: 1. Configure SPI clock. 2. Configure SPI as the slave device. 3. Configure signal pins. Connect FSPICLK to PAD_CLK_TX, FSPICS0 to TXD[7], and FSPID to TXD[0]. 4. Set SPI_RD_BIT_ORDER to invert the bit order. 5. Set SPI_UPDATE to update the configured register value. 6. Reset PARLIO TX unit. 7. Set PARL_IO_TX_EOF_INT_CLR and PARL_IO_TX_EOF_INT_ENA. 8. Configure PARLIO TX unit clock. Espressif Systems 1392 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 38 Parallel IO Controller (PARLIO) 9. Turn off the clock of TX Core clock domain. 10. Configure data bus width as 1 bit. Write 1 to PARL_IO_TX_VALID_OUTPUT_EN. Configure PARL_IO_TX_BITLEN. 11. Configure GDMA outlink list. 12. Poll PARL_IO_TX_READY. 13. Write 1 to PARL_IO_TX_START. 14. Turn on the clock of TX Core clock domain. 15. Start data transfer. 16. Poll PARL_IO_TX_EOF_INT_ST. 17. Set PARL_IO_TX_EOF_INT_CLR. 18. Turn off the clock of TX Core clock domain. 19. Clear PARL_IO_TX_START. 38.8.2 Co-working with I2S In this example, external I2S sends data as a master device and PARLIO RX unit receives data as a slave device. PARLIO supports the transmission of the I2S TDM MSB alignment standard and the TDM PCM standard. When the I2S transfer protocol is the TDM MSB alignment standard, it is required to configure the receive mode of PARLIO as Level Enable mode. When the I2S transfer protocol is the TDM PCM standard, it is required to configure the receive mode of PARLIO as the sub-mode 10 of Pulse Enable mode and set PARL_IO_RX_EXT_EN_INV. This section takes the TDM PCM alignment standard as an example. The specific operation process is as follows: 1. Configure I2S clock. 2. Configure signal pins. Connect I2SO_BCK_out to PAD_CLK_RX, I2SO_WS_out to RXD[7], and I2SO_Data_out to RXD[0]. 3. Configure I2S as the master device. 4. Configure the I2S TX data mode and channel mode required. Set I2S_TX_UPDATE. 5. Reset I2S TX unit and TX FIFO. 6. Enable I2S_TX_DONE_INT. 7. Configure I2S GDMA outlink list. 8. Set I2S_TX_STOP_EN. 9. Reset PARLIO RX unit. 10. Configure PARLIO RX unit clock. 11. Turn off PARLIO RX Core clock domain. Espressif Systems 1393 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 38 Parallel IO Controller (PARLIO) 12. Configure PARLIO receive mode as sub-mode 4 of Pulse Enable mode. Configure the RX unit data bus width as 1 bit. Configure PARL_IO_RX_BITLEN according to the length of the data sent by I2S. Set PARL_IO_RX_REG_UPDATE. 13. Configure PARLIO GDMA inlink list. 14. Set PARL_IO_RX_START. 15. Turn on PARLIO RX Core clock domain. 16. Set I2S_TX_START to start transmitting data. 17. Poll I2S_TX_DONE_INT. 18. Poll GDMA SUC EOF interrupt. 19. Clear I2S_TX_START. 20. Clear PARL_IO_RX_START. Espressif Systems 1394 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 38 Parallel IO Controller (PARLIO) 38.9 Register Summary The addresses in this section are relative to Parallel IO Controller base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access PARLIO RX Configuration Registers PARL_IO_RX_MODE_CFG_REG PARLIO RX sampling mode configuration register 0x0000 R/W PARL_IO_RX_DATA_CFG_REG PARLIO RX data configuration register 0x0004 R/W PARL_IO_RX_GENRL_CFG_REG PARLIO RX general configuration register 0x0008 R/W PARL_IO_RX_START_CFG_REG PARLIO RX start configuration register 0x000C R/W PARLIO TX Configuration Registers PARL_IO_TX_DATA_CFG_REG PARLIO TX data configuration register 0x0010 R/W PARL_IO_TX_START_CFG_REG PARLIO TX start configuration register 0x0014 R/W PARL_IO_TX_GENRL_CFG_REG PARLIO TX general configuration register 0x0018 R/W PARLIO Configuration and Status Registers PARL_IO_FIFO_CFG_REG PARLIO FIFO configuration register 0x001C R/W PARL_IO_REG_UPDATE_REG PARLIO register update configuration register 0x0020 WT PARL_IO_ST_REG PARLIO module status register 0x0024 RO PARLIO Interrupt Configuration and Status Registers PARL_IO_INT_ENA_REG PARLIO interrupt enable signal configuration register 0x0028 R/W PARL_IO_INT_RAW_REG PARLIO interrupt raw signal status register 0x002C R/SS/WTC PARL_IO_INT_ST_REG PARLIO interrupt signal status register 0x0030 RO PARL_IO_INT_CLR_REG PARLIO interrupt clear signal configuration register 0x0034 WT PARLIO RX/TX Status Registers PARL_IO_RX_ST0_REG PARLIO RX status register 0 0x0038 RO PARL_IO_RX_ST1_REG PARLIO RX status register 1 0x003C RO PARL_IO_TX_ST0_REG PARLIO TX status register 0 0x0040 RO PARLIO Clock Configuration Registers PARL_IO_RX_CLK_CFG_REG PARLIO RX clock configuration register 0x0044 R/W PARL_IO_TX_CLK_CFG_REG PARLIO TX clock configuration register 0x0048 R/W PARL_IO_CLK_REG PARLIO clock configuration register 0x0120 R/W PARLIO TX CS Configuration Register PARL_IO_TX_CS_CFG_REG PARLIO TX CS configuration register 0x004C R/W PARLIO Version Register PARL_IO_VERSION_REG Version control register 0x03FC R/W Espressif Systems 1395 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 38 Parallel IO Controller (PARLIO) 38.10 Registers The addresses in this section are relative to Parallel IO Controller base address provided in Table 4.3-2 in Chapter 4 System and Memory. Register 38.1. PARL_IO_RX_MODE_CFG_REG (0x0000) PARL_IO_RX_SMP_MODE_SEL 0x0 31 30 PARL_IO_RX_PULSE_SUBMODE_SEL 0x0 29 27 PARL_IO_RX_EXT_EN_INV 0 26 PARL_IO_RX_SW_EN 0 25 PARL_IO_RX_EXT_EN_SEL 0x7 24 21 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 0 Reset PARL_IO_RX_EXT_EN_SEL Configures the RX external enable signal from IO pins. (R/W) PARL_IO_RX_SW_EN Configures whether to enable data sampling by software. 0: Disable 1: Enable (R/W) PARL_IO_RX_EXT_EN_INV Configures whether to invert the external enable signal. 0: No effect 1: Invert (R/W) PARL_IO_RX_PULSE_SUBMODE_SEL Configures the RXD pulse sampling sub-mode. 0: Positive pulse start (data bit included) & Positive pulse end (data bit included) 1: Positive pulse start (data bit included) & Positive pulse end (data bit excluded) 2: Positive pulse start (data bit excluded) & Positive pulse end (data bit included) 3: Positive pulse start (data bit excluded) & Positive pulse end (data bit excluded) 4: Positive pulse start (data bit included) & Length end 5: Positive pulse start (data bit excluded) & Length end 6 7: Invalid (R/W) PARL_IO_RX_SMP_MODE_SEL Configures the RXD sampling mode. 0: External Level Enable mode 1: External Pulse Enable mode 2: Internal Software Enable mode 3: Invalid (R/W) Espressif Systems 1396 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 38 Parallel IO Controller (PARLIO) Register 38.2. PARL_IO_RX_DATA_CFG_REG (0x0004) PARL_IO_RX_BUS_WID_SEL 0x3 31 29 PARL_IO_RX_DATA_ORDER_INV 0 28 PARL_IO_RX_BITLEN 0x000 27 9 (reserved) 0 0 0 0 0 0 0 0 0 8 0 Reset PARL_IO_RX_BITLEN Configures the expected bit number of RXD. (R/W) PARL_IO_RX_DATA_ORDER_INV Configures whether to invert the bit order of one byte sent from RX FIFO to GDMA. 0: No effect 1: Invert (R/W) PARL_IO_RX_BUS_WID_SEL Configures the RXD bus width. 0: 1 bit 1: 2 bits 2: 4 bits 3: 8 bits 4 15: Invalid and will incur error (R/W) Espressif Systems 1397 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 38 Parallel IO Controller (PARLIO) Register 38.3. PARL_IO_RX_GENRL_CFG_REG (0x0008) (reserved) 0 31 PARL_IO_RX_EOF_GEN_SEL 0 30 PARL_IO_RX_TIMEOUT_EN 1 29 PARL_IO_RX_TIMEOUT_THRES 0xfff 28 13 PARL_IO_RX_GATING_EN 0 12 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 11 0 Reset PARL_IO_RX_GATING_EN Configures whether to enable the clock gating of the RX output clock. 0: Disable 1: Enable (R/W) PARL_IO_RX_TIMEOUT_THRES Configures the threshold of the RX timeout counter. (R/W) PARL_IO_RX_TIMEOUT_EN Configures whether to enable the timeout function to generate GDMA ERR EOF. 0: Disable 1: Enable (R/W) PARL_IO_RX_EOF_GEN_SEL Configures the generation mechanism of GDMA SUC EOF. 0: Generate GDMA SUC EOF by the configured data bit length 1: Generate GDMA SUC EOF by the external enable signal (R/W) Register 38.4. PARL_IO_RX_START_CFG_REG (0x000C) PARL_IO_RX_START 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 0 Reset PARL_IO_RX_START Configures whether to start RX data sampling. 0: No effect 1: Start (R/W) Espressif Systems 1398 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 38 Parallel IO Controller (PARLIO) Register 38.5. PARL_IO_TX_DATA_CFG_REG (0x0010) PARL_IO_TX_BUS_WID_SEL 0x3 31 29 PARL_IO_TX_DATA_ORDER_INV 0 28 PARL_IO_TX_BITLEN 0x000 27 9 (reserved) 0 0 0 0 0 0 0 0 0 8 0 Reset PARL_IO_TX_BITLEN Configures the expected bit number of TXD. (R/W) PARL_IO_TX_DATA_ORDER_INV Configures whether to invert the bit order of one byte sent from TX FIFO to IO data. 0: No effect 1: Invert (R/W) PARL_IO_TX_BUS_WID_SEL Configures the TXD bus width. 0: 1 bit 1: 2 bits 2: 4 bits 3: 8 bits 4 15: Invalid and will incur error (R/W) Register 38.6. PARL_IO_TX_START_CFG_REG (0x0014) PARL_IO_TX_START 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 0 Reset PARL_IO_TX_START Configures whether to start TX data transmission. 0: No effect 1: Start (R/W) Espressif Systems 1399 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 38 Parallel IO Controller (PARLIO) Register 38.7. PARL_IO_TX_GENRL_CFG_REG (0x0018) PARL_IO_TX_VALID_OUTPUT_EN 0 31 PARL_IO_TX_GATING_EN 0 30 PARL_IO_TX_IDLE_VALUE 0x00 29 14 PARL_IO_TX_EOF_GEN_SEL 0 13 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 12 0 Reset PARL_IO_TX_EOF_GEN_SEL Configures the generation mechanism of TX EOF. 0: Generate TX EOF by the configured data bit length 1: Generate TX EOF by the GDMA EOF signal. (R/W) PARL_IO_TX_IDLE_VALUE Configures the data value on TX bus in idle state. (R/W) PARL_IO_TX_GATING_EN Configures whether to enable the clock gating of the TX output clock. 0: Disable 1: Enable (R/W) PARL_IO_TX_VALID_OUTPUT_EN Configures whether to select DMA output data or the chip select signal (CS) as the control source of TXD MSB. 0: Select the DMA output data as the control source 1: Select the chip select signal (CS) as the control source (R/W) Register 38.8. PARL_IO_FIFO_CFG_REG (0x001C) PARL_IO_RX_FIFO_SRST 0 31 PARL_IO_TX_FIFO_SRST 0 30 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29 0 Reset PARL_IO_TX_FIFO_SRST Configures whether to reset async FIFO in the TX unit. 0: No effect 1: Reset (R/W) PARL_IO_RX_FIFO_SRST Configures whether to reset async FIFO in the RX unit. 0: No effect 1: Reset (R/W) Espressif Systems 1400 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 38 Parallel IO Controller (PARLIO) Register 38.9. PARL_IO_REG_UPDATE_REG (0x0020) PARL_IO_RX_REG_UPDATE 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 0 Reset PARL_IO_RX_REG_UPDATE Configures whether to update RX register configuration. 0: No effect 1: Update (WT) Register 38.10. PARL_IO_ST_REG (0x0024) PARL_IO_TX_READY 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 0 Reset PARL_IO_TX_READY Represents whether TX is ready to transmit data. 0: Not ready 1: Ready (RO) Register 38.11. PARL_IO_INT_ENA_REG (0x0028) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PARL_IO_TX_EOF_INT_ENA 0 2 PARL_IO_RX_FIFO_WOVF_INT_ENA 0 1 PARL_IO_TX_FIFO_REMPTY_INT_ENA 0 0 Reset PARL_IO_TX_FIFO_REMPTY_INT_ENA Write 1 to enable TX_FIFO_REMPTY_INT. (R/W) PARL_IO_RX_FIFO_WOVF_INT_ENA Write 1 to enable RX_FIFO_WOVF_INT. (R/W) PARL_IO_TX_EOF_INT_ENA Write 1 to enable TX_EOF_INT. (R/W) Espressif Systems 1401 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 38 Parallel IO Controller (PARLIO) Register 38.12. PARL_IO_INT_RAW_REG (0x002C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PARL_IO_TX_EOF_INT_RAW 0 2 PARL_IO_RX_FIFO_WOVF_INT_RAW 0 1 PARL_IO_TX_FIFO_REMPTY_INT_RAW 0 0 Reset PARL_IO_TX_FIFO_REMPTY_INT_RAW The raw interrupt status of TX_FIFO_REMPTY_INT. (R/WTC/SS) PARL_IO_RX_FIFO_WOVF_INT_RAW The raw interrupt status of RX_FIFO_WOVF_INT. (R/WTC/SS) PARL_IO_TX_EOF_INT_RAW The raw interrupt status of TX_EOF_INT. (R/WTC/SS) Register 38.13. PARL_IO_INT_ST_REG (0x0030) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PARL_IO_TX_EOF_INT_ST 0 2 PARL_IO_RX_FIFO_WOVF_INT_ST 0 1 PARL_IO_TX_FIFO_REMPTY_INT_ST 0 0 Reset PARL_IO_TX_FIFO_REMPTY_INT_ST The masked interrupt status of TX_FIFO_REMPTY_INT. (RO) PARL_IO_RX_FIFO_WOVF_INT_ST The masked interrupt status of RX_FIFO_WOVF_INT. (RO) PARL_IO_TX_EOF_INT_ST The masked interrupt status of TX_EOF_INT. (RO) Espressif Systems 1402 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 38 Parallel IO Controller (PARLIO) Register 38.14. PARL_IO_INT_CLR_REG (0x0034) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 3 PARL_IO_TX_EOF_INT_CLR 0 2 PARL_IO_RX_FIFO_WOVF_INT_CLR 0 1 PARL_IO_TX_FIFO_REMPTY_INT_CLR 0 0 Reset PARL_IO_TX_FIFO_REMPTY_INT_CLR Write 1 to clear TX_FIFO_REMPTY_INT. (WT) PARL_IO_RX_FIFO_WOVF_INT_CLR Write 1 to clear RX_FIFO_WOVF_INT. (WT) PARL_IO_TX_EOF_INT_CLR Write 1 to clear TX_EOF_INT. (WT) Register 38.15. PARL_IO_RX_ST0_REG (0x0038) PARL_IO_RX_FIFO_WR_BIT_CNT 0x000 31 13 PARL_IO_RX_CNT 0x0 12 8 (reserved) 0 0 0 0 0 0 0 0 7 0 Reset PARL_IO_RX_CNT Represents the clock cycle number of reading the RX FIFO. (RO) PARL_IO_RX_FIFO_WR_BIT_CNT Represents the bit number currently written into the RX FIFO. (RO) Register 38.16. PARL_IO_RX_ST1_REG (0x003C) PARL_IO_RX_FIFO_RD_BIT_CNT 0x000 31 13 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 12 0 Reset PARL_IO_RX_FIFO_RD_BIT_CNT Represents the bit number currently read from the RX FIFO. (RO) Espressif Systems 1403 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 38 Parallel IO Controller (PARLIO) Register 38.17. PARL_IO_TX_ST0_REG (0x0040) PARL_IO_TX_FIFO_RD_BIT_CNT 0x000 31 13 PARL_IO_TX_CNT 0x0 12 6 (reserved) 0 0 0 0 0 0 5 0 Reset PARL_IO_TX_CNT Represents the cycle number of reading the TX FIFO. (RO) PARL_IO_TX_FIFO_RD_BIT_CNT Represents the bit number currently read from the TX FIFO. (RO) Register 38.18. PARL_IO_RX_CLK_CFG_REG (0x0044) PARL_IO_RX_CLK_O_INV 0 31 PARL_IO_RX_CLK_I_INV 0 30 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29 0 Reset PARL_IO_RX_CLK_I_INV Configures whether to invert the RX input Core clock. 0: No effect 1: Invert (R/W) PARL_IO_RX_CLK_O_INV Configures whether to invert the RX output Core clock. 0: No effect 1: Invert (R/W) Espressif Systems 1404 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 38 Parallel IO Controller (PARLIO) Register 38.19. PARL_IO_TX_CLK_CFG_REG (0x0048) PARL_IO_TX_CLK_O_INV 0 31 PARL_IO_TX_CLK_I_INV 0 30 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29 0 Reset PARL_IO_TX_CLK_I_INV Configures whether to invert the TX input Core clock. 0: No effect 1: Invert (R/W) PARL_IO_TX_CLK_O_INV Configures whether to invert the TX output Core clock. 0: No effect 1: Invert (R/W) Register 38.20. PARL_IO_TX_CS_CFG_REG (0x004C) PARL_IO_TX_CS_START_DELAY 0x00 31 16 PARL_IO_TX_CS_STOP_DELAY 0x00 15 0 Reset PARL_IO_TX_CS_STOP_DELAY Configures the delay between the end of TX data transmission and the rising edge of TX_CS_O. Unit: TX Core clock cycle (R/W) PARL_IO_TX_CS_START_DELAY Configures the delay between the falling edge of TX_CS_O and the start of TX data transmission. Unit: TX Core clock cycle (R/W) Espressif Systems 1405 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 38 Parallel IO Controller (PARLIO) Register 38.21. PARL_IO_CLK_REG (0x0120) PARL_IO_CLK_EN 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 0 Reset PARL_IO_CLK_EN Register clock gating. 0: Enable the register clock only when reading or writing registers 1: Always enable the register clock (R/W) Register 38.22. PARL_IO_VERSION_REG (0x03FC) (reserved) 0 0 0 0 31 28 PARL_IO_DATE 0x2409230 27 0 Reset PARL_IO_DATE Version control register. (R/W) Espressif Systems 1406 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 39 BitScrambler Chapter 39 BitScrambler The ESP32-C5 has an extensive amount of DMA-capable peripherals (see Chapter 3 GDMA Controller (GDMA)). These can move data from memory to an external device, and vice versa, without any interference from the CPU. This only works if the external device needs or emits the data in question in the same format as the software expects it: if not, the CPU needs to rewrite the format of the data. Examples include a need to swap bytes, reverse bytes, and shift the data left or right. As bitwise operations tend to be fairly CPU-expensive and the purpose of DMA is to not use the CPU in the transfer, ESP32-C5 includes a BitScrambler, which is a dedicated peripheral to change the format of data in between memory and the peripheral. A BitScrambler is capable of performing the aforementioned operations, but as a flexible programmable state machine, it is capable of more advanced things as well. The BitScrambler can be used for memory-to-peripheral, memory-to-memory, and peripheral-to-memory transfers. 39.1 Introduction In ESP32-C5, a DMA-capable peripheral is one that can read data directly from memory and/or write data directly to memory using a DMA channel. The format this data is read/written in is dependent on the peripheral and generally has only a small amount of flexibility. For most DMA-capable peripherals in ESP32-C5, it is possible to attach the BitScrambler to any of these paths for additional flexibility. When the BitScrambler is attached to a peripheral, it gets the chance to modify any data that flows down a DMA channel associated with that peripheral. Data written to the DMA channel will appear on the BitScrambler input, and what the BitScrambler writes to its output will flow down the DMA channel. The BitScrambler contains instruction memory where instructions on how to route the data between input and output can be stored. As such, by writing an appropriate BitScrambler program, the way the data is rewritten by the BitScrambler can be controlled. As shown in Figure 39.1-1, the BitScrambler can either be placed in the DMA TX BitScrambler path, where it modifies data flowing from memory to a peripheral, or in the DMA RX BitScrambler path, where it modifies data flowing from a peripheral to memory. It can also be placed in loopback mode, modifying data from memory to memory. Espressif Systems 1407 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 39 BitScrambler Figure 39.1-1. BitScrambler System Context Diagram 39.2 Feature List The BitScrambler has the following features: • One BitScrambler core, which can be used as either a RX (peripheral-to-memory), or TX (memory-to-peripheral) unit • Support for memory-to-memory transfers • Processing up to 32 bits per DMA clock period • Data path controlled by a BitScrambler program stored in instruction memory • Input registers able to read 0, 8, 16, or 32 bits per clock cycle • Output registers: – Able to write 0, 8, 16, or 32 bits per clock cycle – Data sources for output register bits: 64 bits of input data, two counters, LUT RAM data, data output of last cycle, comparators – With some restrictions, each of the 32 output register bits can come from any bit on the data sources • 8 x 257-bit instruction memory, for storing eight instructions, controlling control flow and the data path • 2048 bytes of lookup table (LUT) memory, configurable as various word widths 39.3 Application Examples • Swapping byte, nibble or bit orders in data • Converting palette-based bitmaps to full RGB bitmaps • Run-length encoding or decoding of data • Generating complicated waveforms for e.g. WS2811 chips Espressif Systems 1408 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 39 BitScrambler 39.4 Architectural Overview The BitScrambler can be separated into a data path, a control path, and the registers that the CPU can use to program them. The data path moves bits between the incoming DMA stream, internal registers, and the outgoing DMA stream. The control path parses the instructions in the instruction memory to control the data path, as well as handle program flow. 39.4.1 Data Path Figure 39.4-1. BitScrambler Data Path Diagram The data path of the BitScrambler is intended to take data from the incoming DMA stream, process it according to the program code stored in instruction memory, and write it to the outgoing DMA stream. 1. Data is read from the incoming DMA stream into a 64-bit register. At the end of an instruction cycle, as specified in the instruction, N bits (with N being 0, 8, 16, or 32) are read from the DMA stream. 2. The data in the register is then shifted toward the LSB of the register with the least significant N bits disappearing. 3. The read data appears as the N most significant bits. Optionally, on startup, the BitScrambler will automatically read the first 64 bits into this register. On the other side of the BitScrambler, data is deposited into a 32-bit output register. At the end of the instruction cycle, depending on what the instruction specifies, the least significant 0, 8, 16, or 32 bits will be written to the outgoing DMA stream. The BitScrambler derives its name from the fact that it can put input bits in any random position in the output, and this is achieved by 32 x 128-to-1 multiplexers. For each of the 32 output register bits, there is one multiplexer that selects the input signals from one of the data sources, dependent on the output of the BitScrambler control path. These data sources are: • 64 bits, shifted in from the input FIFO (i.e., the left DMA FIFO block in Figure 39.4-1). As described before, data from the incoming DMA stream is deposited here. In order to facilitate iterating over input bits in a loop, an instruction can enable relative addressing. In this addressing mode, any mux sourcing a bit from the input FIFO register will actually get the bit offset by the counter A register (i.e., CTR A in Figure 39.4-1). Espressif Systems 1409 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 39 BitScrambler • 32 bits that were sent to the output in the last cycle (i.e., PREV OUTPUT block in Figure 39.4-1). Data sent to the output register will appear on this register one clock cycle later. This allows the BitScrambler to ’remember’ data over multiple clock cycles: by outputting a bit to the output register, even if that bit subsequently is not sent to the output FIFO, the next clock cycle can still access it by selecting from this register. Bits can be remembered longer-term by selecting bits from this register for output again, which makes them appear here in the subsequent cycle. • 8, 16, or 32 bits that are the output of LUT RAM. The address used to select the data is bit 16 to 24, 25 or 26 of the output data of the last cycle, assuming the LUT width is 32, 16 or 8 bits, respectively. The LUT RAM is a part of the BitScrambler that takes an address, looks it up in its memory, and outputs the data located at that specific address. The LUT RAM can be filled when the BitScrambler is initialized, but the BitScrambler itself does not have the ability to modify it. Depending on requirements, the LUT RAM can be initialized in the following modes: – 512 x 32-bit words – 1024 x 16-bit words – 2048 x 8-bit words The LUT RAM can be used to do translations of data, e.g. using a calibration curve for a given sensor. It can also be used to implement mathematical functions, with the address input split into two or more input variables and the data output used as the output of the function; the memory should be loaded with the output of the function for each of the input values. • 32 bits from 2 x 16-bit counters (i.e., CTR A/B block in Figure 39.4-1). This register contains two 16-bit counters, named ’A’ and ’B’. These can be loaded, incremented and decremented via control path instructions. • 30 bits from comparators between counter B and the previous data on the output (PREV OUT in Figure 39.4-1; the 30 bits described here are part of the AUX block there). These allow the result of comparisons being used for output or for program flow. This can be useful in e.g. decoding run-length encoded streams, or generating PWM signals. • 2 bits, one fixed-high, one fixed-low (i.e., part of AUX in Figure 39.4-1). These are useful if a protocol needs an always-high or always-low bit in the output that does not depend on the input data. Note that some sources cannot be accessed at the same time. Specifically, a given instruction cannot source data from both the high 32 bits of the input FIFO source register as well as the counter registers. When data is read from the LUT, for a LUT that is set to a width of N, the top N bits of both the input FIFO register as well as the top N bits of the counter register become unavailable. Espressif Systems 1410 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 39 BitScrambler 39.4.2 Control Path Figure 39.4-2. BitScrambler Control Path Diagram The BitScrambler behavior is governed by a program stored in instruction RAM. The instruction RAM has space for up to eight instructions, each being 257 bits in size. An instruction configures the data path for the clock cycle the instruction runs in, as well as contains opcodes that control program flow. A BitScrambler program is similar to a microprocessor program, in that each cycle the BitScrambler will execute the next instruction in instruction memory, unless the opcode tells it to specifically jump to another location. Concretely, this behaviour is implemented using an instruction pointer (IP, see Figure 39.4-2), which points to the currently executing instruction. Opcodes can also affect the counter registers. The bits of the instruction that configure the data path consist of settings for the 32 muxes, as well as some bits to select the availability of the counter bits or LUT output. It also can put the muxes into relative mode, where if they get a bit from the DMA FIFO, the position of that bit is offset by counter B. 39.5 Functional Description The BitScrambler is a flexible device, with its behavior controlled by the program loaded into it as well as the configuration registers that set several global BitScrambler behaviors as well. As such, a BitScrambler program consists of the contents of the 257-bit x 8 instruction RAM as well as the settings for various configuration registers. Both are described below. 39.5.1 Instructions The 257 bits that make up an instruction are structured as shown in Table 39.5-1. Espressif Systems 1411 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 39 BitScrambler Table 39.5-1. Instruction Structure Bit Field Bit Field 0 - 6 CTL_MUX_SEL_0 133 - 139 CTL_MUX_SEL_19 7 - 13 CTL_MUX_SEL_1 140 - 146 CTL_MUX_SEL_20 14 - 20 CTL_MUX_SEL_2 147 - 153 CTL_MUX_SEL_21 21 - 27 CTL_MUX_SEL_3 154 - 160 CTL_MUX_SEL_22 28 - 34 CTL_MUX_SEL_4 161 - 167 CTL_MUX_SEL_23 35 - 41 CTL_MUX_SEL_5 168 - 174 CTL_MUX_SEL_24 42 - 48 CTL_MUX_SEL_6 175 - 181 CTL_MUX_SEL_25 49 - 55 CTL_MUX_SEL_7 182 - 188 CTL_MUX_SEL_26 56 - 62 CTL_MUX_SEL_8 189 - 195 CTL_MUX_SEL_27 63 - 69 CTL_MUX_SEL_9 196 - 202 CTL_MUX_SEL_28 70 - 76 CTL_MUX_SEL_10 203 - 209 CTL_MUX_SEL_29 77 - 83 CTL_MUX_SEL_11 210 - 216 CTL_MUX_SEL_30 84 - 90 CTL_MUX_SEL_12 217 - 223 CTL_MUX_SEL_31 91 - 97 CTL_MUX_SEL_13 224 - 249 OPCODE 98 - 104 CTL_MUX_SEL_14 250 - 251 CTL_READ_IN 105 - 111 CTL_MUX_SEL_15 252 - 253 CTL_WR_OUT 112 - 118 CTL_MUX_SEL_16 254 CTL_MUX_REL 119 - 125 CTL_MUX_SEL_17 255 CTL_CTR_SRC_SEL 126 - 132 CTL_MUX_SEL_18 256 CTL_LUT_SRC_SEL The meanings of these fields are as follows: • CTL_MUX_SEL_n: This 7-bit field selects the source of bit n in the output register. See Table 39.5-3 for details. • OPCODE: These bits encode an opcode. For the bit pattern of this field, please refer to Table 39.5-4. • CTL_READ_IN: This selects the number of bits that are read from the input FIFO at the end of the instruction: – 0: Do not read any data – 1: Read 8 bits – 2: Read 16 bits – 3: Read 32 bits • CTL_WR_OUT: This selects the number of bits that are written from the output register to the output FIFO at the end of the instruction: – 0: Do not write any data – 1: Write 8 bits – 2: Write 16 bits – 3: Write 32 bits Espressif Systems 1412 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 39 BitScrambler • CTL_MUX_REL, CTL_CTR_SRC_SEL and CTR_LUT_SRC_SEL: Select which bits are available to select using the CTL_MUX_SEL bits. – CTRL_CTR_SRC_SEL (Control Counter Source Select) makes the bits from counter A and B available – CTL_LUT_SRC_SEL (Control LUT Source Select) makes the output value of the LUT RAM available. See Table 39.5-3 for details. – When CTL_MUX_REL (Control Mux Relative) is 1, the BitScrambler applies the value of counter A as an offset to any CTL_MUX_SEL_n value that is 63 or below. The exact behaviour depends on CTR_SRC_SEL, as detailed in Table 39.5-2. Table 39.5-2. Effective CTL_MUX_SEL_n values when CTL_MUX_REL is 1 Condition Effective value of CTL_MUX_SEL CTL_MUX_SEL_n >= 64 CTL_MUX_SEL (unchanged) CTL_MUX_SEL_n < 64 and CTL_CTR_SRC_SEL = 0 (CTL_MUX_SEL_n + CTRA) & 63 CTL_MUX_SEL_n < 31 and CTL_CTR_SRC_SEL = 1 (CTL_MUX_SEL_n + CTRA) & 31 32 <= CTL_MUX_SEL_n < 64 and CTL_CTR_SRC_SEL = 1 ((CTL_MUX_SEL_n + CTRA) & 31) + 32 Of these fields, most are data path configuration items. The field that affects the control path is OPCODE, although CTL_MUX_REL, CTL_CTR_SRC_SEL, and CTR_LUT_SRC_SEL may influence how some of the opcodes work by adjusting the source selection for the IF/IFN opcodes. CTL_MUX_SEL_n: These fields, one for each bit in the output register, select the source for that particular bit. The specific bit chosen is partially dependent on the settings of the CTL_MUX_REL, CTL_CTR_SRC_SEL, and CTR_LUT_SRC_SEL. Given CTL_MUX_SRC_n has value N, the bit is selected as described in Table 39.5-3. Note that the source selection for IF/IFN opcodes is affected in the same way. Table 39.5-3. CTL_MUX_SEL Values Bit Description 0-31 The bit is sourced from bit N in the incoming FIFO register. 32-63 The source of the bit depends on the setting of CTL_CTR_SRC_SEL and CTR_LUT_SRC_SEL: If CTL_CTR_SRC_SEL = 0: the bit is sourced from bit N in the incoming FIFO register. If CTL_CTR_SRC_SEL = 1: the bit is sourced from bit (N-32) of the counter registers. Specifically, if N is 32 to 47, the bit is sourced from bit (N-32) of counter A and if N is 48 to 63, the bit is sourced from bit (N-48) of counter B. If CTL_LUT_SRC_SEL = 1: Depending on the width of the LUT (8, 16, or 32 bits), a read of the top 8, 16, or 32 bits will return data from the LUT rather than what CTL_CTR_SRC_SEL selects. Specifically, given a LUT width of N, 63 will return LUT output bit (N-1), 62 will return LUT output bit (N-2) and so on. 64 CounterB[7:0] =< last[7:0] 65 CounterB[7:0] > last[7:0] 66 CounterB[7:0] = last[7:0] 67 CounterB[7:0] =< last[15:8] 68 CounterB[7:0] > last[15:8] 69 CounterB[7:0] = last[15:8] Espressif Systems 1413 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 39 BitScrambler Bit Description 70 CounterB[7:0] =< last[23:16] 71 CounterB[7:0] > last[23:16] 72 CounterB[7:0] = last[23:16] 73 CounterB[7:0] =< last[31:24] 74 CounterB[7:0] > last[31:24] 75 CounterB[7:0] = last[31:24] 76 CounterB[15:8] =< last[7:0] 77 CounterB[15:8] > last[7:0] 78 CounterB[15:8] = last[7:0] 79 CounterB[15:8] =< last[15:8] 80 CounterB[15:8] > last[15:8] 81 CounterB[15:8] = last[15:8] 82 CounterB[15:8] =< last[23:16] 83 CounterB[15:8] > last[23:16] 84 CounterB[15:8] = last[23:16] 85 CounterB[15:8] =< last[31:24] 86 CounterB[15:8] > last[31:24] 87 CounterB[15:8] = last[31:24] 88 CounterB[15:0] =< last[15:0] 89 CounterB[15:0] > last[15:0] 90 CounterB[15:0] = last[15:0] 91 CounterB[15:0] =< last[31:16] 92 CounterB[15:0] > last[31:16] 93 CounterB[15:0] = last[31:16] 94 Always 0 95 Always 1 96-127 The bits selected here are the same as the bits on the output register at the end of the previous cycle. The BitScrambler recognizes seven opcodes, which are encoded in the opcode fields as shown in Table 39.5-4. Table 39.5-4. Instruction Opcode Opcode Bit 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LOOP 1 c tgt end_val ctr_add ADD 0 c h l 0 0 0 0 0 0 ctr_add IF 0 0 tgt 0 0 0 0 1 0 0 0 0 0 0 0 0 0 src IFN 0 0 tgt 0 0 0 1 0 0 0 0 0 0 0 0 0 0 src LDCTD 0 c h l 0 0 0 0 1 1 ctr_set LDCTI 0 c h l 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDCTI 0 c h l 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The fields are defined as follows: Espressif Systems 1414 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 39 BitScrambler • c: Configures which counter to use. – 0: counter A – 1: counter B • end_val, ctr_add, ctr_set: 16-bit (or 5-bit) value. Please refer to the instruction descriptions below for the meanings of these fields. • tgt: The location of an instruction. Range: 0 7. • h: 1 if the upper 8 bits need to be written back to a counter (if the opcode ends with -H). • l: 1 if the lower 8 bits need to be written back to a counter (if the opcode ends with -L). Note that if an opcode does not specify H or L, it is assumed that the full 16 bits need to be written back and the h and l bits will both be 1. These seven opcodes affect the state of the BitScrambler as follows: Table 39.5-5. LOOP Opcode Loop on counter indicated by c, add ctr_add to the counter, and loop back to tgt until the counter reaches end_val. When that happens, reset the counter and fall through. Argument c: Either A or B, indicates counter to use tgt: 3-bit target instruction addresses end_val: 16-bit value to compare the counter to ctr_add: 5-bit signed value to add to the counter Pseudo-code Espressif Systems 1415 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 39 BitScrambler Table 39.5-6. ADD Opcode Add immediate value to counter indicated by c, and optionally write back only upper or lower 8 bits. Argument c: Either A or B, indicate counter to use ctr_add: 16-bit value to add to counter If opcode is ADDcH, only most significant 8 bits are written back If opcode is ADDcL, only least-significant 8 bits are written back If opcode is ADDc, all 16 bits will be written back (h=1, l=1). Pseudo-code Note The NOP (no operation) pseudo-op is encoded as ‘ADDA 0’. Table 39.5-7. IF Opcode Jump to target if the indicated mux source bit is set. Argument ctl_cond_src: Mux source (see CTR_MUX_SRC sources) tgt: 3-bit target instruction addresses Pseudo-code Note The JMP (always jump) pseudo-op is implemented as an ‘IF 95,tgt’ opcode, using the always- 1 bit from the AUX bits. Table 39.5-8. IFN Opcode Jump to target if the indicated mux source bit is NOT set (note: same as IF but condition is negated). Argument ctl_cond_src: Mux source (see CTR_MUX_SRC sources) tgt: 3-bit target instruction addresses Pseudo-code Espressif Systems 1416 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 39 BitScrambler Table 39.5-9. LDCTD Opcode Load counter direct (from immediate), and optionally only load high or low 8 bits of counter. Argument c: Either A or B, indicate counter to use ctr_set: 16-bit value to set the counter to h: if opcode is LDCTDcH, only most significant 8 bits are set l: if opcode is LDCTDcL, only least-significant 8 bits are set If opcode is LDCTDc, all 16 bits are set (h=1, l=1) Pseudo-code Table 39.5-10. LDCTI Opcode Load counter indirect (from most significant 16 bits of mux output), and optionally only load high or low 8 bits of counter. Argument c: Either A or B, indicate counter to use h: If opcode is LDCTIcH, only the most significant 8 bits are set l: If opcode is LDCTIcL, only the least significant 8 bits are set If opcode is LDCTIc, all 16 bits are set (h=1, l=1) Pseudo-code Espressif Systems 1417 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 39 BitScrambler Table 39.5-11. ADDCTI Opcode Add indirect (from most significant 16 bits of mux output) value to counter. Optionally only add to high or low 8 bits of counter. Argument c: Either A or B, indicate counter to use h: If opcode is ADDCTIcH, bit 24 to 31 of the output mux are added to the most significant 8 bits of the counter l: If opcode is ADDCTIcL, bit 16 to 23 of the output mux are added to the least significant 8 bits of the counter If opcode is ADDCTIc, bit 16 to 31 of the output mux are added to all 16 bits of the counter (h=1, l=1) Pseudo-code 39.5.2 Configuration Registers The BitScrambler is configured using a set of registers. Specifically, these registers are used to write a program into BitScrambler, write its LUT RAM, configure its behaviour, and start and stop BitScrambler operation. They are also used to attach a BitScrambler to a peripheral DMA path. The ESP32-C5 only has one BitScrambler core which can either be placed in the TX path (where data is sent from the memory to a peripheral) or in a RX path (where data is sent from the peripheral to memory). For compatibility with other ESP series chips, when the BitScrambler core is placed in the TX path, it is controlled with the registers prefixed by BITSCRAMBLER_TX_ while when it is placed in the RX path, the registers prefixed by BITSCRAMBLER_RX_ govern its behaviour. Which path is active is decided by BITSCRAMBLER_RX_ENA and BITSCRAMBLER_TX_ENA, of which only one is allowed to be active at any given time. Note: For convenience, in this section we will refer to the TX path registers only; to get the RX path register descriptions, simply swap the prefixes. When modifying the input or output of a peripheral, the BitScrambler needs to be attached to the DMA path of that peripheral. To do this, write the appropriate value for the peripheral into the HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL or HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL field of the HP_SYSTEM_BITSCRAMBLER_PERI_SEL_REG register. The BitScrambler can also run in memory-to-memory mode. For this, the BITSCRAMBLER_LOOP_MODE bit in BITSCRAMBLER_SYS_REG needs to be set to one. In this mode, the TX BitScrambler is put into loopback mode while the RX BitScrambler is unused and unavailable. The BitScrambler still needs to be attached to a peripheral (although the peripheral does not need to be configured); the DMA path for this peripheral will be Espressif Systems 1418 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 39 BitScrambler unusable. Neither the program memory nor the LUT RAM are accessible to the main processor directly. Rather, they need to be written indirectly, by setting an address in one register and then writing the data in a second register. Specifically, for the LUT RAM, the address is written in the BITSCRAMBLER_TX_LUT_IDX field of BITSCRAMBLER_TX_LUT_CFG0_REG and the data is written to or read from BITSCRAMBLER_TX_LUT_CFG1_REG. The width of the LUT, as visible to the BitScrambler, can be configured using the BITSCRAMBLER_TX_LUT_MODE field. Note that when the host processor writes to the LUT in the aforementioned fashion, the addressing and data size needs to adhere to the configured LUT width. Similarly, the instruction memory is written by setting the address up in BITSCRAMBLER_TX_INST_CFG0_REG and writing the data to or reading it from BITSCRAMBLER_TX_INST_CFG1_REG. As the BitScrambler instructions are 257 bits, one instruction needs to be written as 9 32-bit words (with the 257th bit being in the LSB of the 9th word). To achieve that purpose, the BITSCRAMBLER_TX_INST_CFG0_REG register is divided into two fields. The position of the instruction is written into the BITSCRAMBLER_TX_INST_IDX field while the word offset within the instruction is written to BITSCRAMBLER_TX_INST_POS. As the BitScrambler has the ability to generate more or less data than it gets on the input, a BitScrambler-controlled DMA stream can end in one or two ways. The first is that the receiver (either memory in case of the RX BitScrambler, or the peripheral in case of the TX BitScrambler) stops accepting data because it is configured to only receive a limited number of bytes. This case is pretty simple: the BitScrambler will simply halt as it cannot write any more data. The other way is that the transmitter (the peripheral for the RX BitScrambler and the memory for the TX BitScrambler) stops sending data. This is a more complicated situation, as the BitScrambler may or may not be processing some data that needs to be written to the output. In order to allow the BitScrambler to send out the data it is still processing, two methods have been devised to handle a certain amount of data after the input data stream has ended. Both depend on setting BITSCRAMBLER_RX_TAILING_BITS_REG to a certain value N: • EOF-on-N-reads: After the input data stream ends, the BitScrambler reads N dummy bytes from the input. The value of these bytes is zero. After the Nth byte is read, the BitScrambler halts and the DMA stream ends. • EOF-on-N-writes: After the input data stream ends, the BitScrambler is allowed to write N more bytes to the output. During this time, any reads on the input stream return zero-value dummy bytes. After the N’th byte is written, the BitScrambler halts and the DMA stream ends. To configure either mode, set the option bits as follows: Table 39.5-12. Settings for EOF modes Register EOF-on-N-reads EOF-on-N-writes BITSCRAMBLER_TX_RD_DUMMY 1 1 BITSCRAMBLER_TX_FETCH_MODE 0 0 BITSCRAMBLER_TX_EOF_MODE 1 0 BITSCRAMBLER_TX_HALT_MODE 1 1 Espressif Systems 1419 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 39 BitScrambler 39.6 Programming Procedures Note that these instructions are written for a BitScrambler with the TX path enabled, either in the memory-to-peripheral path, or memory-to-memory path if in loopback mode. For the peripheral-to-memory path, the RX path is used. Unless otherwise indicated, you can exchange ”TX” for ”RX” in these instructions to configure the RX path. 1. Attach the BitScrambler to a peripheral by configuring HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL field in HP_SYSTEM_BITSCRAMBLER_PERI_SEL_REG register. Note that this step is required even in loopback mode. 2. Enable the BitScrambler by setting the BITSCRAMBLER_TX_ENA field in the BITSCRAMBLER_TX_CTRL_REG register. Make sure only one of BITSCRAMBLER_TX_ENA and BITSCRAMBLER_RX_ENA is set at any time. 3. Configure loopback mode if required. If loopback mode is needed, set BITSCRAMBLER_LOOP_MODE in the BITSCRAMBLER_SYS_REG register. Otherwise, clear it. 4. Load program into BitScrambler. For each instruction and each 32-bit word within the instruction, set the BITSCRAMBLER_TX_INST_IDX and BITSCRAMBLER_TX_INST_POS fields in the BITSCRAMBLER_TX_INST_CFG0_REG register, then write the word in the BITSCRAMBLER_TX_INST_CFG1_REG register. Note that the 257th bit is written as bit 0 into BITSCRAMBLER_TX_INST_CFG1_REG. 5. Load LUT into BitScrambler, if needed: (a) Configure BITSCRAMBLER_TX_LUT_MODE in BITSCRAMBLER_TX_LUT_CFG0_REG to set the LUT width (b) Write the address to the BITSCRAMBLER_TX_LUT_CFG0_REG (c) Write the data word or the byte itself to BITSCRAMBLER_TX_LUT_CFG1_REG Note that it is acceptable to change the LUT width after writing the data and before starting the BitScrambler. 6. Configure BitScrambler. Dependent on what the BitScrambler program expects, you may need to set or clear the various bits in the BITSCRAMBLER_TX_CTRL_REG register. You may also need to set BITSCRAMBLER_TX_TAILING_BITS_REG to an applicable value. 7. Start the BitScrambler by clearing the BITSCRAMBLER_TX_HALT bit in the BITSCRAMBLER_TX_CTRL_REG register. 8. Start DMA transaction. Please refer to Chapter 3 GDMA Controller (GDMA) for more information about DMA subsystem and refer to the peripheral chapter if loopback mode is not used. 9. Wait until DMA transaction is done. 10. Halt the BitScrambler by setting the BITSCRAMBLER_TX_HALT in the BITSCRAMBLER_TX_CTRL_REG register. 11. Wait for halt state. The BitScrambler is halted when the BITSCRAMBLER_TX_IN_IDLE bit in the BITSCRAMBLER_TX_STATE_REG register is set. Espressif Systems 1420 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 39 BitScrambler 12. Reset the FIFO by writing 1 and then 0 to the BITSCRAMBLER_TX_FIFO_RST bit in the BITSCRAMBLER_TX_CTRL_REG register. 13. The BitScrambler is ready for a new transaction with the current program and LUT configuration. Simply start from step 7 to do this. Espressif Systems 1421 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 39 BitScrambler 39.7 Register Summary The addresses in this section are relative to the Bit-scrambler base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Control and configuration registers BITSCRAMBLER_TX_INST_CFG0_REG BitScrambler TX path instruction memory ad- dress selection register 0x0000 R/W BITSCRAMBLER_TX_INST_CFG1_REG BitScrambler TX path instruction memory ac- cess register 0x0004 R/W BITSCRAMBLER_RX_INST_CFG0_REG BitScrambler RX path instruction memory ad- dress selection register 0x0008 R/W BITSCRAMBLER_RX_INST_CFG1_REG BitScrambler RX path instruction memory ac- cess register 0x000C R/W BITSCRAMBLER_TX_LUT_CFG0_REG BitScrambler TX path LUT memory address se- lection register 0x0010 R/W BITSCRAMBLER_TX_LUT_CFG1_REG BitScrambler TX path LUT memory access reg- ister 0x0014 R/W BITSCRAMBLER_RX_LUT_CFG0_REG BitScrambler RX path LUT memory address selection register 0x0018 R/W BITSCRAMBLER_RX_LUT_CFG1_REG BitScrambler RX path LUT memory access reg- ister 0x001C R/W Configuration registers BITSCRAMBLER_TX_TAILING_BITS_REG BitScrambler TX path extra data length register 0x0020 R/W BITSCRAMBLER_RX_TAILING_BITS_REG BitScrambler RX path extra data length register 0x0024 R/W BITSCRAMBLER_TX_CTRL_REG BitScrambler TX path control register 0x0028 varies BITSCRAMBLER_RX_CTRL_REG BitScrambler RX path control register 0x002C varies BITSCRAMBLER_SYS_REG Loopback control register 0x00F8 R/W Status registers BITSCRAMBLER_TX_STATE_REG BitScrambler TX path status register 0x0030 varies BITSCRAMBLER_RX_STATE_REG BitScrambler RX path status register 0x0034 varies Version register BITSCRAMBLER_VERSION_REG Version control register 0x00FC R/W Espressif Systems 1422 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 39 BitScrambler 39.8 Registers The addresses in this section are relative to the Bit-scrambler base address provided in Table 4.3-2 in Chapter 4 System and Memory. For how to program reserved fields, please refer to Section Programming Reserved Register Field. Register 39.1. BITSCRAMBLER_TX_INST_CFG0_REG (0x0000) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 7 BITSCRAMBLER_TX_INST_POS 0 6 3 BITSCRAMBLER_TX_INST_IDX 0 2 0 Reset BITSCRAMBLER_TX_INST_IDX Configures the index of the BitScrambler instruction to be accessed via BITSCRAMBLER_TX_INST_CFG1_REG. (R/W) BITSCRAMBLER_TX_INST_POS Configures the offset into the 257-bit BitScrambler instruction (in 32-bit increments) to be accessed via BITSCRAMBLER_TX_INST_CFG1_REG. (R/W) Register 39.2. BITSCRAMBLER_TX_INST_CFG1_REG (0x0004) BITSCRAMBLER_TX_INST 4 31 0 Reset BITSCRAMBLER_TX_INST Configures the instruction to be accessed at the address specified by BITSCRAMBLER_TX_INST_CFG0_REG. (R/W) Espressif Systems 1423 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 39 BitScrambler Register 39.3. BITSCRAMBLER_RX_INST_CFG0_REG (0x0008) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 7 BITSCRAMBLER_RX_INST_POS 0 6 3 BITSCRAMBLER_RX_INST_IDX 0 2 0 Reset BITSCRAMBLER_RX_INST_IDX Configures the index of the BitScrambler instruction to be accessed via BITSCRAMBLER_RX_INST_CFG1_REG. (R/W) BITSCRAMBLER_RX_INST_POS Configures the offset into the 257-bit BitScrambler instruction (in 32-bit increments) to be accessed via BITSCRAMBLER_RX_INST_CFG1_REG. (R/W) Register 39.4. BITSCRAMBLER_RX_INST_CFG1_REG (0x000C) BITSCRAMBLER_RX_INST 12 31 0 Reset BITSCRAMBLER_RX_INST Configures the instruction to be accessed at the address specified by BITSCRAMBLER_RX_INST_CFG0_REG. (R/W) Espressif Systems 1424 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 39 BitScrambler Register 39.5. BITSCRAMBLER_TX_LUT_CFG0_REG (0x0010) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 13 BITSCRAMBLER_TX_LUT_MODE 0 12 11 BITSCRAMBLER_TX_LUT_IDX 0 10 0 Reset BITSCRAMBLER_TX_LUT_IDX Configures where in LUT RAM to access. Measurement unit: word size configured by BITSCRAMBLER_TX_LUT_MODE. (R/W) BITSCRAMBLER_TX_LUT_MODE Configures the word size of LUT RAM for Bitscrambler programs. 0: 1 byte 1: 2 bytes 2: 4 bytes 3: Reserved (R/W) Register 39.6. BITSCRAMBLER_TX_LUT_CFG1_REG (0x0014) BITSCRAMBLER_TX_LUT 20 31 0 Reset BITSCRAMBLER_TX_LUT Configures the LUT entry to be accessed at the position specified by BITSCRAMBLER_TX_LUT_CFG0_REG. (R/W) Espressif Systems 1425 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 39 BitScrambler Register 39.7. BITSCRAMBLER_RX_LUT_CFG0_REG (0x0018) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 13 BITSCRAMBLER_RX_LUT_MODE 0 12 11 BITSCRAMBLER_RX_LUT_IDX 0 10 0 Reset BITSCRAMBLER_RX_LUT_IDX Configures where in LUT RAM to access. Measurement unit: word size configured by BITSCRAMBLER_RX_LUT_MODE. (R/W) BITSCRAMBLER_RX_LUT_MODE Configures the word size of LUT RAM for BitScrambler pro- grams. 0: 1 byte 1: 2 bytes 2: 4 bytes 3: Reserved (R/W) Register 39.8. BITSCRAMBLER_RX_LUT_CFG1_REG (0x001C) BITSCRAMBLER_RX_LUT 28 31 0 Reset BITSCRAMBLER_RX_LUT Configures the LUT entry to be accessed at the position specified by BITSCRAMBLER_RX_LUT_CFG0_REG. (R/W) Espressif Systems 1426 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 39 BitScrambler Register 39.9. BITSCRAMBLER_TX_TAILING_BITS_REG (0x0020) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 BITSCRAMBLER_TX_TAILING_BITS 0 15 0 Reset BITSCRAMBLER_TX_TAILING_BITS Configures the length of extra data after getting EOF for the TX BitScrambler path. Measurement unit: bit. (R/W) Register 39.10. BITSCRAMBLER_RX_TAILING_BITS_REG (0x0024) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 BITSCRAMBLER_RX_TAILING_BITS 0 15 0 Reset BITSCRAMBLER_RX_TAILING_BITS Configures the length of extra data after getting EOF for the BitScrambler RX path. Measurement unit: bit. (R/W) Espressif Systems 1427 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 39 BitScrambler Register 39.11. BITSCRAMBLER_TX_CTRL_REG (0x0028) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 9 BITSCRAMBLER_TX_FIFO_RST 0 8 BITSCRAMBLER_TX_RD_DUMMY 0 7 BITSCRAMBLER_TX_HALT_MODE 0 6 BITSCRAMBLER_TX_FETCH_MODE 0 5 BITSCRAMBLER_TX_COND_MODE 0 4 BITSCRAMBLER_TX_EOF_MODE 0 3 BITSCRAMBLER_TX_HALT 1 2 BITSCRAMBLER_TX_PAUSE 0 1 BITSCRAMBLER_TX_ENA 0 0 Reset BITSCRAMBLER_TX_ENA Configures whether to enable the BitScrambler core in the TX path. 0: Disable 1: Enable Note that the BitScrambler core can only be enabled either in the RX or TX path, never both. (R/W) BITSCRAMBLER_TX_PAUSE Configures whether to pause BitScrambler TX path. A paused core can be un-paused to resume execution. 0: Not pause 1: Pause (R/W) BITSCRAMBLER_TX_HALT Configures whether to halt BitScrambler TX path. Halting the BitScram- bler TX path will flush the FIFOs and cannot be resumed; a FIFO reset and a restart is needed. 0: Not halt 1: Halt (R/W) BITSCRAMBLER_TX_EOF_MODE Configures BitScrambler TX path EOF signal generating mode. This is combined with BITSCRAMBLER_TX_TAILING_BITS for use. 0: Data written to the output FIFO are counted to generate delayed EOF 1: Data read from the input FIFO are counted to generate delayed EOF (R/W) BITSCRAMBLER_TX_COND_MODE Configures BitScrambler TX LOOP instruction condition mode. 0: Use the less than operator to get the condition 1: Use not equal operator to get the condition (R/W) BITSCRAMBLER_TX_FETCH_MODE Configures BitScrambler TX path fetch instruction mode. 0: Prefetch by reset 1: Fetch by instructions (R/W) BITSCRAMBLER_TX_HALT_MODE Configures BitScrambler TX path halt mode when BITSCRAM- BLER_TX_HALT is set to 1. 0: Wait for write data back done 1: Ignore write data back (R/W) Continued on the next page... Espressif Systems 1428 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 39 BitScrambler Register 39.11. BITSCRAMBLER_TX_CTRL_REG (0x0028) Continued from the previous page... BITSCRAMBLER_TX_RD_DUMMY Configures BitScrambler TX path read data mode when EOF received. 0: Wait read data 1: Ignore read data (R/W) BITSCRAMBLER_TX_FIFO_RST Configures whether to reset BitScrambler TX FIFO. 0: Not reset 1: Reset (WT) Espressif Systems 1429 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 39 BitScrambler Register 39.12. BITSCRAMBLER_RX_CTRL_REG (0x002C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 9 BITSCRAMBLER_RX_FIFO_RST 0 8 BITSCRAMBLER_RX_RD_DUMMY 0 7 BITSCRAMBLER_RX_HALT_MODE 0 6 BITSCRAMBLER_RX_FETCH_MODE 0 5 BITSCRAMBLER_RX_COND_MODE 0 4 BITSCRAMBLER_RX_EOF_MODE 0 3 BITSCRAMBLER_RX_HALT 1 2 BITSCRAMBLER_RX_PAUSE 0 1 BITSCRAMBLER_RX_ENA 0 0 Reset BITSCRAMBLER_RX_ENA Configures whether to enable the BitScrambler core in the RX path. 0: Disable 1: Enable Note that the BitScrambler core can only be enabled either in the RX or TX path, never both. (R/W) BITSCRAMBLER_RX_PAUSE Configures whether to pause BitScrambler RX path. A paused core can be un-paused to resume execution. 0: Not pause 1: Pause (R/W) BITSCRAMBLER_RX_HALT Configures whether to halt BitScrambler RX path. Halting the BitScram- bler RX path will flush the FIFOs and cannot be resumed; a FIFO reset and a restart is needed. 0: Not halt 1: Halt (R/W) BITSCRAMBLER_RX_EOF_MODE Configures BitScrambler RX path EOF signal generating mode. This is combined with BITSCRAMBLER_RX_TAILING_BITS for use. 0: Data written to the output FIFO are counted to generate delayed EOF 1: Data read from the input FIFO are counted to generate delayed EOF (R/W) BITSCRAMBLER_RX_COND_MODE Configures BitScrambler RX LOOP instruction condition mode. 0: Use the less than operator to get the condition 1: Use not equal operator to get the condition (R/W) BITSCRAMBLER_RX_FETCH_MODE Configures BitScrambler RX path fetch instruction mode 0: Prefetch by reset 1: Fetch by instructions (R/W) Continued on the next page... Espressif Systems 1430 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 39 BitScrambler Register 39.12. BITSCRAMBLER_RX_CTRL_REG (0x002C) Continued from the previous page... BITSCRAMBLER_RX_HALT_MODE Configures BitScrambler RX path halt mode when BITSCRAM- BLER_RX_HALT is set to 1. 0: Wait for write data back done 1: Ignore write data back (R/W) BITSCRAMBLER_RX_RD_DUMMY Configures BitScrambler RX path read data mode when EOF received. 0: Wait read data 1: Ignore read data (R/W) BITSCRAMBLER_RX_FIFO_RST Configures whether to reset BitScrambler RX FIFO. 0: Not reset 1: Reset (WT) Register 39.13. BITSCRAMBLER_SYS_REG (0x00F8) BITSCRAMBLER_CLK_EN 0 31 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 1 BITSCRAMBLER_LOOP_MODE 0 0 Reset BITSCRAMBLER_LOOP_MODE Configures whether to enable BitScrambler TX to DMA RX loop- back mode 0: Disable 1: Enable (R/W) BITSCRAMBLER_CLK_EN Configure whether to enable the configuration register clock to be always-on. 0: turn on during access 1: always-on (R/W) Espressif Systems 1431 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 39 BitScrambler Register 39.14. BITSCRAMBLER_TX_STATE_REG (0x0030) BITSCRAMBLER_TX_EOF_TRACE_CLR 0 31 BITSCRAMBLER_TX_EOF_OVERLOAD 0 30 BITSCRAMBLER_TX_EOF_GET_CNT 0 29 16 (reserved) 0 0 0 0 0 0 0 0 0 0 0 15 5 BITSCRAMBLER_TX_FIFO_EMPTY 1 4 BITSCRAMBLER_TX_IN_PAUSE 0 3 BITSCRAMBLER_TX_IN_WAIT 0 2 BITSCRAMBLER_TX_IN_RUN 0 1 BITSCRAMBLER_TX_IN_IDLE 1 0 Reset BITSCRAMBLER_TX_IN_IDLE Represents whether BitScrambler TX path is halted. 0: Not halted 1: Halted (RO) BITSCRAMBLER_TX_IN_RUN Represents whether BitScrambler TX path is running. 0: Not running 1: Running (RO) BITSCRAMBLER_TX_IN_WAIT Represents whether BitScrambler TX path is waiting for write back done. 0: Not waiting 1: Waiting (RO) BITSCRAMBLER_TX_IN_PAUSE Represents whether BitScrambler TX path is paused. 0: Not paused 1: Paused (RO) BITSCRAMBLER_TX_FIFO_EMPTY Represents whether BitScrambler TX FIFO is empty 0: Not empty 1: Empty (RO) BITSCRAMBLER_TX_EOF_GET_CNT Represents byte count of BitScrambler TX path after EOF is received. (RO) BITSCRAMBLER_TX_EOF_OVERLOAD Represents whether BitScrambler TX path tries to process more than one EOF. 0: Not try to process more than one EOF 1: Try to process more than one EOF (RO) BITSCRAMBLER_TX_EOF_TRACE_CLR Configures whether to clear BITSCRAM- BLER_TX_EOF_OVERLOAD and BITSCRAMBLER_TX_EOF_GET_CNT. 0: Not clear 1: Clear (WT) Espressif Systems 1432 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 39 BitScrambler Register 39.15. BITSCRAMBLER_RX_STATE_REG (0x0034) BITSCRAMBLER_RX_EOF_TRACE_CLR 0 31 BITSCRAMBLER_RX_EOF_OVERLOAD 0 30 BITSCRAMBLER_RX_EOF_GET_CNT 0 29 16 (reserved) 0 0 0 0 0 0 0 0 0 0 0 15 5 BITSCRAMBLER_RX_FIFO_FULL 0 4 BITSCRAMBLER_RX_IN_PAUSE 0 3 BITSCRAMBLER_RX_IN_WAIT 0 2 BITSCRAMBLER_RX_IN_RUN 0 1 BITSCRAMBLER_RX_IN_IDLE 1 0 Reset BITSCRAMBLER_RX_IN_IDLE Represents whether BitScrambler TX path is halted. 0: Not halted 1: Halted (RO) BITSCRAMBLER_RX_IN_RUN Represents whether BitScrambler TX path is running. 0: Not running 1: Running (RO) BITSCRAMBLER_RX_IN_WAIT Represents whether BitScrambler TX path is waiting for write back done. 0: Not waiting 1: Waiting (RO) BITSCRAMBLER_RX_IN_PAUSE Represents whether BitScrambler TX path is paused. 0: Not paused 1: Paused (RO) BITSCRAMBLER_RX_FIFO_FULL Represents whether BitScrambler RX FIFO is full. 0: Not full 1: Full (RO) BITSCRAMBLER_RX_EOF_GET_CNT Represents byte count of BitScrambler TX path after EOF is received. (RO) BITSCRAMBLER_RX_EOF_OVERLOAD Represents whether BitScrambler RX path tries to process more than one EOF. 0: Not try to process more than one EOF 1: Try to process more than one EOF (RO) BITSCRAMBLER_RX_EOF_TRACE_CLR Configures whether to clear BITSCRAM- BLER_RX_EOF_OVERLOAD and BITSCRAMBLER_RX_EOF_GET_CNT. 0: Not clear 1: Clear (WT) Espressif Systems 1433 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 39 BitScrambler Register 39.16. BITSCRAMBLER_VERSION_REG (0x00FC) (reserved) 0 0 0 0 31 28 BITSCRAMBLER_BITSCRAMBLER_VER 0x2310231 27 0 Reset BITSCRAMBLER_BITSCRAMBLER_VER Version control register. (R/W) Espressif Systems 1434 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Part VI Analog Signal Processing This part describes components related to analog-to-digital conversion, voltage comparison, on-chip sensors, and features such as temperature sensing, demonstrating the system’s capabilities in handling analog signals. Espressif Systems 1435 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 40 Temperature Sensor Chapter 40 Temperature Sensor 40.1 Overview ESP32-C5 provides a temperature sensor to monitor temperature changes inside the chip in real time. The sensor converts analog voltage to digital values and supports compensation for the temperature offset. 40.2 Features The temperature sensor has the following features: • Software-triggered temperature measurement. Once triggered, the sensor continuously measures temperature. Software can read the data any time. • Hardware-triggered automatic temperature monitoring • Two modes for automatic monitoring of temperature and support for triggering interrupts • Configurable temperature offset based on the application scenario for improved accuracy • Configurable temperature measurement range • Support for several Event Task Matrix (ETM) related events and tasks 40.3 Architecture Figure 40.3-1 shows the internal structure of the temperature sensor. Espressif Systems 1436 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 40 Temperature Sensor Tsens_data Monitor Tsens Ctrl & Detect Analog Digital HW Timer Tsens_data[7:0] sync_module Tsens_data_apb[7:0] Monitor_trigger over_threshold_apb Tsens_pu_apb Tsens_pu over_threshold Figure 40.3-1. Temperature Sensor Architecture As Figure 40.3-1 shows, the temperature sensor module contains the following major blocks: • Tsens Ctrl & Detect: temperature sensor • HW Timer: triggers automatic temperature monitoring • Tsens_data Monitor: monitors whether the temperature is outside the threshold range • sync_module: Synchronization block between APB clock domain and temperature sensor clock domain 40.4 Functional Description 40.4.1 Temperature Sensor Power Up The temperature sensor can be powered up by setting the APB_SARADC_TSENS_PU register. 40.4.2 Temperature Sensor Clock The temperature sensor has two clock sources: RC_FAST_CLK and XTAL_CLK, selected by PCR_TSENS_CLK_SEL. The clock can be divided with APB_SARADC_TSENS_CLK_DIV. 40.4.3 Automatic Temperature Monitoring Modes Two modes for the automatic temperature monitoring are available for selection by configuring APB_SARADC_WAKEUP_MODE: • Absolute value mode: Espressif Systems 1437 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 40 Temperature Sensor – Monitors the absolute value of the current temperature. Configure APB_SARADC_WAKEUP_TH_LOW and APB_SARADC_WAKEUP_TH_HIGH to set the temperature thresholds. An interrupt will be triggered if the sampled value is above the high threshold or below the low threshold. • Change value mode: – Monitors the temperature changes inside the chip. If the temperature increment of two consecutive samplings exceeds the high threshold configured in APB_SARADC_WAKEUP_TH_HIGH, or the temperature decrement of two consecutive samplings exceeds the low threshold configured in APB_SARADC_WAKEUP_TH_LOW, an interrupt will be triggered. For example, when APB_SARADC_WAKEUP_TH_LOW is configured as 8, if two consecutive sampling values are 28 and 19 respectively, i.e., the temperature decrement is 9, then an interrupt will be triggered. 40.4.4 Temperature Measurement Range and Offset To improve the temperature measurement accuracy, the temperature sensor is designed with five measurement ranges as shown in Table 40.4-1. Each measurement range comes with specific measurement errors. Users do not need to worry about the errors, as they can choose specific offsets to get calibrated data. Table 40.4-1. Temperature Measurement Range and Offset Temperature Measurement Range (°C) Temperature Offset 50 125 –2 20 100 –1 –10 80 0 –30 50 1 –40 20 2 40.4.5 Data Conversion The sensor output value is stored in APB_SARADC_TSENS_OUT. To calculate the actual temperature T (°C) based on V ALU E, use the following equation: T = 0.4386 ∗ V ALUE–27.88 ∗ of f set–20.52 where of f set is the temperature offset shown in Table 40.4-1. 40.5 Programming Procedure The temperature sensor can be started by software as follows: 1. Set APB_SARADC_TSENS_PU to power up the temperature sensor. 2. Set PCR_TSENS_CLK_EN to enable the temperature sensor clock. 3. Configure APB_SARADC_TSENS_CLK_SEL to select the temperature sensor clock. 4. Wait for APB_SARADC_TSENS_XPD_WAIT clock cycles till the temperature sensor releases from reset and starts measuring the temperature. Espressif Systems 1438 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 40 Temperature Sensor 5. Wait for 100 µs (so that the output value gradually approaches the actual temperature) and then read the data from APB_SARADC_TSENS_OUT. To enable hardware-triggered automatic temperature monitoring, add the following programming steps before powering up the sensor: 1. Configure APB_SARADC_TSENS_SAMPLE_RATE to set sampling rate. 2. Configure APB_SARADC_WAKEUP_MODE to select an automatic temperature monitoring mode. 3. Configure APB_SARADC_WAKEUP_TH_HIGH/LOW to set the high and low temperature monitoring thresholds. 4. Set APB_SARADC_WAKEUP_EN to start temperature monitoring. 5. Set APB_SARADC_TSENS_SAMPLE_EN to enable automatic temperature monitoring. In automatic temperature monitoring mode, the output value will not be stored. However, users can get the value anytime from APB_SARADC_TSENS_OUT. 40.6 Interrupts ESP32-C5’s Temperature Sensor can generate the following interrupt signal that will be sent to the Interrupt Matrix. • LP_TSENS_INTR There is one internal interrupt source from the Temperature Sensor that can generate the above interrupt signal: • APB_SARADC_TSENS_INT: Triggered when the temperature sample value exceeds the threshold. Note: For definitions of interrupt, interrupt signal, interrupt source, and their correlations, please refer to Chapter 9 Interrupt Matrix > Section 9.2 Terminology. Each interrupt source can be configured by a common set of registers that are described in Section Interrupt Configuration Registers. The specific registers can be found in Section 40.8 Register Summary. 40.7 Event Task Matrix Feature The temperature sensor on ESP32-C5 supports the Event Task Matrix (ETM) function, which allows the temperature sensor’s ETM tasks to be triggered by any peripherals’ ETM events, or temperature sensor’s ETM events to trigger any peripherals’ ETM tasks. This section introduces the ETM tasks and events related to the temperature sensor. For more information, please refer to Chapter 10 Event Task Matrix (ETM). The temperature sensor can receive the following ETM tasks: • TMPSNSR_TASK_START_SAMPLE: The temperature sensor starts sampling when this task is triggered. • TMPSNSR_TASK_STOP_SAMPLE: The temperature sensor stops sampling when this task is triggered. The temperature sensor can generate the following ETM events: Espressif Systems 1439 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 40 Temperature Sensor • TMPSNSR_EVT_OVER_LIMIT: Generated when the temperature is beyond the threshold. In practical applications, temperature sensor’s ETM events can trigger its own ETM tasks. For example, the TMPSNSR_EVT_OVER_LIMIT event can trigger the TMPSNSR_TASK_STOP_SAMPLE task. Espressif Systems 1440 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 40 Temperature Sensor 40.8 Register Summary The addresses in this section are relative to Temperature Sensor base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Configuration Registers APB_SARADC_INT_ENA_REG Enable register of SAR ADC/temperature sensor interrupts 0x0040 R/W APB_SARADC_INT_RAW_REG Raw register of SAR ADC/temperature sensor interrupts 0x0044 R/WTC/SS APB_SARADC_INT_ST_REG State register of SAR ADC/temperature sensor interrupts 0x0048 RO APB_SARADC_INT_CLR_REG Clear register of SAR ADC/temperature sensor interrupts 0x004C WT APB_SARADC_APB_TSENS_CTRL_REG Temperature sensor control register 1 0x0058 varies APB_SARADC_APB_TSENS_CTRL2_REG Temperature sensor control register 2 0x005C R/W APB_TSENS_WAKE_REG Temperature sensor automatic monitoring mode configuration register 0x0064 varies APB_TSENS_SAMPLE_REG Temperature sensor configuration register 0x0068 R/W Version Control Register APB_SARADC_CTRL_DATE_REG Version control register 0x03FC R/W Espressif Systems 1441 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 40 Temperature Sensor 40.9 Registers The addresses in this section are relative to Temperature Sensor base address provided in Table 4.3-2 in Chapter 4 System and Memory. For how to program reserved fields, please refer to Section Programming Reserved Register Field. Register 40.1. APB_SARADC_APB_TSENS_CTRL_REG (0x0058) (reserved) 0 0 0 0 0 0 0 0 0 31 23 APB_SARADC_TSENS_PU 0 22 APB_SARADC_TSENS_CLK_DIV 6 21 14 APB_SARADC_TSENS_IN_INV 0 13 (reserved) 0 0 0 0 0 12 8 APB_SARADC_TSENS_OUT 0x80 7 0 Reset APB_SARADC_TSENS_OUT Stores the temperature sensor output value. (RO) APB_SARADC_TSENS_IN_INV Configures whether to invert temperature sensor data. 0: No effect 1: Invert (R/W) APB_SARADC_TSENS_CLK_DIV Configures temperature sensor clock division. (R/W) APB_SARADC_TSENS_PU Configures whether to power up temperature sensor. 0: No effect 1: Power up (R/W) Espressif Systems 1442 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 40 Temperature Sensor Register 40.2. APB_SARADC_APB_TSENS_CTRL2_REG (0x005C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 16 APB_SARADC_TSENS_CLK_SEL 0 15 APB_SARADC_TSENS_CLK_INV 0x0 14 APB_SARADC_TSENS_XPD_FORCE 0x0 13 12 APB_SARADC_TSENS_XPD_WAIT 0x2 11 0 Reset APB_SARADC_TSENS_CLK_SEL Configures the working clock for temperature sensor. 0: RC_FAST_CLK 1: XTAL_CLK (R/W) APB_SARADC_TSENS_CLK_INV Configures the phase of the temperature sensor clock. (R/W) APB_SARADC_TSENS_XPD_FORCE Configures whether to enable force power up/down the tem- perature sensor. 0: Disable force power up function 1: Disable force power down function 2: Enable force power up temperature sensor 3: Enable force power down temperature sensor (R/W) APB_SARADC_TSENS_XPD_WAIT Configure the wait time (in clock cycles) for the senor to release from reset. (R/W) Espressif Systems 1443 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 40 Temperature Sensor Register 40.3. APB_TSENS_WAKE_REG (0x0064) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 31 19 APB_SARADC_WAKEUP_EN 0 18 APB_SARADC_WAKEUP_MODE 0 17 APB_SARADC_WAKEUP_OVER_UPPER_TH 0 16 APB_SARADC_WAKEUP_TH_HIGH 0xff 15 8 APB_SARADC_WAKEUP_TH_LOW 0x0 7 0 Reset APB_SARADC_WAKEUP_TH_LOW Configures the low threshold for automatic temperature moni- toring. (R/W) APB_SARADC_WAKEUP_TH_HIGH Configures the high threshold for automatic temperature mon- itoring. (R/W) APB_SARADC_WAKEUP_OVER_UPPER_TH Represents whether the temperature output value exceeds the threshold. Valid only when APB_SARADC_WAKEUP_EN=1. 0: The temperature output value is below the low threshold 1: The temperature output value is above the high threshold (RO) APB_SARADC_WAKEUP_MODE Selects the temperature monitoring mode. 0: Absolute value mode 1: Change value mode (R/W) APB_SARADC_WAKEUP_EN Configures whether to enable the temperature monitoring function. 0: Disable 1: Enable (R/W) Espressif Systems 1444 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 40 Temperature Sensor Register 40.4. APB_TSENS_SAMPLE_REG (0x0068) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 17 APB_SARADC_TSENS_SAMPLE_EN 0 16 APB_SARADC_TSENS_SAMPLE_RATE 20 15 0 Reset APB_SARADC_TSENS_SAMPLE_RATE Configures the sampling rate for hardware-triggered auto- matic temperature monitoring. The sampling period = configured value × the sensor’s working clock cycle. (R/W) APB_SARADC_TSENS_SAMPLE_EN Configures whether to enable automatic temperature moni- toring. 0: Disable 1: Enable (R/W) Register 40.5. APB_SARADC_CTRL_DATE_REG (0x03FC) APB_SARADC_DATE 0x2206240 31 0 Reset APB_SARADC_DATE Version control register for SAR ADC (please refer to Chapter 41 ADC Controller for more information) and the temperature sensor. (R/W) Espressif Systems 1445 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 41 ADC Controller Chapter 41 ADC Controller 41.1 Overview ESP32-C5 integrates one 12-bit successive approximation ADC (SAR ADC) for measuring analog signals from up to six channels. The SAR ADC is managed by the DIG ADC controller that drives ADC sampling. The SAR ADC supports one-shot sampling and multi-channel sampling. 41.2 Terminology The following terms related to SAR ADC are defined in the context of the ESP32-C5 Technical Reference Manual to help readers better understand this document: SAR ADC: Including analog ADC circuit and digital ADC controller. One-shot sampling mode: In this mode, ADC samples one channel at a time. Multi-channel sampling mode: In this mode, ADC sequentially samples a group of channels or con- tinuously samples a single channel. Conversion result: The conversion result is the binary digital value obtained after the analog-to-digital conversion process. It is sometimes written as conversion data. Filtered data: Filtered data is the result of processing conversion data through a filter. Sampling: The term typically refers to the entire process of sampling analog in- puts, converting the sampled data, and transferring the conversion results to memory. In certain contexts and stages of the process, sampling may also refer to the SAR ADC capturing data points from an analog signal. 41.3 Feature List The SAR ADC has the following features: • 12-bit resolution • Analog inputs sampling from up to six pins • One-shot sampling mode and multi-channel sampling mode • Multi-channel sampling mode supports: Espressif Systems 1446 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 41 ADC Controller – configurable channel sampling sequence – two filters whose filter coefficients are configurable – two threshold monitors that can trigger an interrupt when the filtered value is below a low threshold or above a high threshold – continuous transfer of converted data to memory via GDMA interface • Support for several Event Task Matrix (ETM) related events and tasks 41.4 Architectural Overview The major components of SAR ADC and their interconnections are shown in Figure 41.4-1. Analog Domain MTDI MTCK MTDO MTMS GPIO6 Pattern Select APB Interface & Registers Filters GDMA Interface Threshold Monitorx FIFO sar_channel ADC 12-bit data & Analog ack. signal ADC Analog Circuit Control Signal sar_en_pad[4:0] & atten[1:0] Channel[2:0] Atten[1:0] 0~5 0~5 0~5 0~5 0~5 0~5 0~5 0~5 0~3 0~3 0~3 0~3 0~3 0~3 0~3 0~3 Pattern Table once sample done adc_raw_data SAR_CLK : Data Flow DIG ADC Controller ADC_CTRL_CLK : Clock Signal APB_CLK DIG ADC FSM Digital_reader SW One-Shot Trigger SW Control Trigger Signal SAR ADC Input Channels HW Timer Trigger XTAL_32K_N Figure 41.4-1. SAR ADC Architecture As Figure 41.4-1 shows, the SAR ADC module contains the following major functional blocks: • Six channels, connected to six pins on the chip • SAR ADC: analog domain of the SAR ADC module • DIG ADC Controller: digital domain of the SAR ADC module, mainly including: – Clock management module: selects clock source and division – DIG ADC FSM: generates the signals required throughout the ADC sampling process Espressif Systems 1447 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 41 ADC Controller – Digital_reader: reads data from SAR ADC, driven by DIG ADC FSM – Filter: filters ADC converted data in multi-channel sampling mode – Threshold monitorx: threshold monitor 1 and threshold monitor 2. The monitorx will trigger an interrupt when the converted value is below a low threshold or above a high threshold. 41.5 Functional Description 41.5.1 ADC Power Up The ADC can be powered up by setting PMU_XPD_PERIF_I2C and PMU_PERIF_I2C_RST. ADC sampling can be performed right after power-up. Users do not need to worry about wait time, as it has been dealt with in hardware design. 41.5.2 ADC Channels The SAR ADC has six channels that are connected to six pins on the chip. In order to sample an analog signal, the SAR ADC must first select the analog pin to measure via an internal multiplexer. Table 41.5-1 shows the pins used as ADC channels and the corresponding GPIO numbers. Table 41.5-1. SAR ADC Channels Pin Name GPIO Number ADC Channel XTAL_32K_N GPIO1 0 MTMS GPIO2 1 MTDI GPIO3 2 MTCK GPIO4 3 MTDO GPIO5 4 GPIO6 GPIO6 5 41.5.3 ADC Clock Figure 41.5-1 shows the clock structure of SAR ADC. Clock mux Clock divider Clock divider PCR_SAR1_CLK_DIV_NUM PCR_SARADC_CLKM_DIV_NUM PCR_SARADC_CLKM_SEL SAR_CLK ADC_CTRL_CLK XTAL_CLK RC_FAST_CLK PLL_80M_CLK Figure 41.5-1. SAR ADC Clock Structure Espressif Systems 1448 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 41 ADC Controller The system clock for SAR ADC is ADC_CTRL_CLK, which is the operating clock for DIG ADC FSM and other control logic (except APB interface and Digital_reader). ADC_CTRL_CLK has three possible sources: XTAL_CLK, RC_FAST_CLK, and PLL_80M_CLK, selected by PCR_SARADC_CLKM_SEL. SAR_CLK is the operating clock for SAR ADC and Digital_reader. It is divided from ADC_CTRL_CLK and must not exceed 5 MHz. For more information about clocks, please refer to Chapter 7 Reset and Clock. 41.5.4 One-Shot Sampling Mode In one-shot sampling mode, the ADC samples one channel once. This mode is started by software using APB_SARADC_ONETIME_SAMPLE. Once sampling is done, the conversion result is stored in APB_SARADC_DATA. To switch channels, configure APB_SARADC_ONETIME_SAMPLE once again. 41.5.5 Multi-Channel Sampling Mode Multi-channel sampling mode is triggered by a timer that is specifically designed for SAR ADC. In this mode the ADC samples a group of channels according to the sequence defined in the pattern table. The multi-channel sampling mode can also be used for continuous sampling on one channel. The timer is enabled by setting APB_SARADC_TIMER_EN. A trigger target for the timer needs to be configured with APB_SARADC_TIMER_TARGET. When the timer counts up to two times of APB_SARADC_TIMER_TARGET, a sampling operation is triggered. The timer is clocked from ADC_CTRL_CLK. When sampling is complete, the timer resets to 0 and starts counting again. The conversion result is transferred to memory continuously via the GDMA interface. Note: The SAR ADC can only work under one operating mode at one time, either one-shot sampling mode or multi-channel sampling mode. 41.5.6 ADC Conversion and Attenuation The SAR ADC can measure analog voltages from 0 mV to V ref . V ref is the SAR ADC’s internal reference voltage (1100 mV by design). The conversion result (data) is a 12-bit digital value, the raw data. To calculate the voltage V data based on the raw data, please use the formula below: V data = V ref k × data 4095 k is the coefficient corresponding to the configured attenuation. To convert voltages larger than V ref , apply attenuation to the input signals using APB_SARADC_ONETIME_ATTEN. The attenuation can be 0 dB, 2.5 dB, 6 dB, or 12 dB. Espressif Systems 1449 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 41 ADC Controller 41.5.7 DIG ADC FSM In multi-channel sampling mode DIG ADC FSM (hereinafter referred to as FSM) generates all types of signals used in the sampling process. Figure 41.5-2 illustrates how DIG ADC FSM works. Channel [ 2 :0] 0~5 0~5 0~5 0~5 0~5 0~5 0~5 Atten [1:0] 0~3 0~3 0~3 0~3 0~3 0~3 0~3 0~5 0~3 pr Timer table_length sample_start timer_en FSM en_pin atten reader_done xpd_sar_fsm sar_start f s m _ d o n e Figure 41.5-2. DIG ADC FSM Block Diagram Wherein: • Timer: a dedicated timer for the DIG ADC controller to generate signal. • pr: a pointer to the pattern table that defines the conversion rules for ADC. FSM sends out corresponding signals based on the conversion rules. Set APB_SARADC_TIMER_EN to enable the timer. The timeout event of this timer triggers a signal. This signal drives the FSM module to start sampling. When the FSM module receives the signal, it starts the following operations: • Powers up SAR ADC. • Determines the conversion rules (selected sample channels and attenuations) defined in the patterns that the current pr points to. • Outputs the and signals corresponding to the conversion rules to the analog side. • Initiates the signal and starts sampling. When FSM receives the signal from Digital_reader, it starts the following operations: • Stops sampling. • Transfers the conversion result to the filter. Then the threshold monitor transfers the filtered result to memory via GDMA (see Figure 41.4-1). Espressif Systems 1450 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 41 ADC Controller • Updates pr and waits for the next sampling. The pointer pr counts cyclically between 0 and APB_SARADC_SAR_PATT_LEN (table_length). 41.5.8 Pattern Table FSM contains a pattern table consisting of the APB_SARADC_SAR_PATT_TAB1_REG and APB_SARADC_SAR_PATT_TAB2_REG registers. Each register contains four patterns and each pattern is 6 bits wide, as Figure 41.5-3 and Figure 41.5-4 show. (reserved) 0 0 0 0 0 0 0 0 31 24 cmd0 0x0000 23 18 cmd1 0x0000 17 12 cmd2 0x0000 11 6 cmd3 0x0000 5 0 cmd x represents patterns 0 3. Figure 41.5-3. APB_SARADC_SAR_PATT_TAB1_REG Contains Patterns 0 - 3 (reserved) 0 0 0 0 0 0 0 0 31 24 cmd4 0x0000 23 18 cmd5 0x0000 17 12 cmd6 0x0000 11 6 cmd7 0x0000 5 0 cmd x represents patterns 4 7. Figure 41.5-4. APB_SARADC_SAR_PATT_TAB2_REG Contains Patterns 4 - 7 Each pattern is 6 bits wide, consisting of three fields where conversion rules are stored. Figure 41.5-5 shows the pattern format and is followed by the descriptions of each field. (reserved) 0 5 ch_sel xx 4 2 atten x x 1 0 Figure 41.5-5. Pattern Structure atten Configures attenuation: 0: 0 dB 1: 2.5 dB 2: 6 dB 3: 12 dB ch_sel Configures channel: 0: Channel 0 1: Channel 1 2: Channel 2 3: Channel 3 4: Channel 4 5: Channel 5 Espressif Systems 1451 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 41 ADC Controller (reserved) Reserved Pattern Configuration Example Note: When using multi-channel continuous sampling, the attenuation for each channel must be set to be consistent. In this example, two channels are selected for multi-channel sampling: • Channel 0, with an attenuation of 2.5 dB • Channel 2, with an attenuation of 2.5 dB The detailed configuration is as follows: • Configure the first pattern (cmd0): (reserved) 0 5 ch_sel 0 4 2 atten 1 1 0 Figure 41.5-6. cmd0 configuration atten write 1 to this field, to set the attenuation to 2.5 dB. ch_sel write 0 to this field, to select channel 0. • Configure the second pattern (cmd1): (reserved) 0 5 ch_sel 2 4 2 atten 1 1 0 Figure 41.5-7. cmd1 Configuration atten write 1 to this field, to set the attenuation to 2.5 dB. ch_sel write 2 to this field, to select channel 2. • Configure APB_SARADC_SAR_PATT_LEN to 1. Then patterns cmd0 and cmd1 will be used. • Enable the timer so that the DIG ADC controller starts sampling the two channels periodically. 41.5.9 ADC Filters The DIG ADC controller provides two filters for filtering ADC converted data in multi-channel sampling mode. Both filters can be configured to any ADC channel, but cannot be configured to the same channel. If the two filters are configured to the same channel, the first one takes effect. The filtered data is determined by the following equation: data cur = (k − 1)data prev k + data in k + 0.5 • data cur : the filtered data • data in : the ADC converted data Espressif Systems 1452 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 41 ADC Controller • data prev : the last filtered data • k: the filter coefficient The filters are configured as follows: • Configure APB_SARADC_FILTER_CHANNELx to select the ADC channel for filter x (x=0, 1). • Configure APB_SARADC_FILTER_FACTORx to set the coefficient k for filter x. 41.5.10 Threshold Monitors Two threshold monitors are available in the DIG ADC controller to monitor the filtered data in multi-channel sampling mode. When the data is above the high threshold, a high threshold interrupt is triggered; when the data is below the low threshold, a low threshold interrupt is triggered. Both monitors can be configured to any ADC channel, but cannot be configured to the same channel. Threshold monitors are configured as follows: • Set APB_SARADC_THRESx_EN to enable threshold monitor x (x=0, 1). • Configure APB_SARADC_THRESx_LOW to set a low threshold. • Configure APB_SARADC_THRESx_HIGH to set a high threshold. • Configure APB_SARADC_THRESx_CHANNEL to select the channel to monitor. • Set APB_SARADC_THRES_ALL_EN to enable threshold monitoring functionality. 41.5.11 GDMA Support As SAR ADC has only one data register APB_SARADC_DATA for storing converted result from one-shot sampling, it is necessary to enable GDMA when converting data on multiple channels so that the data can be transferred to memory continuously. GDMA support is triggered by the timer in the DIG ADC controller. Users can switch the DMA data path to the DIG ADC controller by configuring APB_SARADC_APB_ADC_TRANS. For specific DMA configuration, please refer to Chapter 3 GDMA Controller (GDMA). GDMA Data Format The ADC eventually passes 32-bit data to GDMA. The data format is shown in Figure 41.5-8. (reserved) xx 31 17 (reserved) x 16 ch_sel xxx 15 13 (reserved) x 12 data x x 11 0 Figure 41.5-8. DMA Data Format data 12-bit ADC conversion result ch_sel 3-bit channel information Espressif Systems 1453 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 41 ADC Controller 41.6 Event Task Matrix Feature The SAR ADC on ESP32-C5 supports the Event Task Matrix (ETM) function, which allows SAR ADC’s ETM tasks to be triggered by any peripherals’ ETM events, or SAR ADC’s ETM events to trigger any peripherals’ ETM tasks. This section introduces the ETM tasks and events related to SAR ADC and temperature sensor. For more information, please refer to Chapter 10 Event Task Matrix (ETM). The SAR ADC can receive the following ETM tasks: • ADC_TASK_SAMPLE0: ADC starts one-shot sampling when this task is triggered. • ADC_TASK_START0: ADC starts multi-channel sampling when this task is triggered. • ADC_TASK_STOP0: ADC stops sampling when this task is triggered. The SAR ADC can generate the following ETM events: • ADC_EVT_CONV_CMPLT0: Generated each time ADC completes a sampling in either one-shot sampling mode or multi-channel sampling mode. • ADC_EVT_EQ_ABOVE_THRESHx: Generated when the ADC filtered data is above the threshold. x = 0, 1, representing threshold monitor 0, 1. • ADC_EVT_EQ_BELOW_THRESHx: Generated when the ADC filtered data is below the threshold. x = 0, 1, representing threshold monitor 0, 1. • ADC_EVT_STARTED0: Generated when ADC begins sampling; one-shot sampling will not trigger this event. • ADC_EVT_STOPPED0: Generated when ADC stops sampling, one-shot sampling will not trigger this event. In practical applications, SAR ADC’s ETM events can trigger its own ETM tasks. For example, the ADC_EVT_EQ_ABOVE_THRESHx event can trigger the ADC_TASK_STOP0 task. 41.7 Interrupts ESP32-C5’s SAR ADC can generate the APB_ADC_INTR interrupt signal that will be sent to the Interrupt Matrix. The following internal interrupt sources from SAR ADC can generate the interrupt signal APB_ADC_INTR: • APB_SARADC_ADC_DONE_INT: Triggered when SAR ADC completes one conversion. • APB_SARADC_THRESx_HIGH_INT: Triggered when the filtered data is above the high threshold of monitor x. • APB_SARADC_THRESx_LOW_INT: Triggered when the filtered data is below the low threshold of monitor x. Note: For definitions of interrupt, interrupt signal, interrupt source, and their correlations, please refer to Chapter 9 Interrupt Matrix > Section 9.2 Terminology. Each interrupt source can be configured by a common set of registers that are described in Section Interrupt Configuration Registers. The specific registers can be found in Section 41.9 Register Summary. Espressif Systems 1454 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 41 ADC Controller 41.8 Programming Procedure 41.8.1 Configuring One-shot Sampling Mode The one-shot sampling mode can be configured with the following procedure: 1. Set PMU_XPD_PERIF_I2C and PMU_PERIF_I2C_RST to power up SAR ADC. 2. Configure PCR_SARADC_CLKM_SEL to select ADC clock source. 3. Configure PCR_SARADC_CLKM_DIV_NUM and PCR_SAR1_CLK_DIV_NUM to set clock division. 4. Set PCR_SARADC_CLKM_EN to enable ADC clock. 5. Set APB_SARADC_ONETIME_SAMPLE to enable the one-shot sampling mode. 6. Configure APB_SARADC_ONETIME_CHANNEL to select sampled channel. 7. Configure APB_SARADC_ONETIME_ATTEN to set attenuation as needed. 8. Set APB_SARADC_ONETIME_START to start one-shot sampling. Once sampling is complete, an APB_SARADC_ADC_DONE_INT_RAW interrupt is generated. Software can read conversion result from APB_SARADC_ADC_DATA. To switch the sampled channel, program from step 6. 41.8.2 Configuring Multi-Channel Sampling Mode The multi-channel sampling mode can be configured with the following procedure: 1. Set PMU_XPD_PERIF_I2C and PMU_PERIF_I2C_RST to power up SAR ADC. 2. Configure PCR_SARADC_CLKM_SEL to select ADC clock source. 3. Configure PCR_SARADC_CLKM_DIV_NUM and PCR_SAR1_CLK_DIV_NUM to set clock division. 4. Set PCR_SARADC_CLKM_EN to enable ADC clock. 5. Configure the pattern table as described in Section 41.5.8 Pattern Table. 6. Configure channels and filtering coefficients as described in Section 41.5.9 ADC Filters. 7. Configure threshold monitoring as described in Section 41.5.10 Threshold Monitors, as needed. 8. Set APB_SARADC_APB_ADC_TRANS to use GDMA. 9. Configure APB_SARADC_TIMER_TARGET to set trigger target for DIG ADC timer. 10. Set APB_SARADC_TIMER_EN to enable the timer. The timer timeout will trigger DIG ADC FSM to start sampling according to the pattern table. The conversion result will be automatically stored in memory. When the sampling reaches the number of limit set in APB_SARADC_APB_ADC_EOF_NUM, it will terminate. Once sampling is complete, an APB_SARADC_ADC_DONE_INT_RAW interrupt will be generated. Espressif Systems 1455 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 41 ADC Controller 41.9 Register Summary The addresses in this section are relative to SAR ADC Controller base address provided in Table 4.3-2 in Chapter 4 System and Memory. The abbreviations given in Column Access are explained in Section Access Types for Registers. Name Description Address Access Configuration Registers APB_SARADC_CTRL_REG SAR ADC control register 1 0x0000 R/W APB_SARADC_CTRL2_REG SAR ADC control register 2 0x0004 R/W APB_SARADC_FILTER_CTRL1_REG Filtering control register 1 0x0008 R/W APB_SARADC_SAR_PATT_TAB1_REG Pattern table register 1 0x0018 R/W APB_SARADC_SAR_PATT_TAB2_REG Pattern table register 2 0x001C R/W APB_SARADC_ONETIME_SAMPLE_REG Configuration register for one-shot sampling 0x0020 R/W APB_SARADC_FILTER_CTRL0_REG Filtering control register 0 0x0028 R/W APB_SARADC_SAR1DATA_STATUS_REG SAR ADC conversion data storage register 0x002C RO APB_SARADC_THRES0_CTRL_REG Filtered data threshold control reg- ister 0 0x0034 R/W APB_SARADC_THRES1_CTRL_REG Filtered data threshold control reg- ister 1 0x0038 R/W APB_SARADC_THRES_CTRL_REG Filtered data threshold control reg- ister 0x003C R/W APB_SARADC_INT_ENA_REG Enable register of SAR ADC inter- rupts 0x0040 R/W APB_SARADC_INT_RAW_REG Raw register of SAR ADC inter- rupts 0x0044 R/WTC/SS APB_SARADC_INT_ST_REG State register of SAR ADC inter- rupts 0x0048 RO APB_SARADC_INT_CLR_REG Clear register of SAR ADC inter- rupts 0x004C WT APB_SARADC_DMA_CONF_REG DMA configuration register for SAR ADC 0x0050 R/W APB_SARADC_CTRL_DATE_REG Version control register 0x03FC R/W Espressif Systems 1456 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 41 ADC Controller 41.10 Registers The addresses in this section are relative to SAR ADC Controller base address provided in Table 4.3-2 in Chapter 4 System and Memory. Register 41.1. APB_SARADC_CTRL_REG (0x0000) (reserved) 0 31 29 APB_SARADC_XPD_SAR_FORCE 0 28 27 (reserved) 0 0 0 26 24 APB_SARADC_SAR_PATT_P_CLEAR 0 23 (reserved) 0 0 0 0 0 22 18 APB_SARADC_SAR_PATT_LEN 7 17 15 (reserved) 4 14 7 APB_SARADC_SAR_CLK_GATED 1 6 (reserved) 0 0 0 0 5 2 APB_SARADC_START 0 1 APB_SARADC_START_FORCE 0 0 Reset APB_SARADC_START_FORCE Configures whether to use software to enable SAR ADC. 0: Select FSM to start SAR ADC 1: Select software to start SAR ADC (R/W) APB_SARADC_START Configures whether to start SAR ADC by software. 0: No effect 1: Start SAR ADC by software Valid only when APB_SARADC_START_FORCE = 1. (R/W) APB_SARADC_SAR_CLK_GATED Configures whether to enable SAR ADC clock gate. 0: Disable 1: Enable (R/W) APB_SARADC_SAR_PATT_LEN Configures how many patterns will be used. 0: Use only cmd0 1: Use cmd0 and cmd1 n: Use cmd0 to cmdn, the maximum n is 7 (R/W) APB_SARADC_SAR_PATT_P_CLEAR Configures whether to clear the pointer of pattern table for DIG ADC controller. 0: No effect 1: Clear (R/W) APB_SARADC_XPD_SAR_FORCE Configures whether to forcibly power up SAR ADC. 0: No effect 1: Forcibly power up SAR ADC (R/W) Espressif Systems 1457 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 41 ADC Controller Register 41.2. APB_SARADC_CTRL2_REG (0x0004) (reserved) 0 0 0 0 0 0 0 31 25 APB_SARADC_TIMER_EN 0 24 APB_SARADC_TIMER_TARGET 10 23 12 (reserved) 0 11 (reserved) 0 10 APB_SARADC_SAR1_INV 0 9 APB_SARADC_MAX_MEAS_NUM 255 8 1 APB_SARADC_MEAS_NUM_LIMIT 0 0 Reset APB_SARADC_MEAS_NUM_LIMIT Configures whether to enable the limitation of SAR ADC’s max- imum conversion times. 0: Disable 1: Enable (R/W) APB_SARADC_MAX_MEAS_NUM Configures the SAR ADC’s maximum conversion times. (R/W) APB_SARADC_SAR1_INV Configures whether to invert the data of SAR ADC. 0: No effect 1: Invert the data of SAR ADC (R/W) APB_SARADC_TIMER_TARGET Configures SAR ADC timer target. (R/W) APB_SARADC_TIMER_EN Configures whether to enable SAR ADC timer trigger. 0: Disable 1: Enable (R/W) Espressif Systems 1458 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 41 ADC Controller Register 41.3. APB_SARADC_FILTER_CTRL1_REG (0x0008) APB_SARADC_FILTER_FACTOR0 0 31 29 APB_SARADC_FILTER_FACTOR1 0 28 26 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 0 Reset APB_SARADC_FILTER_FACTOR1 Configures the filter coefficient k for SAR ADC filter 1. 0: k=0 (i.e., the filter is disabled) 1: k=2 2: k=4 3: k=8 4: k=16 5: k=32 6: k=64 (R/W) APB_SARADC_FILTER_FACTOR0 Configures the filter coefficient k for SAR ADC filter 0 (same as above). (R/W) Register 41.4. APB_SARADC_SAR_PATT_TAB1_REG (0x0018) (reserved) 0 0 0 0 0 0 0 0 31 24 APB_SARADC_SAR_PATT_TAB1 0xffffff 23 0 Reset APB_SARADC_SAR_PATT_TAB1 Configures pattern 0 3 (each pattern takes six bits). For details see Section 41.5.8 Pattern Table. (R/W) Espressif Systems 1459 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 41 ADC Controller Register 41.5. APB_SARADC_SAR_PATT_TAB2_REG (0x001C) (reserved) 0 0 0 0 0 0 0 0 31 24 APB_SARADC_SAR_PATT_TAB2 0xffffff 23 0 Reset APB_SARADC_SAR_PATT_TAB2 Configures pattern 4 7 (each pattern takes six bits). For details see Section 41.5.8 Pattern Table. (R/W) Espressif Systems 1460 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 41 ADC Controller Register 41.6. APB_SARADC_ONETIME_SAMPLE_REG (0x0020) APB_SARADC_ONETIME_SAMPLE 0 31 (reserved) 0 30 APB_SARADC_ONETIME_START 0 29 APB_SARADC_ONETIME_CHANNEL 13 28 25 APB_SARADC_ONETIME_ATTEN 0 24 23 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22 0 Reset APB_SARADC_ONETIME_ATTEN Configures the attenuation for a one-shot sampling. 0: 0 dB 1: 2.5 dB 2: 6 dB 3: 12 dB (R/W) APB_SARADC_ONETIME_CHANNEL Configures the channel for a one-shot sampling. 0: Channel 0 1: Channel 1 2: Channel 2 3: Channel 3 4: Channel 4 5: Channel 5 (R/W) APB_SARADC_ONETIME_START Configures whether to start SAR ADC one-shot sampling. 0: No effect 1: Start (R/W) APB_SARADC_ONETIME_SAMPLE Configures whether to enable SAR ADC one-shot sampling. 0: Disable 1: Enable (R/W) Espressif Systems 1461 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 41 ADC Controller Register 41.7. APB_SARADC_FILTER_CTRL0_REG (0x0028) APB_SARADC_FILTER_RESET 0 31 (reserved) 0 0 0 0 0 30 26 APB_SARADC_FILTER_CHANNEL0 13 25 22 APB_SARADC_FILTER_CHANNEL1 13 21 18 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 0 Reset APB_SARADC_FILTER_CHANNEL1 Configures the filter channel for SAR ADC filter 1. (R/W) APB_SARADC_FILTER_CHANNEL0 Configures the filter channel for SAR ADC filter 0. (R/W) APB_SARADC_FILTER_RESET Configures whether to reset SAR ADC filter. 0: No effect 1: Reset (R/W) Register 41.8. APB_SARADC_SAR1DATA_STATUS_REG (0x002C) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 17 APB_SARADC_DATA 0 16 0 Reset APB_SARADC_DATA Stores SAR ADC conversion data in one-shot sampling mode. (RO) Espressif Systems 1462 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 41 ADC Controller Register 41.9. APB_SARADC_THRES0_CTRL_REG (0x0034) (reserved) 0 31 APB_SARADC_THRES0_LOW 0 30 18 APB_SARADC_THRES0_HIGH 0x1fff 17 5 (reserved) 0 4 APB_SARADC_THRES0_CHANNEL 13 3 0 Reset APB_SARADC_THRES0_CHANNEL Configures the channel for SAR ADC monitor 0. (R/W) APB_SARADC_THRES0_HIGH Configures the high threshold for SAR ADC monitor 0. (R/W) APB_SARADC_THRES0_LOW Configures the low threshold for SAR ADC monitor 0. (R/W) Register 41.10. APB_SARADC_THRES1_CTRL_REG (0x0038) (reserved) 0 31 APB_SARADC_THRES1_LOW 0 30 18 APB_SARADC_THRES1_HIGH 0x1fff 17 5 (reserved) 0 4 APB_SARADC_THRES1_CHANNEL 13 3 0 Reset APB_SARADC_THRES1_CHANNEL Configures the channel for SAR ADC monitor 1. (R/W) APB_SARADC_THRES1_HIGH Configures the high threshold for SAR ADC monitor 1. (R/W) APB_SARADC_THRES1_LOW Configures the low threshold for SAR ADC monitor 1. (R/W) Espressif Systems 1463 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 41 ADC Controller Register 41.11. APB_SARADC_THRES_CTRL_REG (0x003C) APB_SARADC_THRES0_EN 0 31 APB_SARADC_THRES1_EN 0 30 (reserved) 0 0 29 28 APB_SARADC_THRES_ALL_EN 0 27 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 26 0 Reset APB_SARADC_THRES_ALL_EN Configures whether to enable the threshold monitoring for all con- figured channels. 0: Disable 1: Enable (R/W) APB_SARADC_THRES1_EN Configures whether to enable threshold monitor 1. 0: Disable 1: Enable (R/W) APB_SARADC_THRES0_EN Configures whether to enable threshold monitor 0. 0: Disable 1: Enable (R/W) Espressif Systems 1464 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 41 ADC Controller Register 41.12. APB_SARADC_INT_ENA_REG (0x0040) APB_SARADC_ADC_DONE_INT_ENA 0 31 (reserved) 0 30 APB_SARADC_THRES0_HIGH_INT_ENA 0 29 APB_SARADC_THRES1_HIGH_INT_ENA 0 28 APB_SARADC_THRES0_LOW_INT_ENA 0 27 APB_SARADC_THRES1_LOW_INT_ENA 0 26 APB_SARADC_TSENS_INT_ENA 0 25 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 0 Reset APB_SARADC_TSENS_INT_ENA Write 1 to enable the APB_SARADC_TSENS_INT [TBA] interrupt. (R/W) APB_SARADC_THRES1_LOW_INT_ENA Write 1 to enable the APB_SARADC_THRES1_LOW_INT interrupt. (R/W) APB_SARADC_THRES0_LOW_INT_ENA Write 1 to enable the APB_SARADC_THRES0_LOW_INT interrupt. (R/W) APB_SARADC_THRES1_HIGH_INT_ENA Write 1 to enable the APB_SARADC_THRES1_HIGH_INT interrupt. (R/W) APB_SARADC_THRES0_HIGH_INT_ENA Write 1 to enable the APB_SARADC_THRES0_HIGH_INT interrupt. (R/W) APB_SARADC_ADC_DONE_INT_ENA Write 1 to enable the APB_SARADC_ADC_DONE_INT inter- rupt. (R/W) Espressif Systems 1465 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 41 ADC Controller Register 41.13. APB_SARADC_INT_RAW_REG (0x0044) APB_SARADC_ADC_DONE_INT_RAW 0 31 (reserved) 0 30 APB_SARADC_THRES0_HIGH_INT_RAW 0 29 APB_SARADC_THRES1_HIGH_INT_RAW 0 28 APB_SARADC_THRES0_LOW_INT_RAW 0 27 APB_SARADC_THRES1_LOW_INT_RAW 0 26 APB_SARADC_TSENS_INT_RAW 0 25 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 0 Reset APB_SARADC_TSENS_INT_RAW The raw interrupt status of the APB_SARADC_TSENS_INT inter- rupt. (R/WTC/SS) APB_SARADC_THRES1_LOW_INT_RAW The raw interrupt status of the APB_SARADC_THRES1_LOW_INT interrupt. (R/WTC/SS) APB_SARADC_THRES0_LOW_INT_RAW The raw interrupt status of the APB_SARADC_THRES0_LOW_INT interrupt. (R/WTC/SS) APB_SARADC_THRES1_HIGH_INT_RAW The raw interrupt status of the APB_SARADC_THRES1_HIGH_INT interrupt. (R/WTC/SS) APB_SARADC_THRES0_HIGH_INT_RAW The raw interrupt status of the APB_SARADC_THRES0_HIGH_INT interrupt. (R/WTC/SS) APB_SARADC_ADC_DONE_INT_RAW The raw interrupt status of the APB_SARADC_ADC_DONE_INT interrupt. (R/WTC/SS) Espressif Systems 1466 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 41 ADC Controller Register 41.14. APB_SARADC_INT_ST_REG (0x0048) APB_SARADC_ADC_DONE_INT_ST 0 31 (reserved) 0 30 APB_SARADC_THRES0_HIGH_INT_ST 0 29 APB_SARADC_THRES1_HIGH_INT_ST 0 28 APB_SARADC_THRES0_LOW_INT_ST 0 27 APB_SARADC_THRES1_LOW_INT_ST 0 26 APB_SARADC_TSENS_INT_ST 0 25 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 0 Reset APB_SARADC_TSENS_INT_ST The masked interrupt status of the APB_SARADC_TSENS_INT in- terrupt. (RO) APB_SARADC_THRES1_LOW_INT_ST The masked interrupt status of the APB_SARADC_THRES1_LOW_INT interrupt. (RO) APB_SARADC_THRES0_LOW_INT_ST The masked interrupt status of the APB_SARADC_THRES0_LOW_INT interrupt. (RO) APB_SARADC_THRES1_HIGH_INT_ST The masked interrupt status of the APB_SARADC_THRES1_HIGH_INT interrupt. (RO) APB_SARADC_THRES0_HIGH_INT_ST The masked interrupt status of the APB_SARADC_THRES0_HIGH_INT interrupt. (RO) APB_SARADC_ADC_DONE_INT_ST The masked interrupt status of the APB_SARADC_ADC_DONE_INT interrupt. (RO) Espressif Systems 1467 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 41 ADC Controller Register 41.15. APB_SARADC_INT_CLR_REG (0x004C) APB_SARADC_ADC_DONE_INT_CLR 0 31 (reserved) 0 30 APB_SARADC_THRES0_HIGH_INT_CLR 0 29 APB_SARADC_THRES1_HIGH_INT_CLR 0 28 APB_SARADC_THRES0_LOW_INT_CLR 0 27 APB_SARADC_THRES1_LOW_INT_CLR 0 26 APB_SARADC_TSENS_INT_CLR 0 25 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 0 Reset APB_SARADC_TSENS_INT_CLR Write 1 to clear the APB_SARADC_TSENS_INT interrupt. (WT) APB_SARADC_THRES1_LOW_INT_CLR Write 1 to clear the APB_SARADC_THRES1_LOW_INT interrupt. (WT) APB_SARADC_THRES0_LOW_INT_CLR Write 1 to clear the APB_SARADC_THRES0_LOW_INT interrupt. (WT) APB_SARADC_THRES1_HIGH_INT_CLR Write 1 to clear the APB_SARADC_THRES1_HIGH_INT interrupt. (WT) APB_SARADC_THRES0_HIGH_INT_CLR Write 1 to clear the APB_SARADC_THRES0_HIGH_INT interrupt. (WT) APB_SARADC_ADC_DONE_INT_CLR Write 1 to clear the APB_SARADC_ADC_DONE_INT inter- rupt. (WT) Espressif Systems 1468 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 41 ADC Controller Register 41.16. APB_SARADC_DMA_CONF_REG (0x0050) APB_SARADC_APB_ADC_TRANS 0 31 APB_SARADC_APB_ADC_RESET_FSM 0 30 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29 16 APB_SARADC_APB_ADC_EOF_NUM 255 15 0 Reset APB_SARADC_APB_ADC_EOF_NUM Configures the number of samples. When the sampling reaches the configured number, the EOF flag bit sent to GDMA will be pulled high. (R/W) APB_SARADC_APB_ADC_RESET_FSM Configures whether to reset DIG ADC controller status. 0: No effect 1: Reset (R/W) APB_SARADC_APB_ADC_TRANS Configures whether to let DIG ADC controller use GDMA. 0: No effect 1: DIG ADC controller uses DMA (R/W) Espressif Systems 1469 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 42 Analog Voltage Comparator Chapter 42 Analog Voltage Comparator 42.1 Introduction ESP32-C5 integrates an analog voltage comparator. The comparators rely on special pads that support voltage comparison functionality to monitor voltage changes on these pads. The analog voltage comparator has two pads associated with it, for the main voltage and the reference voltage respectively. The voltage comparison result generated by the analog voltage comparator can be used as Event Task Matrix (ETM) events to drive ETM tasks of other peripherals or trigger interrupts. 42.2 Feature List The analog voltage comparator has the following features: • Voltage comparison – Configurable voltage comparison mode – Configurable reference voltage • Interrupt upon changes of voltage comparison result • ETM event generation 42.3 Architectural Overview Figure 42.3-1 shows the structure of the analog voltage comparator. PAD1 PAD0 Comparator VREF + _ mode_control COMP_OUT CHIP Figure 42.3-1. Analog Voltage Comparator Architecture Espressif Systems 1470 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 42 Analog Voltage Comparator As shown in the figure above, the analog voltage comparator consists of: • Two pad interfaces: – PAD1: Main voltage interface – PAD0: External reference voltage interface • VREF: Internal reference voltage interface • mode_control: Register-controlled switch for selecting the reference voltage source • COMP_OUT: Comparator voltage comparison result, which is an on-chip internal signal that cannot be directly accessed externally – If the main voltage is higher than the reference voltage, the COMP_OUT signal is high. – If the main voltage is lower than the reference voltage, the COMP_OUT signal is low. 42.4 Functional Description The analog voltage comparator has the following functions: • Voltage comparison The analog voltage comparator relies on specialized pads that support voltage comparison. Table below shows the mapping between the PAD of analog voltage comparator and GPIO pins. Table 42.4-1. Mapping Between PAD and GPIO Analog Voltage Comparator PAD0 PAD1 Analog voltage comparator GPIO9 GPIO8 The comparison mode and reference voltage are configurable. For detailed configuration procedures, see Section 42.7 Programming Procedures. The voltage comparison results are output as the COMP_OUT signal. • Voltage comparison mode control The analog voltage comparator compares the main voltage with the reference voltage, which can either be internal or external. There are two voltage comparison modes depending on the reference voltage selection: – Comparing the main voltage with the external reference voltage. – Comparing the main voltage with the internal reference voltage. The voltage comparison mode can be configured through GPIO_EXT_PAD_COMP_CONFIG_0_REG. • Reference voltage configuration The internal reference voltage range is 0 (0.7 × VDDPST1) V with a step of 0.1 × VDDPST1 V, where VDDPST1 is the supply voltage of the analog voltage comparator which is equal to the power supply voltage of the chip (usually 3.3 V). The internal reference voltage value can be configured through LPSYSREG_DREF_COMPn (n = 0 1). The external reference voltage is accessed directly from the pad with an input range of 0 (0.7 × VDDPST1) V, same as the internal reference voltage, requiring no additional configuration. Espressif Systems 1471 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 42 Analog Voltage Comparator • Voltage comparison interrupt processing The voltage comparison result, i.e., the COMP_OUT signal, can be either high or low. Whenever the output value changes, a corresponding interrupt signal is generated. 42.5 Event Task Matrix Feature The analog voltage comparator on ESP32-C5 supports the Event Task Matrix (ETM) function, which allows analog voltage comparator ETM events to trigger any peripherals’ ETM tasks. This section introduces the ETM events related to analog voltage comparator. For more information, please refer to Chapter 10 Event Task Matrix (ETM). The analog voltage comparator can generate the following ETM events: • GPIO_EVT_ZERO_DET_POS: Indicates that the COMP_OUT signal changes from low level to high level, i.e., the main voltage changes from below to above the reference voltage. • GPIO_EVT_ZERO_DET_NEG: Indicates that the COMP_OUT signal changes from high level to low level, i.e., the main voltage changes from higher to lower than the reference voltage. The analog voltage comparator does not support any ETM tasks. 42.6 Interrupts ESP32-C5’s analog voltage comparator can generate the GPIO_PAD_COMP_INT interrupt signal that will be sent to the Interrupt Matrix. There are several internal interrupt sources from analog voltage comparator that can generate the above interrupt signal. The interrupt sources from analog voltage comparator are listed with their trigger conditions and the resulted interrupt signal(s) in Table 42.6-1. Table 42.6-1. Analog Voltage Comparator’s Internal Interrupt Sources Internal Interrupt Source Trigger Condition Interrupt Signal GPIO_COMP_ALL_INT Any COMP_OUT signal transition occurs GPIO_PAD_COMP_INT GPIO_COMP_NEG_INT The COMP_OUT signal changes from high level to low level GPIO_PAD_COMP_INT GPIO_COMP_POS_INT The COMP_OUT signal changes from low level to high level GPIO_PAD_COMP_INT Note: For definitions of interrupt, interrupt signal, interrupt source, and their correlations, please refer to Chapter 9 Interrupt Matrix > Section 9.2 Terminology. Each interrupt source can be configured by a common set of registers that are described in Section Interrupt Configuration Registers. The specific registers can be found in Section 6.18.1 HP GPIO Matrix Register Summary. Espressif Systems 1472 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Chapter 42 Analog Voltage Comparator 42.7 Programming Procedures The programming procedure for the analog voltage comparator is as follows: Note: For more information about the register fields mentioned in this section, refer to Chapter 6 GPIO Matrix and IO MUX. 1. Set PCR_IOMUX_FUNC_CLK_EN to 1. 2. Enable the comparator by setting GPIO_EXT_XPD_COMP_0 to 1. 3. Disable normal digital pad functions (including IE, OE, WPU, and WPD) for PAD1, and if using the external reference voltage, also for PAD0. For detailed configuration, see Chapter 6 GPIO Matrix and IO MUX. 4. Configure the comparison mode by setting GPIO_EXT_PAD_COMP_CONFIG_0_REG: • 0: Configures to compare the main voltage with the internal reference voltage; • 1: Configures to compare the main voltage with the external reference voltage. 5. Configure the internal reference voltage through GPIO_EXT_DREF_COMP, which offers a voltage range of 0 (0.7 × VDDPST1) V with a step of 0.1 × VDDPST1 V. Espressif Systems 1473 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Part VII Appendix This part contains the following information starting from the next page: • Related Documentation and Resources • Glossary • Programming Reserved Register Field • Interrupt Configuration Registers • Revision History Espressif Systems 1474 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Related Documentation and Resources Related Documentation and Resources Related Documentation • ESP32-C5 Series Datasheet – Specifications of the ESP32-C5 hardware. • ESP32-C5 Hardware Design Guidelines – Guidelines on how to integrate the ESP32-C5 into your hardware product. • Certificates https://espressif.com/en/support/documents/certificates • ESP32-C5 Product/Process Change Notifications (PCN) https://espressif.com/en/support/documents/pcns?keys=ESP32-C5 • ESP32-C5 Advisories – Information on security, bugs, compatibility, component reliability. https://espressif.com/en/support/documents/advisories?keys=ESP32-C5 • Documentation Updates and Update Notification Subscription https://espressif.com/en/support/download/documents Developer Zone • ESP-IDF Programming Guide for ESP32-C5 – Extensive documentation for the ESP-IDF development framework. • ESP-IDF and other development frameworks on GitHub. https://github.com/espressif • ESP32 BBS Forum – Engineer-to-Engineer (E2E) Community for Espressif products where you can post questions, share knowledge, explore ideas, and help solve problems with fellow engineers. https://esp32.com/ • ESP-FAQ – A summary document of frequently asked questions released by Espressif. https://espressif.com/projects/esp-faq/en/latest/index.html • The ESP Journal – Best Practices, Articles, and Notes from Espressif folks. https://blog.espressif.com/ • See the tabs SDKs and Demos, Apps, Tools, AT Firmware. https://espressif.com/en/support/download/sdks-demos Products • ESP32-C5 Series SoCs – Browse through all ESP32-C5 SoCs. https://espressif.com/en/products/socs?id=ESP32-C5 • ESP32-C5 Series Modules – Browse through all ESP32-C5-based modules. https://espressif.com/en/products/modules?id=ESP32-C5 • ESP32-C5 Series DevKits – Browse through all ESP32-C5-based devkits. https://espressif.com/en/products/devkits?id=ESP32-C5 • ESP Product Selector – Find an Espressif hardware product suitable for your needs by comparing or applying filters. https://products.espressif.com/#/product-selector?language=en Contact Us • See the tabs Sales Questions, Technical Enquiries, Circuit Schematic & PCB Design Review, Get Samples (Online stores), Become Our Supplier, Comments & Suggestions. https://espressif.com/en/contact-us/sales-questions Espressif Systems 1475 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Glossary Glossary Abbreviations for Peripherals ADC ADC Controller AES AES (Advanced Encryption Standard) Accelerator CAN FD Controller Area Network Flexible Data-Rate DSA Digital Signature Algorithm ECC ECC (Elliptic Curve Cryptography) Accelerator ECDSA Elliptic Curve Digital Signature Algorithm eFuse eFuse Controller ETM Event Task Matrix GDMA GDMA (General Direct Memory Access) Controller HMAC HMAC (Hash-based Message Authentication Code) Accelerator I2C I2C (Inter-Integrated Circuit) Controller I2S I2S (Inter-IC Sound) Controller LEDC LED Control PWM (Pulse Width Modulation) MCPWM Motor Control PWM (Pulse Width Modulation) PARLIO Parallel IO Controller PCNT Pulse Count Controller PMS Permission Control RMT Remote Control Peripheral RNG Random Number Generator RSA RSA (Rivest Shamir Adleman) Accelerator SDIO SDIO Slave Controller SHA SHA (Secure Hash Algorithm) Accelerator SPI SPI (Serial Peripheral Interface) Controller TIMG Timer Group TRACE RISC-V Trace Encoder TSENS Temperature Sensor UART UART (Universal Asynchronous Receiver-Transmitter) Controller WDT Watchdog Timers XTS_AES External Memory Encryption and Decryption Abbreviations Related to Registers REG Register. SYSREG System registers are a group of registers that control system reset, memory, clocks, software interrupts, power management, clock gating, etc. ISO Isolation. If a peripheral or other chip component is powered down, the pins, if any, to which its output signals are routed will go into a floating state. ISO registers isolate such pins and keep them at a certain determined value, so that the other non-powered-down peripherals/devices attached to these pins are not affected. Espressif Systems 1476 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Glossary NMI Non-maskable interrupt is a hardware interrupt that cannot be disabled or ig- nored by the CPU instructions. Such interrupts exist to signal the occurrence of a critical error. W1TS Abbreviation added to names of registers/fields to indicate that such register/field should be used to set a field in a corresponding register with a similar name. For example, the register should be used to set the corresponding fields in the register . W1TC Same as W1TS, but used to clear a field in a corresponding register. Espressif Systems 1477 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Glossary Access Types for Registers Sections Register Summary and Register Description in TRM chapters specify access types for registers and their fields. Most frequently used access types and their combinations are as follows: • RO • WO • WT • R/W • R/W1 • WL • R/W/SC • R/W/SS • R/W/SS/SC • R/WC/SS • R/WC/SC • R/WC/SS/SC • R/WS/SC • R/WS/SS • R/WS/SS/SC • R/SS/WTC • R/SC/WTC • R/SS/SC/WTC • RF/WF • R/SS/RC • varies Descriptions of all access types are provided below. R Read. User application can read from this register/field; usually combined with other access types. RO Read only. User application can only read from this register/field. HRO Hardware Read Only. Only hardware can read from this register/field; used for storing default settings for variable parameters. W Write. User application can write to this register/field; usually combined with other access types. WO Write only. User application can only write to this register/field. W1 Write Once. User application can write to this register/field only once; only allowed to write 1; writing 0 is invalid. SS Self set. On a specified event, hardware automatically writes 1 to this register/field; used with 1-bit fields. SC Self clear. On a specified event, hardware automatically writes 0 to this register/field; used with 1-bit and multi-bit fields. SM Self modify. On a specified event, hardware automatically writes a specified value to this register/field; used with multi-bit fields. SU Self update. On a specified event, hardware automatically updates this register/field; used with multi-bit fields. RS Read to set. If user application reads from this register/field, hardware automatically writes 1 to it. RC Read to clear. If user application reads from this register/field, hardware automatically writes 0 to it. RF Read from FIFO. If user application writes new data to FIFO, the register/field automat- ically reads it. WF Write to FIFO. If user application writes new data to this register/field, it automatically passes the data to FIFO via APB bus. WS Write any value to set. If user application writes to this register/field, hardware auto- matically sets this register/field. Espressif Systems 1478 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Glossary W1S Write 1 to set. If user application writes 1 to this register/field, hardware automatically sets this register/field. W0S Write 0 to set. If user application writes 0 to this register/field, hardware automatically sets this register/field. WC Write any value to clear. If user application writes to this register/field, hardware au- tomatically clears this register/field. W1C Write 1 to clear. If user application writes 1 to this register/field, hardware automatically clears this register/field. W0C Write 0 to clear. If user application writes 0 to this register/field, hardware automatically clears this register/field. WT Write 1 to trigger an event. If user application writes 1 to this field, this action triggers an event (pulse in the APB bus) or clears a corresponding WTC field (see WTC). WTC Write to clear. Hardware automatically clears this field if user application writes 1 to the corresponding WT field (see WT). W1T Write 1 to toggle. If user application writes 1 to this field, hardware automatically inverts the corresponding field; otherwise - no effect. W0T Write 0 to toggle. If user application writes 0 to this field, hardware automatically inverts the corresponding field; otherwise - no effect. WL Write if a lock is deactivated. If the lock is deactivated, user application can write to this register/field. varies The access type varies. Different fields of this register might have different access types. Espressif Systems 1479 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Programming Reserved Register Field Programming Reserved Register Field Introduction A field in a register is reserved if the field is not open to users, or produces unpredictable results if configured to values other than defaults. Programming Reserved Register Field The reserved fields should not be modified. It is not possible to write only part of a register since registers must always be written as a whole. As a result, to write an entire register that contains reserved fields, you can choose one of the following two options: 1. Read the value of the register, modify only the fields you want to configure and then write back the value so that reserved fields are untouched. OR 2. Modify only the fields you want to configure and write back the default value of the reserved fields. The default value of a field is provided in the ”Reset” line of a register diagram. For example, the default value of Field_A in Register X is 1. Register 42.1. Register X (Address) (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 31 20 Field_C 0000 19 16 (reserved) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 2 Field_B 0 1 Field_A 1 0 Reset Suppose you want to set Field_A, Field_B, and Field_C of Register X to 0x0, 0x1, and 0x2, you can: • Use option 1 and fill in the reserved fields with the value you have just read. Suppose the register reads as 0x0000_0003. Then, you can modify the fields you want to configure, thus writing 0x0002_0002 to the register. • Use option 2 and fill in the reserved fields with their defaults, thus writing 0x0002_0002 to the register. Espressif Systems 1480 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Interrupt Configuration Registers Interrupt Configuration Registers Generally, the peripherals’ internal interrupt sources can be configured by the following common set of registers: • RAW (Raw Interrupt Status) register: This register indicates the raw interrupt status. Each bit in the register represents a specific internal interrupt source. When an interrupt source triggers, its RAW bit is set to 1. • ENA (Enable) register: This register is used to enable or disable the internal interrupt sources. Each bit in the ENA register corresponds to an internal interrupt source. By manipulating the ENA register, you can mask or unmask individual internal interrupt source as needed. When an internal interrupt source is masked (disabled), it will not generate an interrupt signal, but its value can still be read from the RAW register. • ST (Status) register: This register reflects the status of enabled interrupt sources. Each bit in the ST register corresponds to a specific internal interrupt source. The ST bit being 1 means that both the corresponding RAW bit and ENA bit are 1, indicating that the interrupt source is triggered and not masked. The other combinations of the RAW bit and ENA bit will result in the ST bit being 0. The configuration of ENA/RAW/ST registers is shown in Table 42.7-4. • CLR (Clear) register: The CLR register is responsible for clearing the internal interrupt sources. Writing 1 to the corresponding bit in the CLR register clears the interrupt source. Table 42.7-4. Configuration of ENA/RAW/ST Registers ENA Bit Value RAW Bit Value ST Bit Value 0 Ignored 0 1 0 0 1 1 Espressif Systems 1481 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Revision History Revision History Date Version Release notes 2025-08-22 v0.2 Added the following chapters: • Chapter 5 eFuse Controller (eFuse) • Chapter 9 Interrupt Matrix • Chapter 16 System Registers • Chapter 29 SPI Controller (SPI) • Chapter 32 Pulse Count Controller (PCNT) Updated the following chapters: • Chapter 2 Low-Power CPU: Updated the limitation of the LP CPU and HP CPU atomic access • Chapter 6 GPIO Matrix and IO MUX: Updated the description of GPIO_STRAP_REG • Chapter 34 SDIO Slave Controller (SDIO) and chapter 33 USB Serial/JTAG Controller: Added a note about using SDIO slave controller and USB se- rial/JTAG controller together 2025-05-20 v0.1 Preliminary release Espressif Systems 1482 Submit Documentation Feedback ESP32-C5 TRM (Pre-release v0.2) PRELIMINARY Disclaimer and Copyright Notice Information in this document, including URL references, is subject to change without notice. ALL THIRD PARTY’S INFORMATION IN THIS DOCUMENT IS PROVIDED AS IS WITH NO WARRANTIES TO ITS AUTHENTICITY AND ACCURACY. NO WARRANTY IS PROVIDED TO THIS DOCUMENT FOR ITS MERCHANTABILITY, NON-INFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, NOR DOES ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE. All liability, including liability for infringement of any proprietary rights, relating to use of information in this document is disclaimed. No licenses express or implied, by estoppel or otherwise, to any intellectual property rights are granted herein. The Wi-Fi Alliance Member logo is a trademark of the Wi-Fi Alliance. The Bluetooth logo is a registered trademark of Bluetooth SIG. All trade names, trademarks and registered trademarks mentioned in this document are property of their respective owners, and are hereby acknowledged. Copyright © 2025 Espressif Systems (Shanghai) Co., Ltd. All rights reserved. www.espressif.com