ESP Hardware Design Guidelines Choose target... Choose version... About This Document Product Overview Schematic Checklist PCB Layout Design Download Guidelines Related Documentation and Resources Glossary Revision History Disclaimer and Copyright Notice ESP Hardware Design Guidelines ESP Hardware Design Guidelines Download PDF ESP Hardware Design Guidelines [中文] This document provides guidelines for the ESP32-S31 SoC. To switch to another chip, use the drop-down menu at the top left of the page. Schematic Checklist PCB Layout Design Download Guidelines Resources Latest Version of This Document The document you are reading is the latest version. The full history of releases can be found in Section Revision History. Next Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2023 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Hardware Design Guidelines Choose target... Choose version... About This Document Product Overview Schematic Checklist PCB Layout Design Download Guidelines Related Documentation and Resources Glossary Revision History Disclaimer and Copyright Notice ESP Hardware Design Guidelines Revision History Download PDF Revision History [中文] Revision History Date Version Release Notes 2026-06-23 v0.1 First release Next Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2023 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Hardware Design Guidelines Choose target... Choose version... About This Document Product Overview Schematic Checklist PCB Layout Design General Principles of PCB Layout for the Chip Power Supply Four-Layer PCB Design Crystal RF Flash and PSRAM UART General Principles of PCB Layout for Modules (Positioning a Module on a Base Board) ADC USB SDIO Touch Sensor Electrode Pattern PCB Layout Waterproof and Proximity Sensing Design EMAC Typical Layout Problems and Solutions When ESP32-S31 sends data packages, the voltage ripple is small, but RF TX performance is poor. When ESP32-S31 sends data packages, the power value is much higher or lower than the target power value, and the EVM is relatively poor. TX performance is not bad, but the RX sensitivity is low. Download Guidelines Related Documentation and Resources Glossary Revision History Disclaimer and Copyright Notice ESP Hardware Design Guidelines PCB Layout Design Download PDF PCB Layout Design [中文] This chapter introduces the key points of how to design an ESP32-S31 PCB layout using an ESP32-S31 module (see Figure ESP32-S31 Reference PCB Layout) as an example. ESP32-S31 Reference PCB Layout General Principles of PCB Layout for the Chip It is recommended to use a four-layer PCB design: Layer 1 (TOP): Apply ground copper. Mainly used for signal traces and components. Layer 2 (GND): Apply ground copper. No signal traces here to ensure a complete GND plane. Layer 3 (POWER): Apply ground copper. Route power traces on this layer. Signal traces are allowed. Layer 4 (BOTTOM): Apply ground copper. Signal traces are allowed. A two-layer PCB design can also be used: Layer 1 (TOP): Apply ground copper. Mainly used for components and routing. Layer 2 (BOTTOM): Apply ground copper. Do not place any components on this layer and keep traces to a minimum. Please make sure there is a complete GND plane for the chip, RF, and crystal. Power Supply Four-Layer PCB Design Figure ESP32-S31 Power Traces in a Four-Layer PCB Design shows the power traces in a four-layer PCB design. ESP32-S31 Power Traces in a Four-Layer PCB Design A four-layer PCB design is recommended. Whenever possible, route the power traces on the inner layers (not the ground layer) and connect them to the chip pins through vias. There should be at least two vias if the main power traces need to cross layers. The drill diameter on other power traces should be no smaller than the width of the power traces. The yellow highlighted traces in Figure ESP32-S31 Power Traces in a Four-Layer PCB Design are all power traces of the chip. The width of the main power traces should be no less than 30 mil. The width of VDDA3 and VDDA4 power traces should be no less than 20 mil. The recommended width of other power traces is 10 mil. Ensure the power traces are surrounded by ground copper. The red circles in ESP32-S31 Power Traces in a Four-Layer PCB Design show ESD protection diodes. Place them close to the power input. Add a 10 µF capacitor before the power trace enters the chip. You can also add a 0.1 µF or 1 µF capacitor in parallel. After that, the power trace can branch out in a star-shaped layout to reduce coupling between different power pins. The power supply for pin2 and pin3 is RF related, so please place a 10 µF capacitor for each pin. You can also add a 0.1 µF or 1 µF capacitor in parallel. Add a CLC/LC filter circuit near pin2 and pin3 to suppress high-frequency harmonics. The power trace can be routed at a 45-degree angle to maintain distance from adjacent RF traces. Except for the 10 µF capacitor, it is recommended to use 0201 components. This allows the filter circuit for pin2 and pin3 to be placed closer to the pins, with a GND isolation layer separating them from surrounding RF and GPIO traces, while also maximizing the placement of ground vias. Using 0201 components enables adding a stub at the first capacitor near the chip to suppress harmonic interference. The stub should reference the bottom layer, with keep-out areas on the other three layers. See Figure ESP32-S31 Power Traces for Pins 2 and 3. ESP32-S31 Power Traces for Pins 2 and 3 Place appropriate decoupling capacitors at the rest of the power pins. Ground vias should be added close to the capacitor’s ground pad to ensure a short return path. The ground pad at the bottom of the chip should be connected to the ground plane through at least nine ground vias. The ground pads of the chip and surrounding circuit components should make full contact with the ground copper pour rather than being connected via traces. If you need to add a thermal pad EPAD under the chip on the bottom of the module, it is recommended to employ a square grid on the EPAD, cover the gaps with solder paste, and place ground vias in the gaps, as shown in Figure ESP32-S31 Power Traces in a Four-Layer PCB Design. This helps effectively reduce solder leakage issues when soldering the module EPAD to the substrate. Crystal Figure ESP32-S31 Crystal Layout (with Keep-out Area on Top Layer) shows a reference PCB layout where the crystal is connected to the ground through vias and a keep-out area is maintained around the crystal on the top layer for ground isolation. ESP32-S31 Crystal Layout (with Keep-out Area on Top Layer) If there is sufficient ground on the top layer, it is recommended to maintain a keep-out area around the crystal for ground isolation. This helps to reduce the value of parasitic capacitance and suppress temperature conduction, which can otherwise affect the frequency offset. If there is no sufficient ground, do not maintain any keep-out area. The layout of the crystal should follow the guidelines below: Ensure a complete GND plane for the RF, crystal, and chip. The crystal should be placed far from the clock pin to avoid interference on the chip. The gap should be at least 1.7 mm. It is good practice to add high-density ground vias stitching around the clock trace for better isolation. There should be no vias for the clock input and output traces. Components in series to the crystal trace should be placed close to the chip side. The external matching capacitors should be placed on the two sides of the crystal, preferably at the end of the clock trace, but not connected directly to the series components. This is to make sure the ground pad of the capacitor is close to that of the crystal. Do not route high-frequency digital signal traces under the crystal. It is best not to route any signal trace under the crystal. The vias on the power traces on both sides of the crystal clock trace should be placed as far away from the clock trace as possible, and the two sides of the clock trace should be surrounded by ground copper. As the crystal is a sensitive component, do not place any magnetic components nearby that may cause interference, for example large inductance component, and ensure that there is a clean large-area ground plane around the crystal. RF The RF trace is routed as shown highlighted in pink in Figure ESP32-S31 RF Layout in a Four-layer PCB Design. ESP32-S31 RF Layout in a Four-layer PCB Design The RF layout should meet the following guidelines: The RF trace should have a 50 Ω characteristic impedance. The reference plane is the third layer. For designing the RF trace at 50 Ω impedance, you could refer to the PCB stack-up design shown below. ESP32-S31 PCB Stack-up Design Attention The third layer is used as the reference plane for this module because, with the current stack-up structure, the RF trace width differs too much from the component pad size. To avoid abrupt transitions from the trace to component pads, the area under the RF trace on the second layer is cleared, and the third layer is used as the reference ground plane to obtain RF traces of suitable width. If the stack-up used does not have this issue, it is recommended to use the layer adjacent to the chip as the reference ground plane. A CLCCL matching circuit is required for chip tuning. Please use 0201 components and place them close to the pin in a zigzag. In other words, the two capacitors should not be oriented in the same direction to minimize interference. Add a stub on the ground pad of the grounding capacitor near the chip side in the matching circuit to suppress the seco