ESP Hardware Design Guidelines Choose target... Choose version... About This Document Product Overview Schematic Checklist PCB Layout Design Download Guidelines Related Documentation and Resources Glossary Revision History Disclaimer and Copyright Notice ESP Hardware Design Guidelines » ESP Hardware Design Guidelines Download PDF ESP Hardware Design Guidelines [中文] This document provides guidelines for the ESP32-S3 SoC. To switch to another chip, use the drop-down menu at the top left of the page. Schematic Checklist PCB Layout Design Download Guidelines Resources Latest Version of This Document The document you are reading is the latest version. The full history of releases can be found in Section Revision History. Next Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? 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About This Document Product Overview Schematic Checklist Overview Power Supply Digital Power Supply Analog Power Supply Chip Power-up and Reset Timing Flash and PSRAM In-Package Flash and PSRAM Off-Package Flash and PSRAM Clock Source External Crystal Clock Source (Compulsory) RTC Clock Source (Optional) RF RF Circuit RF Tuning UART SPI Strapping Pins GPIO ADC SDIO USB Touch Sensor PCB Layout Design Download Guidelines Related Documentation and Resources Glossary Revision History Disclaimer and Copyright Notice ESP Hardware Design Guidelines » Schematic Checklist Download PDF Schematic Checklist [中文] Overview The integrated circuitry of ESP32-S3 requires only 20 electrical components (resistors, capacitors, and inductors) and a crystal, as well as an SPI flash. The high integration of ESP32-S3 allows for simple peripheral circuit design. This chapter details the schematic design of ESP32-S3. The following figure shows a reference schematic design of ESP32-S3. It can be used as the basis of your schematic design. ESP32-S3 Reference Schematic Note that Figure ESP32-S3 Reference Schematic shows the connection for 3.3 V, quad, off-package SPI flash/PSRAM. In cases where 1.8 V or 3.3 V, octal, in-package or off-package SPI flash/PSRAM is used, GPIO33 ~ GPIO37 are occupied and cannot be used for other functions. If an in-package SPI flash/PSRAM is used and VDD_SPI is configured to 1.8 V or 3.3 V via the VDD_SPI_FORCE eFuse, the GPIO45 strapping pin no longer affects the VDD_SPI voltage. In these cases, the presence of R1 is optional. For all other cases, refer to ESP32-S3 Chip Series Datasheet > Section VDD_SPI Voltage Control > Table VDD_SPI Voltage Control to determine whether R1 should be populated or not. The connection for 1.8 V, octal, off-package flash/PSRAM is as shown in Figure ESP32-S3 Schematic for Off-Package 1.8 V Octal Flash/PSRAM. When only in-package flash/PSRAM is used, there is no need to populate the resistor on the SPI traces or to care the SPI traces. ESP32-S3 Schematic for Off-Package 1.8 V Octal Flash/PSRAM Any basic ESP32-S3 circuit design may be broken down into the following major building blocks: Power supply Chip power-up and reset timing Flash and PSRAM Clock source RF UART Strapping pins GPIO ADC SDIO USB Touch sensor The rest of this chapter details the specifics of circuit design for each of these sections. Power Supply The general recommendations for power supply design are: When using a single power supply, the recommended power supply voltage is 3.3 V and the output current is no less than 500 mA. It is suggested to add an ESD protection diode and at least 10 μF capacitor at the power entrance. The power scheme is shown in Figure ESP32-S3 Power Scheme. ESP32-S3 Power Scheme More information about power supply pins can be found in ESP32-S3 Series Datasheet > Section Power Supply. Digital Power Supply ESP32-S3 has pin46 VDD3P3_CPU as the digital power supply pin, and pin 20 VDD3P3_RTC as the RTC and partial digital power supply pin, with an operating voltage range of 3.0 V ~ 3.6 V. It is recommended to add a 0.1 μF capacitor close to the digital power supply pins in the circuit. Pin VDD_SPI serves as the power supply for the external device at either 1.8 V or 3.3 V (default). It is recommended to add extra 0.1 μF and 1 μF decoupling capacitors close to VDD_SPI. Please do not add excessively large capacitors. When VDD_SPI operates at 1.8 V, it is powered by ESP32-S3’s internal LDO. The typical current this LDO can offer is 40 mA. When VDD_SPI operates at 3.3 V, it is driven directly by VDD3P3_RTC through a 14 Ω resistor, therefore, there will be some voltage drop from VDD3P3_RTC. Attention When using VDDVDD_SPI_SPI as the power supply pin for in-package or off-package 3.3 V flash/PSRAM, please ensure that VDD3P3_RTC remains above 3.0 V to meet the operating voltage requirements of the flash/PSRAM, considering the voltage drop mentioned earlier. Note that VDD3P3_RTC cannot supply power alone; all power supplies must be powered on at the same time. Depending on the value of EFUSE_VDD_SPI_FORCE, the VDD_SPI voltage can be controlled in two ways, as Table VDD_SPI Voltage Control shows. VDD_SPI Voltage Control EFUSE_VDD_SPI_FORCE GPIO45 EFUSE_VDD_SPI_TIEH Voltage VDD_SPI Power Source 0 0 Ignored 3.3 V VDD3P3_RTC via RSPI (default) 0 1 Ignored 1.8 V Flash Voltage Regulator 1 Ignored 0 1.8 V Flash Voltage Regulator 1 Ignored 1 3.3 V VDD3P3_RTC via RSPI VDD_SPI can also be driven by an external power supply. It is recommended to use the VDD_SPI output to supply power to external or internal flash/PSRAM. Analog Power Supply ESP32-S3’s VDD3P3 pins (pin2 and pin3) and VDDA pins (pin55 and pin56) are the analog power supply pins, working at 3.0 V ~ 3.6 V. For VDD3P3, when ESP32-S3 is transmitting signals, there may be a sudden increase in the current draw, causing power rail collapse. Therefore, it is highly recommended to add a 10 μF capacitor to the power rail, which can work in conjunction with the 1 μF capacitor(s) or other capacitors. It is suggested to add an extra 10 μF capacitor at the power entrance. If the power entrance is close to VDD3P3, then two 10 μF capacitors can be merged into one. Add an LC circuit to the VDD3P3 power rail to suppress high-frequency harmonics. The inductor’s rated current is preferably 500 mA and above. For the remaining capacitor circuits, please refer to ESP32-S3 Reference Schematic. Chip Power-up and Reset Timing ESP32-S3’s CHIP_PU pin can enable the chip when it is high and reset the chip when it is low. When ESP32-S3 uses a 3.3 V system power supply, the power rails need some time to stabilize before CHIP_PU is pulled up and the chip is enabled. Therefore, CHIP_PU needs to be asserted high after the 3.3 V rails have been brought up. To reset the chip, keep the reset voltage VIL_nRST in the range of (–0.3 ~ 0.25 × VDD3P3_RTC) V. To avoid reboots caused by external interferences, make the CHIP_PU trace as short as possible. Figure ESP32-S3 Power-up and Reset Timing shows the power-up and reset timing of ESP32-S3. ESP32-S3 Power-up and Reset Timing Table Description of Timing Parameters for Power-up and Reset provides the specific timing requirements. Description of Timing Parameters for Power-up and Reset Parameter Description Minimum (µs) tSTBL Time reserved for the power rails to stabilize before the CHIP_PU pin is pulled high to activate the chip 50 tRST Time reserved for CHIP_PU to stay below VIL_nRST to reset the chip 50 Attention CHIP_PU must not be left floating. To ensure the correct power-up and reset timing, it is advised to add an RC delay circuit at the CHIP_PU pin. The recommended setting for the RC delay circuit is usually R = 10 kΩ and C = 1 μF. However, specific parameters should be adjusted based on the characteristics of the actual power supply and the power-up and reset timing of the chip. If the user application has one of the following scenarios: Slow power rise or fall, such as during battery charging. Frequent power on/off operations. Unstable power supply, such as in photovoltaic power generation. Then, the RC circuit itself may not meet the timing requirements, resulting in the chip being unable to boot correctly. In this case, additional designs need to be added, such as: Adding an external reset chip or a watchdog chip, typically with a threshold of around 3.0 V. Implementing reset functionality through a button or the main controller. Flash and PSRAM ESP32-S3 requires in-package or off-package flash to store application firmware and data. In-package PSRAM or off-package PSRAM is optional. In-Package Flash and PSRAM The tables list the pin-to-pin mapping between the chip and in-package flash/PSRAM. Please note that the following chip pins can connect at most one flash and one PSRAM. That is to say, when there is only flash in the package, the pin occupied by flash can only connect PSRAM and cannot be used for other functions; when there is only PSRAM, the pin occupied by PSRAM can only connect flash; when there are both flash and PSRAM, the pin occupied cannot connect any more flash or PSRAM. Pin-to-Pin Mapping Between Chip and In-Package Quad SPI Flash ESP32-S3FN8/ESP32-S3FH4R2 In-Package Flash (Quad SPI) SPICLK CLK SPICS0 CS# SPID DI SPIQ DO SPIWP WP# SPIHD HOLD# Pin-to-Pin Mapping Between Chip and In-Package Quad SPI PSRAM ESP32-S3R2/ESP32-S3FH4R2 In-Package PSRAM (2 MB, Quad SPI) SPICLK CLK SPICS1 CE# SPID SI/SIO0 SPIQ SO/SIO1 SPIWP SIO2 SPIHD SIO3 Pin-to-Pin Mapping Between Chip and In-Package Octal SPI PSRAM ESP32-S3R8/ESP32-S3R8V In-Package PSRAM (8 MB, Octal SPI) SPICLK CLK SPICS1 CE# SPID DQ0 SPIQ DQ1 SPIWP DQ2 SPIHD DQ3 GPIO33 DQ4 GPIO34 DQ5 GPIO35 DQ6 GPIO36 DQ7 GPIO37 DQS/DM Off-Package Flash and PSRAM To reduce the risk of software compatibility issues, it is recommended to use flash and PSRAM models officially validated by Espressif. For