ESP Hardware Design Guidelines Choose target... Choose version... About This Document Product Overview Schematic Checklist PCB Layout Design Hardware Development Related Documentation and Resources Glossary Revision History Disclaimer and Copyright Notice ESP Hardware Design Guidelines ESP Hardware Design Guidelines Download PDF ESP Hardware Design Guidelines [中文] This document provides guidelines for the ESP32-P4 SoC. To switch to another chip, use the drop-down menu at the top left of the page. Schematic Checklist PCB Layout Design Hardware Development Latest Version of This Document The document you are reading is the latest version. The full history of releases can be found in Section Revision History. Next Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2023 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Hardware Design Guidelines Choose target... Choose version... About This Document Product Overview Schematic Checklist PCB Layout Design Hardware Development Related Documentation and Resources Glossary Revision History Disclaimer and Copyright Notice ESP Hardware Design Guidelines Revision History Download PDF Revision History [中文] Revision History Date Version Release Notes 2026-07-21 v1.9 Schematic Checklist Section Chip Power-up and Reset Timing: Updated the recommended capacitor value for the CHIP_PU RC delay circuit from 0.1 μF to 1 μF PCB Layout Design Section Power Supply: Promoted to a top-level section 2026-07-06 v1.8 Schematic Checklist Section Internal Voltage Regulators and External DCDC: Added two verified DCDC models: BL8028 and LP3219 Section USB: Standardized the peripheral name: USB 2.0 Full-Speed OTG and USB 2.0 High-Speed OTG 2026-06-11 v1.7 Schematic Checklist Section USB PHY Power Supply: Fixed a typo related to the VDD_USBPHY circuit Section Touch Sensor: Updated descriptions about the touch sensor Fixed inconsistencies between the English and Chinese versions 2026-04-15 v1.6 Schematic Checklist Section HP/LP IO Power Supply: Modified the recommended operating voltage for VDD_IO_0, VDD_IO_4, VDD_IO_5, and VDD_IO_6 Section Flash and PSRAM IO Power Supply: Modified the recommended operating voltage for VDD_FLASHIO 2026-02-05 v1.5 Related Documentation and Resources: Added the reference design for development boards 2026-02-04 v1.4 Schematic Checklist Overview: Added notes on the main differences between chip revisions v1.0/v1.3 (not recommended for new designs) and v3.0 and later versions, and updated the corresponding reference design schematics Section Power Supply: Modified the minimum supply current Section USB PHY Power Supply: Added notes when using DP and DM, and added a reference schematic for VDD_USBPHY Section Analog Power Supply: Modified the operating voltage range of pin VDD_BAT Section Internal Voltage Regulators and External DCDC: Updated notes on VDDO_FLASH output voltage configuration, added notes for circuit layout for different chip revisions, and added the corresponding TLV62569 schematic Section SDIO: Updated SDIO GPIO pin assignment description and fixed a typo in Figure ESP32-P4 SD 3.0 Card Power Circuit Section USB: Added instructions for adding a pull-down resistor on the DP pin (applicable to chip revisions v1.0 and v1.3) Section Ethernet MAC: Corrected EMAC signal RMII_RXDV to RMII_CRSDV PCB Layout Design Section Power Supply: Added recommendation that power traces for pins VDD_BAT and VDD_ANA should be at least 10 mil Related Documentation and Resources: Added Consolidated Pin Overview Excel 2025-11-28 v1.3 Schematic Checklist Section Internal Voltage Regulators and External DCDC: Updated a note about FB_DCDC and EN_DCDC 2025-09-22 v1.2 Schematic Checklist Section Internal Voltage Regulators and External DCDC: Added a note about VDDO_FLASH default voltage and precautions for 1.8 V flash 2025-07-07 v1.1 Schematic Checklist Section HP/LP IO Power Supply: Added a note about VDD_IO_5 Section MIPI PHY Power Supply: Updated descriptions about VDD_MIPI_DPHY and added a note about MIPI signal level Section Internal Voltage Regulators and External DCDC: Updated descriptions about FB_DCDC and EN_DCDC Section SDIO: Added a figure ESP32-P4 SD 3.0 Card Power Circuit PCB Layout Design Section Power Supply: Deleted descriptions about the power traces of VDD_FLASHIO and updated descriptions about the placement of DCDC 2025-04-23 v1.0 First release of ESP32-P4 Hardware Design Guidelines. Next Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2023 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Hardware Design Guidelines Choose target... Choose version... About This Document Product Overview Schematic Checklist Overview Power Supply HP/LP IO Power Supply MIPI PHY Power Supply USB PHY Power Supply Flash and PSRAM IO Power Supply Analog Power Supply Digital Power Supply Internal Voltage Regulators and External DCDC Chip Power-up and Reset Timing Flash and PSRAM Clock Source External Crystal Clock Source (Compulsory) RTC Clock Source (Optional) UART SPI Strapping Pins GPIO ADC SDIO USB Touch Sensor Ethernet MAC MIPI PCB Layout Design Hardware Development Related Documentation and Resources Glossary Revision History Disclaimer and Copyright Notice ESP Hardware Design Guidelines Schematic Checklist Download PDF Schematic Checklist [中文] Overview The integrated circuitry of ESP32-P4 series chips requires only 40 electrical components (resistors, capacitors, and inductors) and a crystal, as well as an SPI flash and a direct current to direct current converter (DCDC). This chapter details the schematic design of ESP32-P4. The following figures show the reference schematics of ESP32-P4, which can be used as the basis of your schematic design. Attention For new designs, please refer to the schematic of chip revisions v3.0 and later versions. ESP32-P4 Reference Schematic (Chip Revisions v3.0 and Later) ESP32-P4 Reference Schematic (Chip Revisions v1.0 and v1.3) Important The main differences between chip revisions v1.0/v1.3 (not recommended for new designs) and v3.0 and later versions include the definition of pin 54, the 1 MΩ resistor on the DP pin, the two 499 kΩ resistors and one 22 pF capacitor in the DCDC circuit. For detailed descriptions of these differences, please refer to the following sections. In chip revisions v3.0 and later versions, pin 54 of ESP32-P4 is defined as VDD_HP_1; in chip revisions v1.0 and v1.3, this pin is defined as NC. Differences between ESP32-P4 chip revisions and how to distinguish them are described in ESP32-P4 Series SoC Errata. Any basic ESP32-P4 circuit design includes the following major building blocks: Power supply Chip power-up and reset timing Flash and PSRAM Clock source UART SPI Strapping pins GPIO ADC SDIO USB Touch sensor Ethernet MAC MIPI The rest of this chapter details the specifics of circuit design for each of these sections. Power Supply The general recommendations for power supply design are: For a single power supply, a voltage of 3.3 V is recommended. The minimum operating supply current of ESP32-P4 is 380 mA (including flash and PSRAM). For the supply current when peripherals are connected, please refer to HP/LP IO Power Supply, MIPI PHY Power Supply and USB PHY Power Supply. Calculate the required supply current based on your application and choose an appropriate power supply chip. It is suggested to add a 10 μF capacitor at each power entrance. The power scheme is as shown in Figure ESP32-P4 Power Scheme. ESP32-P4 Power Scheme More information about power supply pins can be found in ESP32-P4 Series Datasheet > Section Power Supply. HP/LP IO Power Supply Pin No. Pin Name Direction Voltage (V) Max. Current (mA) IO Pin Capacitors (μF) 9 VDD_LP Input 3.0 ~ 3.6 100 LP IO 0.1 21 VDD_IO_0 Input 1.65 ~ 3.6 100 HP IO 0.1 62 VDD_IO_4 Input 1.65 ~ 3.6 100 HP IO 0.1 85 VDD_IO_5 [1] Input 1.65 ~ 3.6 100 HP IO 0.1 96 VDD_IO_6 Input 1.65 ~ 3.6 100 HP IO 0.1 [1] If VDD_IO_5 is used as the IO power supply for SD 3.0 interface, please refer to SDIO for the circuit reference. MIPI PHY Power Supply The VDD_MIPI_DPHY of ESP32-P4 is the power supply pin for MIPI PHY. The operating voltage range is 2.25 V ~ 2.75 V. The maximum current consumption is 50 mA. It is recommended to use the internal voltage regulator for power supply, and place 10 nF + 0.1 μF + 1 μF capacitors near VDD_MIPI_DPHY in the circuit. If the MIPI function is not required, VDD_MIPI_DPHY can be left floating. Attention The voltage level of MIPI signals is defined by the MIPI specification. For details, please refer to the relevant MIPI protocol documentation. Note that this is a different concept from the MIPI DPHY voltage level. The 1.8 V/3.3 V levels mentioned in Camera/Display Datasheet refer to signals other than the MIPI signals (Data Lane & CLK), such as MCLK and I2C. The voltage level of MIPI signals is handled internally by the ESP32-P4’s built-in MIPI DPHY and requires no additional configuration. USB PHY Power Supply The VDD_USBPHY of ESP32-P4 is the power supply pin for USB PHY. The operating voltage range is 2.97 V ~ 3.63 V. The maximum current consumption is 20 mA. It is recommended to place 10 nF + 0.1 μF + 4.7 μF capacitors near VDD_USBPHY in the circuit. If DP and DM are not required, the VDD_USBPHY power supply can be left floating. If DP and DM are required, for chip revisions v1.0 and v1.3 (not recommended for new designs), note that the VDD_USBPHY power supply exhibits leakage current in low power modes. Therefore, it is recommended to add a MOSFET circuit to completely shut off this power supply in low power modes. During the validation phase, a 0 Ω series r