ESP Hardware Design Guidelines Choose target... Choose version... About This Document Product Overview Schematic Checklist PCB Layout Design Download Guidelines Related Documentation and Resources Glossary Revision History Disclaimer and Copyright Notice ESP Hardware Design Guidelines » ESP Hardware Design Guidelines Download PDF ESP Hardware Design Guidelines [中文] This document provides guidelines for the ESP32-C2 SoC. To switch to another chip, use the drop-down menu at the top left of the page. Important The ESP32-C2 SoC series group currently includes only one series, the ESP8684. Therefore, any reference to ESP32-C2 in this document applies to the ESP8684. Schematic Checklist PCB Layout Design Download Guidelines Resources Latest Version of This Document The document you are reading is the latest version. The full history of releases can be found in Section Revision History. Next Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2023 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Hardware Design Guidelines Choose target... Choose version... About This Document Product Overview Schematic Checklist Overview Power Supply Digital Power Supply Analog Power Supply RTC Power Supply Chip Power-up and Reset Timing Flash Clock Source External Crystal Clock Source (Compulsory) RF RF Circuit RF Tuning UART SPI Strapping Pins GPIO ADC PCB Layout Design Download Guidelines Related Documentation and Resources Glossary Revision History Disclaimer and Copyright Notice ESP Hardware Design Guidelines » Schematic Checklist Download PDF Schematic Checklist [中文] Overview The integrated circuitry of ESP32-C2 requires only 15 electrical components (resistors, capacitors, and inductors) and a crystal. The high integration of ESP32-C2 allows for simple peripheral circuit design. This chapter details the schematic design of ESP32-C2. The following figure shows a reference schematic design of ESP32-C2. It can be used as the basis of your schematic design. ESP32-C2 Reference Schematic Important Starting from chip revision v1.1, the ESP32-C2 firmware supports both 26 MHz and 40 MHz crystals. For ESP32-C2 revision v1.0 and previous chips, please use 26 MHz instead of 40 MHz crystal. For details, you can refer to ESP32-C2 Series SoC Errata (PDF). You can also contact the sales team to check the chip revision. Any basic ESP32-C2 circuit design may be broken down into the following major building blocks: Power supply Chip power-up and reset timing Flash Clock source RF UART Strapping pins GPIO ADC The rest of this chapter details the specifics of circuit design for each of these sections. Power Supply The general recommendations for power supply design are: When using a single power supply, the recommended power supply voltage is 3.3 V and the output current is no less than 500 mA. It is suggested to add an ESD protection diode and at least 10 μF capacitor at the power entrance. The power scheme is shown in ESP32-C2 Series Datasheet > Figure ESP32-C2 Power Scheme. More information about power supply pins can be found in ESP32-C2 Series Datasheet > Section Power Supply. Digital Power Supply ESP32-C2 has pin17 VDD3P3_CPU as the digital power supply pin(s) working in a voltage range of 3.0 V ~ 3.6 V. It is recommended to add an extra 0.1 μF decoupling capacitor close to the pin(s). Analog Power Supply ESP32-C2’s VDDA and VDDA3P3 pins are the analog power supply pins, working at 3.0 V ~ 3.6 V. For VDDA3P3, when ESP32-C2 is transmitting signals, there may be a sudden increase in the current draw, causing power rail collapse. Therefore, it is highly recommended to add a 10 μF capacitor to the power rail, which can work in conjunction with the 0.1 μF capacitor(s) or other capacitors. It is suggested to add an extra 10 μF capacitor at the power entrance. If the power entrance is close to VDDA3P3, then two 10 μF capacitors can be merged into one. Add an LC circuit to the VDDA3P3 power rail to suppress high-frequency harmonics. The inductor’s rated current is preferably 500 mA and above. If a two-layer board design is used, it is recommended to change the CLC filter circuit for VDDA3P3 to a CCL structure, as placing the inductance closer to the chip will yield better performance. Please refer to Figure ESP32-C2 Schematic for Analog Power Supply Pins (Two-layer Board) for details. ESP32-C2 Schematic for Analog Power Supply Pins (Two-layer Board) For the remaining capacitor circuits, please refer to ESP32-C2 Reference Schematic. RTC Power Supply ESP32-C2’s VDD3P3_RTC pin is the RTC and analog power pin. It is recommended to place a 0.1 μF decoupling capacitor near this power pin in the circuit. Note that this power supply cannot be used as a single backup power supply. The schematic for the RTC power supply pin is shown in Figure ESP32-C2 Schematic for RTC Power Supply Pin. ESP32-C2 Schematic for RTC Power Supply Pin Chip Power-up and Reset Timing ESP32-C2’s CHIP_EN pin can enable the chip when it is high and reset the chip when it is low. When ESP32-C2 uses a 3.3 V system power supply, the power rails need some time to stabilize before CHIP_EN is pulled up and the chip is enabled. Therefore, CHIP_EN needs to be asserted high after the 3.3 V rails have been brought up. To reset the chip, keep the reset voltage VIL_nRST in the range of (–0.3 ~ 0.25 × VDD) V. To avoid reboots caused by external interferences, make the CHIP_EN trace as short as possible. Figure ESP32-C2 Power-up and Reset Timing shows the power-up and reset timing of ESP32-C2. ESP32-C2 Power-up and Reset Timing Table Description of Timing Parameters for Power-up and Reset provides the specific timing requirements. Description of Timing Parameters for Power-up and Reset Parameter Description Minimum (µs) tSTBL Time reserved for the power rails to stabilize before the CHIP_EN pin is pulled high to activate the chip 50 tRST Time reserved for CHIP_EN to stay below VIL_nRST to reset the chip 50 Attention CHIP_EN must not be left floating. To ensure the correct power-up and reset timing, it is advised to add an RC delay circuit at the CHIP_EN pin. The recommended setting for the RC delay circuit is usually R = 10 kΩ and C = 1 μF. However, specific parameters should be adjusted based on the characteristics of the actual power supply and the power-up and reset timing of the chip. If the user application has one of the following scenarios: Slow power rise or fall, such as during battery charging. Frequent power on/off operations. Unstable power supply, such as in photovoltaic power generation. Then, the RC circuit itself may not meet the timing requirements, resulting in the chip being unable to boot correctly. In this case, additional designs need to be added, such as: Adding an external reset chip or a watchdog chip, typically with a threshold of around 3.0 V. Implementing reset functionality through a button or the main controller. Flash ESP32-C2 series of chips have in-package flash. The pins for flash are not bonded out. Clock Source External Crystal Clock Source (Compulsory) Important Starting from chip revision v1.1, the ESP32-C2 firmware supports both 26 MHz and 40 MHz crystals. For ESP32-C2 revision v1.0 and previous chips, please use 26 MHz instead of 40 MHz crystal. For details, you can refer to ESP32-C2 Series SoC Errata (PDF). You can also contact the sales team to check the chip revision. The circuit for the crystal is shown in Figure ESP32-C2 Schematic for External Crystal. Note that the accuracy of the selected crystal should be within ±10 ppm. ESP32-C2 Schematic for External Crystal Please add a series component on the XTAL_P clock trace. Initially, it is suggested to use an inductor of 24 nH to reduce the impact of high-frequency crystal harmonics on RF performance, and the value should be adjusted after an overall test. The initial values of external capacitors C1 and C2 can be determined according to the formula: \[C_L = \frac{C1 \times C2} {C1+C2} + C_{stray}\] where the value of CL (load capacitance) can be found in the crystal’s datasheet, and the value of Cstray refers to the PCB’s stray capacitance. The values of C1 and C2 need to be further adjusted after an overall test as below: Select TX tone mode using the Certification and Test Tool. Observe the 2.4 GHz signal with a radio communication analyzer or a spectrum analyzer and demodulate it to obtain the actual frequency offset. Adjust the frequency offset to be within ±10 ppm (recommended) by adjusting the external load capacitance. When the center frequency offset is positive, it means that the equivalent load capacitance is small, and the external load capacitance needs to be increased. When the center frequency offset is negative, it means the equivalent load capacitance is large, and the external load capacitance needs to be reduced. External load capacitance at the two sides are usually equal, but in special cases, they may have slightly different values. Note Defects in the manufacturing of crystal (for example, large frequency deviation of more than ±10 ppm, unstable performance within the operating temperature range, etc) may lead to the malfunction of ESP32-C2, resulting in a decrease of the RF performance. It is recommended that the amplitude of the crystal is greater than 500 mV. When Wi-Fi or Bluetooth connection fails, after ruling out software problems, you may follow the steps mentioned above to ensure that the frequency offset meets the requirements by adjusting capacitors at the two sides of the crystal. RF RF Circuit ESP32-C2’s RF circuit is mainly composed of three parts, the RF traces on the PCB board, the chip matching circuit, the antenna and the antenna matching circuit. Each part should meet the following requirements: For the RF traces on the PCB board, 50 Ω impedance control is required. For