ESP Hardware Design Guidelines Choose target... Choose version... About This Document Product Overview Schematic Checklist PCB Layout Design Download Guidelines Related Documentation and Resources Glossary Revision History Disclaimer and Copyright Notice ESP Hardware Design Guidelines ESP Hardware Design Guidelines Download PDF ESP Hardware Design Guidelines [中文] This document provides guidelines for the ESP32 SoC. To switch to another chip, use the drop-down menu at the top left of the page. Schematic Checklist PCB Layout Design Download Guidelines Resources Latest Version of This Document The document you are reading is the latest version. The full history of releases can be found in Section Revision History. Next Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2023 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Hardware Design Guidelines Choose target... Choose version... About This Document Product Overview Schematic Checklist PCB Layout Design General Principles of PCB Layout for the Chip Power Supply Four-Layer PCB Design Two-Layer PCB Design Crystal RF RF Layout on Four-layer PCB RF Layout on Two-layer PCB Flash and PSRAM External RC UART General Principles of PCB Layout for Modules (Positioning a Module on a Base Board) SDIO Touch Sensor Electrode Pattern PCB Layout Typical Layout Problems and Solutions The voltage ripple is not large, but the TX performance of RF is rather poor. When ESP32 sends data packages, the voltage ripple is small, but RF TX performance is poor. When ESP32 sends data packages, the power value is much higher or lower than the target power value, and the EVM is relatively poor. TX performance is not bad, but the RX sensitivity is low. Download Guidelines Related Documentation and Resources Glossary Revision History Disclaimer and Copyright Notice ESP Hardware Design Guidelines PCB Layout Design Download PDF PCB Layout Design [中文] This chapter introduces the key points of how to design an ESP32 PCB layout using an ESP32 module (see Figure ESP32 Reference PCB Layout) as an example. ESP32 Reference PCB Layout General Principles of PCB Layout for the Chip It is recommended to use a four-layer PCB design: Layer 1 (TOP): Signal traces and components. Layer 2 (GND): No signal traces here to ensure a complete GND plane. Layer 3 (POWER): GND plane should be applied to better isolate the RF and crystal. Route power traces and a few signal traces on this layer, provided that there is a complete GND plane under the RF and crystal. Layer 4 (BOTTOM): Route a few signal traces here. It is not recommended to place any components on this layer. A two-layer PCB design can also be used: Layer 1 (TOP): Signal traces and components. Layer 2 (BOTTOM): Do not place any components on this layer and keep traces to a minimum. Please make sure there is a complete GND plane for the chip, RF, and crystal. Power Supply Four-Layer PCB Design Figure ESP32 Power Traces in a Four-Layer PCB Design shows the power traces in a four-layer PCB design. ESP32 Power Traces in a Four-Layer PCB Design A four-layer PCB design is recommended. Whenever possible, route the power traces on the inner layers (not the ground layer) and connect them to the chip pins through vias. There should be at least two vias if the main power traces need to cross layers. The drill diameter on other power traces should be no smaller than the width of the power traces. The yellow highlighted traces in Figure ESP32 Power Traces in a Four-Layer PCB Design are the 3.3 V power traces. The width of the main power traces should be no less than 25 mil. The width of VDD3P3 power traces should be no less than 20 mil. The recommended width of other power traces is 12 ~ 15 mil. Ensure the power traces are surrounded by ground copper. The red circles in ESP32 Power Traces in a Four-Layer PCB Design show ESD protection diodes. Place them close to the power input. Add a 10 µF capacitor before the power trace enters the chip. You can also add a 0.1 µF or 1 µF capacitor in parallel. After that, the power trace can branch out in a star-shaped layout to reduce coupling between different power pins. The power supply for pin 3 and pin 4 is RF related, so please place a 10 µF capacitor for each pin. You can also add a 0.1 µF or 1 µF capacitor in parallel. Add a CLC/LC filter circuit near pin 3 and pin 4 to suppress high-frequency harmonics. The power trace can be routed at a 45-degree angle to maintain distance from adjacent RF traces. Except for the 10 µF capacitor, it is recommended to use 0201 components. This allows the filter circuit for pin 3 and pin 4 to be placed closer to the pins, with a GND isolation layer separating them from surrounding RF and GPIO traces, while also maximizing the placement of ground vias. Using 0201 components enables placing a via to the bottom layer at the first capacitor near the chip, while maintaining a keep-out area on other layers, further reducing harmonic interference. See Figure ESP32 Power Stub. ESP32 Power Stub In Figure ESP32 Power Traces in a Four-Layer PCB Design, the 10 µF capacitor is shared by the analog power supply VDD3P3, and the power entrance since the analog power is close to the chip power entrance. If the chip power entrance is not near VDD3P3, it is recommended to add a 10 µF capacitor to both the chip power entrance and VDD3P3. Place appropriate decoupling capacitors at the rest of the power pins. Ground vias should be added close to the capacitor’s ground pad to ensure a short return path. The ground pad at the bottom of the chip should be connected to the ground plane through at least nine ground vias. The ground pads of the chip and surrounding circuit components should make full contact with the ground copper pour rather than being connected via traces. If you need to add a thermal pad EPAD under the chip on the bottom of the module, it is recommended to employ a square grid on the EPAD, cover the gaps with solder paste, and place ground vias in the gaps, as shown in Figure ESP32 Power Traces in a Four-Layer PCB Design. This helps effectively reduce solder leakage issues when soldering the module EPAD to the substrate. Two-Layer PCB Design Figure ESP32 Power Traces in a Two-Layer PCB Design shows the power traces in a two-layer PCB design. ESP32 Power Traces in a Two-Layer PCB Design For a two-layer design, ensure to provide a continuous reference ground for the chip, RF, and crystal oscillator, as shown in the figure above. In the figure above, the trace VDD33 represents the 3.3 V power trace. Unlike a four-layer design, the power trace should be routed on the top layer as much as possible. Therefore, the thermal pad in the center of the chip should be reduced in size, allowing the power trace to pass between the signal pads and the thermal pad. Vias to the bottom layer should only be used when absolutely necessary. Other layout considerations are the same as for a four-layer design. Crystal Figure ESP32 Crystal Layout shows a reference layout for crystal on ESP32. ESP32 Crystal Layout The layout of the crystal should follow the guidelines below: Ensure a complete GND plane for the RF, crystal, and chip. The crystal should be placed far from the clock pin to avoid interference on the chip. The gap should be at least 2.7 mm. It is good practice to add high-density ground vias stitching around the clock trace for better isolation. There should be no vias for the clock input and output traces. Components in series to the crystal trace should be placed close to the chip side. The external matching capacitors should be placed on the two sides of the crystal, preferably at the end of the clock trace, but not connected directly to the series components. This is to make sure the ground pad of the capacitor is close to that of the crystal. Do not route high-frequency digital signal traces under the crystal. It is best not to route any signal trace under the crystal. The vias on the power traces on both sides of the crystal clock trace should be placed as far away from the clock trace as possible, and the two sides of the clock trace should be surrounded by ground copper. As the crystal is a sensitive component, do not place any magnetic components nearby that may cause interference, for example large inductance component, and ensure that there is a clean large-area ground plane around the crystal. RF RF Layout on Four-layer PCB The RF trace is routed as shown highlighted in pink in Figure ESP32 RF Layout in a Four-layer PCB Design. ESP32 RF Layout in a Four-layer PCB Design The RF layout should meet the following guidelines: The RF trace should have a 50 Ω characteristic impedance. The reference plane is the layer next to the chip. For designing the RF trace at 50 Ω impedance, you could refer to the PCB stack-up design shown below. ESP32 PCB Stack-up Design A CLC matching circuit is required for chip tuning. Please use 0201 components and place them close to the pin in a zigzag. In other words, the two capacitors should not be oriented in the same direction to minimize interference. Add a stub on the ground pad of the grounding capacitor near the chip side in the matching circuit to suppress the second harmonics. It is preferable to keep the stub length 15 mil, and determine the stub width according to the PCB stack-up so that the characteristic impedance of the stub is 100 Ω ± 10%. The reference plane is the third layer, so the area under the trace on the second layer should be cleared. The trace highlighted in Figure ESP32 Stub in a Four-layer PCB Design is the stub. Note that a stub is not required for package types of 0402 and above. It is recommended to keep all layers clear under the IPEX antenna connector. See Figure ESP32 IPEX Antenna Connector Layout. For PCB antennas, make sure to validate them throug