ESP Hardware Design Guidelines Choose target... Choose version... About This Document Product Overview Schematic Checklist PCB Layout Design Download Guidelines Related Documentation and Resources Glossary Revision History Disclaimer and Copyright Notice ESP Hardware Design Guidelines » ESP Hardware Design Guidelines Download PDF ESP Hardware Design Guidelines [中文] This document provides guidelines for the ESP32 SoC. To switch to another chip, use the drop-down menu at the top left of the page. Schematic Checklist PCB Layout Design Download Guidelines Resources Latest Version of This Document The document you are reading is the latest version. The full history of releases can be found in Section Revision History. Next Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? 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About This Document Product Overview Schematic Checklist Overview Power Supply Digital Power Supply Analog Power Supply Chip Power-up and Reset Timing Flash and PSRAM In-Package Flash and PSRAM Off-Package Flash and PSRAM Clock Source External Crystal Clock Source (Compulsory) RTC Clock Source (Optional) RF RF Circuit RF Tuning UART SPI Strapping Pins GPIO ADC External Capacitor SDIO Touch Sensor Ethernet MAC PCB Layout Design Download Guidelines Related Documentation and Resources Glossary Revision History Disclaimer and Copyright Notice ESP Hardware Design Guidelines » Schematic Checklist Download PDF Schematic Checklist [中文] Overview The integrated circuitry of ESP32 requires only 20 electrical components (resistors, capacitors, and inductors) and a crystal, as well as an SPI flash. The high integration of ESP32 allows for simple peripheral circuit design. This chapter details the schematic design of ESP32. The following figure shows a reference schematic design of ESP32. It can be used as the basis of your schematic design. ESP32 Reference Schematic Note that Figure ESP32 Reference Schematic shows the connection method for quad 3.3 V external flash/PSRAM. The SCLK for PSRAM can be assigned to any available GPIO (configured by software). It is recommended to use GPIO17, or share the clock line with flash, i.e., SD_CLK. When using ESP32-D0WDR2-V3 (with in-package quad 3.3 V PSRAM), the connection method for external flash is as shown in ESP32 Reference Schematic. GPIO16 needs a pull-up resistor, with a typical value of 10 kΩ. When using a module with built-in ESP32-D0WDR2-V3, since VDD_SDIO is not led out, the pull-up on GPIO16 needs to be connected to an external 3.3 V power supply. This will result in additional power consumption. If low power consumption is required, use a pull-up resistor of 1 MΩ at the maximum. When using ESP32-U4WDH (with built-in quad 3.3 V flash), the internal flash connection is as shown in ESP32 Schematic for Quad 3.3 V In-Package Flash. When using in-package flash/PSRAM, there is no need to install resistors on the SPI traces, nor to pay special attention to the SPI traces. Whether R9 needs to be installed should be determined according to the ESP32 Chip Series Datasheet > Section Internal LDO (VDD_SDIO) Voltage Control. ESP32 Schematic for Quad 3.3 V In-Package Flash Any basic ESP32 circuit design may be broken down into the following major building blocks: Power supply Chip power-up and reset timing Flash and PSRAM Clock source RF UART Strapping pins GPIO ADC External capacitor SDIO Touch sensor The rest of this chapter details the specifics of circuit design for each of these sections. Power Supply The general recommendations for power supply design are: When using a single power supply, the recommended power supply voltage is 3.3 V and the output current is no less than 500 mA. It is suggested to add an ESD protection diode and at least 10 μF capacitor at the power entrance. The power scheme is shown in Figure ESP32 Power Scheme. ESP32 Power Scheme More information about power supply pins can be found in ESP32 Series Datasheet > Section Power Supply. Digital Power Supply ESP32 has pin37 VDD3P3_CPU as the digital power supply pin, with an operating voltage range of 1.8 V ~ 3.6 V. ESP32 also has pin 20 VDD3P3_RTC as the RTC and partial digital power supply pin, with an operating voltage range of 2.3 V ~ 3.6 V. It is recommended to add a 0.1 μF capacitor close to the digital power supply pins in the circuit. Pin VDD_SDIO serves as the power supply for the external device at either 1.8 V or 3.3 V (default). When VDD_SDIO is in 1.8 V mode, it is powered by ESP32’s internal LDO, which can provide a maximum current of 40 mA and an output voltage range of 1.65 V ~ 2.0 V. It is recommended to add a 2 kΩ pull-down resistor and a 4.7 μF capacitor to ground at the VDD_SDIO pin. When VDD_SDIO is in 3.3 V mode, it is powered by VDD3P3_RTC through an internal resistor of about 6 Ω. Therefore, there will be some voltage drop between VDD_SDIO and VDD3P3_RTC. It is recommended to add a 1 μF filter capacitor close to the VDD_SDIO pin. Attention When using VDDVDD_SDIO_SPI as the power supply pin for in-package or off-package 3.3 V flash/PSRAM, please ensure that VDD3P3_RTC remains above 3.0 V to meet the operating voltage requirements of the flash/PSRAM, considering the voltage drop mentioned earlier. Note that VDD3P3_RTC cannot supply power alone; all power supplies must be powered on at the same time. Depending on the value of EFUSE_SDIO_FORCE, the VDD_SDIO voltage can be controlled in two ways, as Table VDD_SDIO Voltage Control shows. VDD_SDIO Voltage Control EFUSE_SDIO_FORCE MTDI EFUSE_SDIO_TIEH Voltage VDD_SDIO Power Source 0 0 Ignored 3.3 V VDD3P3_RTC via RSPI (default) 0 1 Ignored 1.8 V Flash Voltage Regulator 1 Ignored 0 1.8 V Flash Voltage Regulator 1 Ignored 1 3.3 V VDD3P3_RTC via RSPI VDD_SDIO can also be driven by an external power supply. It is recommended to use the VDD_SDIO output to supply power to external or internal flash/PSRAM. Analog Power Supply ESP32’s VDDA (pin 1/43/46) and VDD3P3 (pin 3/4) are the analog power supply pins, working at 2.3 V ~ 3.6 V. For VDD3P3, when ESP32 is transmitting signals, there may be a sudden increase in the current draw, causing power rail collapse. Therefore, it is highly recommended to add a 10 μF capacitor to the power rail, which can work in conjunction with the 1 μF capacitor(s) or other capacitors. It is suggested to add an extra 10 μF capacitor at the power entrance. If the power entrance is close to VDD3P3, then two 10 μF capacitors can be merged into one. Add an LC circuit to the VDD3P3 power rail to suppress high-frequency harmonics. The inductor’s rated current is preferably 500 mA and above. For the remaining capacitor circuits, please refer to ESP32 Reference Schematic. Chip Power-up and Reset Timing ESP32’s CHIP_PU pin can enable the chip when it is high and reset the chip when it is low. When ESP32 uses a 3.3 V system power supply, the power rails need some time to stabilize before CHIP_PU is pulled up and the chip is enabled. Therefore, CHIP_PU needs to be asserted high after the 3.3 V rails have been brought up. To reset the chip, keep the reset voltage VIL_nRST in the range of (NA ~ 0.6) V. To avoid reboots caused by external interferences, make the CHIP_PU trace as short as possible. Figure ESP32 Power-up and Reset Timing shows the power-up and reset timing of ESP32. ESP32 Power-up and Reset Timing Table Description of Timing Parameters for Power-up and Reset provides the specific timing requirements. Description of Timing Parameters for Power-up and Reset Parameter Description Minimum (µs) tSTBL Time reserved for the power rails to stabilize before the CHIP_PU pin is pulled high to activate the chip 50 tRST Time reserved for CHIP_PU to stay below VIL_nRST to reset the chip 50 Attention CHIP_PU must not be left floating. To ensure the correct power-up and reset timing, it is advised to add an RC delay circuit at the CHIP_PU pin. The recommended setting for the RC delay circuit is usually R = 10 kΩ and C = 1 μF. However, specific parameters should be adjusted based on the characteristics of the actual power supply and the power-up and reset timing of the chip. If the user application has one of the following scenarios: Slow power rise or fall, such as during battery charging. Frequent power on/off operations. Unstable power supply, such as in photovoltaic power generation. Then, the RC circuit itself may not meet the timing requirements, resulting in the chip being unable to boot correctly. In this case, additional designs need to be added, such as: Adding an external reset chip or a watchdog chip, typically with a threshold of around 3.0 V. Implementing reset functionality through a button or the main controller. Flash and PSRAM ESP32 requires in-package or off-package flash to store application firmware and data. In-package PSRAM or off-package PSRAM is optional. In-Package Flash and PSRAM The tables list the pin-to-pin mapping between the chip and in-package flash/PSRAM. Please note that the following chip pins can connect at most one flash and one PSRAM. That is to say, when there is only flash in the package, the pin occupied by flash can only connect PSRAM and cannot be used for other functions; when there is only PSRAM, the pin occupied by PSRAM can only connect flash; when there are both flash and PSRAM, the pin occupied cannot connect any more flash or PSRAM. Pin-to-Pin Mapping Between Chip and In-Package Flash ESP32-U4WDH In-Package Flash (4 MB) SD_DATA_1 IO0/DI GPIO17 IO1/DO SD_DATA_0 IO2/WP# SD_CMD IO3/HOLD# SD_CLK CLK GPIO16 CS# GND VSS VDD_SDIO VDD Pin-to-Pin Mapping Between Chip and In-Package PSRAM ESP32-D0WDR2-V3 In-Package PSRAM (2 MB) SD_DATA_1 SIO0/SI SD_DATA_0 SIO1/SO SD_DATA_3 SIO2 SD_DATA_2 SIO3 SD_CLK SCLK GPIO16 CE# GND VSS VDD