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ESP32 Boards ESP32-DevKitC ESP32-DevKitM-1 ESP32-PICO-KIT-1 ESP32-PICO-DevKitM-2 ESP32-LCDKit ESP32-Ethernet-Kit User Guide What You Need Overview Functionality Overview Functional Description Ethernet Board (A) PoE Board (B) Setup Options Function Switch RMII Clock Selection GPIO Allocation IP101GRI (PHY) Interface GPIO Header 1 GPIO Header 2 GPIO Allocation Summary Start Application Development Initial Setup Now to Development Configure and Load the Ethernet Example Summary of Changes from ESP32-Ethernet-Kit v1.1 Other Versions of ESP32-Ethernet-Kit Related Documents ESP32-Ethernet-Kit v1.0 ESP32-Ethernet-Kit v1.1 Disclaimer and Copyright Notice EOL (End of Life) Boards Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice esp-dev-kits ESP32-Ethernet-Kit ESP32-Ethernet-Kit v1.2 Download PDF ESP32-Ethernet-Kit v1.2 [中文] This guide shows how to get started with the ESP32-Ethernet-Kit development board and also provides information about its functionality and configuration options. The ESP32-Ethernet-Kit is an Ethernet-to-Wi-Fi development board that enables Ethernet devices to be interconnected over Wi-Fi. At the same time, to provide more flexible power supply options, the ESP32-Ethernet-Kit also supports power over Ethernet (PoE). ESP32-Ethernet-Kit v1.2 Overview (click to enlarge) What You Need ESP32-Ethernet-Kit v1.2 board USB 2.0 cable (Standard-A to Micro-B) Computer running Windows, Linux, or macOS You can skip the introduction sections and go directly to Section Start Application Development. Overview ESP32-Ethernet-Kit is an ESP32-based development board produced by Espressif. It consists of two development boards, the Ethernet board A and the PoE board B. The Ethernet board (A) contains Bluetooth®/Wi-Fi dual-mode ESP32-WROVER-E module and IP101GRI, a Single Port 10/100 Fast Ethernet Transceiver (PHY). The PoE board (B) provides power over Ethernet functionality. The A board can work independently, without the board B installed. ESP32-Ethernet-Kit v1.2 (click to enlarge) For the application loading and monitoring, the Ethernet board (A) also features FTDI FT2232H chip - an advanced multi-interface USB bridge. This chip enables to use JTAG for direct debugging of ESP32 through the USB interface without a separate JTAG debugger. Functionality Overview The block diagram below shows the main components of ESP32-Ethernet-Kit and their interconnections. ESP32-Ethernet-Kit block diagram (click to enlarge) Functional Description The following figures and tables describe the key components, interfaces, and controls of the ESP32-Ethernet-Kit. Ethernet Board (A) ESP32-Ethernet-Kit - Ethernet board (A) layout (click to enlarge) The table below provides description starting from the picture’s top right corner and going clockwise. Table 1 Component Description Key Component Description ESP32-WROVER-E This ESP32 module features 64-Mbit PSRAM for flexible extended storage and data processing capabilities. GPIO Header 2 Five unpopulated through-hole solder pads to provide access to selected GPIOs of ESP32. For details, see GPIO Header 2. Function Switch A 4-bit DIP switch used to configure the functionality of selected GPIOs of ESP32. For details see Function Switch. Tx/Rx LEDs Two LEDs to show the status of UART transmission. FT2232H The FT2232H chip serves as a multi-protocol USB-to-serial bridge which can be programmed and controlled via USB to provide communication with ESP32. FT2232H also features USB-to-JTAG interface which is available on channel A of the chip, while USB-to-serial is on channel B. The FT2232H chip enhances user-friendliness in terms of application development and debugging. See ESP32-Ethernet-Kit v1.2 Ethernet board (A) schematic. USB Port USB interface. Power supply for the board as well as the communication interface between a computer and the board. Power Switch Power On/Off Switch. Toggling the switch to 5V0 position powers the board on, toggling to GND position powers the board off. 5V Input The 5 V power supply interface can be more convenient when the board is operating autonomously (not connected to a computer). 5V Power On LED This red LED turns on when power is supplied to the board, either from USB or 5 V Input. DC/DC Converter Provided DC 5 V to 3.3 V conversion, output current up to 2 A. Board B Connectors A pair male and female header pins for mounting the PoE board (B) IP101GRI (PHY) The physical layer (PHY) connection to the Ethernet cable is implemented using the IP101GRI chip. The connection between PHY and ESP32 is done through the reduced media-independent interface (RMII), a variant of the media-independent interface (MII) standard. The PHY supports the IEEE 802.3/802.3u standard of 10/100 Mbps. RJ45 Port Ethernet network data transmission port. Magnetics Module The Magnetics are part of the Ethernet specification to protect against faults and transients, including rejection of common mode signals between the transceiver IC and the cable. The magnetics also provide galvanic isolation between the transceiver and the Ethernet device. Link/Activity LEDs Two LEDs (green and red) that respectively indicate the “Link” and “Activity” statuses of the PHY. BOOT Button Download button. Holding down BOOT and then pressing EN initiates Firmware Download mode for downloading firmware through the serial port. EN Button Reset button. GPIO Header 1 This header provides six unpopulated through-hole solder pads connected to spare GPIOs of ESP32. For details, see GPIO Header 1. Note Automatic firmware download is supported. If following steps and using software described in Section Start Application Development, users do not need to do any operation with BOOT button or EN button. PoE Board (B) This board converts power delivered over the Ethernet cable (PoE) to provide a power supply for the Ethernet board (A). The main components of the PoE board (B) are shown on the block diagram under Functionality Overview. The PoE board (B) has the following features: Support for IEEE 802.3at Power output: 5 V, 1.4 A To take advantage of the PoE functionality the RJ45 Port of the Ethernet board (A) should be connected with an Ethernet cable to a switch that supports PoE. When the Ethernet board (A) detects 5 V power output from the PoE board (B), the USB power will be automatically cut off. ESP32-Ethernet-Kit - PoE board (B) layout (click to enlarge) Table PoE board (B) Key Component Description Board A Connector Four female (left) and four male (right) header pins for connecting the PoE board (B) to Ethernet board (A). The pins on the left accept power coming from a PoE switch. The pins on the right deliver 5 V power supply to the Ethernet board (A). External Power Terminals Optional power supply (26.6 ~ 54 V) to the PoE board (B). Setup Options This section describes options to configure the ESP32-Ethernet-Kit hardware. Function Switch When in On position, this DIP switch is routing listed GPIOs to FT2232H to provide JTAG functionality. When in Off position, the GPIOs may be used for other purposes. DIP SW GPIO Pin 1 GPIO13 2 GPIO12 3 GPIO15 4 GPIO14 RMII Clock Selection The ethernet MAC and PHY under RMII working mode need a common 50 MHz reference clock (i.e., RMII clock) that can be provided either externally, or generated from internal ESP32 APLL (not recommended). Note For additional information on the RMII clock selection, please refer to ESP32-Ethernet-Kit v1.2 Ethernet board (A) schematic, sheet 2, location D2. RMII Clock Sourced Externally by PHY By default, the ESP32-Ethernet-Kit is configured to provide RMII clock for the IP101GRI PHY’s 50M_CLKO output. The clock signal is generated by the frequency multiplication of 25 MHz crystal connected to the PHY. For details, please see the figure below. RMII Clock from IP101GRI PHY (click to enlarge) Please note that the PHY is reset on power-up by pulling the RESET_N signal down with a resistor. ESP32 should assert RESET_N high with GPIO5 to enable PHY. Only this can ensure the power-up of the system. Otherwise, ESP32 may enter download mode. RMII Clock Sourced Internally from ESP32’s APLL Another option is to source the RMII Clock from internal ESP32 APLL, see figure below. The clock signal coming from GPIO0 is first inverted, to account for transmission line delay, and then supplied to the PHY. RMII Clock from ESP Internal APLL (click to enlarge) To implement this option, users need to remove or add some RC components on the board. For details please refer to ESP32-Ethernet-Kit v1.2 Ethernet board (A) schematic, sheet 2, location U2. Note Please note that you need to have RMII Clock Sourced Externally by PHY or by an external clock source in the following cases: If Wi-Fi and Ethernet are used simultaneously, the RMII clock cannot be generated by the internal APLL clock, as it would result in clock instability. APLL is already used for other purposes (e.g., I2S peripheral). GPIO Allocation This section describes the allocation of ESP32 GPIOs to specific interfaces or functions of the ESP32-Ethernet-Kit. IP101GRI (PHY) Interface The allocation of the ESP32 (MAC) pins to IP101GRI (PHY) is shown in the table below. Implementation of ESP32-Ethernet-Kit defaults to Reduced Media-Independent Interface (RMII). No. ESP32 Pin (MAC) IP101GRI (PHY) RMII Interface 1 GPIO21 TX_EN 2 GPIO19 TXD[0] 3 GPIO22 TXD[1] 4 GPIO25 RXD[0] 5 GPIO26 RXD[1] 6 GPIO27 CRS_DV 7 GPIO0 REF_CLK Serial Management Interface 8 GPIO23 MDC 9 GPIO18 MDIO PHY Reset 10 GPIO5 Reset_N Note The allocation of all pins under the ESP32’s RMII Interface is fixed and cannot be changed either through IO MUX or GPIO Matrix. For REF_CLK, GPIO0 supports both input and output modes, while GPIO16 and GPIO17 support only output mode. However, GPIO16 and GPIO17 are not broken out to the ESP32-WROVER-E module and therefore not available for use. If you need to use these pins, please replace the module with one that d