ESP Chip Errata Choose target... Choose version... ESP32-S31 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata ESP32-S31 Series SoC Errata Download PDF ESP32-S31 Series SoC Errata [中文] This document describes known errata in ESP32-S31 series of SoCs. It consists of the following major chapters: Chip Revision Identification Introduces how to identify a specific ESP32-S31 chip revision, or a batch of chips and products built around the ESP32-S31 chips which contains error fixes described in this document. Errata Summary Overview of all bugs and their affected chip revisions. All Errata Descriptions Detailed bug descriptions, including conditions, expected behaviors and actual behaviors, causes, influences on users, workarounds, and solutions. Errata Descriptions by Chip Revisions Classification of bug descriptions by chip revisions. Revision History The release notes for this document. To switch to another chip, use the drop-down menu at the top left of the page. Next Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-S31 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions v0.0 (2) [SPI-855] Flash Boot Fails at 1.8 V VDD_SPI [ECDSA_DS-836] Signatures with Invalid r and s Values Are Incorrectly Accepted Description Workarounds Solution Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata Errata Descriptions by Chip Revisions Chip Revision: v0.0 [ECDSA_DS-836] Signatures with Invalid r and s Values Are Incorrectly Accepted Download PDF [ECDSA_DS-836] Signatures with Invalid r and s Values Are Incorrectly Accepted Affected revisions: v0.0 Description When the signature {r = 0 or n, s = 0 or n} with invalid r and s values is submitted to the ECDSA_DS peripheral against any message and public key, the peripheral incorrectly reports the signature as “valid”. Workarounds Use RSA_DS Secure Boot instead of ECDSA_DS Secure Boot. Solution To be fixed in the next chip revision. Next Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-S31 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions [SPI-855] Flash Boot Fails at 1.8 V VDD_SPI Description Workarounds Solution [ECDSA_DS-836] Signatures with Invalid r and s Values Are Incorrectly Accepted Description Workarounds Solution Errata Descriptions by Chip Revisions Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata All Errata Descriptions Download PDF All Errata Descriptions [中文] [SPI-855] Flash Boot Fails at 1.8 V VDD_SPI Affected revisions: v0.0 Description The voltage corresponding to the default value of EXT_LDO_DREF is not 1.8 V, and the chip cannot boot from flash under 1.8 V VDD_SPI conditions. Workarounds Boot from flash using 3.3 V VDD_SPI. Solution To be fixed in the next chip revision. [ECDSA_DS-836] Signatures with Invalid r and s Values Are Incorrectly Accepted Affected revisions: v0.0 Description When the signature {r = 0 or n, s = 0 or n} with invalid r and s values is submitted to the ECDSA_DS peripheral against any message and public key, the peripheral incorrectly reports the signature as “valid”. Workarounds Use RSA_DS Secure Boot instead of ECDSA_DS Secure Boot. Solution To be fixed in the next chip revision. Next Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-S31 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions v0.0 (2) Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata Errata Descriptions by Chip Revisions Download PDF Errata Descriptions by Chip Revisions Chip Revision v0.0 (2) Next Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-S31 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata Revision History Download PDF Revision History [中文] Table 5 Revision History Date Version Release Notes 2026-07-10 v0.1 First release Next Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-S31 Series SoC Errata Chip Revision Identification Chip Revision Numbering Scheme Primary Identification Methods eFuse Bits Chip Marking Module Marking Additional Identification Methods Date Code PW Number ESP-IDF Release Compatibility Related Documents Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata Chip Revision Identification Download PDF Chip Revision Identification [中文] Espressif is introducing a new vM.X numbering scheme to indicate chip revisions. This guide outlines the structure of this scheme and provides information on chip errata and additional identification methods. Chip Revision Numbering Scheme The new numbering scheme vM.X consists of the major and minor numbers described below. M – Major number, indicating the major revision of the chip product. If this number changes, it means the software used for the previous version of the product is incompatible with the new product, and the software version shall be upgraded for the use of the new product. X – Minor number, indicating the minor revision of the chip product. If this number changes, it means the software used for the previous version of the product is compatible with the new product, and there is no need to upgrade the software. The vM.X scheme replaces previously used chip revision schemes, including ECOx numbers, Vxxx, and other formats if any. Primary Identification Methods eFuse Bits The chip revision is encoded using two eFuse fields: EFUSE_RD_MAC_SYS3_REG[23:22] EFUSE_RD_MAC_SYS3_REG[21:18] Table 1 Chip Revision Identification by eFuse Bits eFuse Bit Chip Revision v0.0 Major Number EFUSE_RD_MAC_SYS3_REG[23] 0 EFUSE_RD_MAC_SYS3_REG[22] 0 Minor Number EFUSE_RD_MAC_SYS3_REG[21] 0 EFUSE_RD_MAC_SYS3_REG[20] 0 EFUSE_RD_MAC_SYS3_REG[19] 0 EFUSE_RD_MAC_SYS3_REG[18] 0 Chip Marking Manufacturing Code line in chip marking Figure 1 Chip Marking Diagram Table 2 Chip Revision Identification by Chip Marking Chip Revision Manufacturing Code v0.0 X A XX Module Marking Specification Identifier line in module marking Figure 2 Module Marking Diagram Table 3 Chip Revision Identification by Module Marking Chip Revision Specification Identifier v0.0 MA XXXX Additional Identification Methods Date Code Some errors in the chip product don’t need to be fixed at the silicon level, or in other words in a new chip revision. In this case, the chip may be identified by Date Code in chip marking (see Chip Marking). For more information, please refer to ESP32-S31 Chip Packaging Information > Chip Silk Marking. PW Number Modules built around the chip may be identified by PW Number in product label (see Module Product Label). For more information, please refer to ESP32-S31 Module Packaging Information > Pizza Box. Figure 3 Module Product Label Note Please note that PW Number is only provided for reels packaged in aluminum moisture barrier bags (MBB). ESP-IDF Release Compatibility Information about ESP-IDF release that supports a specific chip revision is provided in Compatibility Between ESP-IDF Releases and Revisions of Espressif SoCs. Related Documents For more information about the chip revision upgrade and their identification of series products, please refer to ESP32-S31 Product/Process Change Notifications (PCN). For more information about the chip revision numbering scheme, see Compatibility Advisory for Chip Revision Numbering Scheme. Next Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-S31 Series SoC Errata Chip Revision Identificati