ESP Chip Errata Choose target... Choose version... ESP32-S3 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata ESP32-S3 Series SoC Errata Download PDF ESP32-S3 Series SoC Errata [中文] This document describes known errata in ESP32-S3 series of SoCs. It consists of the following major chapters: Chip Revision Identification Introduces how to identify a specific ESP32-S3 chip revision, or a batch of chips and products built around the ESP32-S3 chips which contains error fixes described in this document. Errata Summary Overview of all bugs and their affected chip revisions. All Errata Descriptions Detailed bug descriptions, including conditions, expected behaviors and actual behaviors, causes, influences on users, workarounds, and solutions. Errata Descriptions by Chip Revisions Classification of bug descriptions by chip revisions. Revision History The release notes for this document. To switch to another chip, use the drop-down menu at the top left of the page. Next Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-S3 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions v0.0 (8) [ANALOG-160] Chip Will Be Damaged When BIAS_SLEEP = 0 and PD_CUR = 1 [CACHE-126] Cache Hit Error During Cache Write-Backs [LCD-239] The LCD Module Exhibits Unreliable Behavior When Certain Clock Dividers Are Used [USBOTG-4289] The USB-OTG Download Function Is Unavailable [RMT-176] The Idle State Signal Level Might Run into Error in RMT Continuous TX Mode [RTC-126] RTC Register Read Error After Wake-up from Light-sleep Mode [ADC-183] The Digital Controller (DMA) of SAR ADC2 Cannot Work [TOUCH-100] The TOUCH_SCAN_DONE_INT Interrupt Raw Data Value Is Undefined v0.1 (8) v0.2 (8) Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata Errata Descriptions by Chip Revisions Chip Revision: v0.0 Download PDF Chip Revision: v0.0 Known Errors [ANALOG-160] Chip Will Be Damaged When BIAS_SLEEP = 0 and PD_CUR = 1 [CACHE-126] Cache Hit Error During Cache Write-Backs [LCD-239] The LCD Module Exhibits Unreliable Behavior When Certain Clock Dividers Are Used [USBOTG-4289] The USB-OTG Download Function Is Unavailable [RMT-176] The Idle State Signal Level Might Run into Error in RMT Continuous TX Mode [RTC-126] RTC Register Read Error After Wake-up from Light-sleep Mode [ADC-183] The Digital Controller (DMA) of SAR ADC2 Cannot Work [TOUCH-100] The TOUCH_SCAN_DONE_INT Interrupt Raw Data Value Is Undefined Next Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-S3 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata Revision History Download PDF Revision History [中文] Table 5 Revision History Date Version Release Notes 2025-03-31 v1.3 Added Section [CACHE-126] Cache Hit Error During Cache Write-Backs 2023-11-15 v1.2 Chip Revision Identification Added information about how to identify chip revisions in modules Added Section Additional Identification Methods All Errata Descriptions Adjusted the section order Added Section [RTC-126] RTC Register Read Error After Wake-up from Light-sleep Mode Added Section [LCD-239] The LCD Module Exhibits Unreliable Behavior When Certain Clock Dividers Are Used Added Section [RMT-176] The Idle State Signal Level Might Run into Error in RMT Continuous TX Mode Added Section [TOUCH-100] The TOUCH_SCAN_DONE_INT Interrupt Raw Data Value Is Undefined Other minor updates 2023-01-20 v1.1 Added Section [USBOTG-4289] The USB-OTG Download Function Is Unavailable 2022-10-14 v1.0 First release Next Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-S3 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions v0.0 (8) v0.1 (8) v0.2 (8) [ANALOG-160] Chip Will Be Damaged When BIAS_SLEEP = 0 and PD_CUR = 1 Description Workarounds Solution [CACHE-126] Cache Hit Error During Cache Write-Backs [LCD-239] The LCD Module Exhibits Unreliable Behavior When Certain Clock Dividers Are Used [USBOTG-4289] The USB-OTG Download Function Is Unavailable [RMT-176] The Idle State Signal Level Might Run into Error in RMT Continuous TX Mode [RTC-126] RTC Register Read Error After Wake-up from Light-sleep Mode [ADC-183] The Digital Controller (DMA) of SAR ADC2 Cannot Work [TOUCH-100] The TOUCH_SCAN_DONE_INT Interrupt Raw Data Value Is Undefined Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata Errata Descriptions by Chip Revisions Chip Revision: v0.0 [ANALOG-160] Chip Will Be Damaged When BIAS_SLEEP = 0 and PD_CUR = 1 Download PDF [ANALOG-160] Chip Will Be Damaged When BIAS_SLEEP = 0 and PD_CUR = 1 Affected revisions: v0.0 v0.1 v0.2 Description If the analog power is configured as BIAS_SLEEP = 0 and PD_CUR = 1, the chip will be permanently damaged. This issue might be triggered when ULP and/or touch sensor is used during Light-sleep or Deep-sleep. Workarounds Users are suggested to disable such analog power configuration in sleep mode through software. This issue has been bypassed by disabling the above configuration in ESP-IDF v4.4.2+, v5.0 and above. Solution No fix scheduled. Next Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-S3 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions v0.0 (8) v0.1 (8) v0.2 (8) [ANALOG-160] Chip Will Be Damaged When BIAS_SLEEP = 0 and PD_CUR = 1 [CACHE-126] Cache Hit Error During Cache Write-Backs Description Workarounds Solution [LCD-239] The LCD Module Exhibits Unreliable Behavior When Certain Clock Dividers Are Used [USBOTG-4289] The USB-OTG Download Function Is Unavailable [RMT-176] The Idle State Signal Level Might Run into Error in RMT Continuous TX Mode [RTC-126] RTC Register Read Error After Wake-up from Light-sleep Mode [ADC-183] The Digital Controller (DMA) of SAR ADC2 Cannot Work [TOUCH-100] The TOUCH_SCAN_DONE_INT Interrupt Raw Data Value Is Undefined Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata Errata Descriptions by Chip Revisions Chip Revision: v0.0 [CACHE-126] Cache Hit Error During Cache Write-Backs Download PDF [CACHE-126] Cache Hit Error During Cache Write-Backs Affected revisions: v0.0 v0.1 v0.2 Description When a cache write-back is in progress, if the CPU accesses other addresses within the same cache line, the access request will be treated as a cache miss. This triggers the miss handling module to reload the cache line from external memory, resulting in two identical cache data entries in the same cache line. Due to hardware logic issues, the cache hit logic may select incorrect cache data, causing the CPU to return incorrect results. If the CPU also writes to the cache line, it may cause the data being written back to be lost. For example, the following scenarios may lead to cache hit errors in ESP32-S3: Accessing data in a cache line that is being written back to the cache during an interrupt: During the cache write-back process, when the CPU is waiting for the write-back completion signal, an interrupt request occurs and the interrupt handler is entered, accessing the memory in the same buffer. If the data accessed by the handler and the write-back address are in the same cache line, cache hit errors may occur. Conflicts in a multi-core system: In a multi-core system, if CPU0 is waiting for a cache write-back to complete while CPU1 accesses the same cache line address, cache hit errors may occur. Workarounds During a cache write-back, it is recommended that users take the following precautions at the same time: Disable interrupts on the current CPU, and re-enable them only after the cache write-back has completed. Enable the cache freeze feature to stop another CPU from accessing the cache. This issue has been automatically bypassed using the above methods in ESP-IDF v4.4.6+, v5.0.4+, v5.1.1+, v5.2, and above versions. Solution No fix scheduled. Next Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme.