ESP Chip Errata Choose target... Choose version... ESP32-P4 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata ESP32-P4 Series SoC Errata Download PDF ESP32-P4 Series SoC Errata [中文] This document describes known errata in ESP32-P4 series of SoCs. It consists of the following major chapters: Chip Revision Identification Introduces how to identify a specific ESP32-P4 chip revision, or a batch of chips and products built around the ESP32-P4 chips which contains error fixes described in this document. Errata Summary Overview of all bugs and their affected chip revisions. All Errata Descriptions Detailed bug descriptions, including conditions, expected behaviors and actual behaviors, causes, influences on users, workarounds, and solutions. Errata Descriptions by Chip Revisions Classification of bug descriptions by chip revisions. Revision History The release notes for this document. To switch to another chip, use the drop-down menu at the top left of the page. Next Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-P4 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata Errata Summary Download PDF Errata Summary [中文] Table 3 Errata summary Category Errata No. Descriptions Affected Revisions v0.0 v1.0 v1.3 v3.0 v3.1 v3.2 RMT RMT-176 [RMT-176] The Idle State Signal Level Might Run into Error in RMT Continuous TX Mode Y Y Y I2C I2C-308 [I2C-308] I2C Slave Fails in Multiple-read Under Non-FIFO Mode Y Y Y MSPI MSPI-749 [MSPI-749] Load Access Fault During Chip Power-on or Deep-Sleep Wake-up Y MSPI-750 [MSPI-750] PSRAM Unaligned DMA Read Operations May Return Old Data When Accessing Overlapping Addresses Y MSPI-751 [MSPI-751] Data Errors Caused by Asynchronous Timing Issues in the MSPI Address Overlap Detection Function When Read/Write Operations Overlap at Specific Frequencies Y ROM ROM-764 [ROM-764] Secure Boot Verification Failure Caused by Incorrect Buffer Address in ROM Y ROM-770 [ROM-770] Secure Download Mode Flash Power-On Failure Y ROM-816 [ROM-816] Device Hang When Flash Power-On Sequence Runs Twice with rom_download_xpd_on eFuse Y Analog Analog-765 [Analog-765] Output Regulators Cannot Generate a Reliable Supply When Peripheral Power Domain Is Off Y DMA DMA-767 [DMA-767] DMA Channel 0 Transaction ID Overlap Causes Permission Management Issue Y APM APM-560 [APM-560] Unauthorized AHB Access May Block Subsequent PSRAM or Flash Transactions Y Y Y Y ECDSA_DS 1 ECDSA_DS-836 [ECDSA_DS-836] Signatures with Invalid r and s Values Are Incorrectly Accepted Y Y Y ECDSA_DS-837 [ECDSA_DS-837] Signatures with Invalid s Values Are Incorrectly Accepted Y Y Y 1 ECDSA_DS: ECDSA Digital Signature Peripheral. Next Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-P4 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions v0.0 (4) v1.0 (4) v1.3 (4) v3.0 (8) [MSPI-751] Data Errors Caused by Asynchronous Timing Issues in the MSPI Address Overlap Detection Function When Read/Write Operations Overlap at Specific Frequencies [MSPI-749] Load Access Fault During Chip Power-on or Deep-Sleep Wake-up [DMA-767] DMA Channel 0 Transaction ID Overlap Causes Permission Management Issue [Analog-765] Output Regulators Cannot Generate a Reliable Supply When Peripheral Power Domain Is Off Description Workaround Solution [ROM-764] Secure Boot Verification Failure Caused by Incorrect Buffer Address in ROM [MSPI-750] PSRAM Unaligned DMA Read Operations May Return Old Data When Accessing Overlapping Addresses [APM-560] Unauthorized AHB Access May Block Subsequent PSRAM or Flash Transactions [ECDSA_DS-836] Signatures with Invalid r and s Values Are Incorrectly Accepted v3.1 (2) v3.2 (2) Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata Errata Descriptions by Chip Revisions Chip Revision: v3.0 [Analog-765] Output Regulators Cannot Generate a Reliable Supply When Peripheral Power Domain Is Off Download PDF [Analog-765] Output Regulators Cannot Generate a Reliable Supply When Peripheral Power Domain Is Off Affected revisions: v3.0 Description The output regulators can not generate a reliable supply when the peripheral power domain is turned off. Workaround If you intend to use output regulators as the supply source for external PCB components, do not turn off the peripheral power domain in Light-sleep mode. Solution Fixed in chip revision v3.1. Next Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-P4 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions [RMT-176] The Idle State Signal Level Might Run into Error in RMT Continuous TX Mode Description Workarounds Solution [I2C-308] I2C Slave Fails in Multiple-read Under Non-FIFO Mode Description Workarounds Solution [MSPI-749] Load Access Fault During Chip Power-on or Deep-Sleep Wake-up Description Workarounds Solution [MSPI-750] PSRAM Unaligned DMA Read Operations May Return Old Data When Accessing Overlapping Addresses Description Workarounds Solution [MSPI-751] Data Errors Caused by Asynchronous Timing Issues in the MSPI Address Overlap Detection Function When Read/Write Operations Overlap at Specific Frequencies Description Workaround Solution [ROM-764] Secure Boot Verification Failure Caused by Incorrect Buffer Address in ROM Description Workaround Solution [ROM-770] Secure Download Mode Flash Power-On Failure Description Workaround Solution [ROM-816] Device Hang When Flash Power-On Sequence Runs Twice with rom_download_xpd_on eFuse Description Workaround Solution [Analog-765] Output Regulators Cannot Generate a Reliable Supply When Peripheral Power Domain Is Off Description Workaround Solution [DMA-767] DMA Channel 0 Transaction ID Overlap Causes Permission Management Issue Description Workaround Solution [APM-560] Unauthorized AHB Access May Block Subsequent PSRAM or Flash Transactions Description Workaround Solution [ECDSA_DS-836] Signatures with Invalid r and s Values Are Incorrectly Accepted Description Workarounds Solution [ECDSA_DS-837] Signatures with Invalid s Values Are Incorrectly Accepted Description Workarounds Solution Errata Descriptions by Chip Revisions Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata All Errata Descriptions Download PDF All Errata Descriptions [中文] [RMT-176] The Idle State Signal Level Might Run into Error in RMT Continuous TX Mode Affected revisions: v0.0 v1.0 v1.3 Description In ESP32-P4’s RMT module, if the continuous TX mode is enabled, it is expected that the data transmission stops after the data is sent for RMT_TX_LOOP_NUM_CHn rounds, and after that, the signal level in idle state should be controlled by the “level” field of the end-marker. However, in real situation, after the data transmission stops, the channel’s idle state signal level is not controlled by the “level” field of the end-marker, but by the level in the data wrapped back, which is indeterminate. Workarounds Users are suggested to set RMT_IDLE_OUT_EN_CHn to 1 to only use registers to control the idle level. This issue has been bypassed since the first ESP-IDF version that supports continuous TX mode (v5.2). In these versions of ESP-IDF, it is configured that the idle level can only be controlled by registers. Solution Fixed in chip revision v3.0. [I2C-308] I2C Slave Fails in Multiple-read Under Non-FIFO Mode Affected revisions: v0.0 v1.0 v1.3 Description If the I2C slave non-FIFO mode is enabled and the master performs multiple-read operation on the slave, the master can not correctly read the data from the slave. Workarounds Set I2C_FIFO_ADDR_CFG_EN and I2C_SLV_TX_AUTO_START_EN to 1 and I2C_FIFO_PRT_EN to 0 for the slave. After configuration, the master must access the slave using the following command sequence: RSTART -> WRITE (slave addr, fifo addr) -> RSTART -> WRITE (slave addr) -> READ (NACK) -> STOP, with only one byte allowed to be read each time. Solution Fixed in chip revision v3.0. [MSPI-749] Load Access Fault During Chip Power-on or Deep-Sleep Wake-up Affected revisions: v3.0 Description During the power-on or wake-up process of ESP32-P4, due to abnormal handling inside the MSPI IP read-request channel, the MSPI may fail to correctly process the first and second access requests initiated by the AXI system bus. This can occasionally result in unexpected error responses, causing the boot process to fail. Workarounds Power-on sequence: The power-on sequence is fixed. If the sequence fails, the system can only rely on the watchdog timeout to reset the chip and perform a “second power-on”. After this second power-on, the flash