ESP Chip Errata Choose target... Choose version... ESP32-H2 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata ESP32-H2 Series SoC Errata Download PDF ESP32-H2 Series SoC Errata [中文] This document describes known errata in ESP32-H2 series of SoCs. It consists of the following major chapters: Chip Revision Identification Introduces how to identify a specific ESP32-H2 chip revision, or a batch of chips and products built around the ESP32-H2 chips which contains error fixes described in this document. Errata Summary Overview of all bugs and their affected chip revisions. All Errata Descriptions Detailed bug descriptions, including conditions, expected behaviors and actual behaviors, causes, influences on users, workarounds, and solutions. Errata Descriptions by Chip Revisions Classification of bug descriptions by chip revisions. Revision History The release notes for this document. To switch to another chip, use the drop-down menu at the top left of the page. Next Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-H2 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata Disclaimer and Copyright Notice Download PDF Disclaimer and Copyright Notice [中文] Information in this document, including URL references, is subject to change without notice. All third party’s information in this document is provided as is with no warranties to its authenticity and accuracy. No warranty is provided to this document for its merchantability, non-infringement, fitness for any particular purpose, nor does any warranty otherwise arising out of any proposal, specification or sample. All liability, including liability for infringement of any proprietary rights, relating to use of information in this document is disclaimed. No licenses express or implied, by estoppel or otherwise, to any intellectual property rights are granted herein. The Wi-Fi Alliance Member logo is a trademark of the Wi-Fi Alliance. The Bluetooth logo is a registered trademark of Bluetooth SIG. All trade names, trademarks and registered trademarks mentioned in this document are property of their respective owners, and are hereby acknowledged. Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-H2 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions v0.0 (14) v0.1 (14) [BOOT-9537] Accidentally Enter USB Download Boot Mode If the Power-up Duration Is Too Long [ADC-7227] Unavailable Channel 4 in SRA ADC1 Description Workarounds Solution [AES-11401] CPA Attack-Related Security Vulnerability [ECC-11400] Timing Attack-Related Security Vulnerability [LEDC-253] Unable to Reach 100% Duty Cycle at Maximum Duty Resolution [PCNT-249] Unable to Trigger Step Interrupts [ADC-1477] Loss of Precision in Lower Four Bits of SAR ADC [SPI-304] Enabling Flash Auto Suspend May Cause Abnormalities in Data Read [802.15.4-9538] TX Power Variation in Certain RF Certification [CLK-6996] Inaccurate Calibration of RC_FAST_CLK Clock [CPU-206] Possible Deadlock Due to Out-of-Order Execution of Instructions When Writing to LP SRAM Is Involved [ECDSA_DS-837] Signatures with Invalid s Values Are Incorrectly Accepted [I2C-308] I2C Slave Fails in Multiple-read Under Non-FIFO Mode [RMT-176] The Idle State Signal Level Might Run into Error in RMT Continuous TX Mode v1.2 (2) Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata Errata Descriptions by Chip Revisions Chip Revision: v0.0 [ADC-7227] Unavailable Channel 4 in SRA ADC1 Download PDF [ADC-7227] Unavailable Channel 4 in SRA ADC1 Affected revisions: v0.0 v0.1 Description Channel 4 (ADC1_CH4) of ADC1 is not operational in the ESP32-H2 chip. Workarounds Use other channels instead of ADC1_CH4. Solution Fixed in chip revision v1.2. Next Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-H2 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions v0.0 (14) v0.1 (14) [BOOT-9537] Accidentally Enter USB Download Boot Mode If the Power-up Duration Is Too Long [ADC-7227] Unavailable Channel 4 in SRA ADC1 [AES-11401] CPA Attack-Related Security Vulnerability [ECC-11400] Timing Attack-Related Security Vulnerability [LEDC-253] Unable to Reach 100% Duty Cycle at Maximum Duty Resolution [PCNT-249] Unable to Trigger Step Interrupts [ADC-1477] Loss of Precision in Lower Four Bits of SAR ADC [SPI-304] Enabling Flash Auto Suspend May Cause Abnormalities in Data Read [802.15.4-9538] TX Power Variation in Certain RF Certification [CLK-6996] Inaccurate Calibration of RC_FAST_CLK Clock [CPU-206] Possible Deadlock Due to Out-of-Order Execution of Instructions When Writing to LP SRAM Is Involved [ECDSA_DS-837] Signatures with Invalid s Values Are Incorrectly Accepted [I2C-308] I2C Slave Fails in Multiple-read Under Non-FIFO Mode Description Workarounds Solution [RMT-176] The Idle State Signal Level Might Run into Error in RMT Continuous TX Mode v1.2 (2) Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata Errata Descriptions by Chip Revisions Chip Revision: v0.0 [I2C-308] I2C Slave Fails in Multiple-read Under Non-FIFO Mode Download PDF [I2C-308] I2C Slave Fails in Multiple-read Under Non-FIFO Mode Affected revisions: v0.0 v0.1 Description If the I2C slave non-FIFO mode is enabled and the master performs multiple-read operation on the slave, the master can not correctly read the data from the slave. Workarounds Set I2C_FIFO_ADDR_CFG_EN and I2C_SLV_TX_AUTO_START_EN to 1 and I2C_FIFO_PRT_EN to 0 for the slave. After configuration, the master must access the slave using the following command sequence: RSTART -> WRITE (slave addr, fifo addr) -> RSTART -> WRITE (slave addr) -> READ (NACK) -> STOP, with only one byte allowed to be read each time. Solution Fixed in chip revision v1.2. Next Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-H2 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions v0.0 (14) v0.1 (14) [BOOT-9537] Accidentally Enter USB Download Boot Mode If the Power-up Duration Is Too Long [ADC-7227] Unavailable Channel 4 in SRA ADC1 [AES-11401] CPA Attack-Related Security Vulnerability [ECC-11400] Timing Attack-Related Security Vulnerability [LEDC-253] Unable to Reach 100% Duty Cycle at Maximum Duty Resolution [PCNT-249] Unable to Trigger Step Interrupts [ADC-1477] Loss of Precision in Lower Four Bits of SAR ADC Description Workarounds Solution [SPI-304] Enabling Flash Auto Suspend May Cause Abnormalities in Data Read [802.15.4-9538] TX Power Variation in Certain RF Certification [CLK-6996] Inaccurate Calibration of RC_FAST_CLK Clock [CPU-206] Possible Deadlock Due to Out-of-Order Execution of Instructions When Writing to LP SRAM Is Involved [ECDSA_DS-837] Signatures with Invalid s Values Are Incorrectly Accepted [I2C-308] I2C Slave Fails in Multiple-read Under Non-FIFO Mode [RMT-176] The Idle State Signal Level Might Run into Error in RMT Continuous TX Mode v1.2 (2) Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata Errata Descriptions by Chip Revisions Chip Revision: v0.0 [ADC-1477] Loss of Precision in Lower Four Bits of SAR ADC Download PDF [ADC-1477] Loss of Precision in Lower Four Bits of SAR ADC Affected revisions: v0.0 v0.1 Description The lower four bits of the SAR ADC data bits are missing, causing a loss of precision in the corresponding bits. Workarounds No workaround. Solution Fixed in chip revision v1.2. Next Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-H2 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions v0.0 (14) v0.1 (14) [BOOT-9537] Accidentally Enter USB Download Boot Mode If the Power-up Duration Is Too Long [ADC-7227] Unavailable Channel 4 in SRA ADC1 [AES-11401] CPA Attack-Related Security Vulnerability [ECC-11400]