ESP Chip Errata Choose target... Choose version... ESP32-C61 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata ESP32-C61 Series SoC Errata Download PDF ESP32-C61 Series SoC Errata [中文] This document describes known errata in ESP32-C61 series of SoCs. It consists of the following major chapters: Chip Revision Identification Introduces how to identify a specific ESP32-C61 chip revision, or a batch of chips and products built around the ESP32-C61 chips which contains error fixes described in this document. Errata Summary Overview of all bugs and their affected chip revisions. All Errata Descriptions Detailed bug descriptions, including conditions, expected behaviors and actual behaviors, causes, influences on users, workarounds, and solutions. Errata Descriptions by Chip Revisions Classification of bug descriptions by chip revisions. Revision History The release notes for this document. To switch to another chip, use the drop-down menu at the top left of the page. Next Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-C61 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata Disclaimer and Copyright Notice Download PDF Disclaimer and Copyright Notice [中文] Information in this document, including URL references, is subject to change without notice. All third party’s information in this document is provided as is with no warranties to its authenticity and accuracy. No warranty is provided to this document for its merchantability, non-infringement, fitness for any particular purpose, nor does any warranty otherwise arising out of any proposal, specification or sample. All liability, including liability for infringement of any proprietary rights, relating to use of information in this document is disclaimed. No licenses express or implied, by estoppel or otherwise, to any intellectual property rights are granted herein. The Wi-Fi Alliance Member logo is a trademark of the Wi-Fi Alliance. The Bluetooth logo is a registered trademark of Bluetooth SIG. All trade names, trademarks and registered trademarks mentioned in this document are property of their respective owners, and are hereby acknowledged. Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-C61 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions [CPU-718] PSRAM Read-After-Write Consistency Description Cause Examples Workarounds Solution Errata Descriptions by Chip Revisions Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata All Errata Descriptions Download PDF All Errata Descriptions [中文] [CPU-718] PSRAM Read-After-Write Consistency Affected revisions: v0.0 v0.1 v0.2 v1.0 Description When the CPU performs random read or write accesses to PSRAM through CACHE or DMA, and one of the following conditions is true: PSRAM encryption or decryption is enabled, or When accessing PSRAM via DMA, AHB_DMA_OUT_DATA_BURST_MODE_SEL_CHn is set to 0 or 1. Data-consistency issues may occur for CPU accesses to PSRAM. Cause The MSPI hardware handles CPU read or write requests to PSRAM and uses an internal buffer or cache. Because of this buffering (and encryption or decryption latency), CPU read or write requests received by MSPI are not always executed on the SPI bus immediately. If the CPU performs a write to a PSRAM address and then quickly issues a read to the same physical address, the write may still be delayed inside MSPI. In that case, MSPI can execute the read before the earlier write has actually completed on the PSRAM, leading to stale or inconsistent data being returned. Examples If CACHE reads from an encrypted or decrypted PSRAM region and a cache miss occurs, the data written back can be inconsistent. After a DMA write to PSRAM completes, a subsequent DMA read or CACHE read of the same PSRAM region may return inconsistent data. Workarounds For consistency problems caused by cache misses during encryption or decryption: Avoid enabling PSRAM encryption in workloads that perform random read or write access. For consistency problems when the CPU accesses PSRAM via DMA: Insert a short delay after the DMA write finishes, or before the CPU reads the same physical address, to ensure MSPI has completed the actual PSRAM write. Solution To be fixed in the next chip revision. Next Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-C61 Series SoC Errata Chip Revision Identification Chip Revision Numbering Scheme Primary Identification Methods eFuse Bits Chip Marking Module Marking Additional Identification Methods Date Code PW Number ESP-IDF Release Compatibility Related Documents Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata Chip Revision Identification Download PDF Chip Revision Identification [中文] Espressif is introducing a new vM.X numbering scheme to indicate chip revisions. This guide outlines the structure of this scheme and provides information on chip errata and additional identification methods. Chip Revision Numbering Scheme The new numbering scheme vM.X consists of the major and minor numbers described below. M – Major number, indicating the major revision of the chip product. If this number changes, it means the software used for the previous version of the product is incompatible with the new product, and the software version shall be upgraded for the use of the new product. X – Minor number, indicating the minor revision of the chip product. If this number changes, it means the software used for the previous version of the product is compatible with the new product, and there is no need to upgrade the software. The vM.X scheme replaces previously used chip revision schemes, including ECOx numbers, Vxxx, and other formats if any. Primary Identification Methods eFuse Bits The chip revision is encoded using two eFuse fields: EFUSE_RD_MAC_SYS2_REG[3:0] EFUSE_RD_MAC_SYS2_REG[5:4] Table 1 Chip Revision Identification by eFuse Bits eFuse Bit Chip Revision v0.0 v0.1 v0.2 v1.0 Major Number EFUSE_RD_MAC_SYS2_REG[5] 0 0 0 0 EFUSE_RD_MAC_SYS2_REG[4] 0 0 0 1 Minor Number EFUSE_RD_MAC_SYS2_REG[3] 0 0 0 0 EFUSE_RD_MAC_SYS2_REG[2] 0 0 0 0 EFUSE_RD_MAC_SYS2_REG[1] 0 0 1 0 EFUSE_RD_MAC_SYS2_REG[0] 0 1 0 0 Chip Marking Manufacturing Code line in chip marking Figure 1 Chip Marking Diagram Table 2 Chip Revision Identification by Chip Marking Chip Revision Manufacturing Code v0.0 X A XX v0.1 X B XX v0.2 X C XX v1.0 X D XX Module Marking Specification Identifier line in module marking Figure 2 Module Marking Diagram Table 3 Chip Revision Identification by Module Marking Chip Revision Specification Identifier v0.0 XA XXXX v0.1 MB XXXX v0.2 MC XXXX v1.0 MD XXXX Additional Identification Methods Date Code Some errors in the chip product don’t need to be fixed at the silicon level, or in other words in a new chip revision. In this case, the chip may be identified by Date Code in chip marking (see Chip Marking). For more information, please refer to ESP32-C61 Chip Packaging Information > Chip Silk Marking. PW Number Modules built around the chip may be identified by PW Number in product label (see Module Product Label). For more information, please refer to ESP32-C61 Module Packaging Information > Pizza Box. Figure 3 Module Product Label Note Please note that PW Number is only provided for reels packaged in aluminum moisture barrier bags (MBB). ESP-IDF Release Compatibility Information about ESP-IDF release that supports a specific chip revision is provided in Compatibility Between ESP-IDF Releases and Revisions of Espressif SoCs. Related Documents For more information about the chip revision upgrade and their identification of series products, please refer to ESP32-C61 Product/Process Change Notifications (PCN). For more information about the chip revision numbering scheme, see Compatibility Advisory for Chip Revision Numbering Scheme. Next Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-C61 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions v0.0 (1) v0.1 (1) v0.2 (1) [CPU-718] PSRAM Read-After-Write Consistency v1.0 (1) Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice