ESP Chip Errata Choose target... Choose version... ESP32-C6 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata ESP32-C6 Series SoC Errata Download PDF ESP32-C6 Series SoC Errata [中文] This document describes known errata in ESP32-C6 series of SoCs. It consists of the following major chapters: Chip Revision Identification Introduces how to identify a specific ESP32-C6 chip revision, or a batch of chips and products built around the ESP32-C6 chips which contains error fixes described in this document. Errata Summary Overview of all bugs and their affected chip revisions. All Errata Descriptions Detailed bug descriptions, including conditions, expected behaviors and actual behaviors, causes, influences on users, workarounds, and solutions. Errata Descriptions by Chip Revisions Classification of bug descriptions by chip revisions. Revision History The release notes for this document. To switch to another chip, use the drop-down menu at the top left of the page. Next Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-C6 Series SoC Errata Chip Revision Identification Chip Revision Numbering Scheme Primary Identification Methods eFuse Bits Chip Marking Module Marking Additional Identification Methods Date Code PW Number ESP-IDF Release Compatibility Related Documents Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata Chip Revision Identification Download PDF Chip Revision Identification [中文] Espressif is introducing a new vM.X numbering scheme to indicate chip revisions. This guide outlines the structure of this scheme and provides information on chip errata and additional identification methods. Chip Revision Numbering Scheme The new numbering scheme vM.X consists of the major and minor numbers described below. M – Major number, indicating the major revision of the chip product. If this number changes, it means the software used for the previous version of the product is incompatible with the new product, and the software version shall be upgraded for the use of the new product. X – Minor number, indicating the minor revision of the chip product. If this number changes, it means the software used for the previous version of the product is compatible with the new product, and there is no need to upgrade the software. The vM.X scheme replaces previously used chip revision schemes, including ECOx numbers, Vxxx, and other formats if any. Primary Identification Methods eFuse Bits The chip revision is encoded using two eFuse fields: EFUSE_RD_MAC_SPI_SYS_3_REG[23:22] EFUSE_RD_MAC_SPI_SYS_3_REG[21:18] Table 1 Chip Revision Identification by eFuse Bits eFuse Bit Chip Revision v0.0 v0.1 v0.2 Major Number EFUSE_RD_MAC_SPI_SYS_3_REG[23] 0 0 0 EFUSE_RD_MAC_SPI_SYS_3_REG[22] 0 0 0 Minor Number EFUSE_RD_MAC_SPI_SYS_3_REG[21] 0 0 0 EFUSE_RD_MAC_SPI_SYS_3_REG[20] 0 0 0 EFUSE_RD_MAC_SPI_SYS_3_REG[19] 0 0 1 EFUSE_RD_MAC_SPI_SYS_3_REG[18] 0 1 0 Chip Marking Espressif Tracking Information line in chip marking Figure 1 Chip Marking Diagram Table 2 Chip Revision Identification by Chip Marking Chip Revision Espressif Tracking Information v0.0 X A XXXXXXXX v0.1 X B XXXXXXXX v0.2 X C XXXXXXXX Module Marking Specification Identifier line in module marking Figure 2 Module Marking Diagram Table 3 Chip Revision Identification by Module Marking Chip Revision Specification Identifier v0.0 XA XXXX v0.1 MB XXXX v0.2 MC XXXX Additional Identification Methods Date Code Some errors in the chip product don’t need to be fixed at the silicon level, or in other words in a new chip revision. In this case, the chip may be identified by Date Code in chip marking (see Chip Marking). For more information, please refer to ESP32-C6 Chip Packaging Information > Chip Silk Marking. PW Number Modules built around the chip may be identified by PW Number in product label (see Module Product Label). For more information, please refer to ESP32-C6 Module Packaging Information > Pizza Box. Figure 3 Module Product Label Note Please note that PW Number is only provided for reels packaged in aluminum moisture barrier bags (MBB). ESP-IDF Release Compatibility Information about ESP-IDF release that supports a specific chip revision is provided in Compatibility Between ESP-IDF Releases and Revisions of Espressif SoCs. Related Documents For more information about the chip revision upgrade and their identification of series products, please refer to ESP32-C6 Product/Process Change Notifications (PCN). For more information about the chip revision numbering scheme, see Compatibility Advisory for Chip Revision Numbering Scheme. Next Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-C6 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata Errata Summary Download PDF Errata Summary [中文] Table 4 Errata summary Category Errata No. Descriptions Affected Revisions v0.0 v0.1 v0.2 RISC-V CPU CPU-206 [CPU-206] Possible Deadlock Due to Out-of-Order Execution of Instructions When Writing to LP SRAM Is Involved Y Y Clock CLK-6996 [CLK-6996] Inaccurate Calibration of RC_FAST_CLK Clock Y CLK-8588 [CLK-8588] 32 kHz Internal Slow RC Oscillator May Fail to Oscillate Y Y Y Reset RES-7080 [RES-7080] System Reset Triggered by RTC Watchdog Timer Cannot Be Correctly Reported Y SPI SPI-304 [SPI-304] Enabling Flash Auto Suspend May Cause Abnormalities in Data Read Y Y RMT RMT-176 [RMT-176] The Idle State Signal Level Might Run into Error in RMT Continuous TX Mode Y Y Y SAR ADC ADC-305 [ADC-305] Data Duplication May Occur When SAR ADC Accessing GDMA Y Y ADC-1477 [ADC-1477] Loss of Precision in Lower Four Bits of SAR ADC Y Y Wi-Fi WIFI-9686 [WIFI-9686] ESP32-C6 Cannot Be 802.11mc FTM Initiator Y Y Next Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-C6 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions v0.0 (9) v0.1 (7) [CLK-8588] 32 kHz Internal Slow RC Oscillator May Fail to Oscillate [ADC-305] Data Duplication May Occur When SAR ADC Accessing GDMA [ADC-1477] Loss of Precision in Lower Four Bits of SAR ADC [SPI-304] Enabling Flash Auto Suspend May Cause Abnormalities in Data Read [WIFI-9686] ESP32-C6 Cannot Be 802.11mc FTM Initiator [CPU-206] Possible Deadlock Due to Out-of-Order Execution of Instructions When Writing to LP SRAM Is Involved Description Workarounds Solution [RMT-176] The Idle State Signal Level Might Run into Error in RMT Continuous TX Mode v0.2 (2) Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata Errata Descriptions by Chip Revisions Chip Revision: v0.0 [CPU-206] Possible Deadlock Due to Out-of-Order Execution of Instructions When Writing to LP SRAM Is Involved Download PDF [CPU-206] Possible Deadlock Due to Out-of-Order Execution of Instructions When Writing to LP SRAM Is Involved Affected revisions: v0.0 v0.1 Description When HP CPU executes instructions (instruction A and instruction B successively) in LP SRAM, and instruction A and instruction B happen to follow the following patterns: Instruction A involves writing to memory. Examples: sw/sh/sb Instruction B involves only accessing the instruction bus. Examples: nop/jal/jalr/lui/auipc The address of instruction B is not 4-byte aligned The data written by instruction A to memory is only committed after instruction B has completed execution. This introduces a risk where, after instruction A writing to memory, if an infinite loop is executed in instruction B, the writing of instruction A will never complete. Workarounds When you experience this problem, or when you check the assembly code and see the above mentioned pattern, Add a fence instruction between instruction A and the infinite loop. This can be achieved by using the rv_utils_memory_barrier interface in ESP-IDF. Replace the infinite loop with instruction wfi. This can be achieved by using the rv_utils_wait_for_intr interface in ESP-IDF. Disable the RV32C (compressed) extension when compiling code that to be executed in LP SRAM to avoid instructions with not 4-byte aligned addresses. Solution Fixed in chip revision v0.2. Next Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-C6 Series SoC Errata Chip Revision Identification Errata Summary All