ESP Chip Errata Choose target... Choose version... ESP32-C5 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata ESP32-C5 Series SoC Errata Download PDF ESP32-C5 Series SoC Errata [中文] This document describes known errata in ESP32-C5 series of SoCs. It consists of the following major chapters: Chip Revision Identification Introduces how to identify a specific ESP32-C5 chip revision, or a batch of chips and products built around the ESP32-C5 chips which contains error fixes described in this document. Errata Summary Overview of all bugs and their affected chip revisions. All Errata Descriptions Detailed bug descriptions, including conditions, expected behaviors and actual behaviors, causes, influences on users, workarounds, and solutions. Errata Descriptions by Chip Revisions Classification of bug descriptions by chip revisions. Revision History The release notes for this document. To switch to another chip, use the drop-down menu at the top left of the page. Next Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-C5 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata Revision History Download PDF Revision History [中文] Table 5 Revision History Date Version Release Notes 2026-06-12 v1.2 All Errata Descriptions Added Section [ECC-833] Forcing ECC Memory Power-Down Bypasses ECDSA_DS Signature Verification 2026-03-04 v1.1 Chip Revision Identification Added information about chip revision v1.2 All Errata Descriptions In Section [CPU-718] PSRAM Read-After-Write Consistency, updated solution to “fixed in chip revision v1.2” Added Section [SRAM-436] Internal SRAM Contents May Be Corrupted After Digital Peripheral Power Domain Power-Down Added Section [HUK-576] HUK Is Unavailable Added Section [FLASH-938] Flash Manual Encryption May Fail When CPU Runs at 240 MHz 2025-11-05 v1.0 First release Next Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-C5 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata Disclaimer and Copyright Notice Download PDF Disclaimer and Copyright Notice [中文] Information in this document, including URL references, is subject to change without notice. All third party’s information in this document is provided as is with no warranties to its authenticity and accuracy. No warranty is provided to this document for its merchantability, non-infringement, fitness for any particular purpose, nor does any warranty otherwise arising out of any proposal, specification or sample. All liability, including liability for infringement of any proprietary rights, relating to use of information in this document is disclaimed. No licenses express or implied, by estoppel or otherwise, to any intellectual property rights are granted herein. The Wi-Fi Alliance Member logo is a trademark of the Wi-Fi Alliance. The Bluetooth logo is a registered trademark of Bluetooth SIG. All trade names, trademarks and registered trademarks mentioned in this document are property of their respective owners, and are hereby acknowledged. Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-C5 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions v0.0 (2) v0.1 (2) v1.0 (5) v1.2 (2) Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata Errata Descriptions by Chip Revisions Download PDF Errata Descriptions by Chip Revisions Chip Revision v0.0 (2) v0.1 (2) v1.0 (5) v1.2 (2) Next Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-C5 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions v0.0 (2) [HUK-576] HUK Is Unavailable [CPU-718] PSRAM Read-After-Write Consistency v0.1 (2) v1.0 (5) v1.2 (2) Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata Errata Descriptions by Chip Revisions Chip Revision: v0.0 Download PDF Chip Revision: v0.0 Known Errors [HUK-576] HUK Is Unavailable [CPU-718] PSRAM Read-After-Write Consistency Next Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-C5 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions v0.0 (2) v0.1 (2) v1.0 (5) [ECC-833] Forcing ECC Memory Power-Down Bypasses ECDSA_DS Signature Verification [FLASH-938] Flash Manual Encryption May Fail When CPU Runs at 240 MHz [HUK-576] HUK Is Unavailable [SRAM-436] Internal SRAM Contents May Be Corrupted After Digital Peripheral Power Domain Power-Down [CPU-718] PSRAM Read-After-Write Consistency v1.2 (2) Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata Errata Descriptions by Chip Revisions Chip Revision: v1.0 Download PDF Chip Revision: v1.0 Known Errors [ECC-833] Forcing ECC Memory Power-Down Bypasses ECDSA_DS Signature Verification [FLASH-938] Flash Manual Encryption May Fail When CPU Runs at 240 MHz [HUK-576] HUK Is Unavailable [SRAM-436] Internal SRAM Contents May Be Corrupted After Digital Peripheral Power Domain Power-Down [CPU-718] PSRAM Read-After-Write Consistency Next Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-C5 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions v0.0 (2) v0.1 (2) v1.0 (5) v1.2 (2) [ECC-833] Forcing ECC Memory Power-Down Bypasses ECDSA_DS Signature Verification [FLASH-938] Flash Manual Encryption May Fail When CPU Runs at 240 MHz Description Workaround Solution Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata Errata Descriptions by Chip Revisions Chip Revision: v1.0 [FLASH-938] Flash Manual Encryption May Fail When CPU Runs at 240 MHz Download PDF [FLASH-938] Flash Manual Encryption May Fail When CPU Runs at 240 MHz Affected revisions: v1.0 v1.2 Description On ESP32-C5 chips, flash manual encryption may fail when the CPU frequency is set to 240 MHz due to internal power consumption fluctuations. Workaround When performing flash manual encryption, configure the CPU frequency to 160 MHz or lower. Solution No fix scheduled. Next Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-C5 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions v0.0 (2) v0.1 (2) v1.0 (5) v1.2 (2) [ECC-833] Forcing ECC Memory Power-Down Bypasses ECDSA_DS Signature Verification [FLASH-938] Flash Manual Encryption May Fail When CPU Runs at 240 MHz Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata Errata Descriptions by Chip Revisions Chip Revision: v1.2 Download PDF Chip Revision: v1.2 Known Errors [ECC-833] Forcing ECC Memory Power-Down Bypasses ECDSA_DS Signature Verification [FLASH-938] Flash Manual Encryption May Fail When CPU Runs at 240 MHz Next Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphi