ESP Chip Errata Choose target... Choose version... ESP32-C3 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata ESP32-C3 Series SoC Errata Download PDF ESP32-C3 Series SoC Errata [中文] This document describes known errata in ESP32-C3 series of SoCs. It consists of the following major chapters: Chip Revision Identification Introduces how to identify a specific ESP32-C3 chip revision, or a batch of chips and products built around the ESP32-C3 chips which contains error fixes described in this document. Errata Summary Overview of all bugs and their affected chip revisions. All Errata Descriptions Detailed bug descriptions, including conditions, expected behaviors and actual behaviors, causes, influences on users, workarounds, and solutions. Errata Descriptions by Chip Revisions Classification of bug descriptions by chip revisions. Revision History The release notes for this document. To switch to another chip, use the drop-down menu at the top left of the page. Next Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-C3 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions v0.0 (3) v0.1 (3) v0.2 (3) v0.3 (3) v0.4 (3) v1.1 (3) [ADC-270] SAR ADC Cannot Sample Sufficient Data in DMA Continuous Conversion Mode After Restart [CPU-863] Misaligned Memory Access May Lead to Exception Description Workarounds Solution [ADC-183] The Digital Controller (DMA) of SAR ADC2 Cannot Work Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata Errata Descriptions by Chip Revisions Chip Revision: v0.0 [CPU-863] Misaligned Memory Access May Lead to Exception Download PDF [CPU-863] Misaligned Memory Access May Lead to Exception Affected revisions: v0.0 v0.1 v0.2 v0.3 v0.4 v1.1 Description A misaligned load instruction immediately followed by a store instruction may raise a load access fault exception (exception code 5) when the load address and the store address lie in regions with different access permissions configured via Physical Memory Protection (PMP) or Physical Memory Attributes (PMA). For example, the following sequence commonly triggers this issue when copying an unaligned word from flash or ROM into RAM: lw a0, 0(a1) # unaligned 32-bit address load from a read-only PMP region (e.g., ROM) sw a0, 0(a2) # store to a read-write PMP region (e.g., RAM) Root cause: A misaligned load that crosses a word boundary is split internally into two transactions. Due to a timing alignment issue in the design, the second transaction of the misaligned load can incorrectly be checked against the store’s access permissions instead of its own, triggering an exception. Workarounds The RISC-V specification does not guarantee that hardware supports misaligned accesses. General-purpose RISC-V code should not rely on that support. If misaligned accesses cannot be avoided, such as when porting third-party libraries, use the following workarounds: Insert one or more nop instructions between the misaligned load and the following store. This prevents the incorrect permission check described above. Note Linkers that support the --fix-esp-pmp-misalign option can insert nop instructions between consecutive load and store instructions automatically. This option is conservative, as it may also insert extra nop instructions for pairs that would not trigger this exception, for example, when the accesses are aligned or when both access the same PMP region. When copying memory, use misaligned load/store only for the first and last misaligned words of a data block, and use aligned load/store for the words in between. This approach requires fewer nop instructions and has better performance than inserting nop instructions throughout. Configure the same PMP/PMA permissions for the memory regions accessed by the misaligned load and the following store. This may require saving and restoring the permission settings around the affected code. Solution No fix scheduled. Next Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-C3 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions v0.0 (3) v0.1 (3) v0.2 (3) [ADC-270] SAR ADC Cannot Sample Sufficient Data in DMA Continuous Conversion Mode After Restart [CPU-863] Misaligned Memory Access May Lead to Exception [ADC-183] The Digital Controller (DMA) of SAR ADC2 Cannot Work v0.3 (3) v0.4 (3) v1.1 (3) Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata Errata Descriptions by Chip Revisions Chip Revision: v0.2 Download PDF Chip Revision: v0.2 Known Errors [ADC-270] SAR ADC Cannot Sample Sufficient Data in DMA Continuous Conversion Mode After Restart [CPU-863] Misaligned Memory Access May Lead to Exception [ADC-183] The Digital Controller (DMA) of SAR ADC2 Cannot Work Next Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-C3 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions Revision History Resources and Legal Notices Related Documentation and Resources Related Documentation Developer Zone Products Contact Us Disclaimer and Copyright Notice ESP Chip Errata Related Documentation and Resources Download PDF Related Documentation and Resources [中文] Related Documentation ESP32-C3 Datasheet – Specifications of the ESP32-C3 hardware. ESP32-C3 Technical Reference Manual – Detailed information on how to use the ESP32-C3 memory and peripherals. ESP32-C3 Hardware Design Guidelines – Guidelines on how to integrate the ESP32-C3 into your hardware product. Certificates https://espressif.com/en/support/documents/certificates ESP32-C3 Product/Process Change Notifications (PCN) https://espressif.com/en/support/documents/pcns?keys=ESP32-C3 ESP32-C3 Advisories – Information on security, bugs, compatibility, component reliability. https://espressif.com/en/support/documents/advisories?keys=ESP32-C3 Documentation Updates and Update Notification Subscription https://espressif.com/en/support/download/documents Developer Zone ESP-IDF Programming Guide for ESP32-C3 – Extensive documentation for the ESP-IDF development framework. ESP-IDF and other development frameworks on GitHub. https://github.com/espressif ESP32 BBS Forum – Engineer-to-Engineer (E2E) Community for Espressif products where you can post questions, share knowledge, explore ideas, and help solve problems with fellow engineers. https://esp32.com/ The ESP Journal – Best Practices, Articles, and Notes from Espressif folks. https://blog.espressif.com/ See the tabs SDKs and Demos, Apps, Tools, AT Firmware. https://espressif.com/en/support/download/sdks-demos Products ESP32-C3 Series SoCs – Browse through all ESP32-C3 SoCs. https://espressif.com/en/products/socs?id=ESP32-C3 ESP32-C3 Series Modules – Browse through all ESP32-C3-based modules. https://espressif.com/en/products/modules?id=ESP32-C3 ESP32-C3 Series DevKits – Browse through all ESP32-C3-based devkits. https://espressif.com/en/products/devkits?id=ESP32-C3 ESP Product Selector – Find an Espressif hardware product suitable for your needs by comparing or applying filters. https://products.espressif.com/#/product-selector Contact Us See the tabs Sales Questions, Technical Enquiries, Circuit Schematic & PCB Design Review, Get Samples (Online stores), Become Our Supplier, Comments & Suggestions. https://espressif.com/en/contact-us/sales-questions Next Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-C3 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions v0.0 (3) v0.1 (3) v0.2 (3) v0.3 (3) v0.4 (3) v1.1 (3) [ADC-270] SAR ADC Cannot Sample Sufficient Data in DMA Continuous Conversion Mode After Restart [CPU-863] Misaligned Memory Access May Lead to Exception [ADC-183] The Digital Controller (DMA) of SAR ADC2 Cannot Work Description Workarounds Solution Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata Errata Descriptions by Chip Revisions Chip Revision: v0.0 [ADC-183] The Digital Controller (DMA) of SAR ADC2 Cannot Work Download PDF [ADC-183] The Digital Controller (DMA) of SAR ADC2 Cannot Work Affected revisions: v0.0 v0.1 v0.2 v0.3 v0.4 v1.1 Description The Digital Controller of SAR ADC2, i.e., DIG ADC2 controller, may receive a false sampling enable signal. In such a case, the controller will enter an inopera