ESP Chip Errata Choose target... Choose version... ESP32-C2 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata ESP32-C2 Series SoC Errata Download PDF ESP32-C2 Series SoC Errata [中文] This document describes known errata in ESP32-C2 series of SoCs. It consists of the following major chapters: Chip Revision Identification Introduces how to identify a specific ESP32-C2 chip revision, or a batch of chips and products built around the ESP32-C2 chips which contains error fixes described in this document. Errata Summary Overview of all bugs and their affected chip revisions. All Errata Descriptions Detailed bug descriptions, including conditions, expected behaviors and actual behaviors, causes, influences on users, workarounds, and solutions. Errata Descriptions by Chip Revisions Classification of bug descriptions by chip revisions. Revision History The release notes for this document. To switch to another chip, use the drop-down menu at the top left of the page. Important The ESP32-C2 SoC currently consists of only one series, the ESP8684, so the references of ESP32-C2 in this document refers to the ESP8684 Series SoCs. Next Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-C2 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions v0.0 (2) v1.0 (2) v1.1 (1) [CPU-863] Misaligned Memory Access May Lead to Exception v1.2 (1) v2.0 (1) Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata Errata Descriptions by Chip Revisions Chip Revision: v1.1 Download PDF Chip Revision: v1.1 Known Errors [CPU-863] Misaligned Memory Access May Lead to Exception Next Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-C2 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions v0.0 (2) v1.0 (2) v1.1 (1) v1.2 (1) v2.0 (1) [CPU-863] Misaligned Memory Access May Lead to Exception Description Workarounds Solution Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata Errata Descriptions by Chip Revisions Chip Revision: v0.0 [CPU-863] Misaligned Memory Access May Lead to Exception Download PDF [CPU-863] Misaligned Memory Access May Lead to Exception Affected revisions: v0.0 v1.0 v1.1 v1.2 v2.0 Description A misaligned load instruction immediately followed by a store instruction may raise a load access fault exception (exception code 5) when the load address and the store address lie in regions with different access permissions configured via Physical Memory Protection (PMP) or Physical Memory Attributes (PMA). For example, the following sequence commonly triggers this issue when copying an unaligned word from flash or ROM into RAM: lw a0, 0(a1) # unaligned 32-bit address load from a read-only PMP region (e.g., ROM) sw a0, 0(a2) # store to a read-write PMP region (e.g., RAM) Root cause: A misaligned load that crosses a word boundary is split internally into two transactions. Due to a timing alignment issue in the design, the second transaction of the misaligned load can incorrectly be checked against the store’s access permissions instead of its own, triggering an exception. Workarounds The RISC-V specification does not guarantee that hardware supports misaligned accesses. General-purpose RISC-V code should not rely on that support. If misaligned accesses cannot be avoided, such as when porting third-party libraries, use the following workarounds: Insert one or more nop instructions between the misaligned load and the following store. This prevents the incorrect permission check described above. Note Linkers that support the --fix-esp-pmp-misalign option can insert nop instructions between consecutive load and store instructions automatically. This option is conservative, as it may also insert extra nop instructions for pairs that would not trigger this exception, for example, when the accesses are aligned or when both access the same PMP region. When copying memory, use misaligned load/store only for the first and last misaligned words of a data block, and use aligned load/store for the words in between. This approach requires fewer nop instructions and has better performance than inserting nop instructions throughout. Configure the same PMP/PMA permissions for the memory regions accessed by the misaligned load and the following store. This may require saving and restoring the permission settings around the affected code. Solution No fix scheduled. Next Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-C2 Series SoC Errata Chip Revision Identification Chip Revision Numbering Scheme Primary Identification Methods eFuse Bits Chip Marking Module Marking Additional Identification Methods Date Code PW Number ESP-IDF Release Compatibility Related Documents Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata Chip Revision Identification Download PDF Chip Revision Identification [中文] Espressif is introducing a new vM.X numbering scheme to indicate chip revisions. This guide outlines the structure of this scheme and provides information on chip errata and additional identification methods. Chip Revision Numbering Scheme The new numbering scheme vM.X consists of the major and minor numbers described below. M – Major number, indicating the major revision of the chip product. If this number changes, it means the software used for the previous version of the product is incompatible with the new product, and the software version shall be upgraded for the use of the new product. X – Minor number, indicating the minor revision of the chip product. If this number changes, it means the software used for the previous version of the product is compatible with the new product, and there is no need to upgrade the software. The vM.X scheme replaces previously used chip revision schemes, including ECOx numbers, Vxxx, and other formats if any. Primary Identification Methods eFuse Bits The chip revision is encoded using two eFuse fields: EFUSE_BLK2_DATA1_REG[21:20] EFUSE_BLK2_DATA1_REG[19:16] Table 1 Chip Revision Identification by eFuse Bits eFuse Bit Chip Revision v0.0 v1.0 v1.1 v1.2 v2.0 Major Number EFUSE_BLK2_DATA1_REG[21] 0 0 0 0 1 EFUSE_BLK2_DATA1_REG[20] 0 1 1 1 0 Minor Number EFUSE_BLK2_DATA1_REG[19] 0 0 0 0 0 EFUSE_BLK2_DATA1_REG[18] 0 0 0 0 0 EFUSE_BLK2_DATA1_REG[17] 0 0 0 1 0 EFUSE_BLK2_DATA1_REG[16] 0 0 1 0 0 Chip Marking Espressif Tracking Information line in chip marking Figure 1 Chip Marking Diagram Table 2 Chip Revision Identification by Silk Print Chip Revision Espressif Tracking Information v0.0 X A XXXXXXXX v1.0 X AA XXXXXXX v1.1 X B XXXXXXXX v1.2 X C XXXXXXXX v2.0 X D XXXXXXXX Module Marking Specification Identifier line in module marking Figure 2 Module Marking Diagram Table 3 Chip Revision Identification by Module Marking Chip Revision Specification Identifier v0.0 — 1 v1.0 XA XXXX v1.1 XB XXXX v1.2 MC XXXX v2.0 MD XXXX 1 Missing specification identifier “—” means modules with this chip revision are not mass produced. Additional Identification Methods Date Code Some errors in the chip product don’t need to be fixed at the silicon level, or in other words in a new chip revision. In this case, the chip may be identified by Date Code in chip marking (see Chip Marking). For more information, please refer to ESP32-C2 Chip Packaging Information > Chip Silk Marking. PW Number Modules built around the chip may be identified by PW Number in product label (see Module Product Label). For more information, please refer to ESP32-C2 Module Packaging Information > Pizza Box. Figure 3 Module Product Label Note Please note that PW Number is only provided for reels packaged in aluminum moisture barrier bags (MBB). ESP-IDF Release Compatibility Information about ESP-IDF release that supports a specific chip revision is provided in Compatibility Between ESP-IDF Releases and Revisions of Espressif SoCs. Related Documents For more information about the chip revision upgrade and their identification of series products, please refer to ESP32-C2 Product/Process Change Notifications (PCN). For more information about the chip revision numbering scheme, see Compatibility Advisory for Chip Revision Numbering Scheme. Next Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32-C2 Series SoC Errata Chip Revision Identif