ESP Chip Errata Choose target... Choose version... ESP32 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata ESP32 Series SoC Errata Download PDF ESP32 Series SoC Errata [中文] This document describes known errata in ESP32 series of SoCs. It consists of the following major chapters: Chip Revision Identification Introduces how to identify a specific ESP32 chip revision, or a batch of chips and products built around the ESP32 chips which contains error fixes described in this document. Errata Summary Overview of all bugs and their affected chip revisions. All Errata Descriptions Detailed bug descriptions, including conditions, expected behaviors and actual behaviors, causes, influences on users, workarounds, and solutions. Errata Descriptions by Chip Revisions Classification of bug descriptions by chip revisions. Revision History The release notes for this document. To switch to another chip, use the drop-down menu at the top left of the page. Next Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions v0.0 (30) v1.0 (25) v1.1 (25) v3.0 (23) v3.1 (23) [CLK-3.22] ESP32 Cannot Be Used as the PHY Clock Source If Wi-fi and Ethernet Are Used at the Same Time [CPU-3.18] CPU Has Limitations When Accessing Peripherals in Chips [CPU-3.16] There Are Limitations to the CPU Access to 0x3ff0_0000 ~ 0x3ff1_efff and 0x3ff4_0000 ~ 0x3ff7_ffff Address Spaces [CPU-3.21] When a CPU Is Interrupted While Accessing Five Specific Fifo Registers, Subsequent CPU Accesses Will Get Halted [GPIO-3.6] For Pads With Both GPIO and RTC_GPIO Functionality, the GPIO Pull-up and Pull-down Configuration Register Fields Are Nonfunctional [GPIO-3.14] Within the Same Group of GPIO Pins, Edge Interrupts Cannot Be Used Together With Other Interrupts [GPIO-3.11] When Certain RTC Peripherals Are Powered on, the Inputs of GPIO36 and GPIO39 Will Be Pulled Down for Approximately 80 ns [LEDC-3.12] When the LEDC Is in Decremental Fade Mode, a Duty Overflow Error May Occur [TWAI-3.13.6] After Losing Arbitration, a Dominant Bit on the 3rd Bit of Intermission Is Not Interpreted as an SOF [TWAI-3.13.3] Message Transmitted After Bus-off Recovery Is Erroneous [TWAI-3.13.7] When the 8th Bit of the Error Delimiter Is Dominant, the Error Passive State Is Not Entered [TWAI-3.13.2] Error Status Bit Is Not Frozen During Bus-off Recovery Description Workarounds Solution [TWAI-3.13.5] Receiving an Erroneous Data Frame Can Cause the Data Bytes of the Next Received Data Frame to Be Invalid [TWAI-3.13.10] A Negative Phase Error Where |e| > SJW (N) Will Cause the Remaining Transmitted Bits to Be Left Shifted [TWAI-3.13.1] Receive Error Counter (REC) Is Allowed to Change Whilst in Reset Mode or Bus-off Recovery [TWAI-3.13.11] When the RX Fifo Overruns With 64 or More Messages, the RX Fifo Becomes Unrecoverable [TWAI-3.13.8] Suspend Transmission Is Included Even After Losing Arbitration [TWAI-3.13.9] When a Stuff Error Occurs During Arbitration Whilst Being Transmitter, Any Errors in the Subsequent Error/Overload Frame Will Not Increase the TEC [TWAI-3.13.4] Reading the Interrupt Register May Lead to a Transmit Interrupt Being Lost [UART-3.17] UART fifo_cnt Does Not Indicate the Data Length In Fifo Correctly [ULP-3.19] ULP Coprocessor And Touch Sensors Can Not Be Used In Deep-sleep Mode If RTC_PERIPH Power Domain Is Powered Up [WDT-3.15] {idf_target_name} Chip May Have A Live Lock Under Certain Conditions That Will Cause Interrupt Watchdog Issue [RTC-126] RTC Register Read Error After Wake-up from Light-sleep Mode Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata Errata Descriptions by Chip Revisions Chip Revision: v0.0 [TWAI-3.13.2] Error Status Bit Is Not Frozen During Bus-off Recovery Download PDF [TWAI-3.13.2] Error Status Bit Is Not Frozen During Bus-off Recovery Affected revisions: v0.0 v1.0 v1.1 v3.0 v3.1 Description When the TWAI controller undergoes the bus-off recovery process, the controller must monitor 128 occurrences of the bus free signal (11 consecutive recessive bits) before it can become error active again. The number of bus-free signals remaining is indicated by the transmit error counter (TEC). Because the error status bit is not frozen during bus-off recovery, its value will change when the transmit error counter drops below the user-defined transmit error warning limit (96 by default) thus trigger the error warning limit interrupt before bus-off recovery has completed. Workarounds When undergoing bus-off recovery, an error warning interrupt does not necessarily indicate the completion of recovery. Users should check the STATUS_NODE_BUS_OFF bit to verify whether bus-off recovery has completed. Solution No fix scheduled. Next Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions v0.0 (30) v1.0 (25) v1.1 (25) v3.0 (23) v3.1 (23) [CLK-3.22] ESP32 Cannot Be Used as the PHY Clock Source If Wi-fi and Ethernet Are Used at the Same Time Description Workarounds Solution [CPU-3.18] CPU Has Limitations When Accessing Peripherals in Chips [CPU-3.16] There Are Limitations to the CPU Access to 0x3ff0_0000 ~ 0x3ff1_efff and 0x3ff4_0000 ~ 0x3ff7_ffff Address Spaces [CPU-3.21] When a CPU Is Interrupted While Accessing Five Specific Fifo Registers, Subsequent CPU Accesses Will Get Halted [GPIO-3.6] For Pads With Both GPIO and RTC_GPIO Functionality, the GPIO Pull-up and Pull-down Configuration Register Fields Are Nonfunctional [GPIO-3.14] Within the Same Group of GPIO Pins, Edge Interrupts Cannot Be Used Together With Other Interrupts [GPIO-3.11] When Certain RTC Peripherals Are Powered on, the Inputs of GPIO36 and GPIO39 Will Be Pulled Down for Approximately 80 ns [LEDC-3.12] When the LEDC Is in Decremental Fade Mode, a Duty Overflow Error May Occur [TWAI-3.13.6] After Losing Arbitration, a Dominant Bit on the 3rd Bit of Intermission Is Not Interpreted as an SOF [TWAI-3.13.3] Message Transmitted After Bus-off Recovery Is Erroneous [TWAI-3.13.7] When the 8th Bit of the Error Delimiter Is Dominant, the Error Passive State Is Not Entered [TWAI-3.13.2] Error Status Bit Is Not Frozen During Bus-off Recovery [TWAI-3.13.5] Receiving an Erroneous Data Frame Can Cause the Data Bytes of the Next Received Data Frame to Be Invalid [TWAI-3.13.10] A Negative Phase Error Where |e| > SJW (N) Will Cause the Remaining Transmitted Bits to Be Left Shifted [TWAI-3.13.1] Receive Error Counter (REC) Is Allowed to Change Whilst in Reset Mode or Bus-off Recovery [TWAI-3.13.11] When the RX Fifo Overruns With 64 or More Messages, the RX Fifo Becomes Unrecoverable [TWAI-3.13.8] Suspend Transmission Is Included Even After Losing Arbitration [TWAI-3.13.9] When a Stuff Error Occurs During Arbitration Whilst Being Transmitter, Any Errors in the Subsequent Error/Overload Frame Will Not Increase the TEC [TWAI-3.13.4] Reading the Interrupt Register May Lead to a Transmit Interrupt Being Lost [UART-3.17] UART fifo_cnt Does Not Indicate the Data Length In Fifo Correctly [ULP-3.19] ULP Coprocessor And Touch Sensors Can Not Be Used In Deep-sleep Mode If RTC_PERIPH Power Domain Is Powered Up [WDT-3.15] {idf_target_name} Chip May Have A Live Lock Under Certain Conditions That Will Cause Interrupt Watchdog Issue [RTC-126] RTC Register Read Error After Wake-up from Light-sleep Mode Revision History Resources and Legal Notices Related Documentation and Resources Disclaimer and Copyright Notice ESP Chip Errata Errata Descriptions by Chip Revisions Chip Revision: v0.0 [CLK-3.22] ESP32 Cannot Be Used as the PHY Clock Source If Wi-fi and Ethernet Are Used at the Same Time Download PDF [CLK-3.22] ESP32 Cannot Be Used as the PHY Clock Source If Wi-fi and Ethernet Are Used at the Same Time Affected revisions: v0.0 v1.0 v1.1 v3.0 v3.1 Description In RMII working mode, the Ethernet MAC and PHY require a common 50 MHz reference clock (i.e., the RMII clock). If Wi-Fi and Ethernet are used simultaneously, the RMII clock cannot be generated by the internal APLL clock, as it would result in clock instability. Workarounds If you want to use the internal APLL to generate the reference clock, you need to disable Wi-Fi. If you want to use both Ethernet and Wi-Fi simultaneously, you need to use an external PHY or external clock source to provide the reference clock. Solution No fix scheduled. Next Previous Suggestion on this document? Provide feedback Help improve this document? Edit on GitHub Need more information? Check ESP forum Sales Questions Technical Inquiries © Copyright 2024 - 2026, Espressif Systems (Shanghai) Co., Ltd Built with Sphinx using a theme based on Read the Docs Sphinx Theme. ESP Chip Errata Choose target... Choose version... ESP32 Series SoC Errata Chip Revision Identification Errata Summary All Errata Descriptions Errata Descriptions by Chip Revisions v0.0 (30) v1.0 (25) v1.1 (25) v3.0 (23) v3.1 (23) [CLK-3.22] ESP32 Cannot Be Used as the PHY Clock Source If Wi-fi and Ethernet Are Used at the S